if_sf.c revision 122678
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 122678 2003-11-14 17:16:58Z obrien $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, pci, 1, 1, 1); 121MODULE_DEPEND(sf, ether, 1, 1, 1); 122MODULE_DEPEND(sf, miibus, 1, 1, 1); 123 124static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128}; 129 130static int sf_probe (device_t); 131static int sf_attach (device_t); 132static int sf_detach (device_t); 133static void sf_intr (void *); 134static void sf_stats_update (void *); 135static void sf_rxeof (struct sf_softc *); 136static void sf_txeof (struct sf_softc *); 137static int sf_encap (struct sf_softc *, 138 struct sf_tx_bufdesc_type0 *, 139 struct mbuf *); 140static void sf_start (struct ifnet *); 141static int sf_ioctl (struct ifnet *, u_long, caddr_t); 142static void sf_init (void *); 143static void sf_stop (struct sf_softc *); 144static void sf_watchdog (struct ifnet *); 145static void sf_shutdown (device_t); 146static int sf_ifmedia_upd (struct ifnet *); 147static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148static void sf_reset (struct sf_softc *); 149static int sf_init_rx_ring (struct sf_softc *); 150static void sf_init_tx_ring (struct sf_softc *); 151static int sf_newbuf (struct sf_softc *, 152 struct sf_rx_bufdesc_type0 *, 153 struct mbuf *); 154static void sf_setmulti (struct sf_softc *); 155static int sf_setperf (struct sf_softc *, int, caddr_t); 156static int sf_sethash (struct sf_softc *, caddr_t, int); 157#ifdef notdef 158static int sf_setvlan (struct sf_softc *, int, u_int32_t); 159#endif 160 161static u_int8_t sf_read_eeprom (struct sf_softc *, int); 162static u_int32_t sf_mchash (caddr_t); 163 164static int sf_miibus_readreg (device_t, int, int); 165static int sf_miibus_writereg (device_t, int, int, int); 166static void sf_miibus_statchg (device_t); 167 168static u_int32_t csr_read_4 (struct sf_softc *, int); 169static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170static void sf_txthresh_adjust (struct sf_softc *); 171 172#ifdef SF_USEIOSPACE 173#define SF_RES SYS_RES_IOPORT 174#define SF_RID SF_PCI_LOIO 175#else 176#define SF_RES SYS_RES_MEMORY 177#define SF_RID SF_PCI_LOMEM 178#endif 179 180static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203}; 204 205static devclass_t sf_devclass; 206 207DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 208DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210#define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 212 213#define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 215 216static u_int32_t 217csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220{ 221 u_int32_t val; 222 223#ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226#else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228#endif 229 230 return(val); 231} 232 233static u_int8_t 234sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237{ 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244} 245 246static void 247csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261static u_int32_t 262sf_mchash(addr) 263 caddr_t addr; 264{ 265 u_int32_t crc, carry; 266 int idx, bit; 267 u_int8_t data; 268 269 /* Compute CRC for the address value. */ 270 crc = 0xFFFFFFFF; /* initial value */ 271 272 for (idx = 0; idx < 6; idx++) { 273 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 275 crc <<= 1; 276 if (carry) 277 crc = (crc ^ 0x04c11db6) | carry; 278 } 279 } 280 281 /* return the filter bit position */ 282 return(crc >> 23 & 0x1FF); 283} 284 285/* 286 * Copy the address 'mac' into the perfect RX filter entry at 287 * offset 'idx.' The perfect filter only has 16 entries so do 288 * some sanity tests. 289 */ 290static int 291sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295{ 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314} 315 316/* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321static int 322sf_sethash(sc, mac, prio) 323 struct sf_softc *sc; 324 caddr_t mac; 325 int prio; 326{ 327 u_int32_t h = 0; 328 329 if (mac == NULL) 330 return(EINVAL); 331 332 h = sf_mchash(mac); 333 334 if (prio) { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } else { 338 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 339 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 340 } 341 342 return(0); 343} 344 345#ifdef notdef 346/* 347 * Set a VLAN tag in the receive filter. 348 */ 349static int 350sf_setvlan(sc, idx, vlan) 351 struct sf_softc *sc; 352 int idx; 353 u_int32_t vlan; 354{ 355 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 356 return(EINVAL); 357 358 csr_write_4(sc, SF_RXFILT_HASH_BASE + 359 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 360 361 return(0); 362} 363#endif 364 365static int 366sf_miibus_readreg(dev, phy, reg) 367 device_t dev; 368 int phy, reg; 369{ 370 struct sf_softc *sc; 371 int i; 372 u_int32_t val = 0; 373 374 sc = device_get_softc(dev); 375 376 for (i = 0; i < SF_TIMEOUT; i++) { 377 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 378 if (val & SF_MII_DATAVALID) 379 break; 380 } 381 382 if (i == SF_TIMEOUT) 383 return(0); 384 385 if ((val & 0x0000FFFF) == 0xFFFF) 386 return(0); 387 388 return(val & 0x0000FFFF); 389} 390 391static int 392sf_miibus_writereg(dev, phy, reg, val) 393 device_t dev; 394 int phy, reg, val; 395{ 396 struct sf_softc *sc; 397 int i; 398 int busy; 399 400 sc = device_get_softc(dev); 401 402 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 403 404 for (i = 0; i < SF_TIMEOUT; i++) { 405 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 406 if (!(busy & SF_MII_BUSY)) 407 break; 408 } 409 410 return(0); 411} 412 413static void 414sf_miibus_statchg(dev) 415 device_t dev; 416{ 417 struct sf_softc *sc; 418 struct mii_data *mii; 419 420 sc = device_get_softc(dev); 421 mii = device_get_softc(sc->sf_miibus); 422 423 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 424 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 425 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 426 } else { 427 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 428 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 429 } 430 431 return; 432} 433 434static void 435sf_setmulti(sc) 436 struct sf_softc *sc; 437{ 438 struct ifnet *ifp; 439 int i; 440 struct ifmultiaddr *ifma; 441 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 442 443 ifp = &sc->arpcom.ac_if; 444 445 /* First zot all the existing filters. */ 446 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 447 sf_setperf(sc, i, (char *)&dummy); 448 for (i = SF_RXFILT_HASH_BASE; 449 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 450 csr_write_4(sc, i, 0); 451 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 452 453 /* Now program new ones. */ 454 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 455 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 456 } else { 457 i = 1; 458 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479} 480 481/* 482 * Set media options. 483 */ 484static int 485sf_ifmedia_upd(ifp) 486 struct ifnet *ifp; 487{ 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 sc->sf_link = 0; 494 if (mii->mii_instance) { 495 struct mii_softc *miisc; 496 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 497 mii_phy_reset(miisc); 498 } 499 mii_mediachg(mii); 500 501 return(0); 502} 503 504/* 505 * Report current media status. 506 */ 507static void 508sf_ifmedia_sts(ifp, ifmr) 509 struct ifnet *ifp; 510 struct ifmediareq *ifmr; 511{ 512 struct sf_softc *sc; 513 struct mii_data *mii; 514 515 sc = ifp->if_softc; 516 mii = device_get_softc(sc->sf_miibus); 517 518 mii_pollstat(mii); 519 ifmr->ifm_active = mii->mii_media_active; 520 ifmr->ifm_status = mii->mii_media_status; 521 522 return; 523} 524 525static int 526sf_ioctl(ifp, command, data) 527 struct ifnet *ifp; 528 u_long command; 529 caddr_t data; 530{ 531 struct sf_softc *sc = ifp->if_softc; 532 struct ifreq *ifr = (struct ifreq *) data; 533 struct mii_data *mii; 534 int error = 0; 535 536 SF_LOCK(sc); 537 538 switch(command) { 539 case SIOCSIFFLAGS: 540 if (ifp->if_flags & IFF_UP) { 541 if (ifp->if_flags & IFF_RUNNING && 542 ifp->if_flags & IFF_PROMISC && 543 !(sc->sf_if_flags & IFF_PROMISC)) { 544 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 545 } else if (ifp->if_flags & IFF_RUNNING && 546 !(ifp->if_flags & IFF_PROMISC) && 547 sc->sf_if_flags & IFF_PROMISC) { 548 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 549 } else if (!(ifp->if_flags & IFF_RUNNING)) 550 sf_init(sc); 551 } else { 552 if (ifp->if_flags & IFF_RUNNING) 553 sf_stop(sc); 554 } 555 sc->sf_if_flags = ifp->if_flags; 556 error = 0; 557 break; 558 case SIOCADDMULTI: 559 case SIOCDELMULTI: 560 sf_setmulti(sc); 561 error = 0; 562 break; 563 case SIOCGIFMEDIA: 564 case SIOCSIFMEDIA: 565 mii = device_get_softc(sc->sf_miibus); 566 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 567 break; 568 default: 569 error = ether_ioctl(ifp, command, data); 570 break; 571 } 572 573 SF_UNLOCK(sc); 574 575 return(error); 576} 577 578static void 579sf_reset(sc) 580 struct sf_softc *sc; 581{ 582 register int i; 583 584 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 585 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 586 DELAY(1000); 587 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 588 589 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 590 591 for (i = 0; i < SF_TIMEOUT; i++) { 592 DELAY(10); 593 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 594 break; 595 } 596 597 if (i == SF_TIMEOUT) 598 printf("sf%d: reset never completed!\n", sc->sf_unit); 599 600 /* Wait a little while for the chip to get its brains in order. */ 601 DELAY(1000); 602 return; 603} 604 605/* 606 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 607 * IDs against our list and return a device name if we find a match. 608 * We also check the subsystem ID so that we can identify exactly which 609 * NIC has been found, if possible. 610 */ 611static int 612sf_probe(dev) 613 device_t dev; 614{ 615 struct sf_type *t; 616 617 t = sf_devs; 618 619 while(t->sf_name != NULL) { 620 if ((pci_get_vendor(dev) == t->sf_vid) && 621 (pci_get_device(dev) == t->sf_did)) { 622 switch((pci_read_config(dev, 623 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 624 case AD_SUBSYSID_62011_REV0: 625 case AD_SUBSYSID_62011_REV1: 626 device_set_desc(dev, 627 "Adaptec ANA-62011 10/100BaseTX"); 628 return(0); 629 case AD_SUBSYSID_62022: 630 device_set_desc(dev, 631 "Adaptec ANA-62022 10/100BaseTX"); 632 return(0); 633 case AD_SUBSYSID_62044_REV0: 634 case AD_SUBSYSID_62044_REV1: 635 device_set_desc(dev, 636 "Adaptec ANA-62044 10/100BaseTX"); 637 return(0); 638 case AD_SUBSYSID_62020: 639 device_set_desc(dev, 640 "Adaptec ANA-62020 10/100BaseFX"); 641 return(0); 642 case AD_SUBSYSID_69011: 643 device_set_desc(dev, 644 "Adaptec ANA-69011 10/100BaseTX"); 645 return(0); 646 default: 647 device_set_desc(dev, t->sf_name); 648 return(0); 649 break; 650 } 651 } 652 t++; 653 } 654 655 return(ENXIO); 656} 657 658/* 659 * Attach the interface. Allocate softc structures, do ifmedia 660 * setup and ethernet/BPF attach. 661 */ 662static int 663sf_attach(dev) 664 device_t dev; 665{ 666 int i; 667 struct sf_softc *sc; 668 struct ifnet *ifp; 669 int unit, rid, error = 0; 670 671 sc = device_get_softc(dev); 672 unit = device_get_unit(dev); 673 674 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 675 MTX_DEF | MTX_RECURSE); 676#ifndef BURN_BRIDGES 677 /* 678 * Handle power management nonsense. 679 */ 680 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 681 u_int32_t iobase, membase, irq; 682 683 /* Save important PCI config data. */ 684 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 685 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 686 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 687 688 /* Reset the power state. */ 689 printf("sf%d: chip is in D%d power mode " 690 "-- setting to D0\n", unit, 691 pci_get_powerstate(dev)); 692 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 693 694 /* Restore PCI config data. */ 695 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 696 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 697 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 698 } 699#endif 700 /* 701 * Map control/status registers. 702 */ 703 pci_enable_busmaster(dev); 704 705 rid = SF_RID; 706 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 707 0, ~0, 1, RF_ACTIVE); 708 709 if (sc->sf_res == NULL) { 710 printf ("sf%d: couldn't map ports\n", unit); 711 error = ENXIO; 712 goto fail; 713 } 714 715 sc->sf_btag = rman_get_bustag(sc->sf_res); 716 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 717 718 /* Allocate interrupt */ 719 rid = 0; 720 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 721 RF_SHAREABLE | RF_ACTIVE); 722 723 if (sc->sf_irq == NULL) { 724 printf("sf%d: couldn't map interrupt\n", unit); 725 error = ENXIO; 726 goto fail; 727 } 728 729 callout_handle_init(&sc->sf_stat_ch); 730 /* Reset the adapter. */ 731 sf_reset(sc); 732 733 /* 734 * Get station address from the EEPROM. 735 */ 736 for (i = 0; i < ETHER_ADDR_LEN; i++) 737 sc->arpcom.ac_enaddr[i] = 738 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 739 740 /* 741 * An Adaptec chip was detected. Inform the world. 742 */ 743 printf("sf%d: Ethernet address: %6D\n", unit, 744 sc->arpcom.ac_enaddr, ":"); 745 746 sc->sf_unit = unit; 747 748 /* Allocate the descriptor queues. */ 749 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 750 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 751 752 if (sc->sf_ldata == NULL) { 753 printf("sf%d: no memory for list buffers!\n", unit); 754 error = ENXIO; 755 goto fail; 756 } 757 758 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 759 760 /* Do MII setup. */ 761 if (mii_phy_probe(dev, &sc->sf_miibus, 762 sf_ifmedia_upd, sf_ifmedia_sts)) { 763 printf("sf%d: MII without any phy!\n", sc->sf_unit); 764 error = ENXIO; 765 goto fail; 766 } 767 768 ifp = &sc->arpcom.ac_if; 769 ifp->if_softc = sc; 770 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 771 ifp->if_mtu = ETHERMTU; 772 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 773 ifp->if_ioctl = sf_ioctl; 774 ifp->if_output = ether_output; 775 ifp->if_start = sf_start; 776 ifp->if_watchdog = sf_watchdog; 777 ifp->if_init = sf_init; 778 ifp->if_baudrate = 10000000; 779 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 780 781 /* 782 * Call MI attach routine. 783 */ 784 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 785 786 /* Hook interrupt last to avoid having to lock softc */ 787 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 788 sf_intr, sc, &sc->sf_intrhand); 789 790 if (error) { 791 printf("sf%d: couldn't set up irq\n", unit); 792 ether_ifdetach(ifp); 793 goto fail; 794 } 795 796fail: 797 if (error) 798 sf_detach(dev); 799 800 return(error); 801} 802 803/* 804 * Shutdown hardware and free up resources. This can be called any 805 * time after the mutex has been initialized. It is called in both 806 * the error case in attach and the normal detach case so it needs 807 * to be careful about only freeing resources that have actually been 808 * allocated. 809 */ 810static int 811sf_detach(dev) 812 device_t dev; 813{ 814 struct sf_softc *sc; 815 struct ifnet *ifp; 816 817 sc = device_get_softc(dev); 818 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 819 SF_LOCK(sc); 820 ifp = &sc->arpcom.ac_if; 821 822 /* These should only be active if attach succeeded */ 823 if (device_is_attached(dev)) { 824 sf_stop(sc); 825 ether_ifdetach(ifp); 826 } 827 if (sc->sf_miibus) 828 device_delete_child(dev, sc->sf_miibus); 829 bus_generic_detach(dev); 830 831 if (sc->sf_intrhand) 832 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 833 if (sc->sf_irq) 834 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 835 if (sc->sf_res) 836 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 837 838 if (sc->sf_ldata) 839 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 840 841 SF_UNLOCK(sc); 842 mtx_destroy(&sc->sf_mtx); 843 844 return(0); 845} 846 847static int 848sf_init_rx_ring(sc) 849 struct sf_softc *sc; 850{ 851 struct sf_list_data *ld; 852 int i; 853 854 ld = sc->sf_ldata; 855 856 bzero((char *)ld->sf_rx_dlist_big, 857 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 858 bzero((char *)ld->sf_rx_clist, 859 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 860 861 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 862 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 863 return(ENOBUFS); 864 } 865 866 return(0); 867} 868 869static void 870sf_init_tx_ring(sc) 871 struct sf_softc *sc; 872{ 873 struct sf_list_data *ld; 874 int i; 875 876 ld = sc->sf_ldata; 877 878 bzero((char *)ld->sf_tx_dlist, 879 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 880 bzero((char *)ld->sf_tx_clist, 881 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 882 883 for (i = 0; i < SF_TX_DLIST_CNT; i++) 884 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 885 for (i = 0; i < SF_TX_CLIST_CNT; i++) 886 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 887 888 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 889 sc->sf_tx_cnt = 0; 890 891 return; 892} 893 894static int 895sf_newbuf(sc, c, m) 896 struct sf_softc *sc; 897 struct sf_rx_bufdesc_type0 *c; 898 struct mbuf *m; 899{ 900 struct mbuf *m_new = NULL; 901 902 if (m == NULL) { 903 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 904 if (m_new == NULL) 905 return(ENOBUFS); 906 907 MCLGET(m_new, M_DONTWAIT); 908 if (!(m_new->m_flags & M_EXT)) { 909 m_freem(m_new); 910 return(ENOBUFS); 911 } 912 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 913 } else { 914 m_new = m; 915 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 916 m_new->m_data = m_new->m_ext.ext_buf; 917 } 918 919 m_adj(m_new, sizeof(u_int64_t)); 920 921 c->sf_mbuf = m_new; 922 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 923 c->sf_valid = 1; 924 925 return(0); 926} 927 928/* 929 * The starfire is programmed to use 'normal' mode for packet reception, 930 * which means we use the consumer/producer model for both the buffer 931 * descriptor queue and the completion descriptor queue. The only problem 932 * with this is that it involves a lot of register accesses: we have to 933 * read the RX completion consumer and producer indexes and the RX buffer 934 * producer index, plus the RX completion consumer and RX buffer producer 935 * indexes have to be updated. It would have been easier if Adaptec had 936 * put each index in a separate register, especially given that the damn 937 * NIC has a 512K register space. 938 * 939 * In spite of all the lovely features that Adaptec crammed into the 6915, 940 * it is marred by one truly stupid design flaw, which is that receive 941 * buffer addresses must be aligned on a longword boundary. This forces 942 * the packet payload to be unaligned, which is suboptimal on the x86 and 943 * completely unuseable on the Alpha. Our only recourse is to copy received 944 * packets into properly aligned buffers before handing them off. 945 */ 946 947static void 948sf_rxeof(sc) 949 struct sf_softc *sc; 950{ 951 struct mbuf *m; 952 struct ifnet *ifp; 953 struct sf_rx_bufdesc_type0 *desc; 954 struct sf_rx_cmpdesc_type3 *cur_rx; 955 u_int32_t rxcons, rxprod; 956 int cmpprodidx, cmpconsidx, bufprodidx; 957 958 ifp = &sc->arpcom.ac_if; 959 960 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 961 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 962 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 963 cmpconsidx = SF_IDX_LO(rxcons); 964 bufprodidx = SF_IDX_LO(rxprod); 965 966 while (cmpconsidx != cmpprodidx) { 967 struct mbuf *m0; 968 969 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 970 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 971 m = desc->sf_mbuf; 972 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 973 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 974 975 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 976 ifp->if_ierrors++; 977 sf_newbuf(sc, desc, m); 978 continue; 979 } 980 981 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 982 ifp, NULL); 983 sf_newbuf(sc, desc, m); 984 if (m0 == NULL) { 985 ifp->if_ierrors++; 986 continue; 987 } 988 m = m0; 989 990 ifp->if_ipackets++; 991 (*ifp->if_input)(ifp, m); 992 } 993 994 csr_write_4(sc, SF_CQ_CONSIDX, 995 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 996 csr_write_4(sc, SF_RXDQ_PTR_Q1, 997 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 998 999 return; 1000} 1001 1002/* 1003 * Read the transmit status from the completion queue and release 1004 * mbufs. Note that the buffer descriptor index in the completion 1005 * descriptor is an offset from the start of the transmit buffer 1006 * descriptor list in bytes. This is important because the manual 1007 * gives the impression that it should match the producer/consumer 1008 * index, which is the offset in 8 byte blocks. 1009 */ 1010static void 1011sf_txeof(sc) 1012 struct sf_softc *sc; 1013{ 1014 int txcons, cmpprodidx, cmpconsidx; 1015 struct sf_tx_cmpdesc_type1 *cur_cmp; 1016 struct sf_tx_bufdesc_type0 *cur_tx; 1017 struct ifnet *ifp; 1018 1019 ifp = &sc->arpcom.ac_if; 1020 1021 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1022 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1023 cmpconsidx = SF_IDX_HI(txcons); 1024 1025 while (cmpconsidx != cmpprodidx) { 1026 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1027 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1028 1029 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1030 ifp->if_opackets++; 1031 else { 1032 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1033 sf_txthresh_adjust(sc); 1034 ifp->if_oerrors++; 1035 } 1036 1037 sc->sf_tx_cnt--; 1038 if (cur_tx->sf_mbuf != NULL) { 1039 m_freem(cur_tx->sf_mbuf); 1040 cur_tx->sf_mbuf = NULL; 1041 } else 1042 break; 1043 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1044 } 1045 1046 ifp->if_timer = 0; 1047 ifp->if_flags &= ~IFF_OACTIVE; 1048 1049 csr_write_4(sc, SF_CQ_CONSIDX, 1050 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1051 ((cmpconsidx << 16) & 0xFFFF0000)); 1052 1053 return; 1054} 1055 1056static void 1057sf_txthresh_adjust(sc) 1058 struct sf_softc *sc; 1059{ 1060 u_int32_t txfctl; 1061 u_int8_t txthresh; 1062 1063 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1064 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1065 if (txthresh < 0xFF) { 1066 txthresh++; 1067 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1068 txfctl |= txthresh; 1069#ifdef DIAGNOSTIC 1070 printf("sf%d: tx underrun, increasing " 1071 "tx threshold to %d bytes\n", 1072 sc->sf_unit, txthresh * 4); 1073#endif 1074 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1075 } 1076 1077 return; 1078} 1079 1080static void 1081sf_intr(arg) 1082 void *arg; 1083{ 1084 struct sf_softc *sc; 1085 struct ifnet *ifp; 1086 u_int32_t status; 1087 1088 sc = arg; 1089 SF_LOCK(sc); 1090 1091 ifp = &sc->arpcom.ac_if; 1092 1093 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1094 SF_UNLOCK(sc); 1095 return; 1096 } 1097 1098 /* Disable interrupts. */ 1099 csr_write_4(sc, SF_IMR, 0x00000000); 1100 1101 for (;;) { 1102 status = csr_read_4(sc, SF_ISR); 1103 if (status) 1104 csr_write_4(sc, SF_ISR, status); 1105 1106 if (!(status & SF_INTRS)) 1107 break; 1108 1109 if (status & SF_ISR_RXDQ1_DMADONE) 1110 sf_rxeof(sc); 1111 1112 if (status & SF_ISR_TX_TXDONE || 1113 status & SF_ISR_TX_DMADONE || 1114 status & SF_ISR_TX_QUEUEDONE) 1115 sf_txeof(sc); 1116 1117 if (status & SF_ISR_TX_LOFIFO) 1118 sf_txthresh_adjust(sc); 1119 1120 if (status & SF_ISR_ABNORMALINTR) { 1121 if (status & SF_ISR_STATSOFLOW) { 1122 untimeout(sf_stats_update, sc, 1123 sc->sf_stat_ch); 1124 sf_stats_update(sc); 1125 } else 1126 sf_init(sc); 1127 } 1128 } 1129 1130 /* Re-enable interrupts. */ 1131 csr_write_4(sc, SF_IMR, SF_INTRS); 1132 1133 if (ifp->if_snd.ifq_head != NULL) 1134 sf_start(ifp); 1135 1136 SF_UNLOCK(sc); 1137 return; 1138} 1139 1140static void 1141sf_init(xsc) 1142 void *xsc; 1143{ 1144 struct sf_softc *sc; 1145 struct ifnet *ifp; 1146 struct mii_data *mii; 1147 int i; 1148 1149 sc = xsc; 1150 SF_LOCK(sc); 1151 ifp = &sc->arpcom.ac_if; 1152 mii = device_get_softc(sc->sf_miibus); 1153 1154 sf_stop(sc); 1155 sf_reset(sc); 1156 1157 /* Init all the receive filter registers */ 1158 for (i = SF_RXFILT_PERFECT_BASE; 1159 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1160 csr_write_4(sc, i, 0); 1161 1162 /* Empty stats counter registers. */ 1163 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1164 csr_write_4(sc, SF_STATS_BASE + 1165 (i + sizeof(u_int32_t)), 0); 1166 1167 /* Init our MAC address */ 1168 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1169 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1170 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1171 1172 if (sf_init_rx_ring(sc) == ENOBUFS) { 1173 printf("sf%d: initialization failed: no " 1174 "memory for rx buffers\n", sc->sf_unit); 1175 SF_UNLOCK(sc); 1176 return; 1177 } 1178 1179 sf_init_tx_ring(sc); 1180 1181 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1182 1183 /* If we want promiscuous mode, set the allframes bit. */ 1184 if (ifp->if_flags & IFF_PROMISC) { 1185 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1186 } else { 1187 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1188 } 1189 1190 if (ifp->if_flags & IFF_BROADCAST) { 1191 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1192 } else { 1193 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1194 } 1195 1196 /* 1197 * Load the multicast filter. 1198 */ 1199 sf_setmulti(sc); 1200 1201 /* Init the completion queue indexes */ 1202 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1203 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1204 1205 /* Init the RX completion queue */ 1206 csr_write_4(sc, SF_RXCQ_CTL_1, 1207 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1208 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1209 1210 /* Init RX DMA control. */ 1211 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1212 1213 /* Init the RX buffer descriptor queue. */ 1214 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1215 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1216 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1217 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1218 1219 /* Init the TX completion queue */ 1220 csr_write_4(sc, SF_TXCQ_CTL, 1221 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1222 1223 /* Init the TX buffer descriptor queue. */ 1224 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1225 vtophys(sc->sf_ldata->sf_tx_dlist)); 1226 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1227 csr_write_4(sc, SF_TXDQ_CTL, 1228 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1229 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1230 1231 /* Enable autopadding of short TX frames. */ 1232 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1233 1234 /* Enable interrupts. */ 1235 csr_write_4(sc, SF_IMR, SF_INTRS); 1236 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1237 1238 /* Enable the RX and TX engines. */ 1239 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1240 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1241 1242 /*mii_mediachg(mii);*/ 1243 sf_ifmedia_upd(ifp); 1244 1245 ifp->if_flags |= IFF_RUNNING; 1246 ifp->if_flags &= ~IFF_OACTIVE; 1247 1248 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1249 1250 SF_UNLOCK(sc); 1251 1252 return; 1253} 1254 1255static int 1256sf_encap(sc, c, m_head) 1257 struct sf_softc *sc; 1258 struct sf_tx_bufdesc_type0 *c; 1259 struct mbuf *m_head; 1260{ 1261 int frag = 0; 1262 struct sf_frag *f = NULL; 1263 struct mbuf *m; 1264 1265 m = m_head; 1266 1267 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1268 if (m->m_len != 0) { 1269 if (frag == SF_MAXFRAGS) 1270 break; 1271 f = &c->sf_frags[frag]; 1272 if (frag == 0) 1273 f->sf_pktlen = m_head->m_pkthdr.len; 1274 f->sf_fraglen = m->m_len; 1275 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1276 frag++; 1277 } 1278 } 1279 1280 if (m != NULL) { 1281 struct mbuf *m_new = NULL; 1282 1283 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1284 if (m_new == NULL) { 1285 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1286 return(1); 1287 } 1288 1289 if (m_head->m_pkthdr.len > MHLEN) { 1290 MCLGET(m_new, M_DONTWAIT); 1291 if (!(m_new->m_flags & M_EXT)) { 1292 m_freem(m_new); 1293 printf("sf%d: no memory for tx list\n", 1294 sc->sf_unit); 1295 return(1); 1296 } 1297 } 1298 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1299 mtod(m_new, caddr_t)); 1300 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1301 m_freem(m_head); 1302 m_head = m_new; 1303 f = &c->sf_frags[0]; 1304 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1305 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1306 frag = 1; 1307 } 1308 1309 c->sf_mbuf = m_head; 1310 c->sf_id = SF_TX_BUFDESC_ID; 1311 c->sf_fragcnt = frag; 1312 c->sf_intr = 1; 1313 c->sf_caltcp = 0; 1314 c->sf_crcen = 1; 1315 1316 return(0); 1317} 1318 1319static void 1320sf_start(ifp) 1321 struct ifnet *ifp; 1322{ 1323 struct sf_softc *sc; 1324 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1325 struct mbuf *m_head = NULL; 1326 int i, txprod; 1327 1328 sc = ifp->if_softc; 1329 SF_LOCK(sc); 1330 1331 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1332 SF_UNLOCK(sc); 1333 return; 1334 } 1335 1336 if (ifp->if_flags & IFF_OACTIVE) { 1337 SF_UNLOCK(sc); 1338 return; 1339 } 1340 1341 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1342 i = SF_IDX_HI(txprod) >> 4; 1343 1344 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1345 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1346 sf_init(sc); 1347 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1348 i = SF_IDX_HI(txprod) >> 4; 1349 } 1350 1351 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1352 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1353 ifp->if_flags |= IFF_OACTIVE; 1354 cur_tx = NULL; 1355 break; 1356 } 1357 IF_DEQUEUE(&ifp->if_snd, m_head); 1358 if (m_head == NULL) 1359 break; 1360 1361 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1362 if (sf_encap(sc, cur_tx, m_head)) { 1363 IF_PREPEND(&ifp->if_snd, m_head); 1364 ifp->if_flags |= IFF_OACTIVE; 1365 cur_tx = NULL; 1366 break; 1367 } 1368 1369 /* 1370 * If there's a BPF listener, bounce a copy of this frame 1371 * to him. 1372 */ 1373 BPF_MTAP(ifp, m_head); 1374 1375 SF_INC(i, SF_TX_DLIST_CNT); 1376 sc->sf_tx_cnt++; 1377 /* 1378 * Don't get the TX DMA queue get too full. 1379 */ 1380 if (sc->sf_tx_cnt > 64) 1381 break; 1382 } 1383 1384 if (cur_tx == NULL) { 1385 SF_UNLOCK(sc); 1386 return; 1387 } 1388 1389 /* Transmit */ 1390 csr_write_4(sc, SF_TXDQ_PRODIDX, 1391 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1392 ((i << 20) & 0xFFFF0000)); 1393 1394 ifp->if_timer = 5; 1395 1396 SF_UNLOCK(sc); 1397 1398 return; 1399} 1400 1401static void 1402sf_stop(sc) 1403 struct sf_softc *sc; 1404{ 1405 int i; 1406 struct ifnet *ifp; 1407 1408 SF_LOCK(sc); 1409 1410 ifp = &sc->arpcom.ac_if; 1411 1412 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1413 1414 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1415 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1416 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1417 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1418 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1419 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1420 csr_write_4(sc, SF_TXCQ_CTL, 0); 1421 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1422 csr_write_4(sc, SF_TXDQ_CTL, 0); 1423 sf_reset(sc); 1424 1425 sc->sf_link = 0; 1426 1427 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1428 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1429 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1430 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1431 } 1432 } 1433 1434 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1435 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1436 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1437 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1438 } 1439 } 1440 1441 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1442 SF_UNLOCK(sc); 1443 1444 return; 1445} 1446 1447/* 1448 * Note: it is important that this function not be interrupted. We 1449 * use a two-stage register access scheme: if we are interrupted in 1450 * between setting the indirect address register and reading from the 1451 * indirect data register, the contents of the address register could 1452 * be changed out from under us. 1453 */ 1454static void 1455sf_stats_update(xsc) 1456 void *xsc; 1457{ 1458 struct sf_softc *sc; 1459 struct ifnet *ifp; 1460 struct mii_data *mii; 1461 struct sf_stats stats; 1462 u_int32_t *ptr; 1463 int i; 1464 1465 sc = xsc; 1466 SF_LOCK(sc); 1467 ifp = &sc->arpcom.ac_if; 1468 mii = device_get_softc(sc->sf_miibus); 1469 1470 ptr = (u_int32_t *)&stats; 1471 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1472 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1473 (i + sizeof(u_int32_t))); 1474 1475 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1476 csr_write_4(sc, SF_STATS_BASE + 1477 (i + sizeof(u_int32_t)), 0); 1478 1479 ifp->if_collisions += stats.sf_tx_single_colls + 1480 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1481 1482 mii_tick(mii); 1483 1484 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1485 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1486 sc->sf_link++; 1487 if (ifp->if_snd.ifq_head != NULL) 1488 sf_start(ifp); 1489 } 1490 1491 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1492 1493 SF_UNLOCK(sc); 1494 1495 return; 1496} 1497 1498static void 1499sf_watchdog(ifp) 1500 struct ifnet *ifp; 1501{ 1502 struct sf_softc *sc; 1503 1504 sc = ifp->if_softc; 1505 1506 SF_LOCK(sc); 1507 1508 ifp->if_oerrors++; 1509 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1510 1511 sf_stop(sc); 1512 sf_reset(sc); 1513 sf_init(sc); 1514 1515 if (ifp->if_snd.ifq_head != NULL) 1516 sf_start(ifp); 1517 1518 SF_UNLOCK(sc); 1519 1520 return; 1521} 1522 1523static void 1524sf_shutdown(dev) 1525 device_t dev; 1526{ 1527 struct sf_softc *sc; 1528 1529 sc = device_get_softc(dev); 1530 1531 sf_stop(sc); 1532 1533 return; 1534} 1535