if_sf.c revision 122625
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 35 * Programming manual is available from: 36 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Department of Electical Engineering 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 45 * controller designed with flexibility and reducing CPU load in mind. 46 * The Starfire offers high and low priority buffer queues, a 47 * producer/consumer index mechanism and several different buffer 48 * queue and completion queue descriptor types. Any one of a number 49 * of different driver designs can be used, depending on system and 50 * OS requirements. This driver makes use of type0 transmit frame 51 * descriptors (since BSD fragments packets across an mbuf chain) 52 * and two RX buffer queues prioritized on size (one queue for small 53 * frames that will fit into a single mbuf, another with full size 54 * mbuf clusters for everything else). The producer/consumer indexes 55 * and completion queues are also used. 56 * 57 * One downside to the Starfire has to do with alignment: buffer 58 * queues must be aligned on 256-byte boundaries, and receive buffers 59 * must be aligned on longword boundaries. The receive buffer alignment 60 * causes problems on the Alpha platform, where the packet payload 61 * should be longword aligned. There is no simple way around this. 62 * 63 * For receive filtering, the Starfire offers 16 perfect filter slots 64 * and a 512-bit hash table. 65 * 66 * The Starfire has no internal transceiver, relying instead on an 67 * external MII-based transceiver. Accessing registers on external 68 * PHYs is done through a special register map rather than with the 69 * usual bitbang MDIO method. 70 * 71 * Acesssing the registers on the Starfire is a little tricky. The 72 * Starfire has a 512K internal register space. When programmed for 73 * PCI memory mapped mode, the entire register space can be accessed 74 * directly. However in I/O space mode, only 256 bytes are directly 75 * mapped into PCI I/O space. The other registers can be accessed 76 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 77 * registers inside the 256-byte I/O window. 78 */ 79 80#include <sys/cdefs.h> 81__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 122625 2003-11-13 20:55:53Z obrien $"); 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, pci, 1, 1, 1); 122MODULE_DEPEND(sf, ether, 1, 1, 1); 123MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe (device_t); 132static int sf_attach (device_t); 133static int sf_detach (device_t); 134static void sf_intr (void *); 135static void sf_stats_update (void *); 136static void sf_rxeof (struct sf_softc *); 137static void sf_txeof (struct sf_softc *); 138static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141static void sf_start (struct ifnet *); 142static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143static void sf_init (void *); 144static void sf_stop (struct sf_softc *); 145static void sf_watchdog (struct ifnet *); 146static void sf_shutdown (device_t); 147static int sf_ifmedia_upd (struct ifnet *); 148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149static void sf_reset (struct sf_softc *); 150static int sf_init_rx_ring (struct sf_softc *); 151static void sf_init_tx_ring (struct sf_softc *); 152static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti (struct sf_softc *); 156static int sf_setperf (struct sf_softc *, int, caddr_t); 157static int sf_sethash (struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163static u_int32_t sf_mchash (caddr_t); 164 165static int sf_miibus_readreg (device_t, int, int); 166static int sf_miibus_writereg (device_t, int, int, int); 167static void sf_miibus_statchg (device_t); 168 169static u_int32_t csr_read_4 (struct sf_softc *, int); 170static void csr_write_4 (struct sf_softc *, int, u_int32_t); 171static void sf_txthresh_adjust (struct sf_softc *); 172 173#ifdef SF_USEIOSPACE 174#define SF_RES SYS_RES_IOPORT 175#define SF_RID SF_PCI_LOIO 176#else 177#define SF_RES SYS_RES_MEMORY 178#define SF_RID SF_PCI_LOMEM 179#endif 180 181static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198}; 199 200static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204}; 205 206static devclass_t sf_devclass; 207 208DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 209DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211#define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 213 214#define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 216 217static u_int32_t 218csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221{ 222 u_int32_t val; 223 224#ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227#else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229#endif 230 231 return(val); 232} 233 234static u_int8_t 235sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void 248csr_write_4(sc, reg, val) 249 struct sf_softc *sc; 250 int reg; 251 u_int32_t val; 252{ 253#ifdef SF_USEIOSPACE 254 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 255 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 256#else 257 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 258#endif 259 return; 260} 261 262static u_int32_t 263sf_mchash(addr) 264 caddr_t addr; 265{ 266 u_int32_t crc, carry; 267 int idx, bit; 268 u_int8_t data; 269 270 /* Compute CRC for the address value. */ 271 crc = 0xFFFFFFFF; /* initial value */ 272 273 for (idx = 0; idx < 6; idx++) { 274 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 275 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 276 crc <<= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int 292sf_setperf(sc, idx, mac) 293 struct sf_softc *sc; 294 int idx; 295 caddr_t mac; 296{ 297 u_int16_t *p; 298 299 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 300 return(EINVAL); 301 302 if (mac == NULL) 303 return(EINVAL); 304 305 p = (u_int16_t *)mac; 306 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 313 314 return(0); 315} 316 317/* 318 * Set the bit in the 512-bit hash table that corresponds to the 319 * specified mac address 'mac.' If 'prio' is nonzero, update the 320 * priority hash table instead of the filter hash table. 321 */ 322static int 323sf_sethash(sc, mac, prio) 324 struct sf_softc *sc; 325 caddr_t mac; 326 int prio; 327{ 328 u_int32_t h = 0; 329 330 if (mac == NULL) 331 return(EINVAL); 332 333 h = sf_mchash(mac); 334 335 if (prio) { 336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 338 } else { 339 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 340 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 341 } 342 343 return(0); 344} 345 346#ifdef notdef 347/* 348 * Set a VLAN tag in the receive filter. 349 */ 350static int 351sf_setvlan(sc, idx, vlan) 352 struct sf_softc *sc; 353 int idx; 354 u_int32_t vlan; 355{ 356 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 357 return(EINVAL); 358 359 csr_write_4(sc, SF_RXFILT_HASH_BASE + 360 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 361 362 return(0); 363} 364#endif 365 366static int 367sf_miibus_readreg(dev, phy, reg) 368 device_t dev; 369 int phy, reg; 370{ 371 struct sf_softc *sc; 372 int i; 373 u_int32_t val = 0; 374 375 sc = device_get_softc(dev); 376 377 for (i = 0; i < SF_TIMEOUT; i++) { 378 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 379 if (val & SF_MII_DATAVALID) 380 break; 381 } 382 383 if (i == SF_TIMEOUT) 384 return(0); 385 386 if ((val & 0x0000FFFF) == 0xFFFF) 387 return(0); 388 389 return(val & 0x0000FFFF); 390} 391 392static int 393sf_miibus_writereg(dev, phy, reg, val) 394 device_t dev; 395 int phy, reg, val; 396{ 397 struct sf_softc *sc; 398 int i; 399 int busy; 400 401 sc = device_get_softc(dev); 402 403 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 404 405 for (i = 0; i < SF_TIMEOUT; i++) { 406 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 407 if (!(busy & SF_MII_BUSY)) 408 break; 409 } 410 411 return(0); 412} 413 414static void 415sf_miibus_statchg(dev) 416 device_t dev; 417{ 418 struct sf_softc *sc; 419 struct mii_data *mii; 420 421 sc = device_get_softc(dev); 422 mii = device_get_softc(sc->sf_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 426 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 427 } else { 428 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 429 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 430 } 431 432 return; 433} 434 435static void 436sf_setmulti(sc) 437 struct sf_softc *sc; 438{ 439 struct ifnet *ifp; 440 int i; 441 struct ifmultiaddr *ifma; 442 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 443 444 ifp = &sc->arpcom.ac_if; 445 446 /* First zot all the existing filters. */ 447 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 448 sf_setperf(sc, i, (char *)&dummy); 449 for (i = SF_RXFILT_HASH_BASE; 450 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 451 csr_write_4(sc, i, 0); 452 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 453 454 /* Now program new ones. */ 455 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 456 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 457 } else { 458 i = 1; 459 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 460 if (ifma->ifma_addr->sa_family != AF_LINK) 461 continue; 462 /* 463 * Program the first 15 multicast groups 464 * into the perfect filter. For all others, 465 * use the hash table. 466 */ 467 if (i < SF_RXFILT_PERFECT_CNT) { 468 sf_setperf(sc, i, 469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 470 i++; 471 continue; 472 } 473 474 sf_sethash(sc, 475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 476 } 477 } 478 479 return; 480} 481 482/* 483 * Set media options. 484 */ 485static int 486sf_ifmedia_upd(ifp) 487 struct ifnet *ifp; 488{ 489 struct sf_softc *sc; 490 struct mii_data *mii; 491 492 sc = ifp->if_softc; 493 mii = device_get_softc(sc->sf_miibus); 494 sc->sf_link = 0; 495 if (mii->mii_instance) { 496 struct mii_softc *miisc; 497 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 498 mii_phy_reset(miisc); 499 } 500 mii_mediachg(mii); 501 502 return(0); 503} 504 505/* 506 * Report current media status. 507 */ 508static void 509sf_ifmedia_sts(ifp, ifmr) 510 struct ifnet *ifp; 511 struct ifmediareq *ifmr; 512{ 513 struct sf_softc *sc; 514 struct mii_data *mii; 515 516 sc = ifp->if_softc; 517 mii = device_get_softc(sc->sf_miibus); 518 519 mii_pollstat(mii); 520 ifmr->ifm_active = mii->mii_media_active; 521 ifmr->ifm_status = mii->mii_media_status; 522 523 return; 524} 525 526static int 527sf_ioctl(ifp, command, data) 528 struct ifnet *ifp; 529 u_long command; 530 caddr_t data; 531{ 532 struct sf_softc *sc = ifp->if_softc; 533 struct ifreq *ifr = (struct ifreq *) data; 534 struct mii_data *mii; 535 int error = 0; 536 537 SF_LOCK(sc); 538 539 switch(command) { 540 case SIOCSIFFLAGS: 541 if (ifp->if_flags & IFF_UP) { 542 if (ifp->if_flags & IFF_RUNNING && 543 ifp->if_flags & IFF_PROMISC && 544 !(sc->sf_if_flags & IFF_PROMISC)) { 545 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 546 } else if (ifp->if_flags & IFF_RUNNING && 547 !(ifp->if_flags & IFF_PROMISC) && 548 sc->sf_if_flags & IFF_PROMISC) { 549 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 550 } else if (!(ifp->if_flags & IFF_RUNNING)) 551 sf_init(sc); 552 } else { 553 if (ifp->if_flags & IFF_RUNNING) 554 sf_stop(sc); 555 } 556 sc->sf_if_flags = ifp->if_flags; 557 error = 0; 558 break; 559 case SIOCADDMULTI: 560 case SIOCDELMULTI: 561 sf_setmulti(sc); 562 error = 0; 563 break; 564 case SIOCGIFMEDIA: 565 case SIOCSIFMEDIA: 566 mii = device_get_softc(sc->sf_miibus); 567 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 568 break; 569 default: 570 error = ether_ioctl(ifp, command, data); 571 break; 572 } 573 574 SF_UNLOCK(sc); 575 576 return(error); 577} 578 579static void 580sf_reset(sc) 581 struct sf_softc *sc; 582{ 583 register int i; 584 585 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 586 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 587 DELAY(1000); 588 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 590 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 591 592 for (i = 0; i < SF_TIMEOUT; i++) { 593 DELAY(10); 594 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 595 break; 596 } 597 598 if (i == SF_TIMEOUT) 599 printf("sf%d: reset never completed!\n", sc->sf_unit); 600 601 /* Wait a little while for the chip to get its brains in order. */ 602 DELAY(1000); 603 return; 604} 605 606/* 607 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 608 * IDs against our list and return a device name if we find a match. 609 * We also check the subsystem ID so that we can identify exactly which 610 * NIC has been found, if possible. 611 */ 612static int 613sf_probe(dev) 614 device_t dev; 615{ 616 struct sf_type *t; 617 618 t = sf_devs; 619 620 while(t->sf_name != NULL) { 621 if ((pci_get_vendor(dev) == t->sf_vid) && 622 (pci_get_device(dev) == t->sf_did)) { 623 switch((pci_read_config(dev, 624 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 625 case AD_SUBSYSID_62011_REV0: 626 case AD_SUBSYSID_62011_REV1: 627 device_set_desc(dev, 628 "Adaptec ANA-62011 10/100BaseTX"); 629 return(0); 630 case AD_SUBSYSID_62022: 631 device_set_desc(dev, 632 "Adaptec ANA-62022 10/100BaseTX"); 633 return(0); 634 case AD_SUBSYSID_62044_REV0: 635 case AD_SUBSYSID_62044_REV1: 636 device_set_desc(dev, 637 "Adaptec ANA-62044 10/100BaseTX"); 638 return(0); 639 case AD_SUBSYSID_62020: 640 device_set_desc(dev, 641 "Adaptec ANA-62020 10/100BaseFX"); 642 return(0); 643 case AD_SUBSYSID_69011: 644 device_set_desc(dev, 645 "Adaptec ANA-69011 10/100BaseTX"); 646 return(0); 647 default: 648 device_set_desc(dev, t->sf_name); 649 return(0); 650 break; 651 } 652 } 653 t++; 654 } 655 656 return(ENXIO); 657} 658 659/* 660 * Attach the interface. Allocate softc structures, do ifmedia 661 * setup and ethernet/BPF attach. 662 */ 663static int 664sf_attach(dev) 665 device_t dev; 666{ 667 int i; 668 struct sf_softc *sc; 669 struct ifnet *ifp; 670 int unit, rid, error = 0; 671 672 sc = device_get_softc(dev); 673 unit = device_get_unit(dev); 674 675 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 676 MTX_DEF | MTX_RECURSE); 677#ifndef BURN_BRIDGES 678 /* 679 * Handle power management nonsense. 680 */ 681 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 682 u_int32_t iobase, membase, irq; 683 684 /* Save important PCI config data. */ 685 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 686 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 687 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 688 689 /* Reset the power state. */ 690 printf("sf%d: chip is in D%d power mode " 691 "-- setting to D0\n", unit, 692 pci_get_powerstate(dev)); 693 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 694 695 /* Restore PCI config data. */ 696 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 697 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 698 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 699 } 700#endif 701 /* 702 * Map control/status registers. 703 */ 704 pci_enable_busmaster(dev); 705 706 rid = SF_RID; 707 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 708 0, ~0, 1, RF_ACTIVE); 709 710 if (sc->sf_res == NULL) { 711 printf ("sf%d: couldn't map ports\n", unit); 712 error = ENXIO; 713 goto fail; 714 } 715 716 sc->sf_btag = rman_get_bustag(sc->sf_res); 717 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 718 719 /* Allocate interrupt */ 720 rid = 0; 721 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 722 RF_SHAREABLE | RF_ACTIVE); 723 724 if (sc->sf_irq == NULL) { 725 printf("sf%d: couldn't map interrupt\n", unit); 726 error = ENXIO; 727 goto fail; 728 } 729 730 callout_handle_init(&sc->sf_stat_ch); 731 /* Reset the adapter. */ 732 sf_reset(sc); 733 734 /* 735 * Get station address from the EEPROM. 736 */ 737 for (i = 0; i < ETHER_ADDR_LEN; i++) 738 sc->arpcom.ac_enaddr[i] = 739 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 740 741 /* 742 * An Adaptec chip was detected. Inform the world. 743 */ 744 printf("sf%d: Ethernet address: %6D\n", unit, 745 sc->arpcom.ac_enaddr, ":"); 746 747 sc->sf_unit = unit; 748 749 /* Allocate the descriptor queues. */ 750 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 751 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 752 753 if (sc->sf_ldata == NULL) { 754 printf("sf%d: no memory for list buffers!\n", unit); 755 error = ENXIO; 756 goto fail; 757 } 758 759 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 760 761 /* Do MII setup. */ 762 if (mii_phy_probe(dev, &sc->sf_miibus, 763 sf_ifmedia_upd, sf_ifmedia_sts)) { 764 printf("sf%d: MII without any phy!\n", sc->sf_unit); 765 error = ENXIO; 766 goto fail; 767 } 768 769 ifp = &sc->arpcom.ac_if; 770 ifp->if_softc = sc; 771 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 772 ifp->if_mtu = ETHERMTU; 773 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 774 ifp->if_ioctl = sf_ioctl; 775 ifp->if_output = ether_output; 776 ifp->if_start = sf_start; 777 ifp->if_watchdog = sf_watchdog; 778 ifp->if_init = sf_init; 779 ifp->if_baudrate = 10000000; 780 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 781 782 /* 783 * Call MI attach routine. 784 */ 785 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 786 787 /* Hook interrupt last to avoid having to lock softc */ 788 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 789 sf_intr, sc, &sc->sf_intrhand); 790 791 if (error) { 792 printf("sf%d: couldn't set up irq\n", unit); 793 ether_ifdetach(ifp); 794 goto fail; 795 } 796 797fail: 798 if (error) 799 sf_detach(dev); 800 801 return(error); 802} 803 804/* 805 * Shutdown hardware and free up resources. This can be called any 806 * time after the mutex has been initialized. It is called in both 807 * the error case in attach and the normal detach case so it needs 808 * to be careful about only freeing resources that have actually been 809 * allocated. 810 */ 811static int 812sf_detach(dev) 813 device_t dev; 814{ 815 struct sf_softc *sc; 816 struct ifnet *ifp; 817 818 sc = device_get_softc(dev); 819 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 820 SF_LOCK(sc); 821 ifp = &sc->arpcom.ac_if; 822 823 /* These should only be active if attach succeeded */ 824 if (device_is_attached(dev)) { 825 sf_stop(sc); 826 ether_ifdetach(ifp); 827 } 828 if (sc->sf_miibus) 829 device_delete_child(dev, sc->sf_miibus); 830 bus_generic_detach(dev); 831 832 if (sc->sf_intrhand) 833 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 834 if (sc->sf_irq) 835 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 836 if (sc->sf_res) 837 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 838 839 if (sc->sf_ldata) 840 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 841 842 SF_UNLOCK(sc); 843 mtx_destroy(&sc->sf_mtx); 844 845 return(0); 846} 847 848static int 849sf_init_rx_ring(sc) 850 struct sf_softc *sc; 851{ 852 struct sf_list_data *ld; 853 int i; 854 855 ld = sc->sf_ldata; 856 857 bzero((char *)ld->sf_rx_dlist_big, 858 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 859 bzero((char *)ld->sf_rx_clist, 860 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 861 862 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 863 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 864 return(ENOBUFS); 865 } 866 867 return(0); 868} 869 870static void 871sf_init_tx_ring(sc) 872 struct sf_softc *sc; 873{ 874 struct sf_list_data *ld; 875 int i; 876 877 ld = sc->sf_ldata; 878 879 bzero((char *)ld->sf_tx_dlist, 880 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 881 bzero((char *)ld->sf_tx_clist, 882 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 883 884 for (i = 0; i < SF_TX_DLIST_CNT; i++) 885 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 886 for (i = 0; i < SF_TX_CLIST_CNT; i++) 887 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 888 889 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 890 sc->sf_tx_cnt = 0; 891 892 return; 893} 894 895static int 896sf_newbuf(sc, c, m) 897 struct sf_softc *sc; 898 struct sf_rx_bufdesc_type0 *c; 899 struct mbuf *m; 900{ 901 struct mbuf *m_new = NULL; 902 903 if (m == NULL) { 904 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 905 if (m_new == NULL) 906 return(ENOBUFS); 907 908 MCLGET(m_new, M_DONTWAIT); 909 if (!(m_new->m_flags & M_EXT)) { 910 m_freem(m_new); 911 return(ENOBUFS); 912 } 913 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 914 } else { 915 m_new = m; 916 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 917 m_new->m_data = m_new->m_ext.ext_buf; 918 } 919 920 m_adj(m_new, sizeof(u_int64_t)); 921 922 c->sf_mbuf = m_new; 923 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 924 c->sf_valid = 1; 925 926 return(0); 927} 928 929/* 930 * The starfire is programmed to use 'normal' mode for packet reception, 931 * which means we use the consumer/producer model for both the buffer 932 * descriptor queue and the completion descriptor queue. The only problem 933 * with this is that it involves a lot of register accesses: we have to 934 * read the RX completion consumer and producer indexes and the RX buffer 935 * producer index, plus the RX completion consumer and RX buffer producer 936 * indexes have to be updated. It would have been easier if Adaptec had 937 * put each index in a separate register, especially given that the damn 938 * NIC has a 512K register space. 939 * 940 * In spite of all the lovely features that Adaptec crammed into the 6915, 941 * it is marred by one truly stupid design flaw, which is that receive 942 * buffer addresses must be aligned on a longword boundary. This forces 943 * the packet payload to be unaligned, which is suboptimal on the x86 and 944 * completely unuseable on the Alpha. Our only recourse is to copy received 945 * packets into properly aligned buffers before handing them off. 946 */ 947 948static void 949sf_rxeof(sc) 950 struct sf_softc *sc; 951{ 952 struct mbuf *m; 953 struct ifnet *ifp; 954 struct sf_rx_bufdesc_type0 *desc; 955 struct sf_rx_cmpdesc_type3 *cur_rx; 956 u_int32_t rxcons, rxprod; 957 int cmpprodidx, cmpconsidx, bufprodidx; 958 959 ifp = &sc->arpcom.ac_if; 960 961 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 962 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 963 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 964 cmpconsidx = SF_IDX_LO(rxcons); 965 bufprodidx = SF_IDX_LO(rxprod); 966 967 while (cmpconsidx != cmpprodidx) { 968 struct mbuf *m0; 969 970 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 971 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 972 m = desc->sf_mbuf; 973 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 974 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 975 976 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 977 ifp->if_ierrors++; 978 sf_newbuf(sc, desc, m); 979 continue; 980 } 981 982 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 983 ifp, NULL); 984 sf_newbuf(sc, desc, m); 985 if (m0 == NULL) { 986 ifp->if_ierrors++; 987 continue; 988 } 989 m = m0; 990 991 ifp->if_ipackets++; 992 (*ifp->if_input)(ifp, m); 993 } 994 995 csr_write_4(sc, SF_CQ_CONSIDX, 996 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 997 csr_write_4(sc, SF_RXDQ_PTR_Q1, 998 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 999 1000 return; 1001} 1002 1003/* 1004 * Read the transmit status from the completion queue and release 1005 * mbufs. Note that the buffer descriptor index in the completion 1006 * descriptor is an offset from the start of the transmit buffer 1007 * descriptor list in bytes. This is important because the manual 1008 * gives the impression that it should match the producer/consumer 1009 * index, which is the offset in 8 byte blocks. 1010 */ 1011static void 1012sf_txeof(sc) 1013 struct sf_softc *sc; 1014{ 1015 int txcons, cmpprodidx, cmpconsidx; 1016 struct sf_tx_cmpdesc_type1 *cur_cmp; 1017 struct sf_tx_bufdesc_type0 *cur_tx; 1018 struct ifnet *ifp; 1019 1020 ifp = &sc->arpcom.ac_if; 1021 1022 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1023 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1024 cmpconsidx = SF_IDX_HI(txcons); 1025 1026 while (cmpconsidx != cmpprodidx) { 1027 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1028 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1029 1030 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1031 ifp->if_opackets++; 1032 else { 1033 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1034 sf_txthresh_adjust(sc); 1035 ifp->if_oerrors++; 1036 } 1037 1038 sc->sf_tx_cnt--; 1039 if (cur_tx->sf_mbuf != NULL) { 1040 m_freem(cur_tx->sf_mbuf); 1041 cur_tx->sf_mbuf = NULL; 1042 } else 1043 break; 1044 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1045 } 1046 1047 ifp->if_timer = 0; 1048 ifp->if_flags &= ~IFF_OACTIVE; 1049 1050 csr_write_4(sc, SF_CQ_CONSIDX, 1051 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1052 ((cmpconsidx << 16) & 0xFFFF0000)); 1053 1054 return; 1055} 1056 1057static void 1058sf_txthresh_adjust(sc) 1059 struct sf_softc *sc; 1060{ 1061 u_int32_t txfctl; 1062 u_int8_t txthresh; 1063 1064 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1065 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1066 if (txthresh < 0xFF) { 1067 txthresh++; 1068 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1069 txfctl |= txthresh; 1070#ifdef DIAGNOSTIC 1071 printf("sf%d: tx underrun, increasing " 1072 "tx threshold to %d bytes\n", 1073 sc->sf_unit, txthresh * 4); 1074#endif 1075 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1076 } 1077 1078 return; 1079} 1080 1081static void 1082sf_intr(arg) 1083 void *arg; 1084{ 1085 struct sf_softc *sc; 1086 struct ifnet *ifp; 1087 u_int32_t status; 1088 1089 sc = arg; 1090 SF_LOCK(sc); 1091 1092 ifp = &sc->arpcom.ac_if; 1093 1094 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1095 SF_UNLOCK(sc); 1096 return; 1097 } 1098 1099 /* Disable interrupts. */ 1100 csr_write_4(sc, SF_IMR, 0x00000000); 1101 1102 for (;;) { 1103 status = csr_read_4(sc, SF_ISR); 1104 if (status) 1105 csr_write_4(sc, SF_ISR, status); 1106 1107 if (!(status & SF_INTRS)) 1108 break; 1109 1110 if (status & SF_ISR_RXDQ1_DMADONE) 1111 sf_rxeof(sc); 1112 1113 if (status & SF_ISR_TX_TXDONE || 1114 status & SF_ISR_TX_DMADONE || 1115 status & SF_ISR_TX_QUEUEDONE) 1116 sf_txeof(sc); 1117 1118 if (status & SF_ISR_TX_LOFIFO) 1119 sf_txthresh_adjust(sc); 1120 1121 if (status & SF_ISR_ABNORMALINTR) { 1122 if (status & SF_ISR_STATSOFLOW) { 1123 untimeout(sf_stats_update, sc, 1124 sc->sf_stat_ch); 1125 sf_stats_update(sc); 1126 } else 1127 sf_init(sc); 1128 } 1129 } 1130 1131 /* Re-enable interrupts. */ 1132 csr_write_4(sc, SF_IMR, SF_INTRS); 1133 1134 if (ifp->if_snd.ifq_head != NULL) 1135 sf_start(ifp); 1136 1137 SF_UNLOCK(sc); 1138 return; 1139} 1140 1141static void 1142sf_init(xsc) 1143 void *xsc; 1144{ 1145 struct sf_softc *sc; 1146 struct ifnet *ifp; 1147 struct mii_data *mii; 1148 int i; 1149 1150 sc = xsc; 1151 SF_LOCK(sc); 1152 ifp = &sc->arpcom.ac_if; 1153 mii = device_get_softc(sc->sf_miibus); 1154 1155 sf_stop(sc); 1156 sf_reset(sc); 1157 1158 /* Init all the receive filter registers */ 1159 for (i = SF_RXFILT_PERFECT_BASE; 1160 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1161 csr_write_4(sc, i, 0); 1162 1163 /* Empty stats counter registers. */ 1164 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1165 csr_write_4(sc, SF_STATS_BASE + 1166 (i + sizeof(u_int32_t)), 0); 1167 1168 /* Init our MAC address */ 1169 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1170 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1171 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1172 1173 if (sf_init_rx_ring(sc) == ENOBUFS) { 1174 printf("sf%d: initialization failed: no " 1175 "memory for rx buffers\n", sc->sf_unit); 1176 SF_UNLOCK(sc); 1177 return; 1178 } 1179 1180 sf_init_tx_ring(sc); 1181 1182 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1183 1184 /* If we want promiscuous mode, set the allframes bit. */ 1185 if (ifp->if_flags & IFF_PROMISC) { 1186 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1187 } else { 1188 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1189 } 1190 1191 if (ifp->if_flags & IFF_BROADCAST) { 1192 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1193 } else { 1194 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1195 } 1196 1197 /* 1198 * Load the multicast filter. 1199 */ 1200 sf_setmulti(sc); 1201 1202 /* Init the completion queue indexes */ 1203 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1204 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1205 1206 /* Init the RX completion queue */ 1207 csr_write_4(sc, SF_RXCQ_CTL_1, 1208 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1209 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1210 1211 /* Init RX DMA control. */ 1212 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1213 1214 /* Init the RX buffer descriptor queue. */ 1215 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1216 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1217 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1218 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1219 1220 /* Init the TX completion queue */ 1221 csr_write_4(sc, SF_TXCQ_CTL, 1222 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1223 1224 /* Init the TX buffer descriptor queue. */ 1225 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1226 vtophys(sc->sf_ldata->sf_tx_dlist)); 1227 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1228 csr_write_4(sc, SF_TXDQ_CTL, 1229 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1230 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1231 1232 /* Enable autopadding of short TX frames. */ 1233 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1234 1235 /* Enable interrupts. */ 1236 csr_write_4(sc, SF_IMR, SF_INTRS); 1237 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1238 1239 /* Enable the RX and TX engines. */ 1240 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1241 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1242 1243 /*mii_mediachg(mii);*/ 1244 sf_ifmedia_upd(ifp); 1245 1246 ifp->if_flags |= IFF_RUNNING; 1247 ifp->if_flags &= ~IFF_OACTIVE; 1248 1249 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1250 1251 SF_UNLOCK(sc); 1252 1253 return; 1254} 1255 1256static int 1257sf_encap(sc, c, m_head) 1258 struct sf_softc *sc; 1259 struct sf_tx_bufdesc_type0 *c; 1260 struct mbuf *m_head; 1261{ 1262 int frag = 0; 1263 struct sf_frag *f = NULL; 1264 struct mbuf *m; 1265 1266 m = m_head; 1267 1268 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1269 if (m->m_len != 0) { 1270 if (frag == SF_MAXFRAGS) 1271 break; 1272 f = &c->sf_frags[frag]; 1273 if (frag == 0) 1274 f->sf_pktlen = m_head->m_pkthdr.len; 1275 f->sf_fraglen = m->m_len; 1276 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1277 frag++; 1278 } 1279 } 1280 1281 if (m != NULL) { 1282 struct mbuf *m_new = NULL; 1283 1284 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1285 if (m_new == NULL) { 1286 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1287 return(1); 1288 } 1289 1290 if (m_head->m_pkthdr.len > MHLEN) { 1291 MCLGET(m_new, M_DONTWAIT); 1292 if (!(m_new->m_flags & M_EXT)) { 1293 m_freem(m_new); 1294 printf("sf%d: no memory for tx list\n", 1295 sc->sf_unit); 1296 return(1); 1297 } 1298 } 1299 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1300 mtod(m_new, caddr_t)); 1301 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1302 m_freem(m_head); 1303 m_head = m_new; 1304 f = &c->sf_frags[0]; 1305 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1306 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1307 frag = 1; 1308 } 1309 1310 c->sf_mbuf = m_head; 1311 c->sf_id = SF_TX_BUFDESC_ID; 1312 c->sf_fragcnt = frag; 1313 c->sf_intr = 1; 1314 c->sf_caltcp = 0; 1315 c->sf_crcen = 1; 1316 1317 return(0); 1318} 1319 1320static void 1321sf_start(ifp) 1322 struct ifnet *ifp; 1323{ 1324 struct sf_softc *sc; 1325 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1326 struct mbuf *m_head = NULL; 1327 int i, txprod; 1328 1329 sc = ifp->if_softc; 1330 SF_LOCK(sc); 1331 1332 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1333 SF_UNLOCK(sc); 1334 return; 1335 } 1336 1337 if (ifp->if_flags & IFF_OACTIVE) { 1338 SF_UNLOCK(sc); 1339 return; 1340 } 1341 1342 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1343 i = SF_IDX_HI(txprod) >> 4; 1344 1345 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1346 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1347 sf_init(sc); 1348 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1349 i = SF_IDX_HI(txprod) >> 4; 1350 } 1351 1352 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1353 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1354 ifp->if_flags |= IFF_OACTIVE; 1355 cur_tx = NULL; 1356 break; 1357 } 1358 IF_DEQUEUE(&ifp->if_snd, m_head); 1359 if (m_head == NULL) 1360 break; 1361 1362 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1363 if (sf_encap(sc, cur_tx, m_head)) { 1364 IF_PREPEND(&ifp->if_snd, m_head); 1365 ifp->if_flags |= IFF_OACTIVE; 1366 cur_tx = NULL; 1367 break; 1368 } 1369 1370 /* 1371 * If there's a BPF listener, bounce a copy of this frame 1372 * to him. 1373 */ 1374 BPF_MTAP(ifp, m_head); 1375 1376 SF_INC(i, SF_TX_DLIST_CNT); 1377 sc->sf_tx_cnt++; 1378 /* 1379 * Don't get the TX DMA queue get too full. 1380 */ 1381 if (sc->sf_tx_cnt > 64) 1382 break; 1383 } 1384 1385 if (cur_tx == NULL) { 1386 SF_UNLOCK(sc); 1387 return; 1388 } 1389 1390 /* Transmit */ 1391 csr_write_4(sc, SF_TXDQ_PRODIDX, 1392 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1393 ((i << 20) & 0xFFFF0000)); 1394 1395 ifp->if_timer = 5; 1396 1397 SF_UNLOCK(sc); 1398 1399 return; 1400} 1401 1402static void 1403sf_stop(sc) 1404 struct sf_softc *sc; 1405{ 1406 int i; 1407 struct ifnet *ifp; 1408 1409 SF_LOCK(sc); 1410 1411 ifp = &sc->arpcom.ac_if; 1412 1413 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1414 1415 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1416 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1417 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1418 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1419 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1420 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1421 csr_write_4(sc, SF_TXCQ_CTL, 0); 1422 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1423 csr_write_4(sc, SF_TXDQ_CTL, 0); 1424 sf_reset(sc); 1425 1426 sc->sf_link = 0; 1427 1428 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1429 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1430 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1431 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1432 } 1433 } 1434 1435 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1436 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1437 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1438 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1439 } 1440 } 1441 1442 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1443 SF_UNLOCK(sc); 1444 1445 return; 1446} 1447 1448/* 1449 * Note: it is important that this function not be interrupted. We 1450 * use a two-stage register access scheme: if we are interrupted in 1451 * between setting the indirect address register and reading from the 1452 * indirect data register, the contents of the address register could 1453 * be changed out from under us. 1454 */ 1455static void 1456sf_stats_update(xsc) 1457 void *xsc; 1458{ 1459 struct sf_softc *sc; 1460 struct ifnet *ifp; 1461 struct mii_data *mii; 1462 struct sf_stats stats; 1463 u_int32_t *ptr; 1464 int i; 1465 1466 sc = xsc; 1467 SF_LOCK(sc); 1468 ifp = &sc->arpcom.ac_if; 1469 mii = device_get_softc(sc->sf_miibus); 1470 1471 ptr = (u_int32_t *)&stats; 1472 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1473 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1474 (i + sizeof(u_int32_t))); 1475 1476 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1477 csr_write_4(sc, SF_STATS_BASE + 1478 (i + sizeof(u_int32_t)), 0); 1479 1480 ifp->if_collisions += stats.sf_tx_single_colls + 1481 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1482 1483 mii_tick(mii); 1484 1485 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1486 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1487 sc->sf_link++; 1488 if (ifp->if_snd.ifq_head != NULL) 1489 sf_start(ifp); 1490 } 1491 1492 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1493 1494 SF_UNLOCK(sc); 1495 1496 return; 1497} 1498 1499static void 1500sf_watchdog(ifp) 1501 struct ifnet *ifp; 1502{ 1503 struct sf_softc *sc; 1504 1505 sc = ifp->if_softc; 1506 1507 SF_LOCK(sc); 1508 1509 ifp->if_oerrors++; 1510 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1511 1512 sf_stop(sc); 1513 sf_reset(sc); 1514 sf_init(sc); 1515 1516 if (ifp->if_snd.ifq_head != NULL) 1517 sf_start(ifp); 1518 1519 SF_UNLOCK(sc); 1520 1521 return; 1522} 1523 1524static void 1525sf_shutdown(dev) 1526 device_t dev; 1527{ 1528 struct sf_softc *sc; 1529 1530 sc = device_get_softc(dev); 1531 1532 sf_stop(sc); 1533 1534 return; 1535} 1536