if_sf.c revision 113545
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 35 * Programming manual is available from: 36 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Department of Electical Engineering 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 45 * controller designed with flexibility and reducing CPU load in mind. 46 * The Starfire offers high and low priority buffer queues, a 47 * producer/consumer index mechanism and several different buffer 48 * queue and completion queue descriptor types. Any one of a number 49 * of different driver designs can be used, depending on system and 50 * OS requirements. This driver makes use of type0 transmit frame 51 * descriptors (since BSD fragments packets across an mbuf chain) 52 * and two RX buffer queues prioritized on size (one queue for small 53 * frames that will fit into a single mbuf, another with full size 54 * mbuf clusters for everything else). The producer/consumer indexes 55 * and completion queues are also used. 56 * 57 * One downside to the Starfire has to do with alignment: buffer 58 * queues must be aligned on 256-byte boundaries, and receive buffers 59 * must be aligned on longword boundaries. The receive buffer alignment 60 * causes problems on the Alpha platform, where the packet payload 61 * should be longword aligned. There is no simple way around this. 62 * 63 * For receive filtering, the Starfire offers 16 perfect filter slots 64 * and a 512-bit hash table. 65 * 66 * The Starfire has no internal transceiver, relying instead on an 67 * external MII-based transceiver. Accessing registers on external 68 * PHYs is done through a special register map rather than with the 69 * usual bitbang MDIO method. 70 * 71 * Acesssing the registers on the Starfire is a little tricky. The 72 * Starfire has a 512K internal register space. When programmed for 73 * PCI memory mapped mode, the entire register space can be accessed 74 * directly. However in I/O space mode, only 256 bytes are directly 75 * mapped into PCI I/O space. The other registers can be accessed 76 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 77 * registers inside the 256-byte I/O window. 78 */ 79 80#include <sys/cdefs.h> 81__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 113545 2003-04-16 03:16:57Z mdodd $"); 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, pci, 1, 1, 1); 122MODULE_DEPEND(sf, ether, 1, 1, 1); 123MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe (device_t); 132static int sf_attach (device_t); 133static int sf_detach (device_t); 134static void sf_intr (void *); 135static void sf_stats_update (void *); 136static void sf_rxeof (struct sf_softc *); 137static void sf_txeof (struct sf_softc *); 138static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141static void sf_start (struct ifnet *); 142static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143static void sf_init (void *); 144static void sf_stop (struct sf_softc *); 145static void sf_watchdog (struct ifnet *); 146static void sf_shutdown (device_t); 147static int sf_ifmedia_upd (struct ifnet *); 148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149static void sf_reset (struct sf_softc *); 150static int sf_init_rx_ring (struct sf_softc *); 151static void sf_init_tx_ring (struct sf_softc *); 152static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti (struct sf_softc *); 156static int sf_setperf (struct sf_softc *, int, caddr_t); 157static int sf_sethash (struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163static u_int32_t sf_calchash (caddr_t); 164 165static int sf_miibus_readreg (device_t, int, int); 166static int sf_miibus_writereg (device_t, int, int, int); 167static void sf_miibus_statchg (device_t); 168 169static u_int32_t csr_read_4 (struct sf_softc *, int); 170static void csr_write_4 (struct sf_softc *, int, u_int32_t); 171static void sf_txthresh_adjust (struct sf_softc *); 172 173#ifdef SF_USEIOSPACE 174#define SF_RES SYS_RES_IOPORT 175#define SF_RID SF_PCI_LOIO 176#else 177#define SF_RES SYS_RES_MEMORY 178#define SF_RID SF_PCI_LOMEM 179#endif 180 181static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198}; 199 200static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204}; 205 206static devclass_t sf_devclass; 207 208DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 209DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211#define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 213 214#define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 216 217static u_int32_t 218csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221{ 222 u_int32_t val; 223 224#ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227#else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229#endif 230 231 return(val); 232} 233 234static u_int8_t 235sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void 248csr_write_4(sc, reg, val) 249 struct sf_softc *sc; 250 int reg; 251 u_int32_t val; 252{ 253#ifdef SF_USEIOSPACE 254 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 255 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 256#else 257 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 258#endif 259 return; 260} 261 262static u_int32_t 263sf_calchash(addr) 264 caddr_t addr; 265{ 266 u_int32_t crc, carry; 267 int i, j; 268 u_int8_t c; 269 270 /* Compute CRC for the address value. */ 271 crc = 0xFFFFFFFF; /* initial value */ 272 273 for (i = 0; i < 6; i++) { 274 c = *(addr + i); 275 for (j = 0; j < 8; j++) { 276 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 277 crc <<= 1; 278 c >>= 1; 279 if (carry) 280 crc = (crc ^ 0x04c11db6) | carry; 281 } 282 } 283 284 /* return the filter bit position */ 285 return(crc >> 23 & 0x1FF); 286} 287 288/* 289 * Copy the address 'mac' into the perfect RX filter entry at 290 * offset 'idx.' The perfect filter only has 16 entries so do 291 * some sanity tests. 292 */ 293static int 294sf_setperf(sc, idx, mac) 295 struct sf_softc *sc; 296 int idx; 297 caddr_t mac; 298{ 299 u_int16_t *p; 300 301 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 302 return(EINVAL); 303 304 if (mac == NULL) 305 return(EINVAL); 306 307 p = (u_int16_t *)mac; 308 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 313 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 314 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 315 316 return(0); 317} 318 319/* 320 * Set the bit in the 512-bit hash table that corresponds to the 321 * specified mac address 'mac.' If 'prio' is nonzero, update the 322 * priority hash table instead of the filter hash table. 323 */ 324static int 325sf_sethash(sc, mac, prio) 326 struct sf_softc *sc; 327 caddr_t mac; 328 int prio; 329{ 330 u_int32_t h = 0; 331 332 if (mac == NULL) 333 return(EINVAL); 334 335 h = sf_calchash(mac); 336 337 if (prio) { 338 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 339 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 340 } else { 341 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 342 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 343 } 344 345 return(0); 346} 347 348#ifdef notdef 349/* 350 * Set a VLAN tag in the receive filter. 351 */ 352static int 353sf_setvlan(sc, idx, vlan) 354 struct sf_softc *sc; 355 int idx; 356 u_int32_t vlan; 357{ 358 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 359 return(EINVAL); 360 361 csr_write_4(sc, SF_RXFILT_HASH_BASE + 362 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 363 364 return(0); 365} 366#endif 367 368static int 369sf_miibus_readreg(dev, phy, reg) 370 device_t dev; 371 int phy, reg; 372{ 373 struct sf_softc *sc; 374 int i; 375 u_int32_t val = 0; 376 377 sc = device_get_softc(dev); 378 379 for (i = 0; i < SF_TIMEOUT; i++) { 380 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 381 if (val & SF_MII_DATAVALID) 382 break; 383 } 384 385 if (i == SF_TIMEOUT) 386 return(0); 387 388 if ((val & 0x0000FFFF) == 0xFFFF) 389 return(0); 390 391 return(val & 0x0000FFFF); 392} 393 394static int 395sf_miibus_writereg(dev, phy, reg, val) 396 device_t dev; 397 int phy, reg, val; 398{ 399 struct sf_softc *sc; 400 int i; 401 int busy; 402 403 sc = device_get_softc(dev); 404 405 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 406 407 for (i = 0; i < SF_TIMEOUT; i++) { 408 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 409 if (!(busy & SF_MII_BUSY)) 410 break; 411 } 412 413 return(0); 414} 415 416static void 417sf_miibus_statchg(dev) 418 device_t dev; 419{ 420 struct sf_softc *sc; 421 struct mii_data *mii; 422 423 sc = device_get_softc(dev); 424 mii = device_get_softc(sc->sf_miibus); 425 426 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 427 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 428 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 429 } else { 430 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 431 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 432 } 433 434 return; 435} 436 437static void 438sf_setmulti(sc) 439 struct sf_softc *sc; 440{ 441 struct ifnet *ifp; 442 int i; 443 struct ifmultiaddr *ifma; 444 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 445 446 ifp = &sc->arpcom.ac_if; 447 448 /* First zot all the existing filters. */ 449 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 450 sf_setperf(sc, i, (char *)&dummy); 451 for (i = SF_RXFILT_HASH_BASE; 452 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 453 csr_write_4(sc, i, 0); 454 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 455 456 /* Now program new ones. */ 457 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 458 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 459 } else { 460 i = 1; 461 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 462 if (ifma->ifma_addr->sa_family != AF_LINK) 463 continue; 464 /* 465 * Program the first 15 multicast groups 466 * into the perfect filter. For all others, 467 * use the hash table. 468 */ 469 if (i < SF_RXFILT_PERFECT_CNT) { 470 sf_setperf(sc, i, 471 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 472 i++; 473 continue; 474 } 475 476 sf_sethash(sc, 477 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 478 } 479 } 480 481 return; 482} 483 484/* 485 * Set media options. 486 */ 487static int 488sf_ifmedia_upd(ifp) 489 struct ifnet *ifp; 490{ 491 struct sf_softc *sc; 492 struct mii_data *mii; 493 494 sc = ifp->if_softc; 495 mii = device_get_softc(sc->sf_miibus); 496 sc->sf_link = 0; 497 if (mii->mii_instance) { 498 struct mii_softc *miisc; 499 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 500 mii_phy_reset(miisc); 501 } 502 mii_mediachg(mii); 503 504 return(0); 505} 506 507/* 508 * Report current media status. 509 */ 510static void 511sf_ifmedia_sts(ifp, ifmr) 512 struct ifnet *ifp; 513 struct ifmediareq *ifmr; 514{ 515 struct sf_softc *sc; 516 struct mii_data *mii; 517 518 sc = ifp->if_softc; 519 mii = device_get_softc(sc->sf_miibus); 520 521 mii_pollstat(mii); 522 ifmr->ifm_active = mii->mii_media_active; 523 ifmr->ifm_status = mii->mii_media_status; 524 525 return; 526} 527 528static int 529sf_ioctl(ifp, command, data) 530 struct ifnet *ifp; 531 u_long command; 532 caddr_t data; 533{ 534 struct sf_softc *sc = ifp->if_softc; 535 struct ifreq *ifr = (struct ifreq *) data; 536 struct mii_data *mii; 537 int error = 0; 538 539 SF_LOCK(sc); 540 541 switch(command) { 542 case SIOCSIFFLAGS: 543 if (ifp->if_flags & IFF_UP) { 544 if (ifp->if_flags & IFF_RUNNING && 545 ifp->if_flags & IFF_PROMISC && 546 !(sc->sf_if_flags & IFF_PROMISC)) { 547 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 548 } else if (ifp->if_flags & IFF_RUNNING && 549 !(ifp->if_flags & IFF_PROMISC) && 550 sc->sf_if_flags & IFF_PROMISC) { 551 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 552 } else if (!(ifp->if_flags & IFF_RUNNING)) 553 sf_init(sc); 554 } else { 555 if (ifp->if_flags & IFF_RUNNING) 556 sf_stop(sc); 557 } 558 sc->sf_if_flags = ifp->if_flags; 559 error = 0; 560 break; 561 case SIOCADDMULTI: 562 case SIOCDELMULTI: 563 sf_setmulti(sc); 564 error = 0; 565 break; 566 case SIOCGIFMEDIA: 567 case SIOCSIFMEDIA: 568 mii = device_get_softc(sc->sf_miibus); 569 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 570 break; 571 default: 572 error = ether_ioctl(ifp, command, data); 573 break; 574 } 575 576 SF_UNLOCK(sc); 577 578 return(error); 579} 580 581static void 582sf_reset(sc) 583 struct sf_softc *sc; 584{ 585 register int i; 586 587 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 588 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 DELAY(1000); 590 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 591 592 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 593 594 for (i = 0; i < SF_TIMEOUT; i++) { 595 DELAY(10); 596 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 597 break; 598 } 599 600 if (i == SF_TIMEOUT) 601 printf("sf%d: reset never completed!\n", sc->sf_unit); 602 603 /* Wait a little while for the chip to get its brains in order. */ 604 DELAY(1000); 605 return; 606} 607 608/* 609 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 610 * IDs against our list and return a device name if we find a match. 611 * We also check the subsystem ID so that we can identify exactly which 612 * NIC has been found, if possible. 613 */ 614static int 615sf_probe(dev) 616 device_t dev; 617{ 618 struct sf_type *t; 619 620 t = sf_devs; 621 622 while(t->sf_name != NULL) { 623 if ((pci_get_vendor(dev) == t->sf_vid) && 624 (pci_get_device(dev) == t->sf_did)) { 625 switch((pci_read_config(dev, 626 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 627 case AD_SUBSYSID_62011_REV0: 628 case AD_SUBSYSID_62011_REV1: 629 device_set_desc(dev, 630 "Adaptec ANA-62011 10/100BaseTX"); 631 return(0); 632 break; 633 case AD_SUBSYSID_62022: 634 device_set_desc(dev, 635 "Adaptec ANA-62022 10/100BaseTX"); 636 return(0); 637 break; 638 case AD_SUBSYSID_62044_REV0: 639 case AD_SUBSYSID_62044_REV1: 640 device_set_desc(dev, 641 "Adaptec ANA-62044 10/100BaseTX"); 642 return(0); 643 break; 644 case AD_SUBSYSID_62020: 645 device_set_desc(dev, 646 "Adaptec ANA-62020 10/100BaseFX"); 647 return(0); 648 break; 649 case AD_SUBSYSID_69011: 650 device_set_desc(dev, 651 "Adaptec ANA-69011 10/100BaseTX"); 652 return(0); 653 break; 654 default: 655 device_set_desc(dev, t->sf_name); 656 return(0); 657 break; 658 } 659 } 660 t++; 661 } 662 663 return(ENXIO); 664} 665 666/* 667 * Attach the interface. Allocate softc structures, do ifmedia 668 * setup and ethernet/BPF attach. 669 */ 670static int 671sf_attach(dev) 672 device_t dev; 673{ 674 int i; 675 struct sf_softc *sc; 676 struct ifnet *ifp; 677 int unit, rid, error = 0; 678 679 sc = device_get_softc(dev); 680 unit = device_get_unit(dev); 681 682 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 683 MTX_DEF | MTX_RECURSE); 684 685 /* 686 * Handle power management nonsense. 687 */ 688 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 689 u_int32_t iobase, membase, irq; 690 691 /* Save important PCI config data. */ 692 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 693 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 694 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 695 696 /* Reset the power state. */ 697 printf("sf%d: chip is in D%d power mode " 698 "-- setting to D0\n", unit, 699 pci_get_powerstate(dev)); 700 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 701 702 /* Restore PCI config data. */ 703 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 704 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 705 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 706 } 707 708 /* 709 * Map control/status registers. 710 */ 711 pci_enable_busmaster(dev); 712 713 rid = SF_RID; 714 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 715 0, ~0, 1, RF_ACTIVE); 716 717 if (sc->sf_res == NULL) { 718 printf ("sf%d: couldn't map ports\n", unit); 719 error = ENXIO; 720 goto fail; 721 } 722 723 sc->sf_btag = rman_get_bustag(sc->sf_res); 724 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 725 726 /* Allocate interrupt */ 727 rid = 0; 728 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 729 RF_SHAREABLE | RF_ACTIVE); 730 731 if (sc->sf_irq == NULL) { 732 printf("sf%d: couldn't map interrupt\n", unit); 733 error = ENXIO; 734 goto fail; 735 } 736 737 callout_handle_init(&sc->sf_stat_ch); 738 /* Reset the adapter. */ 739 sf_reset(sc); 740 741 /* 742 * Get station address from the EEPROM. 743 */ 744 for (i = 0; i < ETHER_ADDR_LEN; i++) 745 sc->arpcom.ac_enaddr[i] = 746 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 747 748 /* 749 * An Adaptec chip was detected. Inform the world. 750 */ 751 printf("sf%d: Ethernet address: %6D\n", unit, 752 sc->arpcom.ac_enaddr, ":"); 753 754 sc->sf_unit = unit; 755 756 /* Allocate the descriptor queues. */ 757 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 758 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 759 760 if (sc->sf_ldata == NULL) { 761 printf("sf%d: no memory for list buffers!\n", unit); 762 error = ENXIO; 763 goto fail; 764 } 765 766 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 767 768 /* Do MII setup. */ 769 if (mii_phy_probe(dev, &sc->sf_miibus, 770 sf_ifmedia_upd, sf_ifmedia_sts)) { 771 printf("sf%d: MII without any phy!\n", sc->sf_unit); 772 error = ENXIO; 773 goto fail; 774 } 775 776 ifp = &sc->arpcom.ac_if; 777 ifp->if_softc = sc; 778 ifp->if_unit = unit; 779 ifp->if_name = "sf"; 780 ifp->if_mtu = ETHERMTU; 781 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 782 ifp->if_ioctl = sf_ioctl; 783 ifp->if_output = ether_output; 784 ifp->if_start = sf_start; 785 ifp->if_watchdog = sf_watchdog; 786 ifp->if_init = sf_init; 787 ifp->if_baudrate = 10000000; 788 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 789 790 /* 791 * Call MI attach routine. 792 */ 793 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 794 795 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 796 sf_intr, sc, &sc->sf_intrhand); 797 798 if (error) { 799 printf("sf%d: couldn't set up irq\n", unit); 800 goto fail; 801 } 802 803fail: 804 if (error) 805 sf_detach(dev); 806 807 return(error); 808} 809 810static int 811sf_detach(dev) 812 device_t dev; 813{ 814 struct sf_softc *sc; 815 struct ifnet *ifp; 816 817 sc = device_get_softc(dev); 818 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 819 SF_LOCK(sc); 820 ifp = &sc->arpcom.ac_if; 821 822 if (device_is_alive(dev)) { 823 if (bus_child_present(dev)) 824 sf_stop(sc); 825 ether_ifdetach(ifp); 826 device_delete_child(dev, sc->sf_miibus); 827 bus_generic_detach(dev); 828 } 829 830 if (sc->sf_intrhand) 831 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 832 if (sc->sf_irq) 833 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 834 if (sc->sf_res) 835 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 836 837 if (sc->sf_ldata) 838 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 839 840 SF_UNLOCK(sc); 841 mtx_destroy(&sc->sf_mtx); 842 843 return(0); 844} 845 846static int 847sf_init_rx_ring(sc) 848 struct sf_softc *sc; 849{ 850 struct sf_list_data *ld; 851 int i; 852 853 ld = sc->sf_ldata; 854 855 bzero((char *)ld->sf_rx_dlist_big, 856 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 857 bzero((char *)ld->sf_rx_clist, 858 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 859 860 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 861 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 862 return(ENOBUFS); 863 } 864 865 return(0); 866} 867 868static void 869sf_init_tx_ring(sc) 870 struct sf_softc *sc; 871{ 872 struct sf_list_data *ld; 873 int i; 874 875 ld = sc->sf_ldata; 876 877 bzero((char *)ld->sf_tx_dlist, 878 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 879 bzero((char *)ld->sf_tx_clist, 880 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 881 882 for (i = 0; i < SF_TX_DLIST_CNT; i++) 883 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 884 for (i = 0; i < SF_TX_CLIST_CNT; i++) 885 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 886 887 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 888 sc->sf_tx_cnt = 0; 889 890 return; 891} 892 893static int 894sf_newbuf(sc, c, m) 895 struct sf_softc *sc; 896 struct sf_rx_bufdesc_type0 *c; 897 struct mbuf *m; 898{ 899 struct mbuf *m_new = NULL; 900 901 if (m == NULL) { 902 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 903 if (m_new == NULL) 904 return(ENOBUFS); 905 906 MCLGET(m_new, M_DONTWAIT); 907 if (!(m_new->m_flags & M_EXT)) { 908 m_freem(m_new); 909 return(ENOBUFS); 910 } 911 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 912 } else { 913 m_new = m; 914 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 915 m_new->m_data = m_new->m_ext.ext_buf; 916 } 917 918 m_adj(m_new, sizeof(u_int64_t)); 919 920 c->sf_mbuf = m_new; 921 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 922 c->sf_valid = 1; 923 924 return(0); 925} 926 927/* 928 * The starfire is programmed to use 'normal' mode for packet reception, 929 * which means we use the consumer/producer model for both the buffer 930 * descriptor queue and the completion descriptor queue. The only problem 931 * with this is that it involves a lot of register accesses: we have to 932 * read the RX completion consumer and producer indexes and the RX buffer 933 * producer index, plus the RX completion consumer and RX buffer producer 934 * indexes have to be updated. It would have been easier if Adaptec had 935 * put each index in a separate register, especially given that the damn 936 * NIC has a 512K register space. 937 * 938 * In spite of all the lovely features that Adaptec crammed into the 6915, 939 * it is marred by one truly stupid design flaw, which is that receive 940 * buffer addresses must be aligned on a longword boundary. This forces 941 * the packet payload to be unaligned, which is suboptimal on the x86 and 942 * completely unuseable on the Alpha. Our only recourse is to copy received 943 * packets into properly aligned buffers before handing them off. 944 */ 945 946static void 947sf_rxeof(sc) 948 struct sf_softc *sc; 949{ 950 struct mbuf *m; 951 struct ifnet *ifp; 952 struct sf_rx_bufdesc_type0 *desc; 953 struct sf_rx_cmpdesc_type3 *cur_rx; 954 u_int32_t rxcons, rxprod; 955 int cmpprodidx, cmpconsidx, bufprodidx; 956 957 ifp = &sc->arpcom.ac_if; 958 959 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 960 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 961 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 962 cmpconsidx = SF_IDX_LO(rxcons); 963 bufprodidx = SF_IDX_LO(rxprod); 964 965 while (cmpconsidx != cmpprodidx) { 966 struct mbuf *m0; 967 968 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 969 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 970 m = desc->sf_mbuf; 971 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 972 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 973 974 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 975 ifp->if_ierrors++; 976 sf_newbuf(sc, desc, m); 977 continue; 978 } 979 980 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 981 ifp, NULL); 982 sf_newbuf(sc, desc, m); 983 if (m0 == NULL) { 984 ifp->if_ierrors++; 985 continue; 986 } 987 m = m0; 988 989 ifp->if_ipackets++; 990 (*ifp->if_input)(ifp, m); 991 } 992 993 csr_write_4(sc, SF_CQ_CONSIDX, 994 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 995 csr_write_4(sc, SF_RXDQ_PTR_Q1, 996 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 997 998 return; 999} 1000 1001/* 1002 * Read the transmit status from the completion queue and release 1003 * mbufs. Note that the buffer descriptor index in the completion 1004 * descriptor is an offset from the start of the transmit buffer 1005 * descriptor list in bytes. This is important because the manual 1006 * gives the impression that it should match the producer/consumer 1007 * index, which is the offset in 8 byte blocks. 1008 */ 1009static void 1010sf_txeof(sc) 1011 struct sf_softc *sc; 1012{ 1013 int txcons, cmpprodidx, cmpconsidx; 1014 struct sf_tx_cmpdesc_type1 *cur_cmp; 1015 struct sf_tx_bufdesc_type0 *cur_tx; 1016 struct ifnet *ifp; 1017 1018 ifp = &sc->arpcom.ac_if; 1019 1020 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1021 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1022 cmpconsidx = SF_IDX_HI(txcons); 1023 1024 while (cmpconsidx != cmpprodidx) { 1025 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1026 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1027 1028 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1029 ifp->if_opackets++; 1030 else { 1031 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1032 sf_txthresh_adjust(sc); 1033 ifp->if_oerrors++; 1034 } 1035 1036 sc->sf_tx_cnt--; 1037 if (cur_tx->sf_mbuf != NULL) { 1038 m_freem(cur_tx->sf_mbuf); 1039 cur_tx->sf_mbuf = NULL; 1040 } else 1041 break; 1042 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1043 } 1044 1045 ifp->if_timer = 0; 1046 ifp->if_flags &= ~IFF_OACTIVE; 1047 1048 csr_write_4(sc, SF_CQ_CONSIDX, 1049 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1050 ((cmpconsidx << 16) & 0xFFFF0000)); 1051 1052 return; 1053} 1054 1055static void 1056sf_txthresh_adjust(sc) 1057 struct sf_softc *sc; 1058{ 1059 u_int32_t txfctl; 1060 u_int8_t txthresh; 1061 1062 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1063 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1064 if (txthresh < 0xFF) { 1065 txthresh++; 1066 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1067 txfctl |= txthresh; 1068#ifdef DIAGNOSTIC 1069 printf("sf%d: tx underrun, increasing " 1070 "tx threshold to %d bytes\n", 1071 sc->sf_unit, txthresh * 4); 1072#endif 1073 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1074 } 1075 1076 return; 1077} 1078 1079static void 1080sf_intr(arg) 1081 void *arg; 1082{ 1083 struct sf_softc *sc; 1084 struct ifnet *ifp; 1085 u_int32_t status; 1086 1087 sc = arg; 1088 SF_LOCK(sc); 1089 1090 ifp = &sc->arpcom.ac_if; 1091 1092 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1093 SF_UNLOCK(sc); 1094 return; 1095 } 1096 1097 /* Disable interrupts. */ 1098 csr_write_4(sc, SF_IMR, 0x00000000); 1099 1100 for (;;) { 1101 status = csr_read_4(sc, SF_ISR); 1102 if (status) 1103 csr_write_4(sc, SF_ISR, status); 1104 1105 if (!(status & SF_INTRS)) 1106 break; 1107 1108 if (status & SF_ISR_RXDQ1_DMADONE) 1109 sf_rxeof(sc); 1110 1111 if (status & SF_ISR_TX_TXDONE || 1112 status & SF_ISR_TX_DMADONE || 1113 status & SF_ISR_TX_QUEUEDONE) 1114 sf_txeof(sc); 1115 1116 if (status & SF_ISR_TX_LOFIFO) 1117 sf_txthresh_adjust(sc); 1118 1119 if (status & SF_ISR_ABNORMALINTR) { 1120 if (status & SF_ISR_STATSOFLOW) { 1121 untimeout(sf_stats_update, sc, 1122 sc->sf_stat_ch); 1123 sf_stats_update(sc); 1124 } else 1125 sf_init(sc); 1126 } 1127 } 1128 1129 /* Re-enable interrupts. */ 1130 csr_write_4(sc, SF_IMR, SF_INTRS); 1131 1132 if (ifp->if_snd.ifq_head != NULL) 1133 sf_start(ifp); 1134 1135 SF_UNLOCK(sc); 1136 return; 1137} 1138 1139static void 1140sf_init(xsc) 1141 void *xsc; 1142{ 1143 struct sf_softc *sc; 1144 struct ifnet *ifp; 1145 struct mii_data *mii; 1146 int i; 1147 1148 sc = xsc; 1149 SF_LOCK(sc); 1150 ifp = &sc->arpcom.ac_if; 1151 mii = device_get_softc(sc->sf_miibus); 1152 1153 sf_stop(sc); 1154 sf_reset(sc); 1155 1156 /* Init all the receive filter registers */ 1157 for (i = SF_RXFILT_PERFECT_BASE; 1158 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1159 csr_write_4(sc, i, 0); 1160 1161 /* Empty stats counter registers. */ 1162 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1163 csr_write_4(sc, SF_STATS_BASE + 1164 (i + sizeof(u_int32_t)), 0); 1165 1166 /* Init our MAC address */ 1167 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1168 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1169 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1170 1171 if (sf_init_rx_ring(sc) == ENOBUFS) { 1172 printf("sf%d: initialization failed: no " 1173 "memory for rx buffers\n", sc->sf_unit); 1174 SF_UNLOCK(sc); 1175 return; 1176 } 1177 1178 sf_init_tx_ring(sc); 1179 1180 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1181 1182 /* If we want promiscuous mode, set the allframes bit. */ 1183 if (ifp->if_flags & IFF_PROMISC) { 1184 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1185 } else { 1186 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1187 } 1188 1189 if (ifp->if_flags & IFF_BROADCAST) { 1190 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1191 } else { 1192 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1193 } 1194 1195 /* 1196 * Load the multicast filter. 1197 */ 1198 sf_setmulti(sc); 1199 1200 /* Init the completion queue indexes */ 1201 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1202 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1203 1204 /* Init the RX completion queue */ 1205 csr_write_4(sc, SF_RXCQ_CTL_1, 1206 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1207 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1208 1209 /* Init RX DMA control. */ 1210 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1211 1212 /* Init the RX buffer descriptor queue. */ 1213 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1214 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1215 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1216 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1217 1218 /* Init the TX completion queue */ 1219 csr_write_4(sc, SF_TXCQ_CTL, 1220 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1221 1222 /* Init the TX buffer descriptor queue. */ 1223 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1224 vtophys(sc->sf_ldata->sf_tx_dlist)); 1225 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1226 csr_write_4(sc, SF_TXDQ_CTL, 1227 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1228 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1229 1230 /* Enable autopadding of short TX frames. */ 1231 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1232 1233 /* Enable interrupts. */ 1234 csr_write_4(sc, SF_IMR, SF_INTRS); 1235 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1236 1237 /* Enable the RX and TX engines. */ 1238 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1239 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1240 1241 /*mii_mediachg(mii);*/ 1242 sf_ifmedia_upd(ifp); 1243 1244 ifp->if_flags |= IFF_RUNNING; 1245 ifp->if_flags &= ~IFF_OACTIVE; 1246 1247 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1248 1249 SF_UNLOCK(sc); 1250 1251 return; 1252} 1253 1254static int 1255sf_encap(sc, c, m_head) 1256 struct sf_softc *sc; 1257 struct sf_tx_bufdesc_type0 *c; 1258 struct mbuf *m_head; 1259{ 1260 int frag = 0; 1261 struct sf_frag *f = NULL; 1262 struct mbuf *m; 1263 1264 m = m_head; 1265 1266 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1267 if (m->m_len != 0) { 1268 if (frag == SF_MAXFRAGS) 1269 break; 1270 f = &c->sf_frags[frag]; 1271 if (frag == 0) 1272 f->sf_pktlen = m_head->m_pkthdr.len; 1273 f->sf_fraglen = m->m_len; 1274 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1275 frag++; 1276 } 1277 } 1278 1279 if (m != NULL) { 1280 struct mbuf *m_new = NULL; 1281 1282 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1283 if (m_new == NULL) { 1284 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1285 return(1); 1286 } 1287 1288 if (m_head->m_pkthdr.len > MHLEN) { 1289 MCLGET(m_new, M_DONTWAIT); 1290 if (!(m_new->m_flags & M_EXT)) { 1291 m_freem(m_new); 1292 printf("sf%d: no memory for tx list\n", 1293 sc->sf_unit); 1294 return(1); 1295 } 1296 } 1297 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1298 mtod(m_new, caddr_t)); 1299 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1300 m_freem(m_head); 1301 m_head = m_new; 1302 f = &c->sf_frags[0]; 1303 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1304 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1305 frag = 1; 1306 } 1307 1308 c->sf_mbuf = m_head; 1309 c->sf_id = SF_TX_BUFDESC_ID; 1310 c->sf_fragcnt = frag; 1311 c->sf_intr = 1; 1312 c->sf_caltcp = 0; 1313 c->sf_crcen = 1; 1314 1315 return(0); 1316} 1317 1318static void 1319sf_start(ifp) 1320 struct ifnet *ifp; 1321{ 1322 struct sf_softc *sc; 1323 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1324 struct mbuf *m_head = NULL; 1325 int i, txprod; 1326 1327 sc = ifp->if_softc; 1328 SF_LOCK(sc); 1329 1330 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1331 SF_UNLOCK(sc); 1332 return; 1333 } 1334 1335 if (ifp->if_flags & IFF_OACTIVE) { 1336 SF_UNLOCK(sc); 1337 return; 1338 } 1339 1340 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1341 i = SF_IDX_HI(txprod) >> 4; 1342 1343 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1344 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1345 sf_init(sc); 1346 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1347 i = SF_IDX_HI(txprod) >> 4; 1348 } 1349 1350 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1351 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1352 ifp->if_flags |= IFF_OACTIVE; 1353 cur_tx = NULL; 1354 break; 1355 } 1356 IF_DEQUEUE(&ifp->if_snd, m_head); 1357 if (m_head == NULL) 1358 break; 1359 1360 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1361 if (sf_encap(sc, cur_tx, m_head)) { 1362 IF_PREPEND(&ifp->if_snd, m_head); 1363 ifp->if_flags |= IFF_OACTIVE; 1364 cur_tx = NULL; 1365 break; 1366 } 1367 1368 /* 1369 * If there's a BPF listener, bounce a copy of this frame 1370 * to him. 1371 */ 1372 BPF_MTAP(ifp, m_head); 1373 1374 SF_INC(i, SF_TX_DLIST_CNT); 1375 sc->sf_tx_cnt++; 1376 /* 1377 * Don't get the TX DMA queue get too full. 1378 */ 1379 if (sc->sf_tx_cnt > 64) 1380 break; 1381 } 1382 1383 if (cur_tx == NULL) { 1384 SF_UNLOCK(sc); 1385 return; 1386 } 1387 1388 /* Transmit */ 1389 csr_write_4(sc, SF_TXDQ_PRODIDX, 1390 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1391 ((i << 20) & 0xFFFF0000)); 1392 1393 ifp->if_timer = 5; 1394 1395 SF_UNLOCK(sc); 1396 1397 return; 1398} 1399 1400static void 1401sf_stop(sc) 1402 struct sf_softc *sc; 1403{ 1404 int i; 1405 struct ifnet *ifp; 1406 1407 SF_LOCK(sc); 1408 1409 ifp = &sc->arpcom.ac_if; 1410 1411 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1412 1413 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1414 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1415 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1416 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1417 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1418 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1419 csr_write_4(sc, SF_TXCQ_CTL, 0); 1420 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1421 csr_write_4(sc, SF_TXDQ_CTL, 0); 1422 sf_reset(sc); 1423 1424 sc->sf_link = 0; 1425 1426 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1427 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1428 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1429 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1430 } 1431 } 1432 1433 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1434 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1435 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1436 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1437 } 1438 } 1439 1440 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1441 SF_UNLOCK(sc); 1442 1443 return; 1444} 1445 1446/* 1447 * Note: it is important that this function not be interrupted. We 1448 * use a two-stage register access scheme: if we are interrupted in 1449 * between setting the indirect address register and reading from the 1450 * indirect data register, the contents of the address register could 1451 * be changed out from under us. 1452 */ 1453static void 1454sf_stats_update(xsc) 1455 void *xsc; 1456{ 1457 struct sf_softc *sc; 1458 struct ifnet *ifp; 1459 struct mii_data *mii; 1460 struct sf_stats stats; 1461 u_int32_t *ptr; 1462 int i; 1463 1464 sc = xsc; 1465 SF_LOCK(sc); 1466 ifp = &sc->arpcom.ac_if; 1467 mii = device_get_softc(sc->sf_miibus); 1468 1469 ptr = (u_int32_t *)&stats; 1470 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1471 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1472 (i + sizeof(u_int32_t))); 1473 1474 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1475 csr_write_4(sc, SF_STATS_BASE + 1476 (i + sizeof(u_int32_t)), 0); 1477 1478 ifp->if_collisions += stats.sf_tx_single_colls + 1479 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1480 1481 mii_tick(mii); 1482 1483 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1484 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1485 sc->sf_link++; 1486 if (ifp->if_snd.ifq_head != NULL) 1487 sf_start(ifp); 1488 } 1489 1490 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1491 1492 SF_UNLOCK(sc); 1493 1494 return; 1495} 1496 1497static void 1498sf_watchdog(ifp) 1499 struct ifnet *ifp; 1500{ 1501 struct sf_softc *sc; 1502 1503 sc = ifp->if_softc; 1504 1505 SF_LOCK(sc); 1506 1507 ifp->if_oerrors++; 1508 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1509 1510 sf_stop(sc); 1511 sf_reset(sc); 1512 sf_init(sc); 1513 1514 if (ifp->if_snd.ifq_head != NULL) 1515 sf_start(ifp); 1516 1517 SF_UNLOCK(sc); 1518 1519 return; 1520} 1521 1522static void 1523sf_shutdown(dev) 1524 device_t dev; 1525{ 1526 struct sf_softc *sc; 1527 1528 sc = device_get_softc(dev); 1529 1530 sf_stop(sc); 1531 1532 return; 1533} 1534