if_sf.c revision 113506
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 35 * Programming manual is available from: 36 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Department of Electical Engineering 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 45 * controller designed with flexibility and reducing CPU load in mind. 46 * The Starfire offers high and low priority buffer queues, a 47 * producer/consumer index mechanism and several different buffer 48 * queue and completion queue descriptor types. Any one of a number 49 * of different driver designs can be used, depending on system and 50 * OS requirements. This driver makes use of type0 transmit frame 51 * descriptors (since BSD fragments packets across an mbuf chain) 52 * and two RX buffer queues prioritized on size (one queue for small 53 * frames that will fit into a single mbuf, another with full size 54 * mbuf clusters for everything else). The producer/consumer indexes 55 * and completion queues are also used. 56 * 57 * One downside to the Starfire has to do with alignment: buffer 58 * queues must be aligned on 256-byte boundaries, and receive buffers 59 * must be aligned on longword boundaries. The receive buffer alignment 60 * causes problems on the Alpha platform, where the packet payload 61 * should be longword aligned. There is no simple way around this. 62 * 63 * For receive filtering, the Starfire offers 16 perfect filter slots 64 * and a 512-bit hash table. 65 * 66 * The Starfire has no internal transceiver, relying instead on an 67 * external MII-based transceiver. Accessing registers on external 68 * PHYs is done through a special register map rather than with the 69 * usual bitbang MDIO method. 70 * 71 * Acesssing the registers on the Starfire is a little tricky. The 72 * Starfire has a 512K internal register space. When programmed for 73 * PCI memory mapped mode, the entire register space can be accessed 74 * directly. However in I/O space mode, only 256 bytes are directly 75 * mapped into PCI I/O space. The other registers can be accessed 76 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 77 * registers inside the 256-byte I/O window. 78 */ 79 80#include <sys/cdefs.h> 81__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 113506 2003-04-15 06:37:30Z mdodd $"); 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, pci, 1, 1, 1); 122MODULE_DEPEND(sf, ether, 1, 1, 1); 123MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe (device_t); 132static int sf_attach (device_t); 133static int sf_detach (device_t); 134static void sf_intr (void *); 135static void sf_stats_update (void *); 136static void sf_rxeof (struct sf_softc *); 137static void sf_txeof (struct sf_softc *); 138static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141static void sf_start (struct ifnet *); 142static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143static void sf_init (void *); 144static void sf_stop (struct sf_softc *); 145static void sf_watchdog (struct ifnet *); 146static void sf_shutdown (device_t); 147static int sf_ifmedia_upd (struct ifnet *); 148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149static void sf_reset (struct sf_softc *); 150static int sf_init_rx_ring (struct sf_softc *); 151static void sf_init_tx_ring (struct sf_softc *); 152static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti (struct sf_softc *); 156static int sf_setperf (struct sf_softc *, int, caddr_t); 157static int sf_sethash (struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163static u_int32_t sf_calchash (caddr_t); 164 165static int sf_miibus_readreg (device_t, int, int); 166static int sf_miibus_writereg (device_t, int, int, int); 167static void sf_miibus_statchg (device_t); 168 169static u_int32_t csr_read_4 (struct sf_softc *, int); 170static void csr_write_4 (struct sf_softc *, int, u_int32_t); 171static void sf_txthresh_adjust (struct sf_softc *); 172 173#ifdef SF_USEIOSPACE 174#define SF_RES SYS_RES_IOPORT 175#define SF_RID SF_PCI_LOIO 176#else 177#define SF_RES SYS_RES_MEMORY 178#define SF_RID SF_PCI_LOMEM 179#endif 180 181static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198}; 199 200static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204}; 205 206static devclass_t sf_devclass; 207 208DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 209DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211#define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 213 214#define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 216 217static u_int32_t 218csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221{ 222 u_int32_t val; 223 224#ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227#else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229#endif 230 231 return(val); 232} 233 234static u_int8_t 235sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void 248csr_write_4(sc, reg, val) 249 struct sf_softc *sc; 250 int reg; 251 u_int32_t val; 252{ 253#ifdef SF_USEIOSPACE 254 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 255 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 256#else 257 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 258#endif 259 return; 260} 261 262static u_int32_t 263sf_calchash(addr) 264 caddr_t addr; 265{ 266 u_int32_t crc, carry; 267 int i, j; 268 u_int8_t c; 269 270 /* Compute CRC for the address value. */ 271 crc = 0xFFFFFFFF; /* initial value */ 272 273 for (i = 0; i < 6; i++) { 274 c = *(addr + i); 275 for (j = 0; j < 8; j++) { 276 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 277 crc <<= 1; 278 c >>= 1; 279 if (carry) 280 crc = (crc ^ 0x04c11db6) | carry; 281 } 282 } 283 284 /* return the filter bit position */ 285 return(crc >> 23 & 0x1FF); 286} 287 288/* 289 * Copy the address 'mac' into the perfect RX filter entry at 290 * offset 'idx.' The perfect filter only has 16 entries so do 291 * some sanity tests. 292 */ 293static int 294sf_setperf(sc, idx, mac) 295 struct sf_softc *sc; 296 int idx; 297 caddr_t mac; 298{ 299 u_int16_t *p; 300 301 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 302 return(EINVAL); 303 304 if (mac == NULL) 305 return(EINVAL); 306 307 p = (u_int16_t *)mac; 308 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 313 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 314 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 315 316 return(0); 317} 318 319/* 320 * Set the bit in the 512-bit hash table that corresponds to the 321 * specified mac address 'mac.' If 'prio' is nonzero, update the 322 * priority hash table instead of the filter hash table. 323 */ 324static int 325sf_sethash(sc, mac, prio) 326 struct sf_softc *sc; 327 caddr_t mac; 328 int prio; 329{ 330 u_int32_t h = 0; 331 332 if (mac == NULL) 333 return(EINVAL); 334 335 h = sf_calchash(mac); 336 337 if (prio) { 338 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 339 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 340 } else { 341 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 342 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 343 } 344 345 return(0); 346} 347 348#ifdef notdef 349/* 350 * Set a VLAN tag in the receive filter. 351 */ 352static int 353sf_setvlan(sc, idx, vlan) 354 struct sf_softc *sc; 355 int idx; 356 u_int32_t vlan; 357{ 358 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 359 return(EINVAL); 360 361 csr_write_4(sc, SF_RXFILT_HASH_BASE + 362 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 363 364 return(0); 365} 366#endif 367 368static int 369sf_miibus_readreg(dev, phy, reg) 370 device_t dev; 371 int phy, reg; 372{ 373 struct sf_softc *sc; 374 int i; 375 u_int32_t val = 0; 376 377 sc = device_get_softc(dev); 378 379 for (i = 0; i < SF_TIMEOUT; i++) { 380 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 381 if (val & SF_MII_DATAVALID) 382 break; 383 } 384 385 if (i == SF_TIMEOUT) 386 return(0); 387 388 if ((val & 0x0000FFFF) == 0xFFFF) 389 return(0); 390 391 return(val & 0x0000FFFF); 392} 393 394static int 395sf_miibus_writereg(dev, phy, reg, val) 396 device_t dev; 397 int phy, reg, val; 398{ 399 struct sf_softc *sc; 400 int i; 401 int busy; 402 403 sc = device_get_softc(dev); 404 405 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 406 407 for (i = 0; i < SF_TIMEOUT; i++) { 408 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 409 if (!(busy & SF_MII_BUSY)) 410 break; 411 } 412 413 return(0); 414} 415 416static void 417sf_miibus_statchg(dev) 418 device_t dev; 419{ 420 struct sf_softc *sc; 421 struct mii_data *mii; 422 423 sc = device_get_softc(dev); 424 mii = device_get_softc(sc->sf_miibus); 425 426 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 427 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 428 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 429 } else { 430 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 431 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 432 } 433 434 return; 435} 436 437static void 438sf_setmulti(sc) 439 struct sf_softc *sc; 440{ 441 struct ifnet *ifp; 442 int i; 443 struct ifmultiaddr *ifma; 444 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 445 446 ifp = &sc->arpcom.ac_if; 447 448 /* First zot all the existing filters. */ 449 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 450 sf_setperf(sc, i, (char *)&dummy); 451 for (i = SF_RXFILT_HASH_BASE; 452 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 453 csr_write_4(sc, i, 0); 454 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 455 456 /* Now program new ones. */ 457 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 458 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 459 } else { 460 i = 1; 461 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 462 if (ifma->ifma_addr->sa_family != AF_LINK) 463 continue; 464 /* 465 * Program the first 15 multicast groups 466 * into the perfect filter. For all others, 467 * use the hash table. 468 */ 469 if (i < SF_RXFILT_PERFECT_CNT) { 470 sf_setperf(sc, i, 471 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 472 i++; 473 continue; 474 } 475 476 sf_sethash(sc, 477 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 478 } 479 } 480 481 return; 482} 483 484/* 485 * Set media options. 486 */ 487static int 488sf_ifmedia_upd(ifp) 489 struct ifnet *ifp; 490{ 491 struct sf_softc *sc; 492 struct mii_data *mii; 493 494 sc = ifp->if_softc; 495 mii = device_get_softc(sc->sf_miibus); 496 sc->sf_link = 0; 497 if (mii->mii_instance) { 498 struct mii_softc *miisc; 499 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 500 mii_phy_reset(miisc); 501 } 502 mii_mediachg(mii); 503 504 return(0); 505} 506 507/* 508 * Report current media status. 509 */ 510static void 511sf_ifmedia_sts(ifp, ifmr) 512 struct ifnet *ifp; 513 struct ifmediareq *ifmr; 514{ 515 struct sf_softc *sc; 516 struct mii_data *mii; 517 518 sc = ifp->if_softc; 519 mii = device_get_softc(sc->sf_miibus); 520 521 mii_pollstat(mii); 522 ifmr->ifm_active = mii->mii_media_active; 523 ifmr->ifm_status = mii->mii_media_status; 524 525 return; 526} 527 528static int 529sf_ioctl(ifp, command, data) 530 struct ifnet *ifp; 531 u_long command; 532 caddr_t data; 533{ 534 struct sf_softc *sc = ifp->if_softc; 535 struct ifreq *ifr = (struct ifreq *) data; 536 struct mii_data *mii; 537 int error = 0; 538 539 SF_LOCK(sc); 540 541 switch(command) { 542 case SIOCSIFFLAGS: 543 if (ifp->if_flags & IFF_UP) { 544 if (ifp->if_flags & IFF_RUNNING && 545 ifp->if_flags & IFF_PROMISC && 546 !(sc->sf_if_flags & IFF_PROMISC)) { 547 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 548 } else if (ifp->if_flags & IFF_RUNNING && 549 !(ifp->if_flags & IFF_PROMISC) && 550 sc->sf_if_flags & IFF_PROMISC) { 551 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 552 } else if (!(ifp->if_flags & IFF_RUNNING)) 553 sf_init(sc); 554 } else { 555 if (ifp->if_flags & IFF_RUNNING) 556 sf_stop(sc); 557 } 558 sc->sf_if_flags = ifp->if_flags; 559 error = 0; 560 break; 561 case SIOCADDMULTI: 562 case SIOCDELMULTI: 563 sf_setmulti(sc); 564 error = 0; 565 break; 566 case SIOCGIFMEDIA: 567 case SIOCSIFMEDIA: 568 mii = device_get_softc(sc->sf_miibus); 569 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 570 break; 571 default: 572 error = ether_ioctl(ifp, command, data); 573 break; 574 } 575 576 SF_UNLOCK(sc); 577 578 return(error); 579} 580 581static void 582sf_reset(sc) 583 struct sf_softc *sc; 584{ 585 register int i; 586 587 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 588 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 DELAY(1000); 590 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 591 592 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 593 594 for (i = 0; i < SF_TIMEOUT; i++) { 595 DELAY(10); 596 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 597 break; 598 } 599 600 if (i == SF_TIMEOUT) 601 printf("sf%d: reset never completed!\n", sc->sf_unit); 602 603 /* Wait a little while for the chip to get its brains in order. */ 604 DELAY(1000); 605 return; 606} 607 608/* 609 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 610 * IDs against our list and return a device name if we find a match. 611 * We also check the subsystem ID so that we can identify exactly which 612 * NIC has been found, if possible. 613 */ 614static int 615sf_probe(dev) 616 device_t dev; 617{ 618 struct sf_type *t; 619 620 t = sf_devs; 621 622 while(t->sf_name != NULL) { 623 if ((pci_get_vendor(dev) == t->sf_vid) && 624 (pci_get_device(dev) == t->sf_did)) { 625 switch((pci_read_config(dev, 626 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 627 case AD_SUBSYSID_62011_REV0: 628 case AD_SUBSYSID_62011_REV1: 629 device_set_desc(dev, 630 "Adaptec ANA-62011 10/100BaseTX"); 631 return(0); 632 break; 633 case AD_SUBSYSID_62022: 634 device_set_desc(dev, 635 "Adaptec ANA-62022 10/100BaseTX"); 636 return(0); 637 break; 638 case AD_SUBSYSID_62044_REV0: 639 case AD_SUBSYSID_62044_REV1: 640 device_set_desc(dev, 641 "Adaptec ANA-62044 10/100BaseTX"); 642 return(0); 643 break; 644 case AD_SUBSYSID_62020: 645 device_set_desc(dev, 646 "Adaptec ANA-62020 10/100BaseFX"); 647 return(0); 648 break; 649 case AD_SUBSYSID_69011: 650 device_set_desc(dev, 651 "Adaptec ANA-69011 10/100BaseTX"); 652 return(0); 653 break; 654 default: 655 device_set_desc(dev, t->sf_name); 656 return(0); 657 break; 658 } 659 } 660 t++; 661 } 662 663 return(ENXIO); 664} 665 666/* 667 * Attach the interface. Allocate softc structures, do ifmedia 668 * setup and ethernet/BPF attach. 669 */ 670static int 671sf_attach(dev) 672 device_t dev; 673{ 674 int i; 675 u_int32_t command; 676 struct sf_softc *sc; 677 struct ifnet *ifp; 678 int unit, rid, error = 0; 679 680 sc = device_get_softc(dev); 681 unit = device_get_unit(dev); 682 683 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 684 MTX_DEF | MTX_RECURSE); 685 686 /* 687 * Handle power management nonsense. 688 */ 689 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 690 u_int32_t iobase, membase, irq; 691 692 /* Save important PCI config data. */ 693 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 694 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 695 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 696 697 /* Reset the power state. */ 698 printf("sf%d: chip is in D%d power mode " 699 "-- setting to D0\n", unit, 700 pci_get_powerstate(dev)); 701 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 702 703 /* Restore PCI config data. */ 704 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 705 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 706 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 707 } 708 709 /* 710 * Map control/status registers. 711 */ 712 pci_enable_busmaster(dev); 713 pci_enable_io(dev, SYS_RES_IOPORT); 714 pci_enable_io(dev, SYS_RES_MEMORY); 715 command = pci_read_config(dev, PCIR_COMMAND, 4); 716 717#ifdef SF_USEIOSPACE 718 if (!(command & PCIM_CMD_PORTEN)) { 719 printf("sf%d: failed to enable I/O ports!\n", unit); 720 error = ENXIO; 721 goto fail; 722 } 723#else 724 if (!(command & PCIM_CMD_MEMEN)) { 725 printf("sf%d: failed to enable memory mapping!\n", unit); 726 error = ENXIO; 727 goto fail; 728 } 729#endif 730 731 rid = SF_RID; 732 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 733 0, ~0, 1, RF_ACTIVE); 734 735 if (sc->sf_res == NULL) { 736 printf ("sf%d: couldn't map ports\n", unit); 737 error = ENXIO; 738 goto fail; 739 } 740 741 sc->sf_btag = rman_get_bustag(sc->sf_res); 742 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 743 744 /* Allocate interrupt */ 745 rid = 0; 746 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 747 RF_SHAREABLE | RF_ACTIVE); 748 749 if (sc->sf_irq == NULL) { 750 printf("sf%d: couldn't map interrupt\n", unit); 751 error = ENXIO; 752 goto fail; 753 } 754 755 callout_handle_init(&sc->sf_stat_ch); 756 /* Reset the adapter. */ 757 sf_reset(sc); 758 759 /* 760 * Get station address from the EEPROM. 761 */ 762 for (i = 0; i < ETHER_ADDR_LEN; i++) 763 sc->arpcom.ac_enaddr[i] = 764 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 765 766 /* 767 * An Adaptec chip was detected. Inform the world. 768 */ 769 printf("sf%d: Ethernet address: %6D\n", unit, 770 sc->arpcom.ac_enaddr, ":"); 771 772 sc->sf_unit = unit; 773 774 /* Allocate the descriptor queues. */ 775 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 776 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 777 778 if (sc->sf_ldata == NULL) { 779 printf("sf%d: no memory for list buffers!\n", unit); 780 error = ENXIO; 781 goto fail; 782 } 783 784 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 785 786 /* Do MII setup. */ 787 if (mii_phy_probe(dev, &sc->sf_miibus, 788 sf_ifmedia_upd, sf_ifmedia_sts)) { 789 printf("sf%d: MII without any phy!\n", sc->sf_unit); 790 error = ENXIO; 791 goto fail; 792 } 793 794 ifp = &sc->arpcom.ac_if; 795 ifp->if_softc = sc; 796 ifp->if_unit = unit; 797 ifp->if_name = "sf"; 798 ifp->if_mtu = ETHERMTU; 799 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 800 ifp->if_ioctl = sf_ioctl; 801 ifp->if_output = ether_output; 802 ifp->if_start = sf_start; 803 ifp->if_watchdog = sf_watchdog; 804 ifp->if_init = sf_init; 805 ifp->if_baudrate = 10000000; 806 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 807 808 /* 809 * Call MI attach routine. 810 */ 811 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 812 813 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 814 sf_intr, sc, &sc->sf_intrhand); 815 816 if (error) { 817 printf("sf%d: couldn't set up irq\n", unit); 818 goto fail; 819 } 820 821fail: 822 if (error) 823 sf_detach(dev); 824 825 return(error); 826} 827 828static int 829sf_detach(dev) 830 device_t dev; 831{ 832 struct sf_softc *sc; 833 struct ifnet *ifp; 834 835 sc = device_get_softc(dev); 836 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 837 SF_LOCK(sc); 838 ifp = &sc->arpcom.ac_if; 839 840 if (device_is_alive(dev)) { 841 if (bus_child_present(dev)) 842 sf_stop(sc); 843 ether_ifdetach(ifp); 844 device_delete_child(dev, sc->sf_miibus); 845 bus_generic_detach(dev); 846 } 847 848 if (sc->sf_intrhand) 849 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 850 if (sc->sf_irq) 851 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 852 if (sc->sf_res) 853 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 854 855 if (sc->sf_ldata) 856 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 857 858 SF_UNLOCK(sc); 859 mtx_destroy(&sc->sf_mtx); 860 861 return(0); 862} 863 864static int 865sf_init_rx_ring(sc) 866 struct sf_softc *sc; 867{ 868 struct sf_list_data *ld; 869 int i; 870 871 ld = sc->sf_ldata; 872 873 bzero((char *)ld->sf_rx_dlist_big, 874 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 875 bzero((char *)ld->sf_rx_clist, 876 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 877 878 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 879 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 880 return(ENOBUFS); 881 } 882 883 return(0); 884} 885 886static void 887sf_init_tx_ring(sc) 888 struct sf_softc *sc; 889{ 890 struct sf_list_data *ld; 891 int i; 892 893 ld = sc->sf_ldata; 894 895 bzero((char *)ld->sf_tx_dlist, 896 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 897 bzero((char *)ld->sf_tx_clist, 898 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 899 900 for (i = 0; i < SF_TX_DLIST_CNT; i++) 901 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 902 for (i = 0; i < SF_TX_CLIST_CNT; i++) 903 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 904 905 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 906 sc->sf_tx_cnt = 0; 907 908 return; 909} 910 911static int 912sf_newbuf(sc, c, m) 913 struct sf_softc *sc; 914 struct sf_rx_bufdesc_type0 *c; 915 struct mbuf *m; 916{ 917 struct mbuf *m_new = NULL; 918 919 if (m == NULL) { 920 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 921 if (m_new == NULL) 922 return(ENOBUFS); 923 924 MCLGET(m_new, M_DONTWAIT); 925 if (!(m_new->m_flags & M_EXT)) { 926 m_freem(m_new); 927 return(ENOBUFS); 928 } 929 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 930 } else { 931 m_new = m; 932 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 933 m_new->m_data = m_new->m_ext.ext_buf; 934 } 935 936 m_adj(m_new, sizeof(u_int64_t)); 937 938 c->sf_mbuf = m_new; 939 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 940 c->sf_valid = 1; 941 942 return(0); 943} 944 945/* 946 * The starfire is programmed to use 'normal' mode for packet reception, 947 * which means we use the consumer/producer model for both the buffer 948 * descriptor queue and the completion descriptor queue. The only problem 949 * with this is that it involves a lot of register accesses: we have to 950 * read the RX completion consumer and producer indexes and the RX buffer 951 * producer index, plus the RX completion consumer and RX buffer producer 952 * indexes have to be updated. It would have been easier if Adaptec had 953 * put each index in a separate register, especially given that the damn 954 * NIC has a 512K register space. 955 * 956 * In spite of all the lovely features that Adaptec crammed into the 6915, 957 * it is marred by one truly stupid design flaw, which is that receive 958 * buffer addresses must be aligned on a longword boundary. This forces 959 * the packet payload to be unaligned, which is suboptimal on the x86 and 960 * completely unuseable on the Alpha. Our only recourse is to copy received 961 * packets into properly aligned buffers before handing them off. 962 */ 963 964static void 965sf_rxeof(sc) 966 struct sf_softc *sc; 967{ 968 struct mbuf *m; 969 struct ifnet *ifp; 970 struct sf_rx_bufdesc_type0 *desc; 971 struct sf_rx_cmpdesc_type3 *cur_rx; 972 u_int32_t rxcons, rxprod; 973 int cmpprodidx, cmpconsidx, bufprodidx; 974 975 ifp = &sc->arpcom.ac_if; 976 977 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 978 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 979 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 980 cmpconsidx = SF_IDX_LO(rxcons); 981 bufprodidx = SF_IDX_LO(rxprod); 982 983 while (cmpconsidx != cmpprodidx) { 984 struct mbuf *m0; 985 986 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 987 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 988 m = desc->sf_mbuf; 989 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 990 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 991 992 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 993 ifp->if_ierrors++; 994 sf_newbuf(sc, desc, m); 995 continue; 996 } 997 998 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 999 ifp, NULL); 1000 sf_newbuf(sc, desc, m); 1001 if (m0 == NULL) { 1002 ifp->if_ierrors++; 1003 continue; 1004 } 1005 m = m0; 1006 1007 ifp->if_ipackets++; 1008 (*ifp->if_input)(ifp, m); 1009 } 1010 1011 csr_write_4(sc, SF_CQ_CONSIDX, 1012 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1013 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1014 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1015 1016 return; 1017} 1018 1019/* 1020 * Read the transmit status from the completion queue and release 1021 * mbufs. Note that the buffer descriptor index in the completion 1022 * descriptor is an offset from the start of the transmit buffer 1023 * descriptor list in bytes. This is important because the manual 1024 * gives the impression that it should match the producer/consumer 1025 * index, which is the offset in 8 byte blocks. 1026 */ 1027static void 1028sf_txeof(sc) 1029 struct sf_softc *sc; 1030{ 1031 int txcons, cmpprodidx, cmpconsidx; 1032 struct sf_tx_cmpdesc_type1 *cur_cmp; 1033 struct sf_tx_bufdesc_type0 *cur_tx; 1034 struct ifnet *ifp; 1035 1036 ifp = &sc->arpcom.ac_if; 1037 1038 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1039 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1040 cmpconsidx = SF_IDX_HI(txcons); 1041 1042 while (cmpconsidx != cmpprodidx) { 1043 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1044 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1045 1046 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1047 ifp->if_opackets++; 1048 else { 1049 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1050 sf_txthresh_adjust(sc); 1051 ifp->if_oerrors++; 1052 } 1053 1054 sc->sf_tx_cnt--; 1055 if (cur_tx->sf_mbuf != NULL) { 1056 m_freem(cur_tx->sf_mbuf); 1057 cur_tx->sf_mbuf = NULL; 1058 } else 1059 break; 1060 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1061 } 1062 1063 ifp->if_timer = 0; 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 1066 csr_write_4(sc, SF_CQ_CONSIDX, 1067 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1068 ((cmpconsidx << 16) & 0xFFFF0000)); 1069 1070 return; 1071} 1072 1073static void 1074sf_txthresh_adjust(sc) 1075 struct sf_softc *sc; 1076{ 1077 u_int32_t txfctl; 1078 u_int8_t txthresh; 1079 1080 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1081 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1082 if (txthresh < 0xFF) { 1083 txthresh++; 1084 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1085 txfctl |= txthresh; 1086#ifdef DIAGNOSTIC 1087 printf("sf%d: tx underrun, increasing " 1088 "tx threshold to %d bytes\n", 1089 sc->sf_unit, txthresh * 4); 1090#endif 1091 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1092 } 1093 1094 return; 1095} 1096 1097static void 1098sf_intr(arg) 1099 void *arg; 1100{ 1101 struct sf_softc *sc; 1102 struct ifnet *ifp; 1103 u_int32_t status; 1104 1105 sc = arg; 1106 SF_LOCK(sc); 1107 1108 ifp = &sc->arpcom.ac_if; 1109 1110 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1111 SF_UNLOCK(sc); 1112 return; 1113 } 1114 1115 /* Disable interrupts. */ 1116 csr_write_4(sc, SF_IMR, 0x00000000); 1117 1118 for (;;) { 1119 status = csr_read_4(sc, SF_ISR); 1120 if (status) 1121 csr_write_4(sc, SF_ISR, status); 1122 1123 if (!(status & SF_INTRS)) 1124 break; 1125 1126 if (status & SF_ISR_RXDQ1_DMADONE) 1127 sf_rxeof(sc); 1128 1129 if (status & SF_ISR_TX_TXDONE || 1130 status & SF_ISR_TX_DMADONE || 1131 status & SF_ISR_TX_QUEUEDONE) 1132 sf_txeof(sc); 1133 1134 if (status & SF_ISR_TX_LOFIFO) 1135 sf_txthresh_adjust(sc); 1136 1137 if (status & SF_ISR_ABNORMALINTR) { 1138 if (status & SF_ISR_STATSOFLOW) { 1139 untimeout(sf_stats_update, sc, 1140 sc->sf_stat_ch); 1141 sf_stats_update(sc); 1142 } else 1143 sf_init(sc); 1144 } 1145 } 1146 1147 /* Re-enable interrupts. */ 1148 csr_write_4(sc, SF_IMR, SF_INTRS); 1149 1150 if (ifp->if_snd.ifq_head != NULL) 1151 sf_start(ifp); 1152 1153 SF_UNLOCK(sc); 1154 return; 1155} 1156 1157static void 1158sf_init(xsc) 1159 void *xsc; 1160{ 1161 struct sf_softc *sc; 1162 struct ifnet *ifp; 1163 struct mii_data *mii; 1164 int i; 1165 1166 sc = xsc; 1167 SF_LOCK(sc); 1168 ifp = &sc->arpcom.ac_if; 1169 mii = device_get_softc(sc->sf_miibus); 1170 1171 sf_stop(sc); 1172 sf_reset(sc); 1173 1174 /* Init all the receive filter registers */ 1175 for (i = SF_RXFILT_PERFECT_BASE; 1176 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1177 csr_write_4(sc, i, 0); 1178 1179 /* Empty stats counter registers. */ 1180 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1181 csr_write_4(sc, SF_STATS_BASE + 1182 (i + sizeof(u_int32_t)), 0); 1183 1184 /* Init our MAC address */ 1185 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1186 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1187 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1188 1189 if (sf_init_rx_ring(sc) == ENOBUFS) { 1190 printf("sf%d: initialization failed: no " 1191 "memory for rx buffers\n", sc->sf_unit); 1192 SF_UNLOCK(sc); 1193 return; 1194 } 1195 1196 sf_init_tx_ring(sc); 1197 1198 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1199 1200 /* If we want promiscuous mode, set the allframes bit. */ 1201 if (ifp->if_flags & IFF_PROMISC) { 1202 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1203 } else { 1204 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1205 } 1206 1207 if (ifp->if_flags & IFF_BROADCAST) { 1208 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1209 } else { 1210 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1211 } 1212 1213 /* 1214 * Load the multicast filter. 1215 */ 1216 sf_setmulti(sc); 1217 1218 /* Init the completion queue indexes */ 1219 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1220 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1221 1222 /* Init the RX completion queue */ 1223 csr_write_4(sc, SF_RXCQ_CTL_1, 1224 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1225 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1226 1227 /* Init RX DMA control. */ 1228 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1229 1230 /* Init the RX buffer descriptor queue. */ 1231 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1232 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1233 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1234 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1235 1236 /* Init the TX completion queue */ 1237 csr_write_4(sc, SF_TXCQ_CTL, 1238 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1239 1240 /* Init the TX buffer descriptor queue. */ 1241 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1242 vtophys(sc->sf_ldata->sf_tx_dlist)); 1243 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1244 csr_write_4(sc, SF_TXDQ_CTL, 1245 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1246 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1247 1248 /* Enable autopadding of short TX frames. */ 1249 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1250 1251 /* Enable interrupts. */ 1252 csr_write_4(sc, SF_IMR, SF_INTRS); 1253 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1254 1255 /* Enable the RX and TX engines. */ 1256 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1257 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1258 1259 /*mii_mediachg(mii);*/ 1260 sf_ifmedia_upd(ifp); 1261 1262 ifp->if_flags |= IFF_RUNNING; 1263 ifp->if_flags &= ~IFF_OACTIVE; 1264 1265 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1266 1267 SF_UNLOCK(sc); 1268 1269 return; 1270} 1271 1272static int 1273sf_encap(sc, c, m_head) 1274 struct sf_softc *sc; 1275 struct sf_tx_bufdesc_type0 *c; 1276 struct mbuf *m_head; 1277{ 1278 int frag = 0; 1279 struct sf_frag *f = NULL; 1280 struct mbuf *m; 1281 1282 m = m_head; 1283 1284 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1285 if (m->m_len != 0) { 1286 if (frag == SF_MAXFRAGS) 1287 break; 1288 f = &c->sf_frags[frag]; 1289 if (frag == 0) 1290 f->sf_pktlen = m_head->m_pkthdr.len; 1291 f->sf_fraglen = m->m_len; 1292 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1293 frag++; 1294 } 1295 } 1296 1297 if (m != NULL) { 1298 struct mbuf *m_new = NULL; 1299 1300 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1301 if (m_new == NULL) { 1302 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1303 return(1); 1304 } 1305 1306 if (m_head->m_pkthdr.len > MHLEN) { 1307 MCLGET(m_new, M_DONTWAIT); 1308 if (!(m_new->m_flags & M_EXT)) { 1309 m_freem(m_new); 1310 printf("sf%d: no memory for tx list\n", 1311 sc->sf_unit); 1312 return(1); 1313 } 1314 } 1315 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1316 mtod(m_new, caddr_t)); 1317 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1318 m_freem(m_head); 1319 m_head = m_new; 1320 f = &c->sf_frags[0]; 1321 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1322 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1323 frag = 1; 1324 } 1325 1326 c->sf_mbuf = m_head; 1327 c->sf_id = SF_TX_BUFDESC_ID; 1328 c->sf_fragcnt = frag; 1329 c->sf_intr = 1; 1330 c->sf_caltcp = 0; 1331 c->sf_crcen = 1; 1332 1333 return(0); 1334} 1335 1336static void 1337sf_start(ifp) 1338 struct ifnet *ifp; 1339{ 1340 struct sf_softc *sc; 1341 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1342 struct mbuf *m_head = NULL; 1343 int i, txprod; 1344 1345 sc = ifp->if_softc; 1346 SF_LOCK(sc); 1347 1348 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1349 SF_UNLOCK(sc); 1350 return; 1351 } 1352 1353 if (ifp->if_flags & IFF_OACTIVE) { 1354 SF_UNLOCK(sc); 1355 return; 1356 } 1357 1358 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1359 i = SF_IDX_HI(txprod) >> 4; 1360 1361 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1362 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1363 sf_init(sc); 1364 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1365 i = SF_IDX_HI(txprod) >> 4; 1366 } 1367 1368 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1369 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1370 ifp->if_flags |= IFF_OACTIVE; 1371 cur_tx = NULL; 1372 break; 1373 } 1374 IF_DEQUEUE(&ifp->if_snd, m_head); 1375 if (m_head == NULL) 1376 break; 1377 1378 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1379 if (sf_encap(sc, cur_tx, m_head)) { 1380 IF_PREPEND(&ifp->if_snd, m_head); 1381 ifp->if_flags |= IFF_OACTIVE; 1382 cur_tx = NULL; 1383 break; 1384 } 1385 1386 /* 1387 * If there's a BPF listener, bounce a copy of this frame 1388 * to him. 1389 */ 1390 BPF_MTAP(ifp, m_head); 1391 1392 SF_INC(i, SF_TX_DLIST_CNT); 1393 sc->sf_tx_cnt++; 1394 /* 1395 * Don't get the TX DMA queue get too full. 1396 */ 1397 if (sc->sf_tx_cnt > 64) 1398 break; 1399 } 1400 1401 if (cur_tx == NULL) { 1402 SF_UNLOCK(sc); 1403 return; 1404 } 1405 1406 /* Transmit */ 1407 csr_write_4(sc, SF_TXDQ_PRODIDX, 1408 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1409 ((i << 20) & 0xFFFF0000)); 1410 1411 ifp->if_timer = 5; 1412 1413 SF_UNLOCK(sc); 1414 1415 return; 1416} 1417 1418static void 1419sf_stop(sc) 1420 struct sf_softc *sc; 1421{ 1422 int i; 1423 struct ifnet *ifp; 1424 1425 SF_LOCK(sc); 1426 1427 ifp = &sc->arpcom.ac_if; 1428 1429 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1430 1431 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1432 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1433 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1434 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1435 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1436 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1437 csr_write_4(sc, SF_TXCQ_CTL, 0); 1438 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1439 csr_write_4(sc, SF_TXDQ_CTL, 0); 1440 sf_reset(sc); 1441 1442 sc->sf_link = 0; 1443 1444 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1445 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1446 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1447 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1448 } 1449 } 1450 1451 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1452 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1453 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1454 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1455 } 1456 } 1457 1458 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1459 SF_UNLOCK(sc); 1460 1461 return; 1462} 1463 1464/* 1465 * Note: it is important that this function not be interrupted. We 1466 * use a two-stage register access scheme: if we are interrupted in 1467 * between setting the indirect address register and reading from the 1468 * indirect data register, the contents of the address register could 1469 * be changed out from under us. 1470 */ 1471static void 1472sf_stats_update(xsc) 1473 void *xsc; 1474{ 1475 struct sf_softc *sc; 1476 struct ifnet *ifp; 1477 struct mii_data *mii; 1478 struct sf_stats stats; 1479 u_int32_t *ptr; 1480 int i; 1481 1482 sc = xsc; 1483 SF_LOCK(sc); 1484 ifp = &sc->arpcom.ac_if; 1485 mii = device_get_softc(sc->sf_miibus); 1486 1487 ptr = (u_int32_t *)&stats; 1488 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1489 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1490 (i + sizeof(u_int32_t))); 1491 1492 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1493 csr_write_4(sc, SF_STATS_BASE + 1494 (i + sizeof(u_int32_t)), 0); 1495 1496 ifp->if_collisions += stats.sf_tx_single_colls + 1497 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1498 1499 mii_tick(mii); 1500 1501 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1502 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1503 sc->sf_link++; 1504 if (ifp->if_snd.ifq_head != NULL) 1505 sf_start(ifp); 1506 } 1507 1508 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1509 1510 SF_UNLOCK(sc); 1511 1512 return; 1513} 1514 1515static void 1516sf_watchdog(ifp) 1517 struct ifnet *ifp; 1518{ 1519 struct sf_softc *sc; 1520 1521 sc = ifp->if_softc; 1522 1523 SF_LOCK(sc); 1524 1525 ifp->if_oerrors++; 1526 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1527 1528 sf_stop(sc); 1529 sf_reset(sc); 1530 sf_init(sc); 1531 1532 if (ifp->if_snd.ifq_head != NULL) 1533 sf_start(ifp); 1534 1535 SF_UNLOCK(sc); 1536 1537 return; 1538} 1539 1540static void 1541sf_shutdown(dev) 1542 device_t dev; 1543{ 1544 struct sf_softc *sc; 1545 1546 sc = device_get_softc(dev); 1547 1548 sf_stop(sc); 1549 1550 return; 1551} 1552