if_sf.c revision 113038
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 35 * Programming manual is available from: 36 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Department of Electical Engineering 40 * Columbia University, New York City 41 */ 42 43/* 44 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 45 * controller designed with flexibility and reducing CPU load in mind. 46 * The Starfire offers high and low priority buffer queues, a 47 * producer/consumer index mechanism and several different buffer 48 * queue and completion queue descriptor types. Any one of a number 49 * of different driver designs can be used, depending on system and 50 * OS requirements. This driver makes use of type0 transmit frame 51 * descriptors (since BSD fragments packets across an mbuf chain) 52 * and two RX buffer queues prioritized on size (one queue for small 53 * frames that will fit into a single mbuf, another with full size 54 * mbuf clusters for everything else). The producer/consumer indexes 55 * and completion queues are also used. 56 * 57 * One downside to the Starfire has to do with alignment: buffer 58 * queues must be aligned on 256-byte boundaries, and receive buffers 59 * must be aligned on longword boundaries. The receive buffer alignment 60 * causes problems on the Alpha platform, where the packet payload 61 * should be longword aligned. There is no simple way around this. 62 * 63 * For receive filtering, the Starfire offers 16 perfect filter slots 64 * and a 512-bit hash table. 65 * 66 * The Starfire has no internal transceiver, relying instead on an 67 * external MII-based transceiver. Accessing registers on external 68 * PHYs is done through a special register map rather than with the 69 * usual bitbang MDIO method. 70 * 71 * Acesssing the registers on the Starfire is a little tricky. The 72 * Starfire has a 512K internal register space. When programmed for 73 * PCI memory mapped mode, the entire register space can be accessed 74 * directly. However in I/O space mode, only 256 bytes are directly 75 * mapped into PCI I/O space. The other registers can be accessed 76 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 77 * registers inside the 256-byte I/O window. 78 */ 79 80#include <sys/cdefs.h> 81__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 113038 2003-04-03 21:36:33Z obrien $"); 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, miibus, 1, 1, 1); 122 123static struct sf_type sf_devs[] = { 124 { AD_VENDORID, AD_DEVICEID_STARFIRE, 125 "Adaptec AIC-6915 10/100BaseTX" }, 126 { 0, 0, NULL } 127}; 128 129static int sf_probe (device_t); 130static int sf_attach (device_t); 131static int sf_detach (device_t); 132static void sf_intr (void *); 133static void sf_stats_update (void *); 134static void sf_rxeof (struct sf_softc *); 135static void sf_txeof (struct sf_softc *); 136static int sf_encap (struct sf_softc *, 137 struct sf_tx_bufdesc_type0 *, 138 struct mbuf *); 139static void sf_start (struct ifnet *); 140static int sf_ioctl (struct ifnet *, u_long, caddr_t); 141static void sf_init (void *); 142static void sf_stop (struct sf_softc *); 143static void sf_watchdog (struct ifnet *); 144static void sf_shutdown (device_t); 145static int sf_ifmedia_upd (struct ifnet *); 146static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 147static void sf_reset (struct sf_softc *); 148static int sf_init_rx_ring (struct sf_softc *); 149static void sf_init_tx_ring (struct sf_softc *); 150static int sf_newbuf (struct sf_softc *, 151 struct sf_rx_bufdesc_type0 *, 152 struct mbuf *); 153static void sf_setmulti (struct sf_softc *); 154static int sf_setperf (struct sf_softc *, int, caddr_t); 155static int sf_sethash (struct sf_softc *, caddr_t, int); 156#ifdef notdef 157static int sf_setvlan (struct sf_softc *, int, u_int32_t); 158#endif 159 160static u_int8_t sf_read_eeprom (struct sf_softc *, int); 161static u_int32_t sf_calchash (caddr_t); 162 163static int sf_miibus_readreg (device_t, int, int); 164static int sf_miibus_writereg (device_t, int, int, int); 165static void sf_miibus_statchg (device_t); 166 167static u_int32_t csr_read_4 (struct sf_softc *, int); 168static void csr_write_4 (struct sf_softc *, int, u_int32_t); 169static void sf_txthresh_adjust (struct sf_softc *); 170 171#ifdef SF_USEIOSPACE 172#define SF_RES SYS_RES_IOPORT 173#define SF_RID SF_PCI_LOIO 174#else 175#define SF_RES SYS_RES_MEMORY 176#define SF_RID SF_PCI_LOMEM 177#endif 178 179static device_method_t sf_methods[] = { 180 /* Device interface */ 181 DEVMETHOD(device_probe, sf_probe), 182 DEVMETHOD(device_attach, sf_attach), 183 DEVMETHOD(device_detach, sf_detach), 184 DEVMETHOD(device_shutdown, sf_shutdown), 185 186 /* bus interface */ 187 DEVMETHOD(bus_print_child, bus_generic_print_child), 188 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 189 190 /* MII interface */ 191 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 192 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 193 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 194 195 { 0, 0 } 196}; 197 198static driver_t sf_driver = { 199 "sf", 200 sf_methods, 201 sizeof(struct sf_softc), 202}; 203 204static devclass_t sf_devclass; 205 206DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 207DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 208 209#define SF_SETBIT(sc, reg, x) \ 210 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 211 212#define SF_CLRBIT(sc, reg, x) \ 213 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 214 215static u_int32_t 216csr_read_4(sc, reg) 217 struct sf_softc *sc; 218 int reg; 219{ 220 u_int32_t val; 221 222#ifdef SF_USEIOSPACE 223 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 224 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 225#else 226 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 227#endif 228 229 return(val); 230} 231 232static u_int8_t 233sf_read_eeprom(sc, reg) 234 struct sf_softc *sc; 235 int reg; 236{ 237 u_int8_t val; 238 239 val = (csr_read_4(sc, SF_EEADDR_BASE + 240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 241 242 return(val); 243} 244 245static void 246csr_write_4(sc, reg, val) 247 struct sf_softc *sc; 248 int reg; 249 u_int32_t val; 250{ 251#ifdef SF_USEIOSPACE 252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 254#else 255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 256#endif 257 return; 258} 259 260static u_int32_t 261sf_calchash(addr) 262 caddr_t addr; 263{ 264 u_int32_t crc, carry; 265 int i, j; 266 u_int8_t c; 267 268 /* Compute CRC for the address value. */ 269 crc = 0xFFFFFFFF; /* initial value */ 270 271 for (i = 0; i < 6; i++) { 272 c = *(addr + i); 273 for (j = 0; j < 8; j++) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 275 crc <<= 1; 276 c >>= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int 292sf_setperf(sc, idx, mac) 293 struct sf_softc *sc; 294 int idx; 295 caddr_t mac; 296{ 297 u_int16_t *p; 298 299 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 300 return(EINVAL); 301 302 if (mac == NULL) 303 return(EINVAL); 304 305 p = (u_int16_t *)mac; 306 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 313 314 return(0); 315} 316 317/* 318 * Set the bit in the 512-bit hash table that corresponds to the 319 * specified mac address 'mac.' If 'prio' is nonzero, update the 320 * priority hash table instead of the filter hash table. 321 */ 322static int 323sf_sethash(sc, mac, prio) 324 struct sf_softc *sc; 325 caddr_t mac; 326 int prio; 327{ 328 u_int32_t h = 0; 329 330 if (mac == NULL) 331 return(EINVAL); 332 333 h = sf_calchash(mac); 334 335 if (prio) { 336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 338 } else { 339 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 340 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 341 } 342 343 return(0); 344} 345 346#ifdef notdef 347/* 348 * Set a VLAN tag in the receive filter. 349 */ 350static int 351sf_setvlan(sc, idx, vlan) 352 struct sf_softc *sc; 353 int idx; 354 u_int32_t vlan; 355{ 356 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 357 return(EINVAL); 358 359 csr_write_4(sc, SF_RXFILT_HASH_BASE + 360 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 361 362 return(0); 363} 364#endif 365 366static int 367sf_miibus_readreg(dev, phy, reg) 368 device_t dev; 369 int phy, reg; 370{ 371 struct sf_softc *sc; 372 int i; 373 u_int32_t val = 0; 374 375 sc = device_get_softc(dev); 376 377 for (i = 0; i < SF_TIMEOUT; i++) { 378 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 379 if (val & SF_MII_DATAVALID) 380 break; 381 } 382 383 if (i == SF_TIMEOUT) 384 return(0); 385 386 if ((val & 0x0000FFFF) == 0xFFFF) 387 return(0); 388 389 return(val & 0x0000FFFF); 390} 391 392static int 393sf_miibus_writereg(dev, phy, reg, val) 394 device_t dev; 395 int phy, reg, val; 396{ 397 struct sf_softc *sc; 398 int i; 399 int busy; 400 401 sc = device_get_softc(dev); 402 403 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 404 405 for (i = 0; i < SF_TIMEOUT; i++) { 406 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 407 if (!(busy & SF_MII_BUSY)) 408 break; 409 } 410 411 return(0); 412} 413 414static void 415sf_miibus_statchg(dev) 416 device_t dev; 417{ 418 struct sf_softc *sc; 419 struct mii_data *mii; 420 421 sc = device_get_softc(dev); 422 mii = device_get_softc(sc->sf_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 426 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 427 } else { 428 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 429 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 430 } 431 432 return; 433} 434 435static void 436sf_setmulti(sc) 437 struct sf_softc *sc; 438{ 439 struct ifnet *ifp; 440 int i; 441 struct ifmultiaddr *ifma; 442 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 443 444 ifp = &sc->arpcom.ac_if; 445 446 /* First zot all the existing filters. */ 447 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 448 sf_setperf(sc, i, (char *)&dummy); 449 for (i = SF_RXFILT_HASH_BASE; 450 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 451 csr_write_4(sc, i, 0); 452 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 453 454 /* Now program new ones. */ 455 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 456 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 457 } else { 458 i = 1; 459 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 460 if (ifma->ifma_addr->sa_family != AF_LINK) 461 continue; 462 /* 463 * Program the first 15 multicast groups 464 * into the perfect filter. For all others, 465 * use the hash table. 466 */ 467 if (i < SF_RXFILT_PERFECT_CNT) { 468 sf_setperf(sc, i, 469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 470 i++; 471 continue; 472 } 473 474 sf_sethash(sc, 475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 476 } 477 } 478 479 return; 480} 481 482/* 483 * Set media options. 484 */ 485static int 486sf_ifmedia_upd(ifp) 487 struct ifnet *ifp; 488{ 489 struct sf_softc *sc; 490 struct mii_data *mii; 491 492 sc = ifp->if_softc; 493 mii = device_get_softc(sc->sf_miibus); 494 sc->sf_link = 0; 495 if (mii->mii_instance) { 496 struct mii_softc *miisc; 497 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 498 mii_phy_reset(miisc); 499 } 500 mii_mediachg(mii); 501 502 return(0); 503} 504 505/* 506 * Report current media status. 507 */ 508static void 509sf_ifmedia_sts(ifp, ifmr) 510 struct ifnet *ifp; 511 struct ifmediareq *ifmr; 512{ 513 struct sf_softc *sc; 514 struct mii_data *mii; 515 516 sc = ifp->if_softc; 517 mii = device_get_softc(sc->sf_miibus); 518 519 mii_pollstat(mii); 520 ifmr->ifm_active = mii->mii_media_active; 521 ifmr->ifm_status = mii->mii_media_status; 522 523 return; 524} 525 526static int 527sf_ioctl(ifp, command, data) 528 struct ifnet *ifp; 529 u_long command; 530 caddr_t data; 531{ 532 struct sf_softc *sc = ifp->if_softc; 533 struct ifreq *ifr = (struct ifreq *) data; 534 struct mii_data *mii; 535 int error = 0; 536 537 SF_LOCK(sc); 538 539 switch(command) { 540 case SIOCSIFFLAGS: 541 if (ifp->if_flags & IFF_UP) { 542 if (ifp->if_flags & IFF_RUNNING && 543 ifp->if_flags & IFF_PROMISC && 544 !(sc->sf_if_flags & IFF_PROMISC)) { 545 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 546 } else if (ifp->if_flags & IFF_RUNNING && 547 !(ifp->if_flags & IFF_PROMISC) && 548 sc->sf_if_flags & IFF_PROMISC) { 549 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 550 } else if (!(ifp->if_flags & IFF_RUNNING)) 551 sf_init(sc); 552 } else { 553 if (ifp->if_flags & IFF_RUNNING) 554 sf_stop(sc); 555 } 556 sc->sf_if_flags = ifp->if_flags; 557 error = 0; 558 break; 559 case SIOCADDMULTI: 560 case SIOCDELMULTI: 561 sf_setmulti(sc); 562 error = 0; 563 break; 564 case SIOCGIFMEDIA: 565 case SIOCSIFMEDIA: 566 mii = device_get_softc(sc->sf_miibus); 567 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 568 break; 569 default: 570 error = ether_ioctl(ifp, command, data); 571 break; 572 } 573 574 SF_UNLOCK(sc); 575 576 return(error); 577} 578 579static void 580sf_reset(sc) 581 struct sf_softc *sc; 582{ 583 register int i; 584 585 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 586 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 587 DELAY(1000); 588 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 590 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 591 592 for (i = 0; i < SF_TIMEOUT; i++) { 593 DELAY(10); 594 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 595 break; 596 } 597 598 if (i == SF_TIMEOUT) 599 printf("sf%d: reset never completed!\n", sc->sf_unit); 600 601 /* Wait a little while for the chip to get its brains in order. */ 602 DELAY(1000); 603 return; 604} 605 606/* 607 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 608 * IDs against our list and return a device name if we find a match. 609 * We also check the subsystem ID so that we can identify exactly which 610 * NIC has been found, if possible. 611 */ 612static int 613sf_probe(dev) 614 device_t dev; 615{ 616 struct sf_type *t; 617 618 t = sf_devs; 619 620 while(t->sf_name != NULL) { 621 if ((pci_get_vendor(dev) == t->sf_vid) && 622 (pci_get_device(dev) == t->sf_did)) { 623 switch((pci_read_config(dev, 624 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 625 case AD_SUBSYSID_62011_REV0: 626 case AD_SUBSYSID_62011_REV1: 627 device_set_desc(dev, 628 "Adaptec ANA-62011 10/100BaseTX"); 629 return(0); 630 break; 631 case AD_SUBSYSID_62022: 632 device_set_desc(dev, 633 "Adaptec ANA-62022 10/100BaseTX"); 634 return(0); 635 break; 636 case AD_SUBSYSID_62044_REV0: 637 case AD_SUBSYSID_62044_REV1: 638 device_set_desc(dev, 639 "Adaptec ANA-62044 10/100BaseTX"); 640 return(0); 641 break; 642 case AD_SUBSYSID_62020: 643 device_set_desc(dev, 644 "Adaptec ANA-62020 10/100BaseFX"); 645 return(0); 646 break; 647 case AD_SUBSYSID_69011: 648 device_set_desc(dev, 649 "Adaptec ANA-69011 10/100BaseTX"); 650 return(0); 651 break; 652 default: 653 device_set_desc(dev, t->sf_name); 654 return(0); 655 break; 656 } 657 } 658 t++; 659 } 660 661 return(ENXIO); 662} 663 664/* 665 * Attach the interface. Allocate softc structures, do ifmedia 666 * setup and ethernet/BPF attach. 667 */ 668static int 669sf_attach(dev) 670 device_t dev; 671{ 672 int i; 673 u_int32_t command; 674 struct sf_softc *sc; 675 struct ifnet *ifp; 676 int unit, rid, error = 0; 677 678 sc = device_get_softc(dev); 679 unit = device_get_unit(dev); 680 681 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 682 MTX_DEF | MTX_RECURSE); 683 684 /* 685 * Handle power management nonsense. 686 */ 687 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 688 u_int32_t iobase, membase, irq; 689 690 /* Save important PCI config data. */ 691 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 692 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 693 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 694 695 /* Reset the power state. */ 696 printf("sf%d: chip is in D%d power mode " 697 "-- setting to D0\n", unit, 698 pci_get_powerstate(dev)); 699 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 700 701 /* Restore PCI config data. */ 702 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 703 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 704 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 705 } 706 707 /* 708 * Map control/status registers. 709 */ 710 pci_enable_busmaster(dev); 711 pci_enable_io(dev, SYS_RES_IOPORT); 712 pci_enable_io(dev, SYS_RES_MEMORY); 713 command = pci_read_config(dev, PCIR_COMMAND, 4); 714 715#ifdef SF_USEIOSPACE 716 if (!(command & PCIM_CMD_PORTEN)) { 717 printf("sf%d: failed to enable I/O ports!\n", unit); 718 error = ENXIO; 719 goto fail; 720 } 721#else 722 if (!(command & PCIM_CMD_MEMEN)) { 723 printf("sf%d: failed to enable memory mapping!\n", unit); 724 error = ENXIO; 725 goto fail; 726 } 727#endif 728 729 rid = SF_RID; 730 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 731 0, ~0, 1, RF_ACTIVE); 732 733 if (sc->sf_res == NULL) { 734 printf ("sf%d: couldn't map ports\n", unit); 735 error = ENXIO; 736 goto fail; 737 } 738 739 sc->sf_btag = rman_get_bustag(sc->sf_res); 740 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 741 742 /* Allocate interrupt */ 743 rid = 0; 744 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 745 RF_SHAREABLE | RF_ACTIVE); 746 747 if (sc->sf_irq == NULL) { 748 printf("sf%d: couldn't map interrupt\n", unit); 749 error = ENXIO; 750 goto fail; 751 } 752 753 callout_handle_init(&sc->sf_stat_ch); 754 /* Reset the adapter. */ 755 sf_reset(sc); 756 757 /* 758 * Get station address from the EEPROM. 759 */ 760 for (i = 0; i < ETHER_ADDR_LEN; i++) 761 sc->arpcom.ac_enaddr[i] = 762 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 763 764 /* 765 * An Adaptec chip was detected. Inform the world. 766 */ 767 printf("sf%d: Ethernet address: %6D\n", unit, 768 sc->arpcom.ac_enaddr, ":"); 769 770 sc->sf_unit = unit; 771 772 /* Allocate the descriptor queues. */ 773 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 774 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 775 776 if (sc->sf_ldata == NULL) { 777 printf("sf%d: no memory for list buffers!\n", unit); 778 error = ENXIO; 779 goto fail; 780 } 781 782 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 783 784 /* Do MII setup. */ 785 if (mii_phy_probe(dev, &sc->sf_miibus, 786 sf_ifmedia_upd, sf_ifmedia_sts)) { 787 printf("sf%d: MII without any phy!\n", sc->sf_unit); 788 error = ENXIO; 789 goto fail; 790 } 791 792 ifp = &sc->arpcom.ac_if; 793 ifp->if_softc = sc; 794 ifp->if_unit = unit; 795 ifp->if_name = "sf"; 796 ifp->if_mtu = ETHERMTU; 797 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 798 ifp->if_ioctl = sf_ioctl; 799 ifp->if_output = ether_output; 800 ifp->if_start = sf_start; 801 ifp->if_watchdog = sf_watchdog; 802 ifp->if_init = sf_init; 803 ifp->if_baudrate = 10000000; 804 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 805 806 /* 807 * Call MI attach routine. 808 */ 809 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 810 811 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 812 sf_intr, sc, &sc->sf_intrhand); 813 814 if (error) { 815 printf("sf%d: couldn't set up irq\n", unit); 816 goto fail; 817 } 818 819fail: 820 if (error) 821 sf_detach(dev); 822 823 return(error); 824} 825 826static int 827sf_detach(dev) 828 device_t dev; 829{ 830 struct sf_softc *sc; 831 struct ifnet *ifp; 832 833 sc = device_get_softc(dev); 834 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 835 SF_LOCK(sc); 836 ifp = &sc->arpcom.ac_if; 837 838 if (device_is_alive(dev)) { 839 if (bus_child_present(dev)) 840 sf_stop(sc); 841 ether_ifdetach(ifp); 842 device_delete_child(dev, sc->sf_miibus); 843 bus_generic_detach(dev); 844 } 845 846 if (sc->sf_intrhand) 847 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 848 if (sc->sf_irq) 849 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 850 if (sc->sf_res) 851 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 852 853 if (sc->sf_ldata) 854 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 855 856 SF_UNLOCK(sc); 857 mtx_destroy(&sc->sf_mtx); 858 859 return(0); 860} 861 862static int 863sf_init_rx_ring(sc) 864 struct sf_softc *sc; 865{ 866 struct sf_list_data *ld; 867 int i; 868 869 ld = sc->sf_ldata; 870 871 bzero((char *)ld->sf_rx_dlist_big, 872 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 873 bzero((char *)ld->sf_rx_clist, 874 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 875 876 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 877 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 878 return(ENOBUFS); 879 } 880 881 return(0); 882} 883 884static void 885sf_init_tx_ring(sc) 886 struct sf_softc *sc; 887{ 888 struct sf_list_data *ld; 889 int i; 890 891 ld = sc->sf_ldata; 892 893 bzero((char *)ld->sf_tx_dlist, 894 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 895 bzero((char *)ld->sf_tx_clist, 896 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 897 898 for (i = 0; i < SF_TX_DLIST_CNT; i++) 899 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 900 for (i = 0; i < SF_TX_CLIST_CNT; i++) 901 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 902 903 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 904 sc->sf_tx_cnt = 0; 905 906 return; 907} 908 909static int 910sf_newbuf(sc, c, m) 911 struct sf_softc *sc; 912 struct sf_rx_bufdesc_type0 *c; 913 struct mbuf *m; 914{ 915 struct mbuf *m_new = NULL; 916 917 if (m == NULL) { 918 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 919 if (m_new == NULL) 920 return(ENOBUFS); 921 922 MCLGET(m_new, M_DONTWAIT); 923 if (!(m_new->m_flags & M_EXT)) { 924 m_freem(m_new); 925 return(ENOBUFS); 926 } 927 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 928 } else { 929 m_new = m; 930 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 931 m_new->m_data = m_new->m_ext.ext_buf; 932 } 933 934 m_adj(m_new, sizeof(u_int64_t)); 935 936 c->sf_mbuf = m_new; 937 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 938 c->sf_valid = 1; 939 940 return(0); 941} 942 943/* 944 * The starfire is programmed to use 'normal' mode for packet reception, 945 * which means we use the consumer/producer model for both the buffer 946 * descriptor queue and the completion descriptor queue. The only problem 947 * with this is that it involves a lot of register accesses: we have to 948 * read the RX completion consumer and producer indexes and the RX buffer 949 * producer index, plus the RX completion consumer and RX buffer producer 950 * indexes have to be updated. It would have been easier if Adaptec had 951 * put each index in a separate register, especially given that the damn 952 * NIC has a 512K register space. 953 * 954 * In spite of all the lovely features that Adaptec crammed into the 6915, 955 * it is marred by one truly stupid design flaw, which is that receive 956 * buffer addresses must be aligned on a longword boundary. This forces 957 * the packet payload to be unaligned, which is suboptimal on the x86 and 958 * completely unuseable on the Alpha. Our only recourse is to copy received 959 * packets into properly aligned buffers before handing them off. 960 */ 961 962static void 963sf_rxeof(sc) 964 struct sf_softc *sc; 965{ 966 struct mbuf *m; 967 struct ifnet *ifp; 968 struct sf_rx_bufdesc_type0 *desc; 969 struct sf_rx_cmpdesc_type3 *cur_rx; 970 u_int32_t rxcons, rxprod; 971 int cmpprodidx, cmpconsidx, bufprodidx; 972 973 ifp = &sc->arpcom.ac_if; 974 975 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 976 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 977 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 978 cmpconsidx = SF_IDX_LO(rxcons); 979 bufprodidx = SF_IDX_LO(rxprod); 980 981 while (cmpconsidx != cmpprodidx) { 982 struct mbuf *m0; 983 984 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 985 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 986 m = desc->sf_mbuf; 987 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 988 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 989 990 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 991 ifp->if_ierrors++; 992 sf_newbuf(sc, desc, m); 993 continue; 994 } 995 996 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 997 ifp, NULL); 998 sf_newbuf(sc, desc, m); 999 if (m0 == NULL) { 1000 ifp->if_ierrors++; 1001 continue; 1002 } 1003 m = m0; 1004 1005 ifp->if_ipackets++; 1006 (*ifp->if_input)(ifp, m); 1007 } 1008 1009 csr_write_4(sc, SF_CQ_CONSIDX, 1010 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1011 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1012 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1013 1014 return; 1015} 1016 1017/* 1018 * Read the transmit status from the completion queue and release 1019 * mbufs. Note that the buffer descriptor index in the completion 1020 * descriptor is an offset from the start of the transmit buffer 1021 * descriptor list in bytes. This is important because the manual 1022 * gives the impression that it should match the producer/consumer 1023 * index, which is the offset in 8 byte blocks. 1024 */ 1025static void 1026sf_txeof(sc) 1027 struct sf_softc *sc; 1028{ 1029 int txcons, cmpprodidx, cmpconsidx; 1030 struct sf_tx_cmpdesc_type1 *cur_cmp; 1031 struct sf_tx_bufdesc_type0 *cur_tx; 1032 struct ifnet *ifp; 1033 1034 ifp = &sc->arpcom.ac_if; 1035 1036 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1037 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1038 cmpconsidx = SF_IDX_HI(txcons); 1039 1040 while (cmpconsidx != cmpprodidx) { 1041 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1042 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1043 1044 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1045 ifp->if_opackets++; 1046 else { 1047 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1048 sf_txthresh_adjust(sc); 1049 ifp->if_oerrors++; 1050 } 1051 1052 sc->sf_tx_cnt--; 1053 if (cur_tx->sf_mbuf != NULL) { 1054 m_freem(cur_tx->sf_mbuf); 1055 cur_tx->sf_mbuf = NULL; 1056 } else 1057 break; 1058 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1059 } 1060 1061 ifp->if_timer = 0; 1062 ifp->if_flags &= ~IFF_OACTIVE; 1063 1064 csr_write_4(sc, SF_CQ_CONSIDX, 1065 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1066 ((cmpconsidx << 16) & 0xFFFF0000)); 1067 1068 return; 1069} 1070 1071static void 1072sf_txthresh_adjust(sc) 1073 struct sf_softc *sc; 1074{ 1075 u_int32_t txfctl; 1076 u_int8_t txthresh; 1077 1078 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1079 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1080 if (txthresh < 0xFF) { 1081 txthresh++; 1082 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1083 txfctl |= txthresh; 1084#ifdef DIAGNOSTIC 1085 printf("sf%d: tx underrun, increasing " 1086 "tx threshold to %d bytes\n", 1087 sc->sf_unit, txthresh * 4); 1088#endif 1089 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1090 } 1091 1092 return; 1093} 1094 1095static void 1096sf_intr(arg) 1097 void *arg; 1098{ 1099 struct sf_softc *sc; 1100 struct ifnet *ifp; 1101 u_int32_t status; 1102 1103 sc = arg; 1104 SF_LOCK(sc); 1105 1106 ifp = &sc->arpcom.ac_if; 1107 1108 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1109 SF_UNLOCK(sc); 1110 return; 1111 } 1112 1113 /* Disable interrupts. */ 1114 csr_write_4(sc, SF_IMR, 0x00000000); 1115 1116 for (;;) { 1117 status = csr_read_4(sc, SF_ISR); 1118 if (status) 1119 csr_write_4(sc, SF_ISR, status); 1120 1121 if (!(status & SF_INTRS)) 1122 break; 1123 1124 if (status & SF_ISR_RXDQ1_DMADONE) 1125 sf_rxeof(sc); 1126 1127 if (status & SF_ISR_TX_TXDONE || 1128 status & SF_ISR_TX_DMADONE || 1129 status & SF_ISR_TX_QUEUEDONE) 1130 sf_txeof(sc); 1131 1132 if (status & SF_ISR_TX_LOFIFO) 1133 sf_txthresh_adjust(sc); 1134 1135 if (status & SF_ISR_ABNORMALINTR) { 1136 if (status & SF_ISR_STATSOFLOW) { 1137 untimeout(sf_stats_update, sc, 1138 sc->sf_stat_ch); 1139 sf_stats_update(sc); 1140 } else 1141 sf_init(sc); 1142 } 1143 } 1144 1145 /* Re-enable interrupts. */ 1146 csr_write_4(sc, SF_IMR, SF_INTRS); 1147 1148 if (ifp->if_snd.ifq_head != NULL) 1149 sf_start(ifp); 1150 1151 SF_UNLOCK(sc); 1152 return; 1153} 1154 1155static void 1156sf_init(xsc) 1157 void *xsc; 1158{ 1159 struct sf_softc *sc; 1160 struct ifnet *ifp; 1161 struct mii_data *mii; 1162 int i; 1163 1164 sc = xsc; 1165 SF_LOCK(sc); 1166 ifp = &sc->arpcom.ac_if; 1167 mii = device_get_softc(sc->sf_miibus); 1168 1169 sf_stop(sc); 1170 sf_reset(sc); 1171 1172 /* Init all the receive filter registers */ 1173 for (i = SF_RXFILT_PERFECT_BASE; 1174 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1175 csr_write_4(sc, i, 0); 1176 1177 /* Empty stats counter registers. */ 1178 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1179 csr_write_4(sc, SF_STATS_BASE + 1180 (i + sizeof(u_int32_t)), 0); 1181 1182 /* Init our MAC address */ 1183 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1184 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1185 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1186 1187 if (sf_init_rx_ring(sc) == ENOBUFS) { 1188 printf("sf%d: initialization failed: no " 1189 "memory for rx buffers\n", sc->sf_unit); 1190 SF_UNLOCK(sc); 1191 return; 1192 } 1193 1194 sf_init_tx_ring(sc); 1195 1196 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1197 1198 /* If we want promiscuous mode, set the allframes bit. */ 1199 if (ifp->if_flags & IFF_PROMISC) { 1200 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1201 } else { 1202 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1203 } 1204 1205 if (ifp->if_flags & IFF_BROADCAST) { 1206 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1207 } else { 1208 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1209 } 1210 1211 /* 1212 * Load the multicast filter. 1213 */ 1214 sf_setmulti(sc); 1215 1216 /* Init the completion queue indexes */ 1217 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1218 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1219 1220 /* Init the RX completion queue */ 1221 csr_write_4(sc, SF_RXCQ_CTL_1, 1222 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1223 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1224 1225 /* Init RX DMA control. */ 1226 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1227 1228 /* Init the RX buffer descriptor queue. */ 1229 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1230 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1231 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1232 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1233 1234 /* Init the TX completion queue */ 1235 csr_write_4(sc, SF_TXCQ_CTL, 1236 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1237 1238 /* Init the TX buffer descriptor queue. */ 1239 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1240 vtophys(sc->sf_ldata->sf_tx_dlist)); 1241 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1242 csr_write_4(sc, SF_TXDQ_CTL, 1243 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1244 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1245 1246 /* Enable autopadding of short TX frames. */ 1247 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1248 1249 /* Enable interrupts. */ 1250 csr_write_4(sc, SF_IMR, SF_INTRS); 1251 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1252 1253 /* Enable the RX and TX engines. */ 1254 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1255 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1256 1257 /*mii_mediachg(mii);*/ 1258 sf_ifmedia_upd(ifp); 1259 1260 ifp->if_flags |= IFF_RUNNING; 1261 ifp->if_flags &= ~IFF_OACTIVE; 1262 1263 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1264 1265 SF_UNLOCK(sc); 1266 1267 return; 1268} 1269 1270static int 1271sf_encap(sc, c, m_head) 1272 struct sf_softc *sc; 1273 struct sf_tx_bufdesc_type0 *c; 1274 struct mbuf *m_head; 1275{ 1276 int frag = 0; 1277 struct sf_frag *f = NULL; 1278 struct mbuf *m; 1279 1280 m = m_head; 1281 1282 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1283 if (m->m_len != 0) { 1284 if (frag == SF_MAXFRAGS) 1285 break; 1286 f = &c->sf_frags[frag]; 1287 if (frag == 0) 1288 f->sf_pktlen = m_head->m_pkthdr.len; 1289 f->sf_fraglen = m->m_len; 1290 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1291 frag++; 1292 } 1293 } 1294 1295 if (m != NULL) { 1296 struct mbuf *m_new = NULL; 1297 1298 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1299 if (m_new == NULL) { 1300 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1301 return(1); 1302 } 1303 1304 if (m_head->m_pkthdr.len > MHLEN) { 1305 MCLGET(m_new, M_DONTWAIT); 1306 if (!(m_new->m_flags & M_EXT)) { 1307 m_freem(m_new); 1308 printf("sf%d: no memory for tx list\n", 1309 sc->sf_unit); 1310 return(1); 1311 } 1312 } 1313 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1314 mtod(m_new, caddr_t)); 1315 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1316 m_freem(m_head); 1317 m_head = m_new; 1318 f = &c->sf_frags[0]; 1319 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1320 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1321 frag = 1; 1322 } 1323 1324 c->sf_mbuf = m_head; 1325 c->sf_id = SF_TX_BUFDESC_ID; 1326 c->sf_fragcnt = frag; 1327 c->sf_intr = 1; 1328 c->sf_caltcp = 0; 1329 c->sf_crcen = 1; 1330 1331 return(0); 1332} 1333 1334static void 1335sf_start(ifp) 1336 struct ifnet *ifp; 1337{ 1338 struct sf_softc *sc; 1339 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1340 struct mbuf *m_head = NULL; 1341 int i, txprod; 1342 1343 sc = ifp->if_softc; 1344 SF_LOCK(sc); 1345 1346 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1347 SF_UNLOCK(sc); 1348 return; 1349 } 1350 1351 if (ifp->if_flags & IFF_OACTIVE) { 1352 SF_UNLOCK(sc); 1353 return; 1354 } 1355 1356 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1357 i = SF_IDX_HI(txprod) >> 4; 1358 1359 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1360 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1361 sf_init(sc); 1362 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1363 i = SF_IDX_HI(txprod) >> 4; 1364 } 1365 1366 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1367 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1368 ifp->if_flags |= IFF_OACTIVE; 1369 cur_tx = NULL; 1370 break; 1371 } 1372 IF_DEQUEUE(&ifp->if_snd, m_head); 1373 if (m_head == NULL) 1374 break; 1375 1376 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1377 if (sf_encap(sc, cur_tx, m_head)) { 1378 IF_PREPEND(&ifp->if_snd, m_head); 1379 ifp->if_flags |= IFF_OACTIVE; 1380 cur_tx = NULL; 1381 break; 1382 } 1383 1384 /* 1385 * If there's a BPF listener, bounce a copy of this frame 1386 * to him. 1387 */ 1388 BPF_MTAP(ifp, m_head); 1389 1390 SF_INC(i, SF_TX_DLIST_CNT); 1391 sc->sf_tx_cnt++; 1392 /* 1393 * Don't get the TX DMA queue get too full. 1394 */ 1395 if (sc->sf_tx_cnt > 64) 1396 break; 1397 } 1398 1399 if (cur_tx == NULL) { 1400 SF_UNLOCK(sc); 1401 return; 1402 } 1403 1404 /* Transmit */ 1405 csr_write_4(sc, SF_TXDQ_PRODIDX, 1406 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1407 ((i << 20) & 0xFFFF0000)); 1408 1409 ifp->if_timer = 5; 1410 1411 SF_UNLOCK(sc); 1412 1413 return; 1414} 1415 1416static void 1417sf_stop(sc) 1418 struct sf_softc *sc; 1419{ 1420 int i; 1421 struct ifnet *ifp; 1422 1423 SF_LOCK(sc); 1424 1425 ifp = &sc->arpcom.ac_if; 1426 1427 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1428 1429 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1430 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1431 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1432 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1433 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1434 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1435 csr_write_4(sc, SF_TXCQ_CTL, 0); 1436 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1437 csr_write_4(sc, SF_TXDQ_CTL, 0); 1438 sf_reset(sc); 1439 1440 sc->sf_link = 0; 1441 1442 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1443 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1444 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1445 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1446 } 1447 } 1448 1449 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1450 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1451 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1452 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1453 } 1454 } 1455 1456 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1457 SF_UNLOCK(sc); 1458 1459 return; 1460} 1461 1462/* 1463 * Note: it is important that this function not be interrupted. We 1464 * use a two-stage register access scheme: if we are interrupted in 1465 * between setting the indirect address register and reading from the 1466 * indirect data register, the contents of the address register could 1467 * be changed out from under us. 1468 */ 1469static void 1470sf_stats_update(xsc) 1471 void *xsc; 1472{ 1473 struct sf_softc *sc; 1474 struct ifnet *ifp; 1475 struct mii_data *mii; 1476 struct sf_stats stats; 1477 u_int32_t *ptr; 1478 int i; 1479 1480 sc = xsc; 1481 SF_LOCK(sc); 1482 ifp = &sc->arpcom.ac_if; 1483 mii = device_get_softc(sc->sf_miibus); 1484 1485 ptr = (u_int32_t *)&stats; 1486 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1487 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1488 (i + sizeof(u_int32_t))); 1489 1490 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1491 csr_write_4(sc, SF_STATS_BASE + 1492 (i + sizeof(u_int32_t)), 0); 1493 1494 ifp->if_collisions += stats.sf_tx_single_colls + 1495 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1496 1497 mii_tick(mii); 1498 1499 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1500 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1501 sc->sf_link++; 1502 if (ifp->if_snd.ifq_head != NULL) 1503 sf_start(ifp); 1504 } 1505 1506 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1507 1508 SF_UNLOCK(sc); 1509 1510 return; 1511} 1512 1513static void 1514sf_watchdog(ifp) 1515 struct ifnet *ifp; 1516{ 1517 struct sf_softc *sc; 1518 1519 sc = ifp->if_softc; 1520 1521 SF_LOCK(sc); 1522 1523 ifp->if_oerrors++; 1524 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1525 1526 sf_stop(sc); 1527 sf_reset(sc); 1528 sf_init(sc); 1529 1530 if (ifp->if_snd.ifq_head != NULL) 1531 sf_start(ifp); 1532 1533 SF_UNLOCK(sc); 1534 1535 return; 1536} 1537 1538static void 1539sf_shutdown(dev) 1540 device_t dev; 1541{ 1542 struct sf_softc *sc; 1543 1544 sc = device_get_softc(dev); 1545 1546 sf_stop(sc); 1547 1548 return; 1549} 1550