if_sf.c revision 112872
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 112872 2003-03-31 17:29:43Z njl $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, miibus, 1, 1, 1); 121 122#ifndef lint 123static const char rcsid[] = 124 "$FreeBSD: head/sys/dev/sf/if_sf.c 112872 2003-03-31 17:29:43Z njl $"; 125#endif 126 127static struct sf_type sf_devs[] = { 128 { AD_VENDORID, AD_DEVICEID_STARFIRE, 129 "Adaptec AIC-6915 10/100BaseTX" }, 130 { 0, 0, NULL } 131}; 132 133static int sf_probe (device_t); 134static int sf_attach (device_t); 135static int sf_detach (device_t); 136static void sf_intr (void *); 137static void sf_stats_update (void *); 138static void sf_rxeof (struct sf_softc *); 139static void sf_txeof (struct sf_softc *); 140static int sf_encap (struct sf_softc *, 141 struct sf_tx_bufdesc_type0 *, 142 struct mbuf *); 143static void sf_start (struct ifnet *); 144static int sf_ioctl (struct ifnet *, u_long, caddr_t); 145static void sf_init (void *); 146static void sf_stop (struct sf_softc *); 147static void sf_watchdog (struct ifnet *); 148static void sf_shutdown (device_t); 149static int sf_ifmedia_upd (struct ifnet *); 150static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151static void sf_reset (struct sf_softc *); 152static int sf_init_rx_ring (struct sf_softc *); 153static void sf_init_tx_ring (struct sf_softc *); 154static int sf_newbuf (struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *); 157static void sf_setmulti (struct sf_softc *); 158static int sf_setperf (struct sf_softc *, int, caddr_t); 159static int sf_sethash (struct sf_softc *, caddr_t, int); 160#ifdef notdef 161static int sf_setvlan (struct sf_softc *, int, u_int32_t); 162#endif 163 164static u_int8_t sf_read_eeprom (struct sf_softc *, int); 165static u_int32_t sf_calchash (caddr_t); 166 167static int sf_miibus_readreg (device_t, int, int); 168static int sf_miibus_writereg (device_t, int, int, int); 169static void sf_miibus_statchg (device_t); 170 171static u_int32_t csr_read_4 (struct sf_softc *, int); 172static void csr_write_4 (struct sf_softc *, int, u_int32_t); 173static void sf_txthresh_adjust (struct sf_softc *); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 218 219static u_int32_t 220csr_read_4(sc, reg) 221 struct sf_softc *sc; 222 int reg; 223{ 224 u_int32_t val; 225 226#ifdef SF_USEIOSPACE 227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 229#else 230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 231#endif 232 233 return(val); 234} 235 236static u_int8_t 237sf_read_eeprom(sc, reg) 238 struct sf_softc *sc; 239 int reg; 240{ 241 u_int8_t val; 242 243 val = (csr_read_4(sc, SF_EEADDR_BASE + 244 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 245 246 return(val); 247} 248 249static void 250csr_write_4(sc, reg, val) 251 struct sf_softc *sc; 252 int reg; 253 u_int32_t val; 254{ 255#ifdef SF_USEIOSPACE 256 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 257 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 258#else 259 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 260#endif 261 return; 262} 263 264static u_int32_t 265sf_calchash(addr) 266 caddr_t addr; 267{ 268 u_int32_t crc, carry; 269 int i, j; 270 u_int8_t c; 271 272 /* Compute CRC for the address value. */ 273 crc = 0xFFFFFFFF; /* initial value */ 274 275 for (i = 0; i < 6; i++) { 276 c = *(addr + i); 277 for (j = 0; j < 8; j++) { 278 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 279 crc <<= 1; 280 c >>= 1; 281 if (carry) 282 crc = (crc ^ 0x04c11db6) | carry; 283 } 284 } 285 286 /* return the filter bit position */ 287 return(crc >> 23 & 0x1FF); 288} 289 290/* 291 * Copy the address 'mac' into the perfect RX filter entry at 292 * offset 'idx.' The perfect filter only has 16 entries so do 293 * some sanity tests. 294 */ 295static int 296sf_setperf(sc, idx, mac) 297 struct sf_softc *sc; 298 int idx; 299 caddr_t mac; 300{ 301 u_int16_t *p; 302 303 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 304 return(EINVAL); 305 306 if (mac == NULL) 307 return(EINVAL); 308 309 p = (u_int16_t *)mac; 310 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 313 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 314 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 315 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 316 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 317 318 return(0); 319} 320 321/* 322 * Set the bit in the 512-bit hash table that corresponds to the 323 * specified mac address 'mac.' If 'prio' is nonzero, update the 324 * priority hash table instead of the filter hash table. 325 */ 326static int 327sf_sethash(sc, mac, prio) 328 struct sf_softc *sc; 329 caddr_t mac; 330 int prio; 331{ 332 u_int32_t h = 0; 333 334 if (mac == NULL) 335 return(EINVAL); 336 337 h = sf_calchash(mac); 338 339 if (prio) { 340 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 341 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 342 } else { 343 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 344 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 345 } 346 347 return(0); 348} 349 350#ifdef notdef 351/* 352 * Set a VLAN tag in the receive filter. 353 */ 354static int 355sf_setvlan(sc, idx, vlan) 356 struct sf_softc *sc; 357 int idx; 358 u_int32_t vlan; 359{ 360 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 361 return(EINVAL); 362 363 csr_write_4(sc, SF_RXFILT_HASH_BASE + 364 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 365 366 return(0); 367} 368#endif 369 370static int 371sf_miibus_readreg(dev, phy, reg) 372 device_t dev; 373 int phy, reg; 374{ 375 struct sf_softc *sc; 376 int i; 377 u_int32_t val = 0; 378 379 sc = device_get_softc(dev); 380 381 for (i = 0; i < SF_TIMEOUT; i++) { 382 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 383 if (val & SF_MII_DATAVALID) 384 break; 385 } 386 387 if (i == SF_TIMEOUT) 388 return(0); 389 390 if ((val & 0x0000FFFF) == 0xFFFF) 391 return(0); 392 393 return(val & 0x0000FFFF); 394} 395 396static int 397sf_miibus_writereg(dev, phy, reg, val) 398 device_t dev; 399 int phy, reg, val; 400{ 401 struct sf_softc *sc; 402 int i; 403 int busy; 404 405 sc = device_get_softc(dev); 406 407 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 408 409 for (i = 0; i < SF_TIMEOUT; i++) { 410 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 411 if (!(busy & SF_MII_BUSY)) 412 break; 413 } 414 415 return(0); 416} 417 418static void 419sf_miibus_statchg(dev) 420 device_t dev; 421{ 422 struct sf_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 mii = device_get_softc(sc->sf_miibus); 427 428 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 429 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 430 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 431 } else { 432 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 433 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 434 } 435 436 return; 437} 438 439static void 440sf_setmulti(sc) 441 struct sf_softc *sc; 442{ 443 struct ifnet *ifp; 444 int i; 445 struct ifmultiaddr *ifma; 446 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 447 448 ifp = &sc->arpcom.ac_if; 449 450 /* First zot all the existing filters. */ 451 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 452 sf_setperf(sc, i, (char *)&dummy); 453 for (i = SF_RXFILT_HASH_BASE; 454 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 455 csr_write_4(sc, i, 0); 456 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 457 458 /* Now program new ones. */ 459 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 460 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 461 } else { 462 i = 1; 463 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 464 if (ifma->ifma_addr->sa_family != AF_LINK) 465 continue; 466 /* 467 * Program the first 15 multicast groups 468 * into the perfect filter. For all others, 469 * use the hash table. 470 */ 471 if (i < SF_RXFILT_PERFECT_CNT) { 472 sf_setperf(sc, i, 473 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 474 i++; 475 continue; 476 } 477 478 sf_sethash(sc, 479 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 480 } 481 } 482 483 return; 484} 485 486/* 487 * Set media options. 488 */ 489static int 490sf_ifmedia_upd(ifp) 491 struct ifnet *ifp; 492{ 493 struct sf_softc *sc; 494 struct mii_data *mii; 495 496 sc = ifp->if_softc; 497 mii = device_get_softc(sc->sf_miibus); 498 sc->sf_link = 0; 499 if (mii->mii_instance) { 500 struct mii_softc *miisc; 501 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 502 mii_phy_reset(miisc); 503 } 504 mii_mediachg(mii); 505 506 return(0); 507} 508 509/* 510 * Report current media status. 511 */ 512static void 513sf_ifmedia_sts(ifp, ifmr) 514 struct ifnet *ifp; 515 struct ifmediareq *ifmr; 516{ 517 struct sf_softc *sc; 518 struct mii_data *mii; 519 520 sc = ifp->if_softc; 521 mii = device_get_softc(sc->sf_miibus); 522 523 mii_pollstat(mii); 524 ifmr->ifm_active = mii->mii_media_active; 525 ifmr->ifm_status = mii->mii_media_status; 526 527 return; 528} 529 530static int 531sf_ioctl(ifp, command, data) 532 struct ifnet *ifp; 533 u_long command; 534 caddr_t data; 535{ 536 struct sf_softc *sc = ifp->if_softc; 537 struct ifreq *ifr = (struct ifreq *) data; 538 struct mii_data *mii; 539 int error = 0; 540 541 SF_LOCK(sc); 542 543 switch(command) { 544 case SIOCSIFFLAGS: 545 if (ifp->if_flags & IFF_UP) { 546 if (ifp->if_flags & IFF_RUNNING && 547 ifp->if_flags & IFF_PROMISC && 548 !(sc->sf_if_flags & IFF_PROMISC)) { 549 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 550 } else if (ifp->if_flags & IFF_RUNNING && 551 !(ifp->if_flags & IFF_PROMISC) && 552 sc->sf_if_flags & IFF_PROMISC) { 553 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 554 } else if (!(ifp->if_flags & IFF_RUNNING)) 555 sf_init(sc); 556 } else { 557 if (ifp->if_flags & IFF_RUNNING) 558 sf_stop(sc); 559 } 560 sc->sf_if_flags = ifp->if_flags; 561 error = 0; 562 break; 563 case SIOCADDMULTI: 564 case SIOCDELMULTI: 565 sf_setmulti(sc); 566 error = 0; 567 break; 568 case SIOCGIFMEDIA: 569 case SIOCSIFMEDIA: 570 mii = device_get_softc(sc->sf_miibus); 571 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 572 break; 573 default: 574 error = ether_ioctl(ifp, command, data); 575 break; 576 } 577 578 SF_UNLOCK(sc); 579 580 return(error); 581} 582 583static void 584sf_reset(sc) 585 struct sf_softc *sc; 586{ 587 register int i; 588 589 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 590 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 591 DELAY(1000); 592 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 593 594 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 595 596 for (i = 0; i < SF_TIMEOUT; i++) { 597 DELAY(10); 598 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 599 break; 600 } 601 602 if (i == SF_TIMEOUT) 603 printf("sf%d: reset never completed!\n", sc->sf_unit); 604 605 /* Wait a little while for the chip to get its brains in order. */ 606 DELAY(1000); 607 return; 608} 609 610/* 611 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 612 * IDs against our list and return a device name if we find a match. 613 * We also check the subsystem ID so that we can identify exactly which 614 * NIC has been found, if possible. 615 */ 616static int 617sf_probe(dev) 618 device_t dev; 619{ 620 struct sf_type *t; 621 622 t = sf_devs; 623 624 while(t->sf_name != NULL) { 625 if ((pci_get_vendor(dev) == t->sf_vid) && 626 (pci_get_device(dev) == t->sf_did)) { 627 switch((pci_read_config(dev, 628 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 629 case AD_SUBSYSID_62011_REV0: 630 case AD_SUBSYSID_62011_REV1: 631 device_set_desc(dev, 632 "Adaptec ANA-62011 10/100BaseTX"); 633 return(0); 634 break; 635 case AD_SUBSYSID_62022: 636 device_set_desc(dev, 637 "Adaptec ANA-62022 10/100BaseTX"); 638 return(0); 639 break; 640 case AD_SUBSYSID_62044_REV0: 641 case AD_SUBSYSID_62044_REV1: 642 device_set_desc(dev, 643 "Adaptec ANA-62044 10/100BaseTX"); 644 return(0); 645 break; 646 case AD_SUBSYSID_62020: 647 device_set_desc(dev, 648 "Adaptec ANA-62020 10/100BaseFX"); 649 return(0); 650 break; 651 case AD_SUBSYSID_69011: 652 device_set_desc(dev, 653 "Adaptec ANA-69011 10/100BaseTX"); 654 return(0); 655 break; 656 default: 657 device_set_desc(dev, t->sf_name); 658 return(0); 659 break; 660 } 661 } 662 t++; 663 } 664 665 return(ENXIO); 666} 667 668/* 669 * Attach the interface. Allocate softc structures, do ifmedia 670 * setup and ethernet/BPF attach. 671 */ 672static int 673sf_attach(dev) 674 device_t dev; 675{ 676 int i; 677 u_int32_t command; 678 struct sf_softc *sc; 679 struct ifnet *ifp; 680 int unit, rid, error = 0; 681 682 sc = device_get_softc(dev); 683 unit = device_get_unit(dev); 684 685 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 686 MTX_DEF | MTX_RECURSE); 687 688 /* 689 * Handle power management nonsense. 690 */ 691 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 692 u_int32_t iobase, membase, irq; 693 694 /* Save important PCI config data. */ 695 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 696 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 697 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 698 699 /* Reset the power state. */ 700 printf("sf%d: chip is in D%d power mode " 701 "-- setting to D0\n", unit, 702 pci_get_powerstate(dev)); 703 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 704 705 /* Restore PCI config data. */ 706 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 707 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 708 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 709 } 710 711 /* 712 * Map control/status registers. 713 */ 714 pci_enable_busmaster(dev); 715 pci_enable_io(dev, SYS_RES_IOPORT); 716 pci_enable_io(dev, SYS_RES_MEMORY); 717 command = pci_read_config(dev, PCIR_COMMAND, 4); 718 719#ifdef SF_USEIOSPACE 720 if (!(command & PCIM_CMD_PORTEN)) { 721 printf("sf%d: failed to enable I/O ports!\n", unit); 722 error = ENXIO; 723 goto fail; 724 } 725#else 726 if (!(command & PCIM_CMD_MEMEN)) { 727 printf("sf%d: failed to enable memory mapping!\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731#endif 732 733 rid = SF_RID; 734 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 735 0, ~0, 1, RF_ACTIVE); 736 737 if (sc->sf_res == NULL) { 738 printf ("sf%d: couldn't map ports\n", unit); 739 error = ENXIO; 740 goto fail; 741 } 742 743 sc->sf_btag = rman_get_bustag(sc->sf_res); 744 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 745 746 /* Allocate interrupt */ 747 rid = 0; 748 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 749 RF_SHAREABLE | RF_ACTIVE); 750 751 if (sc->sf_irq == NULL) { 752 printf("sf%d: couldn't map interrupt\n", unit); 753 error = ENXIO; 754 goto fail; 755 } 756 757 callout_handle_init(&sc->sf_stat_ch); 758 /* Reset the adapter. */ 759 sf_reset(sc); 760 761 /* 762 * Get station address from the EEPROM. 763 */ 764 for (i = 0; i < ETHER_ADDR_LEN; i++) 765 sc->arpcom.ac_enaddr[i] = 766 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 767 768 /* 769 * An Adaptec chip was detected. Inform the world. 770 */ 771 printf("sf%d: Ethernet address: %6D\n", unit, 772 sc->arpcom.ac_enaddr, ":"); 773 774 sc->sf_unit = unit; 775 776 /* Allocate the descriptor queues. */ 777 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 778 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 779 780 if (sc->sf_ldata == NULL) { 781 printf("sf%d: no memory for list buffers!\n", unit); 782 error = ENXIO; 783 goto fail; 784 } 785 786 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 787 788 /* Do MII setup. */ 789 if (mii_phy_probe(dev, &sc->sf_miibus, 790 sf_ifmedia_upd, sf_ifmedia_sts)) { 791 printf("sf%d: MII without any phy!\n", sc->sf_unit); 792 error = ENXIO; 793 goto fail; 794 } 795 796 ifp = &sc->arpcom.ac_if; 797 ifp->if_softc = sc; 798 ifp->if_unit = unit; 799 ifp->if_name = "sf"; 800 ifp->if_mtu = ETHERMTU; 801 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 802 ifp->if_ioctl = sf_ioctl; 803 ifp->if_output = ether_output; 804 ifp->if_start = sf_start; 805 ifp->if_watchdog = sf_watchdog; 806 ifp->if_init = sf_init; 807 ifp->if_baudrate = 10000000; 808 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 809 810 /* 811 * Call MI attach routine. 812 */ 813 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 814 815 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 816 sf_intr, sc, &sc->sf_intrhand); 817 818 if (error) { 819 printf("sf%d: couldn't set up irq\n", unit); 820 goto fail; 821 } 822 823fail: 824 if (error) 825 sf_detach(dev); 826 827 return(error); 828} 829 830static int 831sf_detach(dev) 832 device_t dev; 833{ 834 struct sf_softc *sc; 835 struct ifnet *ifp; 836 837 sc = device_get_softc(dev); 838 KASSERT(mtx_initialized(&sc->sf_mtx), "sf mutex not initialized"); 839 SF_LOCK(sc); 840 ifp = &sc->arpcom.ac_if; 841 842 if (device_is_alive(dev)) { 843 if (bus_child_present(dev)) 844 sf_stop(sc); 845 ether_ifdetach(ifp); 846 device_delete_child(dev, sc->sf_miibus); 847 bus_generic_detach(dev); 848 } 849 850 if (sc->sf_intrhand) 851 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 852 if (sc->sf_irq) 853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 854 if (sc->sf_res) 855 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 856 857 if (sc->sf_ldata) 858 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 859 860 SF_UNLOCK(sc); 861 mtx_destroy(&sc->sf_mtx); 862 863 return(0); 864} 865 866static int 867sf_init_rx_ring(sc) 868 struct sf_softc *sc; 869{ 870 struct sf_list_data *ld; 871 int i; 872 873 ld = sc->sf_ldata; 874 875 bzero((char *)ld->sf_rx_dlist_big, 876 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 877 bzero((char *)ld->sf_rx_clist, 878 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 879 880 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 881 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 882 return(ENOBUFS); 883 } 884 885 return(0); 886} 887 888static void 889sf_init_tx_ring(sc) 890 struct sf_softc *sc; 891{ 892 struct sf_list_data *ld; 893 int i; 894 895 ld = sc->sf_ldata; 896 897 bzero((char *)ld->sf_tx_dlist, 898 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 899 bzero((char *)ld->sf_tx_clist, 900 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 901 902 for (i = 0; i < SF_TX_DLIST_CNT; i++) 903 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 904 for (i = 0; i < SF_TX_CLIST_CNT; i++) 905 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 906 907 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 908 sc->sf_tx_cnt = 0; 909 910 return; 911} 912 913static int 914sf_newbuf(sc, c, m) 915 struct sf_softc *sc; 916 struct sf_rx_bufdesc_type0 *c; 917 struct mbuf *m; 918{ 919 struct mbuf *m_new = NULL; 920 921 if (m == NULL) { 922 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 923 if (m_new == NULL) 924 return(ENOBUFS); 925 926 MCLGET(m_new, M_DONTWAIT); 927 if (!(m_new->m_flags & M_EXT)) { 928 m_freem(m_new); 929 return(ENOBUFS); 930 } 931 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 932 } else { 933 m_new = m; 934 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 935 m_new->m_data = m_new->m_ext.ext_buf; 936 } 937 938 m_adj(m_new, sizeof(u_int64_t)); 939 940 c->sf_mbuf = m_new; 941 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 942 c->sf_valid = 1; 943 944 return(0); 945} 946 947/* 948 * The starfire is programmed to use 'normal' mode for packet reception, 949 * which means we use the consumer/producer model for both the buffer 950 * descriptor queue and the completion descriptor queue. The only problem 951 * with this is that it involves a lot of register accesses: we have to 952 * read the RX completion consumer and producer indexes and the RX buffer 953 * producer index, plus the RX completion consumer and RX buffer producer 954 * indexes have to be updated. It would have been easier if Adaptec had 955 * put each index in a separate register, especially given that the damn 956 * NIC has a 512K register space. 957 * 958 * In spite of all the lovely features that Adaptec crammed into the 6915, 959 * it is marred by one truly stupid design flaw, which is that receive 960 * buffer addresses must be aligned on a longword boundary. This forces 961 * the packet payload to be unaligned, which is suboptimal on the x86 and 962 * completely unuseable on the Alpha. Our only recourse is to copy received 963 * packets into properly aligned buffers before handing them off. 964 */ 965 966static void 967sf_rxeof(sc) 968 struct sf_softc *sc; 969{ 970 struct mbuf *m; 971 struct ifnet *ifp; 972 struct sf_rx_bufdesc_type0 *desc; 973 struct sf_rx_cmpdesc_type3 *cur_rx; 974 u_int32_t rxcons, rxprod; 975 int cmpprodidx, cmpconsidx, bufprodidx; 976 977 ifp = &sc->arpcom.ac_if; 978 979 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 980 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 981 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 982 cmpconsidx = SF_IDX_LO(rxcons); 983 bufprodidx = SF_IDX_LO(rxprod); 984 985 while (cmpconsidx != cmpprodidx) { 986 struct mbuf *m0; 987 988 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 989 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 990 m = desc->sf_mbuf; 991 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 992 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 993 994 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 995 ifp->if_ierrors++; 996 sf_newbuf(sc, desc, m); 997 continue; 998 } 999 1000 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 1001 ifp, NULL); 1002 sf_newbuf(sc, desc, m); 1003 if (m0 == NULL) { 1004 ifp->if_ierrors++; 1005 continue; 1006 } 1007 m = m0; 1008 1009 ifp->if_ipackets++; 1010 (*ifp->if_input)(ifp, m); 1011 } 1012 1013 csr_write_4(sc, SF_CQ_CONSIDX, 1014 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1015 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1016 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1017 1018 return; 1019} 1020 1021/* 1022 * Read the transmit status from the completion queue and release 1023 * mbufs. Note that the buffer descriptor index in the completion 1024 * descriptor is an offset from the start of the transmit buffer 1025 * descriptor list in bytes. This is important because the manual 1026 * gives the impression that it should match the producer/consumer 1027 * index, which is the offset in 8 byte blocks. 1028 */ 1029static void 1030sf_txeof(sc) 1031 struct sf_softc *sc; 1032{ 1033 int txcons, cmpprodidx, cmpconsidx; 1034 struct sf_tx_cmpdesc_type1 *cur_cmp; 1035 struct sf_tx_bufdesc_type0 *cur_tx; 1036 struct ifnet *ifp; 1037 1038 ifp = &sc->arpcom.ac_if; 1039 1040 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1041 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1042 cmpconsidx = SF_IDX_HI(txcons); 1043 1044 while (cmpconsidx != cmpprodidx) { 1045 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1046 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1047 1048 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1049 ifp->if_opackets++; 1050 else { 1051 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1052 sf_txthresh_adjust(sc); 1053 ifp->if_oerrors++; 1054 } 1055 1056 sc->sf_tx_cnt--; 1057 if (cur_tx->sf_mbuf != NULL) { 1058 m_freem(cur_tx->sf_mbuf); 1059 cur_tx->sf_mbuf = NULL; 1060 } else 1061 break; 1062 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1063 } 1064 1065 ifp->if_timer = 0; 1066 ifp->if_flags &= ~IFF_OACTIVE; 1067 1068 csr_write_4(sc, SF_CQ_CONSIDX, 1069 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1070 ((cmpconsidx << 16) & 0xFFFF0000)); 1071 1072 return; 1073} 1074 1075static void 1076sf_txthresh_adjust(sc) 1077 struct sf_softc *sc; 1078{ 1079 u_int32_t txfctl; 1080 u_int8_t txthresh; 1081 1082 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1083 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1084 if (txthresh < 0xFF) { 1085 txthresh++; 1086 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1087 txfctl |= txthresh; 1088#ifdef DIAGNOSTIC 1089 printf("sf%d: tx underrun, increasing " 1090 "tx threshold to %d bytes\n", 1091 sc->sf_unit, txthresh * 4); 1092#endif 1093 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1094 } 1095 1096 return; 1097} 1098 1099static void 1100sf_intr(arg) 1101 void *arg; 1102{ 1103 struct sf_softc *sc; 1104 struct ifnet *ifp; 1105 u_int32_t status; 1106 1107 sc = arg; 1108 SF_LOCK(sc); 1109 1110 ifp = &sc->arpcom.ac_if; 1111 1112 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1113 SF_UNLOCK(sc); 1114 return; 1115 } 1116 1117 /* Disable interrupts. */ 1118 csr_write_4(sc, SF_IMR, 0x00000000); 1119 1120 for (;;) { 1121 status = csr_read_4(sc, SF_ISR); 1122 if (status) 1123 csr_write_4(sc, SF_ISR, status); 1124 1125 if (!(status & SF_INTRS)) 1126 break; 1127 1128 if (status & SF_ISR_RXDQ1_DMADONE) 1129 sf_rxeof(sc); 1130 1131 if (status & SF_ISR_TX_TXDONE || 1132 status & SF_ISR_TX_DMADONE || 1133 status & SF_ISR_TX_QUEUEDONE) 1134 sf_txeof(sc); 1135 1136 if (status & SF_ISR_TX_LOFIFO) 1137 sf_txthresh_adjust(sc); 1138 1139 if (status & SF_ISR_ABNORMALINTR) { 1140 if (status & SF_ISR_STATSOFLOW) { 1141 untimeout(sf_stats_update, sc, 1142 sc->sf_stat_ch); 1143 sf_stats_update(sc); 1144 } else 1145 sf_init(sc); 1146 } 1147 } 1148 1149 /* Re-enable interrupts. */ 1150 csr_write_4(sc, SF_IMR, SF_INTRS); 1151 1152 if (ifp->if_snd.ifq_head != NULL) 1153 sf_start(ifp); 1154 1155 SF_UNLOCK(sc); 1156 return; 1157} 1158 1159static void 1160sf_init(xsc) 1161 void *xsc; 1162{ 1163 struct sf_softc *sc; 1164 struct ifnet *ifp; 1165 struct mii_data *mii; 1166 int i; 1167 1168 sc = xsc; 1169 SF_LOCK(sc); 1170 ifp = &sc->arpcom.ac_if; 1171 mii = device_get_softc(sc->sf_miibus); 1172 1173 sf_stop(sc); 1174 sf_reset(sc); 1175 1176 /* Init all the receive filter registers */ 1177 for (i = SF_RXFILT_PERFECT_BASE; 1178 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1179 csr_write_4(sc, i, 0); 1180 1181 /* Empty stats counter registers. */ 1182 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1183 csr_write_4(sc, SF_STATS_BASE + 1184 (i + sizeof(u_int32_t)), 0); 1185 1186 /* Init our MAC address */ 1187 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1188 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1189 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1190 1191 if (sf_init_rx_ring(sc) == ENOBUFS) { 1192 printf("sf%d: initialization failed: no " 1193 "memory for rx buffers\n", sc->sf_unit); 1194 SF_UNLOCK(sc); 1195 return; 1196 } 1197 1198 sf_init_tx_ring(sc); 1199 1200 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1201 1202 /* If we want promiscuous mode, set the allframes bit. */ 1203 if (ifp->if_flags & IFF_PROMISC) { 1204 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1205 } else { 1206 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1207 } 1208 1209 if (ifp->if_flags & IFF_BROADCAST) { 1210 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1211 } else { 1212 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1213 } 1214 1215 /* 1216 * Load the multicast filter. 1217 */ 1218 sf_setmulti(sc); 1219 1220 /* Init the completion queue indexes */ 1221 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1222 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1223 1224 /* Init the RX completion queue */ 1225 csr_write_4(sc, SF_RXCQ_CTL_1, 1226 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1227 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1228 1229 /* Init RX DMA control. */ 1230 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1231 1232 /* Init the RX buffer descriptor queue. */ 1233 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1234 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1235 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1236 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1237 1238 /* Init the TX completion queue */ 1239 csr_write_4(sc, SF_TXCQ_CTL, 1240 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1241 1242 /* Init the TX buffer descriptor queue. */ 1243 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1244 vtophys(sc->sf_ldata->sf_tx_dlist)); 1245 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1246 csr_write_4(sc, SF_TXDQ_CTL, 1247 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1248 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1249 1250 /* Enable autopadding of short TX frames. */ 1251 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1252 1253 /* Enable interrupts. */ 1254 csr_write_4(sc, SF_IMR, SF_INTRS); 1255 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1256 1257 /* Enable the RX and TX engines. */ 1258 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1259 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1260 1261 /*mii_mediachg(mii);*/ 1262 sf_ifmedia_upd(ifp); 1263 1264 ifp->if_flags |= IFF_RUNNING; 1265 ifp->if_flags &= ~IFF_OACTIVE; 1266 1267 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1268 1269 SF_UNLOCK(sc); 1270 1271 return; 1272} 1273 1274static int 1275sf_encap(sc, c, m_head) 1276 struct sf_softc *sc; 1277 struct sf_tx_bufdesc_type0 *c; 1278 struct mbuf *m_head; 1279{ 1280 int frag = 0; 1281 struct sf_frag *f = NULL; 1282 struct mbuf *m; 1283 1284 m = m_head; 1285 1286 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1287 if (m->m_len != 0) { 1288 if (frag == SF_MAXFRAGS) 1289 break; 1290 f = &c->sf_frags[frag]; 1291 if (frag == 0) 1292 f->sf_pktlen = m_head->m_pkthdr.len; 1293 f->sf_fraglen = m->m_len; 1294 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1295 frag++; 1296 } 1297 } 1298 1299 if (m != NULL) { 1300 struct mbuf *m_new = NULL; 1301 1302 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1303 if (m_new == NULL) { 1304 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1305 return(1); 1306 } 1307 1308 if (m_head->m_pkthdr.len > MHLEN) { 1309 MCLGET(m_new, M_DONTWAIT); 1310 if (!(m_new->m_flags & M_EXT)) { 1311 m_freem(m_new); 1312 printf("sf%d: no memory for tx list\n", 1313 sc->sf_unit); 1314 return(1); 1315 } 1316 } 1317 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1318 mtod(m_new, caddr_t)); 1319 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1320 m_freem(m_head); 1321 m_head = m_new; 1322 f = &c->sf_frags[0]; 1323 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1324 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1325 frag = 1; 1326 } 1327 1328 c->sf_mbuf = m_head; 1329 c->sf_id = SF_TX_BUFDESC_ID; 1330 c->sf_fragcnt = frag; 1331 c->sf_intr = 1; 1332 c->sf_caltcp = 0; 1333 c->sf_crcen = 1; 1334 1335 return(0); 1336} 1337 1338static void 1339sf_start(ifp) 1340 struct ifnet *ifp; 1341{ 1342 struct sf_softc *sc; 1343 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1344 struct mbuf *m_head = NULL; 1345 int i, txprod; 1346 1347 sc = ifp->if_softc; 1348 SF_LOCK(sc); 1349 1350 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1351 SF_UNLOCK(sc); 1352 return; 1353 } 1354 1355 if (ifp->if_flags & IFF_OACTIVE) { 1356 SF_UNLOCK(sc); 1357 return; 1358 } 1359 1360 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1361 i = SF_IDX_HI(txprod) >> 4; 1362 1363 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1364 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1365 sf_init(sc); 1366 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1367 i = SF_IDX_HI(txprod) >> 4; 1368 } 1369 1370 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1371 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1372 ifp->if_flags |= IFF_OACTIVE; 1373 cur_tx = NULL; 1374 break; 1375 } 1376 IF_DEQUEUE(&ifp->if_snd, m_head); 1377 if (m_head == NULL) 1378 break; 1379 1380 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1381 if (sf_encap(sc, cur_tx, m_head)) { 1382 IF_PREPEND(&ifp->if_snd, m_head); 1383 ifp->if_flags |= IFF_OACTIVE; 1384 cur_tx = NULL; 1385 break; 1386 } 1387 1388 /* 1389 * If there's a BPF listener, bounce a copy of this frame 1390 * to him. 1391 */ 1392 BPF_MTAP(ifp, m_head); 1393 1394 SF_INC(i, SF_TX_DLIST_CNT); 1395 sc->sf_tx_cnt++; 1396 /* 1397 * Don't get the TX DMA queue get too full. 1398 */ 1399 if (sc->sf_tx_cnt > 64) 1400 break; 1401 } 1402 1403 if (cur_tx == NULL) { 1404 SF_UNLOCK(sc); 1405 return; 1406 } 1407 1408 /* Transmit */ 1409 csr_write_4(sc, SF_TXDQ_PRODIDX, 1410 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1411 ((i << 20) & 0xFFFF0000)); 1412 1413 ifp->if_timer = 5; 1414 1415 SF_UNLOCK(sc); 1416 1417 return; 1418} 1419 1420static void 1421sf_stop(sc) 1422 struct sf_softc *sc; 1423{ 1424 int i; 1425 struct ifnet *ifp; 1426 1427 SF_LOCK(sc); 1428 1429 ifp = &sc->arpcom.ac_if; 1430 1431 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1432 1433 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1434 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1435 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1436 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1437 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1438 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1439 csr_write_4(sc, SF_TXCQ_CTL, 0); 1440 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1441 csr_write_4(sc, SF_TXDQ_CTL, 0); 1442 sf_reset(sc); 1443 1444 sc->sf_link = 0; 1445 1446 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1447 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1448 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1449 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1450 } 1451 } 1452 1453 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1454 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1455 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1456 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1457 } 1458 } 1459 1460 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1461 SF_UNLOCK(sc); 1462 1463 return; 1464} 1465 1466/* 1467 * Note: it is important that this function not be interrupted. We 1468 * use a two-stage register access scheme: if we are interrupted in 1469 * between setting the indirect address register and reading from the 1470 * indirect data register, the contents of the address register could 1471 * be changed out from under us. 1472 */ 1473static void 1474sf_stats_update(xsc) 1475 void *xsc; 1476{ 1477 struct sf_softc *sc; 1478 struct ifnet *ifp; 1479 struct mii_data *mii; 1480 struct sf_stats stats; 1481 u_int32_t *ptr; 1482 int i; 1483 1484 sc = xsc; 1485 SF_LOCK(sc); 1486 ifp = &sc->arpcom.ac_if; 1487 mii = device_get_softc(sc->sf_miibus); 1488 1489 ptr = (u_int32_t *)&stats; 1490 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1491 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1492 (i + sizeof(u_int32_t))); 1493 1494 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1495 csr_write_4(sc, SF_STATS_BASE + 1496 (i + sizeof(u_int32_t)), 0); 1497 1498 ifp->if_collisions += stats.sf_tx_single_colls + 1499 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1500 1501 mii_tick(mii); 1502 1503 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1504 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1505 sc->sf_link++; 1506 if (ifp->if_snd.ifq_head != NULL) 1507 sf_start(ifp); 1508 } 1509 1510 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1511 1512 SF_UNLOCK(sc); 1513 1514 return; 1515} 1516 1517static void 1518sf_watchdog(ifp) 1519 struct ifnet *ifp; 1520{ 1521 struct sf_softc *sc; 1522 1523 sc = ifp->if_softc; 1524 1525 SF_LOCK(sc); 1526 1527 ifp->if_oerrors++; 1528 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1529 1530 sf_stop(sc); 1531 sf_reset(sc); 1532 sf_init(sc); 1533 1534 if (ifp->if_snd.ifq_head != NULL) 1535 sf_start(ifp); 1536 1537 SF_UNLOCK(sc); 1538 1539 return; 1540} 1541 1542static void 1543sf_shutdown(dev) 1544 device_t dev; 1545{ 1546 struct sf_softc *sc; 1547 1548 sc = device_get_softc(dev); 1549 1550 sf_stop(sc); 1551 1552 return; 1553} 1554