if_sf.c revision 103139
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 103139 2002-09-09 17:39:48Z ticso $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, miibus, 1, 1, 1); 121 122#ifndef lint 123static const char rcsid[] = 124 "$FreeBSD: head/sys/dev/sf/if_sf.c 103139 2002-09-09 17:39:48Z ticso $"; 125#endif 126 127static struct sf_type sf_devs[] = { 128 { AD_VENDORID, AD_DEVICEID_STARFIRE, 129 "Adaptec AIC-6915 10/100BaseTX" }, 130 { 0, 0, NULL } 131}; 132 133static int sf_probe (device_t); 134static int sf_attach (device_t); 135static int sf_detach (device_t); 136static void sf_intr (void *); 137static void sf_stats_update (void *); 138static void sf_rxeof (struct sf_softc *); 139static void sf_txeof (struct sf_softc *); 140static int sf_encap (struct sf_softc *, 141 struct sf_tx_bufdesc_type0 *, 142 struct mbuf *); 143static void sf_start (struct ifnet *); 144static int sf_ioctl (struct ifnet *, u_long, caddr_t); 145static void sf_init (void *); 146static void sf_stop (struct sf_softc *); 147static void sf_watchdog (struct ifnet *); 148static void sf_shutdown (device_t); 149static int sf_ifmedia_upd (struct ifnet *); 150static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151static void sf_reset (struct sf_softc *); 152static int sf_init_rx_ring (struct sf_softc *); 153static void sf_init_tx_ring (struct sf_softc *); 154static int sf_newbuf (struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *); 157static void sf_setmulti (struct sf_softc *); 158static int sf_setperf (struct sf_softc *, int, caddr_t); 159static int sf_sethash (struct sf_softc *, caddr_t, int); 160#ifdef notdef 161static int sf_setvlan (struct sf_softc *, int, u_int32_t); 162#endif 163 164static u_int8_t sf_read_eeprom (struct sf_softc *, int); 165static u_int32_t sf_calchash (caddr_t); 166 167static int sf_miibus_readreg (device_t, int, int); 168static int sf_miibus_writereg (device_t, int, int, int); 169static void sf_miibus_statchg (device_t); 170 171static u_int32_t csr_read_4 (struct sf_softc *, int); 172static void csr_write_4 (struct sf_softc *, int, u_int32_t); 173static void sf_txthresh_adjust (struct sf_softc *); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 218 219static u_int32_t 220csr_read_4(sc, reg) 221 struct sf_softc *sc; 222 int reg; 223{ 224 u_int32_t val; 225 226#ifdef SF_USEIOSPACE 227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 229#else 230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 231#endif 232 233 return(val); 234} 235 236static u_int8_t 237sf_read_eeprom(sc, reg) 238 struct sf_softc *sc; 239 int reg; 240{ 241 u_int8_t val; 242 243 val = (csr_read_4(sc, SF_EEADDR_BASE + 244 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 245 246 return(val); 247} 248 249static void 250csr_write_4(sc, reg, val) 251 struct sf_softc *sc; 252 int reg; 253 u_int32_t val; 254{ 255#ifdef SF_USEIOSPACE 256 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 257 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 258#else 259 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 260#endif 261 return; 262} 263 264static u_int32_t 265sf_calchash(addr) 266 caddr_t addr; 267{ 268 u_int32_t crc, carry; 269 int i, j; 270 u_int8_t c; 271 272 /* Compute CRC for the address value. */ 273 crc = 0xFFFFFFFF; /* initial value */ 274 275 for (i = 0; i < 6; i++) { 276 c = *(addr + i); 277 for (j = 0; j < 8; j++) { 278 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 279 crc <<= 1; 280 c >>= 1; 281 if (carry) 282 crc = (crc ^ 0x04c11db6) | carry; 283 } 284 } 285 286 /* return the filter bit position */ 287 return(crc >> 23 & 0x1FF); 288} 289 290/* 291 * Copy the address 'mac' into the perfect RX filter entry at 292 * offset 'idx.' The perfect filter only has 16 entries so do 293 * some sanity tests. 294 */ 295static int 296sf_setperf(sc, idx, mac) 297 struct sf_softc *sc; 298 int idx; 299 caddr_t mac; 300{ 301 u_int16_t *p; 302 303 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 304 return(EINVAL); 305 306 if (mac == NULL) 307 return(EINVAL); 308 309 p = (u_int16_t *)mac; 310 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 313 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 314 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 315 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 316 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 317 318 return(0); 319} 320 321/* 322 * Set the bit in the 512-bit hash table that corresponds to the 323 * specified mac address 'mac.' If 'prio' is nonzero, update the 324 * priority hash table instead of the filter hash table. 325 */ 326static int 327sf_sethash(sc, mac, prio) 328 struct sf_softc *sc; 329 caddr_t mac; 330 int prio; 331{ 332 u_int32_t h = 0; 333 334 if (mac == NULL) 335 return(EINVAL); 336 337 h = sf_calchash(mac); 338 339 if (prio) { 340 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 341 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 342 } else { 343 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 344 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 345 } 346 347 return(0); 348} 349 350#ifdef notdef 351/* 352 * Set a VLAN tag in the receive filter. 353 */ 354static int 355sf_setvlan(sc, idx, vlan) 356 struct sf_softc *sc; 357 int idx; 358 u_int32_t vlan; 359{ 360 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 361 return(EINVAL); 362 363 csr_write_4(sc, SF_RXFILT_HASH_BASE + 364 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 365 366 return(0); 367} 368#endif 369 370static int 371sf_miibus_readreg(dev, phy, reg) 372 device_t dev; 373 int phy, reg; 374{ 375 struct sf_softc *sc; 376 int i; 377 u_int32_t val = 0; 378 379 sc = device_get_softc(dev); 380 381 for (i = 0; i < SF_TIMEOUT; i++) { 382 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 383 if (val & SF_MII_DATAVALID) 384 break; 385 } 386 387 if (i == SF_TIMEOUT) 388 return(0); 389 390 if ((val & 0x0000FFFF) == 0xFFFF) 391 return(0); 392 393 return(val & 0x0000FFFF); 394} 395 396static int 397sf_miibus_writereg(dev, phy, reg, val) 398 device_t dev; 399 int phy, reg, val; 400{ 401 struct sf_softc *sc; 402 int i; 403 int busy; 404 405 sc = device_get_softc(dev); 406 407 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 408 409 for (i = 0; i < SF_TIMEOUT; i++) { 410 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 411 if (!(busy & SF_MII_BUSY)) 412 break; 413 } 414 415 return(0); 416} 417 418static void 419sf_miibus_statchg(dev) 420 device_t dev; 421{ 422 struct sf_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 mii = device_get_softc(sc->sf_miibus); 427 428 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 429 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 430 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 431 } else { 432 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 433 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 434 } 435 436 return; 437} 438 439static void 440sf_setmulti(sc) 441 struct sf_softc *sc; 442{ 443 struct ifnet *ifp; 444 int i; 445 struct ifmultiaddr *ifma; 446 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 447 448 ifp = &sc->arpcom.ac_if; 449 450 /* First zot all the existing filters. */ 451 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 452 sf_setperf(sc, i, (char *)&dummy); 453 for (i = SF_RXFILT_HASH_BASE; 454 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 455 csr_write_4(sc, i, 0); 456 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 457 458 /* Now program new ones. */ 459 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 460 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 461 } else { 462 i = 1; 463 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 464 if (ifma->ifma_addr->sa_family != AF_LINK) 465 continue; 466 /* 467 * Program the first 15 multicast groups 468 * into the perfect filter. For all others, 469 * use the hash table. 470 */ 471 if (i < SF_RXFILT_PERFECT_CNT) { 472 sf_setperf(sc, i, 473 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 474 i++; 475 continue; 476 } 477 478 sf_sethash(sc, 479 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 480 } 481 } 482 483 return; 484} 485 486/* 487 * Set media options. 488 */ 489static int 490sf_ifmedia_upd(ifp) 491 struct ifnet *ifp; 492{ 493 struct sf_softc *sc; 494 struct mii_data *mii; 495 496 sc = ifp->if_softc; 497 mii = device_get_softc(sc->sf_miibus); 498 sc->sf_link = 0; 499 if (mii->mii_instance) { 500 struct mii_softc *miisc; 501 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 502 mii_phy_reset(miisc); 503 } 504 mii_mediachg(mii); 505 506 return(0); 507} 508 509/* 510 * Report current media status. 511 */ 512static void 513sf_ifmedia_sts(ifp, ifmr) 514 struct ifnet *ifp; 515 struct ifmediareq *ifmr; 516{ 517 struct sf_softc *sc; 518 struct mii_data *mii; 519 520 sc = ifp->if_softc; 521 mii = device_get_softc(sc->sf_miibus); 522 523 mii_pollstat(mii); 524 ifmr->ifm_active = mii->mii_media_active; 525 ifmr->ifm_status = mii->mii_media_status; 526 527 return; 528} 529 530static int 531sf_ioctl(ifp, command, data) 532 struct ifnet *ifp; 533 u_long command; 534 caddr_t data; 535{ 536 struct sf_softc *sc = ifp->if_softc; 537 struct ifreq *ifr = (struct ifreq *) data; 538 struct mii_data *mii; 539 int error = 0; 540 541 SF_LOCK(sc); 542 543 switch(command) { 544 case SIOCSIFADDR: 545 case SIOCGIFADDR: 546 case SIOCSIFMTU: 547 error = ether_ioctl(ifp, command, data); 548 break; 549 case SIOCSIFFLAGS: 550 if (ifp->if_flags & IFF_UP) { 551 if (ifp->if_flags & IFF_RUNNING && 552 ifp->if_flags & IFF_PROMISC && 553 !(sc->sf_if_flags & IFF_PROMISC)) { 554 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 555 } else if (ifp->if_flags & IFF_RUNNING && 556 !(ifp->if_flags & IFF_PROMISC) && 557 sc->sf_if_flags & IFF_PROMISC) { 558 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 559 } else if (!(ifp->if_flags & IFF_RUNNING)) 560 sf_init(sc); 561 } else { 562 if (ifp->if_flags & IFF_RUNNING) 563 sf_stop(sc); 564 } 565 sc->sf_if_flags = ifp->if_flags; 566 error = 0; 567 break; 568 case SIOCADDMULTI: 569 case SIOCDELMULTI: 570 sf_setmulti(sc); 571 error = 0; 572 break; 573 case SIOCGIFMEDIA: 574 case SIOCSIFMEDIA: 575 mii = device_get_softc(sc->sf_miibus); 576 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 577 break; 578 default: 579 error = EINVAL; 580 break; 581 } 582 583 SF_UNLOCK(sc); 584 585 return(error); 586} 587 588static void 589sf_reset(sc) 590 struct sf_softc *sc; 591{ 592 register int i; 593 594 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 595 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 596 DELAY(1000); 597 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 598 599 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 600 601 for (i = 0; i < SF_TIMEOUT; i++) { 602 DELAY(10); 603 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 604 break; 605 } 606 607 if (i == SF_TIMEOUT) 608 printf("sf%d: reset never completed!\n", sc->sf_unit); 609 610 /* Wait a little while for the chip to get its brains in order. */ 611 DELAY(1000); 612 return; 613} 614 615/* 616 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 617 * IDs against our list and return a device name if we find a match. 618 * We also check the subsystem ID so that we can identify exactly which 619 * NIC has been found, if possible. 620 */ 621static int 622sf_probe(dev) 623 device_t dev; 624{ 625 struct sf_type *t; 626 627 t = sf_devs; 628 629 while(t->sf_name != NULL) { 630 if ((pci_get_vendor(dev) == t->sf_vid) && 631 (pci_get_device(dev) == t->sf_did)) { 632 switch((pci_read_config(dev, 633 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 634 case AD_SUBSYSID_62011_REV0: 635 case AD_SUBSYSID_62011_REV1: 636 device_set_desc(dev, 637 "Adaptec ANA-62011 10/100BaseTX"); 638 return(0); 639 break; 640 case AD_SUBSYSID_62022: 641 device_set_desc(dev, 642 "Adaptec ANA-62022 10/100BaseTX"); 643 return(0); 644 break; 645 case AD_SUBSYSID_62044_REV0: 646 case AD_SUBSYSID_62044_REV1: 647 device_set_desc(dev, 648 "Adaptec ANA-62044 10/100BaseTX"); 649 return(0); 650 break; 651 case AD_SUBSYSID_62020: 652 device_set_desc(dev, 653 "Adaptec ANA-62020 10/100BaseFX"); 654 return(0); 655 break; 656 case AD_SUBSYSID_69011: 657 device_set_desc(dev, 658 "Adaptec ANA-69011 10/100BaseTX"); 659 return(0); 660 break; 661 default: 662 device_set_desc(dev, t->sf_name); 663 return(0); 664 break; 665 } 666 } 667 t++; 668 } 669 670 return(ENXIO); 671} 672 673/* 674 * Attach the interface. Allocate softc structures, do ifmedia 675 * setup and ethernet/BPF attach. 676 */ 677static int 678sf_attach(dev) 679 device_t dev; 680{ 681 int i; 682 u_int32_t command; 683 struct sf_softc *sc; 684 struct ifnet *ifp; 685 int unit, rid, error = 0; 686 687 sc = device_get_softc(dev); 688 unit = device_get_unit(dev); 689 bzero(sc, sizeof(struct sf_softc)); 690 691 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 692 MTX_DEF | MTX_RECURSE); 693 SF_LOCK(sc); 694 /* 695 * Handle power management nonsense. 696 */ 697 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 698 u_int32_t iobase, membase, irq; 699 700 /* Save important PCI config data. */ 701 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 702 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 703 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 704 705 /* Reset the power state. */ 706 printf("sf%d: chip is in D%d power mode " 707 "-- setting to D0\n", unit, 708 pci_get_powerstate(dev)); 709 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 710 711 /* Restore PCI config data. */ 712 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 713 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 714 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 715 } 716 717 /* 718 * Map control/status registers. 719 */ 720 pci_enable_busmaster(dev); 721 pci_enable_io(dev, SYS_RES_IOPORT); 722 pci_enable_io(dev, SYS_RES_MEMORY); 723 command = pci_read_config(dev, PCIR_COMMAND, 4); 724 725#ifdef SF_USEIOSPACE 726 if (!(command & PCIM_CMD_PORTEN)) { 727 printf("sf%d: failed to enable I/O ports!\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731#else 732 if (!(command & PCIM_CMD_MEMEN)) { 733 printf("sf%d: failed to enable memory mapping!\n", unit); 734 error = ENXIO; 735 goto fail; 736 } 737#endif 738 739 rid = SF_RID; 740 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 741 0, ~0, 1, RF_ACTIVE); 742 743 if (sc->sf_res == NULL) { 744 printf ("sf%d: couldn't map ports\n", unit); 745 error = ENXIO; 746 goto fail; 747 } 748 749 sc->sf_btag = rman_get_bustag(sc->sf_res); 750 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 751 752 /* Allocate interrupt */ 753 rid = 0; 754 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 755 RF_SHAREABLE | RF_ACTIVE); 756 757 if (sc->sf_irq == NULL) { 758 printf("sf%d: couldn't map interrupt\n", unit); 759 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 760 error = ENXIO; 761 goto fail; 762 } 763 764 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 765 sf_intr, sc, &sc->sf_intrhand); 766 767 if (error) { 768 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 769 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 770 printf("sf%d: couldn't set up irq\n", unit); 771 goto fail; 772 } 773 774 callout_handle_init(&sc->sf_stat_ch); 775 /* Reset the adapter. */ 776 sf_reset(sc); 777 778 /* 779 * Get station address from the EEPROM. 780 */ 781 for (i = 0; i < ETHER_ADDR_LEN; i++) 782 sc->arpcom.ac_enaddr[i] = 783 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 784 785 /* 786 * An Adaptec chip was detected. Inform the world. 787 */ 788 printf("sf%d: Ethernet address: %6D\n", unit, 789 sc->arpcom.ac_enaddr, ":"); 790 791 sc->sf_unit = unit; 792 793 /* Allocate the descriptor queues. */ 794 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 795 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 796 797 if (sc->sf_ldata == NULL) { 798 printf("sf%d: no memory for list buffers!\n", unit); 799 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 800 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 801 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 802 error = ENXIO; 803 goto fail; 804 } 805 806 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 807 808 /* Do MII setup. */ 809 if (mii_phy_probe(dev, &sc->sf_miibus, 810 sf_ifmedia_upd, sf_ifmedia_sts)) { 811 printf("sf%d: MII without any phy!\n", sc->sf_unit); 812 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 813 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 814 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 815 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 816 error = ENXIO; 817 goto fail; 818 } 819 820 ifp = &sc->arpcom.ac_if; 821 ifp->if_softc = sc; 822 ifp->if_unit = unit; 823 ifp->if_name = "sf"; 824 ifp->if_mtu = ETHERMTU; 825 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 826 ifp->if_ioctl = sf_ioctl; 827 ifp->if_output = ether_output; 828 ifp->if_start = sf_start; 829 ifp->if_watchdog = sf_watchdog; 830 ifp->if_init = sf_init; 831 ifp->if_baudrate = 10000000; 832 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 833 834 /* 835 * Call MI attach routine. 836 */ 837 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 838 SF_UNLOCK(sc); 839 return(0); 840 841fail: 842 SF_UNLOCK(sc); 843 mtx_destroy(&sc->sf_mtx); 844 return(error); 845} 846 847static int 848sf_detach(dev) 849 device_t dev; 850{ 851 struct sf_softc *sc; 852 struct ifnet *ifp; 853 854 sc = device_get_softc(dev); 855 SF_LOCK(sc); 856 ifp = &sc->arpcom.ac_if; 857 858 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 859 sf_stop(sc); 860 861 bus_generic_detach(dev); 862 device_delete_child(dev, sc->sf_miibus); 863 864 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 865 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 866 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 867 868 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 869 870 SF_UNLOCK(sc); 871 mtx_destroy(&sc->sf_mtx); 872 873 return(0); 874} 875 876static int 877sf_init_rx_ring(sc) 878 struct sf_softc *sc; 879{ 880 struct sf_list_data *ld; 881 int i; 882 883 ld = sc->sf_ldata; 884 885 bzero((char *)ld->sf_rx_dlist_big, 886 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 887 bzero((char *)ld->sf_rx_clist, 888 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 889 890 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 891 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 892 return(ENOBUFS); 893 } 894 895 return(0); 896} 897 898static void 899sf_init_tx_ring(sc) 900 struct sf_softc *sc; 901{ 902 struct sf_list_data *ld; 903 int i; 904 905 ld = sc->sf_ldata; 906 907 bzero((char *)ld->sf_tx_dlist, 908 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 909 bzero((char *)ld->sf_tx_clist, 910 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 911 912 for (i = 0; i < SF_TX_DLIST_CNT; i++) 913 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 914 for (i = 0; i < SF_TX_CLIST_CNT; i++) 915 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 916 917 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 918 sc->sf_tx_cnt = 0; 919 920 return; 921} 922 923static int 924sf_newbuf(sc, c, m) 925 struct sf_softc *sc; 926 struct sf_rx_bufdesc_type0 *c; 927 struct mbuf *m; 928{ 929 struct mbuf *m_new = NULL; 930 931 if (m == NULL) { 932 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 933 if (m_new == NULL) 934 return(ENOBUFS); 935 936 MCLGET(m_new, M_DONTWAIT); 937 if (!(m_new->m_flags & M_EXT)) { 938 m_freem(m_new); 939 return(ENOBUFS); 940 } 941 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 942 } else { 943 m_new = m; 944 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 945 m_new->m_data = m_new->m_ext.ext_buf; 946 } 947 948 m_adj(m_new, sizeof(u_int64_t)); 949 950 c->sf_mbuf = m_new; 951 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 952 c->sf_valid = 1; 953 954 return(0); 955} 956 957/* 958 * The starfire is programmed to use 'normal' mode for packet reception, 959 * which means we use the consumer/producer model for both the buffer 960 * descriptor queue and the completion descriptor queue. The only problem 961 * with this is that it involves a lot of register accesses: we have to 962 * read the RX completion consumer and producer indexes and the RX buffer 963 * producer index, plus the RX completion consumer and RX buffer producer 964 * indexes have to be updated. It would have been easier if Adaptec had 965 * put each index in a separate register, especially given that the damn 966 * NIC has a 512K register space. 967 * 968 * In spite of all the lovely features that Adaptec crammed into the 6915, 969 * it is marred by one truly stupid design flaw, which is that receive 970 * buffer addresses must be aligned on a longword boundary. This forces 971 * the packet payload to be unaligned, which is suboptimal on the x86 and 972 * completely unuseable on the Alpha. Our only recourse is to copy received 973 * packets into properly aligned buffers before handing them off. 974 */ 975 976static void 977sf_rxeof(sc) 978 struct sf_softc *sc; 979{ 980 struct ether_header *eh; 981 struct mbuf *m; 982 struct ifnet *ifp; 983 struct sf_rx_bufdesc_type0 *desc; 984 struct sf_rx_cmpdesc_type3 *cur_rx; 985 u_int32_t rxcons, rxprod; 986 int cmpprodidx, cmpconsidx, bufprodidx; 987 988 ifp = &sc->arpcom.ac_if; 989 990 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 991 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 992 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 993 cmpconsidx = SF_IDX_LO(rxcons); 994 bufprodidx = SF_IDX_LO(rxprod); 995 996 while (cmpconsidx != cmpprodidx) { 997 struct mbuf *m0; 998 999 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 1000 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 1001 m = desc->sf_mbuf; 1002 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 1003 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 1004 1005 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 1006 ifp->if_ierrors++; 1007 sf_newbuf(sc, desc, m); 1008 continue; 1009 } 1010 1011 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 1012 ifp, NULL); 1013 sf_newbuf(sc, desc, m); 1014 if (m0 == NULL) { 1015 ifp->if_ierrors++; 1016 continue; 1017 } 1018 m = m0; 1019 1020 eh = mtod(m, struct ether_header *); 1021 ifp->if_ipackets++; 1022 1023 /* Remove header from mbuf and pass it on. */ 1024 m_adj(m, sizeof(struct ether_header)); 1025 ether_input(ifp, eh, m); 1026 } 1027 1028 csr_write_4(sc, SF_CQ_CONSIDX, 1029 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1030 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1031 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1032 1033 return; 1034} 1035 1036/* 1037 * Read the transmit status from the completion queue and release 1038 * mbufs. Note that the buffer descriptor index in the completion 1039 * descriptor is an offset from the start of the transmit buffer 1040 * descriptor list in bytes. This is important because the manual 1041 * gives the impression that it should match the producer/consumer 1042 * index, which is the offset in 8 byte blocks. 1043 */ 1044static void 1045sf_txeof(sc) 1046 struct sf_softc *sc; 1047{ 1048 int txcons, cmpprodidx, cmpconsidx; 1049 struct sf_tx_cmpdesc_type1 *cur_cmp; 1050 struct sf_tx_bufdesc_type0 *cur_tx; 1051 struct ifnet *ifp; 1052 1053 ifp = &sc->arpcom.ac_if; 1054 1055 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1056 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1057 cmpconsidx = SF_IDX_HI(txcons); 1058 1059 while (cmpconsidx != cmpprodidx) { 1060 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1061 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1062 1063 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1064 ifp->if_opackets++; 1065 else { 1066 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1067 sf_txthresh_adjust(sc); 1068 ifp->if_oerrors++; 1069 } 1070 1071 sc->sf_tx_cnt--; 1072 if (cur_tx->sf_mbuf != NULL) { 1073 m_freem(cur_tx->sf_mbuf); 1074 cur_tx->sf_mbuf = NULL; 1075 } else 1076 break; 1077 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1078 } 1079 1080 ifp->if_timer = 0; 1081 ifp->if_flags &= ~IFF_OACTIVE; 1082 1083 csr_write_4(sc, SF_CQ_CONSIDX, 1084 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1085 ((cmpconsidx << 16) & 0xFFFF0000)); 1086 1087 return; 1088} 1089 1090static void 1091sf_txthresh_adjust(sc) 1092 struct sf_softc *sc; 1093{ 1094 u_int32_t txfctl; 1095 u_int8_t txthresh; 1096 1097 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1098 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1099 if (txthresh < 0xFF) { 1100 txthresh++; 1101 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1102 txfctl |= txthresh; 1103#ifdef DIAGNOSTIC 1104 printf("sf%d: tx underrun, increasing " 1105 "tx threshold to %d bytes\n", 1106 sc->sf_unit, txthresh * 4); 1107#endif 1108 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1109 } 1110 1111 return; 1112} 1113 1114static void 1115sf_intr(arg) 1116 void *arg; 1117{ 1118 struct sf_softc *sc; 1119 struct ifnet *ifp; 1120 u_int32_t status; 1121 1122 sc = arg; 1123 SF_LOCK(sc); 1124 1125 ifp = &sc->arpcom.ac_if; 1126 1127 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1128 SF_UNLOCK(sc); 1129 return; 1130 } 1131 1132 /* Disable interrupts. */ 1133 csr_write_4(sc, SF_IMR, 0x00000000); 1134 1135 for (;;) { 1136 status = csr_read_4(sc, SF_ISR); 1137 if (status) 1138 csr_write_4(sc, SF_ISR, status); 1139 1140 if (!(status & SF_INTRS)) 1141 break; 1142 1143 if (status & SF_ISR_RXDQ1_DMADONE) 1144 sf_rxeof(sc); 1145 1146 if (status & SF_ISR_TX_TXDONE || 1147 status & SF_ISR_TX_DMADONE || 1148 status & SF_ISR_TX_QUEUEDONE) 1149 sf_txeof(sc); 1150 1151 if (status & SF_ISR_TX_LOFIFO) 1152 sf_txthresh_adjust(sc); 1153 1154 if (status & SF_ISR_ABNORMALINTR) { 1155 if (status & SF_ISR_STATSOFLOW) { 1156 untimeout(sf_stats_update, sc, 1157 sc->sf_stat_ch); 1158 sf_stats_update(sc); 1159 } else 1160 sf_init(sc); 1161 } 1162 } 1163 1164 /* Re-enable interrupts. */ 1165 csr_write_4(sc, SF_IMR, SF_INTRS); 1166 1167 if (ifp->if_snd.ifq_head != NULL) 1168 sf_start(ifp); 1169 1170 SF_UNLOCK(sc); 1171 return; 1172} 1173 1174static void 1175sf_init(xsc) 1176 void *xsc; 1177{ 1178 struct sf_softc *sc; 1179 struct ifnet *ifp; 1180 struct mii_data *mii; 1181 int i; 1182 1183 sc = xsc; 1184 SF_LOCK(sc); 1185 ifp = &sc->arpcom.ac_if; 1186 mii = device_get_softc(sc->sf_miibus); 1187 1188 sf_stop(sc); 1189 sf_reset(sc); 1190 1191 /* Init all the receive filter registers */ 1192 for (i = SF_RXFILT_PERFECT_BASE; 1193 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1194 csr_write_4(sc, i, 0); 1195 1196 /* Empty stats counter registers. */ 1197 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1198 csr_write_4(sc, SF_STATS_BASE + 1199 (i + sizeof(u_int32_t)), 0); 1200 1201 /* Init our MAC address */ 1202 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1203 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1204 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1205 1206 if (sf_init_rx_ring(sc) == ENOBUFS) { 1207 printf("sf%d: initialization failed: no " 1208 "memory for rx buffers\n", sc->sf_unit); 1209 SF_UNLOCK(sc); 1210 return; 1211 } 1212 1213 sf_init_tx_ring(sc); 1214 1215 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1216 1217 /* If we want promiscuous mode, set the allframes bit. */ 1218 if (ifp->if_flags & IFF_PROMISC) { 1219 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1220 } else { 1221 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1222 } 1223 1224 if (ifp->if_flags & IFF_BROADCAST) { 1225 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1226 } else { 1227 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1228 } 1229 1230 /* 1231 * Load the multicast filter. 1232 */ 1233 sf_setmulti(sc); 1234 1235 /* Init the completion queue indexes */ 1236 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1237 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1238 1239 /* Init the RX completion queue */ 1240 csr_write_4(sc, SF_RXCQ_CTL_1, 1241 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1242 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1243 1244 /* Init RX DMA control. */ 1245 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1246 1247 /* Init the RX buffer descriptor queue. */ 1248 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1249 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1250 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1251 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1252 1253 /* Init the TX completion queue */ 1254 csr_write_4(sc, SF_TXCQ_CTL, 1255 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1256 1257 /* Init the TX buffer descriptor queue. */ 1258 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1259 vtophys(sc->sf_ldata->sf_tx_dlist)); 1260 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1261 csr_write_4(sc, SF_TXDQ_CTL, 1262 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1263 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1264 1265 /* Enable autopadding of short TX frames. */ 1266 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1267 1268 /* Enable interrupts. */ 1269 csr_write_4(sc, SF_IMR, SF_INTRS); 1270 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1271 1272 /* Enable the RX and TX engines. */ 1273 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1274 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1275 1276 /*mii_mediachg(mii);*/ 1277 sf_ifmedia_upd(ifp); 1278 1279 ifp->if_flags |= IFF_RUNNING; 1280 ifp->if_flags &= ~IFF_OACTIVE; 1281 1282 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1283 1284 SF_UNLOCK(sc); 1285 1286 return; 1287} 1288 1289static int 1290sf_encap(sc, c, m_head) 1291 struct sf_softc *sc; 1292 struct sf_tx_bufdesc_type0 *c; 1293 struct mbuf *m_head; 1294{ 1295 int frag = 0; 1296 struct sf_frag *f = NULL; 1297 struct mbuf *m; 1298 1299 m = m_head; 1300 1301 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1302 if (m->m_len != 0) { 1303 if (frag == SF_MAXFRAGS) 1304 break; 1305 f = &c->sf_frags[frag]; 1306 if (frag == 0) 1307 f->sf_pktlen = m_head->m_pkthdr.len; 1308 f->sf_fraglen = m->m_len; 1309 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1310 frag++; 1311 } 1312 } 1313 1314 if (m != NULL) { 1315 struct mbuf *m_new = NULL; 1316 1317 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1318 if (m_new == NULL) { 1319 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1320 return(1); 1321 } 1322 1323 if (m_head->m_pkthdr.len > MHLEN) { 1324 MCLGET(m_new, M_DONTWAIT); 1325 if (!(m_new->m_flags & M_EXT)) { 1326 m_freem(m_new); 1327 printf("sf%d: no memory for tx list\n", 1328 sc->sf_unit); 1329 return(1); 1330 } 1331 } 1332 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1333 mtod(m_new, caddr_t)); 1334 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1335 m_freem(m_head); 1336 m_head = m_new; 1337 f = &c->sf_frags[0]; 1338 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1339 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1340 frag = 1; 1341 } 1342 1343 c->sf_mbuf = m_head; 1344 c->sf_id = SF_TX_BUFDESC_ID; 1345 c->sf_fragcnt = frag; 1346 c->sf_intr = 1; 1347 c->sf_caltcp = 0; 1348 c->sf_crcen = 1; 1349 1350 return(0); 1351} 1352 1353static void 1354sf_start(ifp) 1355 struct ifnet *ifp; 1356{ 1357 struct sf_softc *sc; 1358 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1359 struct mbuf *m_head = NULL; 1360 int i, txprod; 1361 1362 sc = ifp->if_softc; 1363 SF_LOCK(sc); 1364 1365 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1366 SF_UNLOCK(sc); 1367 return; 1368 } 1369 1370 if (ifp->if_flags & IFF_OACTIVE) { 1371 SF_UNLOCK(sc); 1372 return; 1373 } 1374 1375 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1376 i = SF_IDX_HI(txprod) >> 4; 1377 1378 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1379 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1380 sf_init(sc); 1381 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1382 i = SF_IDX_HI(txprod) >> 4; 1383 } 1384 1385 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1386 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1387 ifp->if_flags |= IFF_OACTIVE; 1388 cur_tx = NULL; 1389 break; 1390 } 1391 IF_DEQUEUE(&ifp->if_snd, m_head); 1392 if (m_head == NULL) 1393 break; 1394 1395 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1396 if (sf_encap(sc, cur_tx, m_head)) { 1397 IF_PREPEND(&ifp->if_snd, m_head); 1398 ifp->if_flags |= IFF_OACTIVE; 1399 cur_tx = NULL; 1400 break; 1401 } 1402 1403 /* 1404 * If there's a BPF listener, bounce a copy of this frame 1405 * to him. 1406 */ 1407 if (ifp->if_bpf) 1408 bpf_mtap(ifp, m_head); 1409 1410 SF_INC(i, SF_TX_DLIST_CNT); 1411 sc->sf_tx_cnt++; 1412 /* 1413 * Don't get the TX DMA queue get too full. 1414 */ 1415 if (sc->sf_tx_cnt > 64) 1416 break; 1417 } 1418 1419 if (cur_tx == NULL) { 1420 SF_UNLOCK(sc); 1421 return; 1422 } 1423 1424 /* Transmit */ 1425 csr_write_4(sc, SF_TXDQ_PRODIDX, 1426 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1427 ((i << 20) & 0xFFFF0000)); 1428 1429 ifp->if_timer = 5; 1430 1431 SF_UNLOCK(sc); 1432 1433 return; 1434} 1435 1436static void 1437sf_stop(sc) 1438 struct sf_softc *sc; 1439{ 1440 int i; 1441 struct ifnet *ifp; 1442 1443 SF_LOCK(sc); 1444 1445 ifp = &sc->arpcom.ac_if; 1446 1447 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1448 1449 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1450 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1451 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1452 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1453 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1454 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1455 csr_write_4(sc, SF_TXCQ_CTL, 0); 1456 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1457 csr_write_4(sc, SF_TXDQ_CTL, 0); 1458 sf_reset(sc); 1459 1460 sc->sf_link = 0; 1461 1462 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1463 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1464 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1465 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1466 } 1467 } 1468 1469 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1470 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1471 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1472 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1473 } 1474 } 1475 1476 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1477 SF_UNLOCK(sc); 1478 1479 return; 1480} 1481 1482/* 1483 * Note: it is important that this function not be interrupted. We 1484 * use a two-stage register access scheme: if we are interrupted in 1485 * between setting the indirect address register and reading from the 1486 * indirect data register, the contents of the address register could 1487 * be changed out from under us. 1488 */ 1489static void 1490sf_stats_update(xsc) 1491 void *xsc; 1492{ 1493 struct sf_softc *sc; 1494 struct ifnet *ifp; 1495 struct mii_data *mii; 1496 struct sf_stats stats; 1497 u_int32_t *ptr; 1498 int i; 1499 1500 sc = xsc; 1501 SF_LOCK(sc); 1502 ifp = &sc->arpcom.ac_if; 1503 mii = device_get_softc(sc->sf_miibus); 1504 1505 ptr = (u_int32_t *)&stats; 1506 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1507 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1508 (i + sizeof(u_int32_t))); 1509 1510 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1511 csr_write_4(sc, SF_STATS_BASE + 1512 (i + sizeof(u_int32_t)), 0); 1513 1514 ifp->if_collisions += stats.sf_tx_single_colls + 1515 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1516 1517 mii_tick(mii); 1518 1519 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1520 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1521 sc->sf_link++; 1522 if (ifp->if_snd.ifq_head != NULL) 1523 sf_start(ifp); 1524 } 1525 1526 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1527 1528 SF_UNLOCK(sc); 1529 1530 return; 1531} 1532 1533static void 1534sf_watchdog(ifp) 1535 struct ifnet *ifp; 1536{ 1537 struct sf_softc *sc; 1538 1539 sc = ifp->if_softc; 1540 1541 SF_LOCK(sc); 1542 1543 ifp->if_oerrors++; 1544 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1545 1546 sf_stop(sc); 1547 sf_reset(sc); 1548 sf_init(sc); 1549 1550 if (ifp->if_snd.ifq_head != NULL) 1551 sf_start(ifp); 1552 1553 SF_UNLOCK(sc); 1554 1555 return; 1556} 1557 1558static void 1559sf_shutdown(dev) 1560 device_t dev; 1561{ 1562 struct sf_softc *sc; 1563 1564 sc = device_get_softc(dev); 1565 1566 sf_stop(sc); 1567 1568 return; 1569} 1570