sdhci_pci.c revision 322119
1241600Sgonzo/*- 2241600Sgonzo * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3241600Sgonzo * All rights reserved. 4241600Sgonzo * 5241600Sgonzo * Redistribution and use in source and binary forms, with or without 6241600Sgonzo * modification, are permitted provided that the following conditions 7241600Sgonzo * are met: 8241600Sgonzo * 1. Redistributions of source code must retain the above copyright 9241600Sgonzo * notice, this list of conditions and the following disclaimer. 10241600Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11241600Sgonzo * notice, this list of conditions and the following disclaimer in the 12241600Sgonzo * documentation and/or other materials provided with the distribution. 13241600Sgonzo * 14241600Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15241600Sgonzo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16241600Sgonzo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17241600Sgonzo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18241600Sgonzo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19241600Sgonzo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20241600Sgonzo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21241600Sgonzo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22241600Sgonzo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23241600Sgonzo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24241600Sgonzo */ 25241600Sgonzo 26241600Sgonzo#include <sys/cdefs.h> 27241600Sgonzo__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/sdhci_pci.c 322119 2017-08-06 16:07:25Z marius $"); 28241600Sgonzo 29241600Sgonzo#include <sys/param.h> 30241600Sgonzo#include <sys/systm.h> 31241600Sgonzo#include <sys/bus.h> 32241600Sgonzo#include <sys/kernel.h> 33241600Sgonzo#include <sys/lock.h> 34241600Sgonzo#include <sys/module.h> 35241600Sgonzo#include <sys/mutex.h> 36241600Sgonzo#include <sys/resource.h> 37241600Sgonzo#include <sys/rman.h> 38241600Sgonzo#include <sys/sysctl.h> 39241600Sgonzo#include <sys/taskqueue.h> 40241600Sgonzo 41241600Sgonzo#include <dev/pci/pcireg.h> 42241600Sgonzo#include <dev/pci/pcivar.h> 43241600Sgonzo 44241600Sgonzo#include <machine/bus.h> 45241600Sgonzo#include <machine/resource.h> 46241600Sgonzo 47241600Sgonzo#include <dev/mmc/bridge.h> 48241600Sgonzo 49318197Smarius#include <dev/sdhci/sdhci.h> 50318197Smarius 51241600Sgonzo#include "mmcbr_if.h" 52241600Sgonzo#include "sdhci_if.h" 53241600Sgonzo 54241600Sgonzo/* 55241600Sgonzo * PCI registers 56241600Sgonzo */ 57318197Smarius#define PCI_SDHCI_IFPIO 0x00 58318197Smarius#define PCI_SDHCI_IFDMA 0x01 59318197Smarius#define PCI_SDHCI_IFVENDOR 0x02 60241600Sgonzo 61318197Smarius#define PCI_SLOT_INFO 0x40 /* 8 bits */ 62318197Smarius#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 63318197Smarius#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 64241600Sgonzo 65241600Sgonzo/* 66241600Sgonzo * RICOH specific PCI registers 67241600Sgonzo */ 68241600Sgonzo#define SDHC_PCI_MODE_KEY 0xf9 69241600Sgonzo#define SDHC_PCI_MODE 0x150 70312399Smarius#define SDHC_PCI_MODE_SD20 0x10 71241600Sgonzo#define SDHC_PCI_BASE_FREQ_KEY 0xfc 72241600Sgonzo#define SDHC_PCI_BASE_FREQ 0xe1 73241600Sgonzo 74241600Sgonzostatic const struct sdhci_device { 75241600Sgonzo uint32_t model; 76241600Sgonzo uint16_t subvendor; 77270885Smarius const char *desc; 78241600Sgonzo u_int quirks; 79241600Sgonzo} sdhci_devices[] = { 80318197Smarius { 0x08221180, 0xffff, "RICOH R5C822 SD", 81241600Sgonzo SDHCI_QUIRK_FORCE_DMA }, 82318197Smarius { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 83276469Smarius SDHCI_QUIRK_FORCE_DMA | 84276469Smarius SDHCI_QUIRK_LOWER_FREQUENCY }, 85318197Smarius { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 86241600Sgonzo SDHCI_QUIRK_LOWER_FREQUENCY }, 87318197Smarius { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 88241600Sgonzo SDHCI_QUIRK_FORCE_DMA }, 89318197Smarius { 0x05501524, 0xffff, "ENE CB712 SD", 90241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 91318197Smarius { 0x05511524, 0xffff, "ENE CB712 SD 2", 92241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 93318197Smarius { 0x07501524, 0xffff, "ENE CB714 SD", 94241600Sgonzo SDHCI_QUIRK_RESET_ON_IOS | 95241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 96318197Smarius { 0x07511524, 0xffff, "ENE CB714 SD 2", 97241600Sgonzo SDHCI_QUIRK_RESET_ON_IOS | 98241600Sgonzo SDHCI_QUIRK_BROKEN_TIMINGS }, 99318197Smarius { 0x410111ab, 0xffff, "Marvell CaFe SD", 100241600Sgonzo SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 101318197Smarius { 0x2381197B, 0xffff, "JMicron JMB38X SD", 102241600Sgonzo SDHCI_QUIRK_32BIT_DMA_SIZE | 103241600Sgonzo SDHCI_QUIRK_RESET_AFTER_REQUEST }, 104289359Sadrian { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 105289359Sadrian SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 106312399Smarius { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 107312399Smarius SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 108318197Smarius SDHCI_QUIRK_INTEL_POWER_UP_RESET | 109318494Smarius SDHCI_QUIRK_WAIT_WHILE_BUSY | 110318494Smarius SDHCI_QUIRK_MMC_DDR52 | 111318494Smarius SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 112318494Smarius SDHCI_QUIRK_PRESET_VALUE_BROKEN}, 113318197Smarius { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 114318494Smarius SDHCI_QUIRK_WAIT_WHILE_BUSY | 115318494Smarius SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 116312399Smarius { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 117312399Smarius SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 118318197Smarius SDHCI_QUIRK_INTEL_POWER_UP_RESET | 119318494Smarius SDHCI_QUIRK_WAIT_WHILE_BUSY | 120318494Smarius SDHCI_QUIRK_MMC_DDR52 | 121318494Smarius SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 122318494Smarius SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 123312399Smarius { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 124312399Smarius SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 125312399Smarius SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 126318197Smarius SDHCI_QUIRK_INTEL_POWER_UP_RESET | 127318494Smarius SDHCI_QUIRK_WAIT_WHILE_BUSY | 128318494Smarius SDHCI_QUIRK_MMC_DDR52 | 129318494Smarius SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 130318494Smarius SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 131318197Smarius { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 132318494Smarius SDHCI_QUIRK_WAIT_WHILE_BUSY | 133318494Smarius SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 134318197Smarius { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 135318496Smarius SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 136318494Smarius SDHCI_QUIRK_WAIT_WHILE_BUSY | 137318494Smarius SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 138312399Smarius { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 139318496Smarius SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 140312399Smarius SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 141318197Smarius SDHCI_QUIRK_INTEL_POWER_UP_RESET | 142318494Smarius SDHCI_QUIRK_WAIT_WHILE_BUSY | 143318494Smarius SDHCI_QUIRK_MMC_DDR52 | 144318494Smarius SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 145318494Smarius SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 146241600Sgonzo { 0, 0xffff, NULL, 147241600Sgonzo 0 } 148241600Sgonzo}; 149241600Sgonzo 150241600Sgonzostruct sdhci_pci_softc { 151241600Sgonzo u_int quirks; /* Chip specific quirks */ 152241600Sgonzo struct resource *irq_res; /* IRQ resource */ 153318197Smarius void *intrhand; /* Interrupt handle */ 154241600Sgonzo 155241600Sgonzo int num_slots; /* Number of slots on this controller */ 156241600Sgonzo struct sdhci_slot slots[6]; 157241600Sgonzo struct resource *mem_res[6]; /* Memory resource */ 158312399Smarius uint8_t cfg_freq; /* Saved frequency */ 159312399Smarius uint8_t cfg_mode; /* Saved mode */ 160241600Sgonzo}; 161241600Sgonzo 162270885Smariusstatic int sdhci_enable_msi = 1; 163270885SmariusSYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 164270885Smarius 0, "Enable MSI interrupts"); 165241600Sgonzo 166241600Sgonzostatic uint8_t 167318197Smariussdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 168241600Sgonzo{ 169241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 170241600Sgonzo 171241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 172241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 173241600Sgonzo return bus_read_1(sc->mem_res[slot->num], off); 174241600Sgonzo} 175241600Sgonzo 176241600Sgonzostatic void 177318197Smariussdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 178318197Smarius bus_size_t off, uint8_t val) 179241600Sgonzo{ 180241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 181241600Sgonzo 182241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 183241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 184241600Sgonzo bus_write_1(sc->mem_res[slot->num], off, val); 185241600Sgonzo} 186241600Sgonzo 187241600Sgonzostatic uint16_t 188318197Smariussdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 189241600Sgonzo{ 190241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 191241600Sgonzo 192241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 193241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 194241600Sgonzo return bus_read_2(sc->mem_res[slot->num], off); 195241600Sgonzo} 196241600Sgonzo 197241600Sgonzostatic void 198318197Smariussdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 199318197Smarius bus_size_t off, uint16_t val) 200241600Sgonzo{ 201241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 202241600Sgonzo 203241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 204241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 205241600Sgonzo bus_write_2(sc->mem_res[slot->num], off, val); 206241600Sgonzo} 207241600Sgonzo 208241600Sgonzostatic uint32_t 209318197Smariussdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 210241600Sgonzo{ 211241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 212241600Sgonzo 213241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 214241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 215241600Sgonzo return bus_read_4(sc->mem_res[slot->num], off); 216241600Sgonzo} 217241600Sgonzo 218241600Sgonzostatic void 219318197Smariussdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 220318197Smarius bus_size_t off, uint32_t val) 221241600Sgonzo{ 222241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 223241600Sgonzo 224241600Sgonzo bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 225241600Sgonzo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 226241600Sgonzo bus_write_4(sc->mem_res[slot->num], off, val); 227241600Sgonzo} 228241600Sgonzo 229241600Sgonzostatic void 230318197Smariussdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 231241600Sgonzo bus_size_t off, uint32_t *data, bus_size_t count) 232241600Sgonzo{ 233241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 234241600Sgonzo 235241600Sgonzo bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 236241600Sgonzo} 237241600Sgonzo 238241600Sgonzostatic void 239318197Smariussdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 240241600Sgonzo bus_size_t off, uint32_t *data, bus_size_t count) 241241600Sgonzo{ 242241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 243241600Sgonzo 244241600Sgonzo bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 245241600Sgonzo} 246241600Sgonzo 247241600Sgonzostatic void sdhci_pci_intr(void *arg); 248241600Sgonzo 249241600Sgonzostatic void 250241600Sgonzosdhci_lower_frequency(device_t dev) 251241600Sgonzo{ 252276469Smarius struct sdhci_pci_softc *sc = device_get_softc(dev); 253241600Sgonzo 254276469Smarius /* 255276469Smarius * Enable SD2.0 mode. 256276469Smarius * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 257276469Smarius */ 258241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 259276469Smarius sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 260241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 261241600Sgonzo pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 262241600Sgonzo 263241600Sgonzo /* 264241600Sgonzo * Some SD/MMC cards don't work with the default base 265276469Smarius * clock frequency of 200 MHz. Lower it to 50 MHz. 266241600Sgonzo */ 267241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 268276469Smarius sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 269241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 270241600Sgonzo pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 271241600Sgonzo} 272241600Sgonzo 273276469Smariusstatic void 274276469Smariussdhci_restore_frequency(device_t dev) 275276469Smarius{ 276276469Smarius struct sdhci_pci_softc *sc = device_get_softc(dev); 277276469Smarius 278276469Smarius /* Restore mode. */ 279276469Smarius pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 280276469Smarius pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 281276469Smarius pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 282276469Smarius 283276469Smarius /* Restore frequency. */ 284276469Smarius pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 285276469Smarius pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 286276469Smarius pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 287276469Smarius} 288276469Smarius 289241600Sgonzostatic int 290241600Sgonzosdhci_pci_probe(device_t dev) 291241600Sgonzo{ 292241600Sgonzo uint32_t model; 293241600Sgonzo uint16_t subvendor; 294241600Sgonzo uint8_t class, subclass; 295241600Sgonzo int i, result; 296270885Smarius 297241600Sgonzo model = (uint32_t)pci_get_device(dev) << 16; 298241600Sgonzo model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 299241600Sgonzo subvendor = pci_get_subvendor(dev); 300241600Sgonzo class = pci_get_class(dev); 301241600Sgonzo subclass = pci_get_subclass(dev); 302270885Smarius 303241600Sgonzo result = ENXIO; 304241600Sgonzo for (i = 0; sdhci_devices[i].model != 0; i++) { 305241600Sgonzo if (sdhci_devices[i].model == model && 306241600Sgonzo (sdhci_devices[i].subvendor == 0xffff || 307241600Sgonzo sdhci_devices[i].subvendor == subvendor)) { 308241600Sgonzo device_set_desc(dev, sdhci_devices[i].desc); 309241600Sgonzo result = BUS_PROBE_DEFAULT; 310241600Sgonzo break; 311241600Sgonzo } 312241600Sgonzo } 313241600Sgonzo if (result == ENXIO && class == PCIC_BASEPERIPH && 314241600Sgonzo subclass == PCIS_BASEPERIPH_SDHC) { 315241600Sgonzo device_set_desc(dev, "Generic SD HCI"); 316241600Sgonzo result = BUS_PROBE_GENERIC; 317241600Sgonzo } 318270885Smarius 319241600Sgonzo return (result); 320241600Sgonzo} 321241600Sgonzo 322241600Sgonzostatic int 323241600Sgonzosdhci_pci_attach(device_t dev) 324241600Sgonzo{ 325241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 326318197Smarius struct sdhci_slot *slot; 327241600Sgonzo uint32_t model; 328241600Sgonzo uint16_t subvendor; 329270885Smarius int bar, err, rid, slots, i; 330241600Sgonzo 331241600Sgonzo model = (uint32_t)pci_get_device(dev) << 16; 332241600Sgonzo model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 333241600Sgonzo subvendor = pci_get_subvendor(dev); 334241600Sgonzo /* Apply chip specific quirks. */ 335241600Sgonzo for (i = 0; sdhci_devices[i].model != 0; i++) { 336241600Sgonzo if (sdhci_devices[i].model == model && 337241600Sgonzo (sdhci_devices[i].subvendor == 0xffff || 338241600Sgonzo sdhci_devices[i].subvendor == subvendor)) { 339241600Sgonzo sc->quirks = sdhci_devices[i].quirks; 340241600Sgonzo break; 341241600Sgonzo } 342241600Sgonzo } 343318494Smarius sc->quirks &= ~sdhci_quirk_clear; 344318494Smarius sc->quirks |= sdhci_quirk_set; 345318496Smarius 346241600Sgonzo /* Some controllers need to be bumped into the right mode. */ 347241600Sgonzo if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 348241600Sgonzo sdhci_lower_frequency(dev); 349241600Sgonzo /* Read slots info from PCI registers. */ 350241600Sgonzo slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 351241600Sgonzo bar = PCI_SLOT_INFO_FIRST_BAR(slots); 352241600Sgonzo slots = PCI_SLOT_INFO_SLOTS(slots); 353241600Sgonzo if (slots > 6 || bar > 5) { 354241600Sgonzo device_printf(dev, "Incorrect slots information (%d, %d).\n", 355241600Sgonzo slots, bar); 356241600Sgonzo return (EINVAL); 357241600Sgonzo } 358241600Sgonzo /* Allocate IRQ. */ 359270885Smarius i = 1; 360270885Smarius rid = 0; 361270885Smarius if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 362270885Smarius rid = 1; 363270885Smarius sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 364270885Smarius RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 365241600Sgonzo if (sc->irq_res == NULL) { 366241600Sgonzo device_printf(dev, "Can't allocate IRQ\n"); 367270885Smarius pci_release_msi(dev); 368241600Sgonzo return (ENOMEM); 369241600Sgonzo } 370241600Sgonzo /* Scan all slots. */ 371241600Sgonzo for (i = 0; i < slots; i++) { 372318197Smarius slot = &sc->slots[sc->num_slots]; 373241600Sgonzo 374241600Sgonzo /* Allocate memory. */ 375270885Smarius rid = PCIR_BAR(bar + i); 376296135Sjhibbits sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 377296135Sjhibbits &rid, RF_ACTIVE); 378241600Sgonzo if (sc->mem_res[i] == NULL) { 379318197Smarius device_printf(dev, 380318197Smarius "Can't allocate memory for slot %d\n", i); 381241600Sgonzo continue; 382241600Sgonzo } 383318197Smarius 384289359Sadrian slot->quirks = sc->quirks; 385241600Sgonzo 386241600Sgonzo if (sdhci_init_slot(dev, slot, i) != 0) 387241600Sgonzo continue; 388241600Sgonzo 389241600Sgonzo sc->num_slots++; 390241600Sgonzo } 391241600Sgonzo device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 392241600Sgonzo /* Activate the interrupt */ 393241600Sgonzo err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 394241600Sgonzo NULL, sdhci_pci_intr, sc, &sc->intrhand); 395241600Sgonzo if (err) 396241600Sgonzo device_printf(dev, "Can't setup IRQ\n"); 397241600Sgonzo pci_enable_busmaster(dev); 398241600Sgonzo /* Process cards detection. */ 399318197Smarius for (i = 0; i < sc->num_slots; i++) 400318197Smarius sdhci_start_slot(&sc->slots[i]); 401241600Sgonzo 402241600Sgonzo return (0); 403241600Sgonzo} 404241600Sgonzo 405241600Sgonzostatic int 406241600Sgonzosdhci_pci_detach(device_t dev) 407241600Sgonzo{ 408241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 409241600Sgonzo int i; 410241600Sgonzo 411241600Sgonzo bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 412241600Sgonzo bus_release_resource(dev, SYS_RES_IRQ, 413270885Smarius rman_get_rid(sc->irq_res), sc->irq_res); 414270885Smarius pci_release_msi(dev); 415241600Sgonzo 416241600Sgonzo for (i = 0; i < sc->num_slots; i++) { 417318197Smarius sdhci_cleanup_slot(&sc->slots[i]); 418241600Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 419270885Smarius rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 420241600Sgonzo } 421276469Smarius if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 422276469Smarius sdhci_restore_frequency(dev); 423241600Sgonzo return (0); 424241600Sgonzo} 425241600Sgonzo 426241600Sgonzostatic int 427276469Smariussdhci_pci_shutdown(device_t dev) 428276469Smarius{ 429276469Smarius struct sdhci_pci_softc *sc = device_get_softc(dev); 430276469Smarius 431276469Smarius if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 432276469Smarius sdhci_restore_frequency(dev); 433276469Smarius return (0); 434276469Smarius} 435276469Smarius 436276469Smariusstatic int 437241600Sgonzosdhci_pci_suspend(device_t dev) 438241600Sgonzo{ 439241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 440241600Sgonzo int i, err; 441241600Sgonzo 442241600Sgonzo err = bus_generic_suspend(dev); 443241600Sgonzo if (err) 444241600Sgonzo return (err); 445241600Sgonzo for (i = 0; i < sc->num_slots; i++) 446270885Smarius sdhci_generic_suspend(&sc->slots[i]); 447241600Sgonzo return (0); 448241600Sgonzo} 449241600Sgonzo 450241600Sgonzostatic int 451241600Sgonzosdhci_pci_resume(device_t dev) 452241600Sgonzo{ 453241600Sgonzo struct sdhci_pci_softc *sc = device_get_softc(dev); 454299414Strasz int i, err; 455241600Sgonzo 456241600Sgonzo for (i = 0; i < sc->num_slots; i++) 457241600Sgonzo sdhci_generic_resume(&sc->slots[i]); 458299414Strasz err = bus_generic_resume(dev); 459299414Strasz if (err) 460299414Strasz return (err); 461299414Strasz if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 462299414Strasz sdhci_lower_frequency(dev); 463299414Strasz return (0); 464241600Sgonzo} 465241600Sgonzo 466241600Sgonzostatic void 467241600Sgonzosdhci_pci_intr(void *arg) 468241600Sgonzo{ 469241600Sgonzo struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 470241600Sgonzo int i; 471241600Sgonzo 472318197Smarius for (i = 0; i < sc->num_slots; i++) 473318197Smarius sdhci_generic_intr(&sc->slots[i]); 474241600Sgonzo} 475241600Sgonzo 476241600Sgonzostatic device_method_t sdhci_methods[] = { 477241600Sgonzo /* device_if */ 478318197Smarius DEVMETHOD(device_probe, sdhci_pci_probe), 479318197Smarius DEVMETHOD(device_attach, sdhci_pci_attach), 480318197Smarius DEVMETHOD(device_detach, sdhci_pci_detach), 481318197Smarius DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 482318197Smarius DEVMETHOD(device_suspend, sdhci_pci_suspend), 483318197Smarius DEVMETHOD(device_resume, sdhci_pci_resume), 484241600Sgonzo 485241600Sgonzo /* Bus interface */ 486241600Sgonzo DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 487241600Sgonzo DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 488241600Sgonzo 489241600Sgonzo /* mmcbr_if */ 490318197Smarius DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 491318494Smarius DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 492322119Smarius DEVMETHOD(mmcbr_tune, sdhci_generic_tune), 493322119Smarius DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 494318197Smarius DEVMETHOD(mmcbr_request, sdhci_generic_request), 495318197Smarius DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 496312399Smarius DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 497312399Smarius DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 498241600Sgonzo 499318494Smarius /* SDHCI accessors */ 500241600Sgonzo DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 501241600Sgonzo DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 502241600Sgonzo DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 503241600Sgonzo DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 504241600Sgonzo DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 505241600Sgonzo DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 506241600Sgonzo DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 507241600Sgonzo DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 508318494Smarius DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), 509241600Sgonzo 510246128Ssbz DEVMETHOD_END 511241600Sgonzo}; 512241600Sgonzo 513241600Sgonzostatic driver_t sdhci_pci_driver = { 514241600Sgonzo "sdhci_pci", 515241600Sgonzo sdhci_methods, 516241600Sgonzo sizeof(struct sdhci_pci_softc), 517241600Sgonzo}; 518241600Sgonzostatic devclass_t sdhci_pci_devclass; 519241600Sgonzo 520270885SmariusDRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 521270885Smarius NULL); 522241600SgonzoMODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 523318197SmariusMMC_DECLARE_BRIDGE(sdhci_pci); 524