1/*- 2 * Copyright (c) 2012 Thomas Skibo 3 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27/* Generic driver to attach sdhci controllers on simplebus. 28 * Derived mainly from sdhci_pci.c 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/11/sys/dev/sdhci/sdhci_fdt.c 343504 2019-01-27 19:04:28Z marius $"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/module.h> 40#include <sys/mutex.h> 41#include <sys/resource.h> 42#include <sys/rman.h> 43#include <sys/sysctl.h> 44#include <sys/taskqueue.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48 49#include <dev/fdt/fdt_common.h> 50#include <dev/ofw/ofw_bus.h> 51#include <dev/ofw/ofw_bus_subr.h> 52 53#include <dev/mmc/bridge.h> 54 55#include <dev/sdhci/sdhci.h> 56 57#include "mmcbr_if.h" 58#include "sdhci_if.h" 59 60#define MAX_SLOTS 6 61 62struct sdhci_fdt_softc { 63 device_t dev; /* Controller device */ 64 u_int quirks; /* Chip specific quirks */ 65 u_int caps; /* If we override SDHCI_CAPABILITIES */ 66 uint32_t max_clk; /* Max possible freq */ 67 struct resource *irq_res; /* IRQ resource */ 68 void *intrhand; /* Interrupt handle */ 69 70 int num_slots; /* Number of slots on this controller*/ 71 struct sdhci_slot slots[MAX_SLOTS]; 72 struct resource *mem_res[MAX_SLOTS]; /* Memory resource */ 73 74 bool wp_inverted; /* WP pin is inverted */ 75 bool no_18v; /* No 1.8V support */ 76}; 77 78static uint8_t 79sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 80{ 81 struct sdhci_fdt_softc *sc = device_get_softc(dev); 82 83 return (bus_read_1(sc->mem_res[slot->num], off)); 84} 85 86static void 87sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 88 uint8_t val) 89{ 90 struct sdhci_fdt_softc *sc = device_get_softc(dev); 91 92 bus_write_1(sc->mem_res[slot->num], off, val); 93} 94 95static uint16_t 96sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 97{ 98 struct sdhci_fdt_softc *sc = device_get_softc(dev); 99 100 return (bus_read_2(sc->mem_res[slot->num], off)); 101} 102 103static void 104sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 105 uint16_t val) 106{ 107 struct sdhci_fdt_softc *sc = device_get_softc(dev); 108 109 bus_write_2(sc->mem_res[slot->num], off, val); 110} 111 112static uint32_t 113sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 114{ 115 struct sdhci_fdt_softc *sc = device_get_softc(dev); 116 uint32_t val32; 117 118 val32 = bus_read_4(sc->mem_res[slot->num], off); 119 if (off == SDHCI_CAPABILITIES && sc->no_18v) 120 val32 &= ~SDHCI_CAN_VDD_180; 121 122 return (val32); 123} 124 125static void 126sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 127 uint32_t val) 128{ 129 struct sdhci_fdt_softc *sc = device_get_softc(dev); 130 131 bus_write_4(sc->mem_res[slot->num], off, val); 132} 133 134static void 135sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, 136 bus_size_t off, uint32_t *data, bus_size_t count) 137{ 138 struct sdhci_fdt_softc *sc = device_get_softc(dev); 139 140 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); 141} 142 143static void 144sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 145 bus_size_t off, uint32_t *data, bus_size_t count) 146{ 147 struct sdhci_fdt_softc *sc = device_get_softc(dev); 148 149 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); 150} 151 152static void 153sdhci_fdt_intr(void *arg) 154{ 155 struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; 156 int i; 157 158 for (i = 0; i < sc->num_slots; i++) 159 sdhci_generic_intr(&sc->slots[i]); 160} 161 162static int 163sdhci_fdt_get_ro(device_t bus, device_t dev) 164{ 165 struct sdhci_fdt_softc *sc = device_get_softc(bus); 166 167 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); 168} 169 170static int 171sdhci_fdt_probe(device_t dev) 172{ 173 struct sdhci_fdt_softc *sc = device_get_softc(dev); 174 phandle_t node; 175 pcell_t cid; 176 177 sc->quirks = 0; 178 sc->num_slots = 1; 179 sc->max_clk = 0; 180 181 if (!ofw_bus_status_okay(dev)) 182 return (ENXIO); 183 184 if (ofw_bus_is_compatible(dev, "sdhci_generic")) { 185 device_set_desc(dev, "generic fdt SDHCI controller"); 186 } else if (ofw_bus_is_compatible(dev, "xlnx,zy7_sdhci")) { 187 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 188 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); 189 } else 190 return (ENXIO); 191 192 node = ofw_bus_get_node(dev); 193 194 /* Allow dts to patch quirks, slots, and max-frequency. */ 195 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 196 sc->quirks = cid; 197 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) 198 sc->num_slots = cid; 199 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 200 sc->max_clk = cid; 201 if (OF_hasprop(node, "no-1-8-v")) 202 sc->no_18v = true; 203 if (OF_hasprop(node, "wp-inverted")) 204 sc->wp_inverted = true; 205 206 return (0); 207} 208 209static int 210sdhci_fdt_attach(device_t dev) 211{ 212 struct sdhci_fdt_softc *sc = device_get_softc(dev); 213 struct sdhci_slot *slot; 214 int err, slots, rid, i; 215 216 sc->dev = dev; 217 218 /* Allocate IRQ. */ 219 rid = 0; 220 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 221 RF_ACTIVE); 222 if (sc->irq_res == NULL) { 223 device_printf(dev, "Can't allocate IRQ\n"); 224 return (ENOMEM); 225 } 226 227 /* Scan all slots. */ 228 slots = sc->num_slots; /* number of slots determined in probe(). */ 229 sc->num_slots = 0; 230 for (i = 0; i < slots; i++) { 231 slot = &sc->slots[sc->num_slots]; 232 233 /* Allocate memory. */ 234 rid = 0; 235 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 236 &rid, RF_ACTIVE); 237 if (sc->mem_res[i] == NULL) { 238 device_printf(dev, 239 "Can't allocate memory for slot %d\n", i); 240 continue; 241 } 242 243 slot->quirks = sc->quirks; 244 slot->caps = sc->caps; 245 slot->max_clk = sc->max_clk; 246 247 if (sdhci_init_slot(dev, slot, i) != 0) 248 continue; 249 250 sc->num_slots++; 251 } 252 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 253 254 /* Activate the interrupt */ 255 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 256 NULL, sdhci_fdt_intr, sc, &sc->intrhand); 257 if (err) { 258 device_printf(dev, "Cannot setup IRQ\n"); 259 return (err); 260 } 261 262 /* Process cards detection. */ 263 for (i = 0; i < sc->num_slots; i++) 264 sdhci_start_slot(&sc->slots[i]); 265 266 return (0); 267} 268 269static int 270sdhci_fdt_detach(device_t dev) 271{ 272 struct sdhci_fdt_softc *sc = device_get_softc(dev); 273 int i; 274 275 bus_generic_detach(dev); 276 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 277 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 278 sc->irq_res); 279 280 for (i = 0; i < sc->num_slots; i++) { 281 sdhci_cleanup_slot(&sc->slots[i]); 282 bus_release_resource(dev, SYS_RES_MEMORY, 283 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 284 } 285 286 return (0); 287} 288 289static device_method_t sdhci_fdt_methods[] = { 290 /* device_if */ 291 DEVMETHOD(device_probe, sdhci_fdt_probe), 292 DEVMETHOD(device_attach, sdhci_fdt_attach), 293 DEVMETHOD(device_detach, sdhci_fdt_detach), 294 295 /* Bus interface */ 296 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 297 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 298 299 /* mmcbr_if */ 300 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 301 DEVMETHOD(mmcbr_request, sdhci_generic_request), 302 DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro), 303 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 304 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 305 306 /* SDHCI registers accessors */ 307 DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), 308 DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2), 309 DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4), 310 DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4), 311 DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1), 312 DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2), 313 DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), 314 DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), 315 316 DEVMETHOD_END 317}; 318 319static driver_t sdhci_fdt_driver = { 320 "sdhci_fdt", 321 sdhci_fdt_methods, 322 sizeof(struct sdhci_fdt_softc), 323}; 324static devclass_t sdhci_fdt_devclass; 325 326DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, sdhci_fdt_devclass, 327 NULL, NULL); 328SDHCI_DEPEND(sdhci_fdt); 329MMC_DECLARE_BRIDGE(sdhci_fdt); 330