safe.c revision 232874
1117845Ssam/*- 2117845Ssam * Copyright (c) 2003 Sam Leffler, Errno Consulting 3117845Ssam * Copyright (c) 2003 Global Technology Associates, Inc. 4117845Ssam * All rights reserved. 5117845Ssam * 6117845Ssam * Redistribution and use in source and binary forms, with or without 7117845Ssam * modification, are permitted provided that the following conditions 8117845Ssam * are met: 9117845Ssam * 1. Redistributions of source code must retain the above copyright 10117845Ssam * notice, this list of conditions and the following disclaimer. 11117845Ssam * 2. Redistributions in binary form must reproduce the above copyright 12117845Ssam * notice, this list of conditions and the following disclaimer in the 13117845Ssam * documentation and/or other materials provided with the distribution. 14117845Ssam * 15117845Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16117845Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17117845Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18117845Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19117845Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20117845Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21117845Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22117845Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23117845Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24117845Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25117845Ssam * SUCH DAMAGE. 26117845Ssam */ 27117845Ssam 28117845Ssam#include <sys/cdefs.h> 29117845Ssam__FBSDID("$FreeBSD: head/sys/dev/safe/safe.c 232874 2012-03-12 18:15:08Z scottl $"); 30117845Ssam 31117845Ssam/* 32117845Ssam * SafeNet SafeXcel-1141 hardware crypto accelerator 33117845Ssam */ 34117845Ssam#include "opt_safe.h" 35117845Ssam 36117845Ssam#include <sys/param.h> 37117845Ssam#include <sys/systm.h> 38117845Ssam#include <sys/proc.h> 39117845Ssam#include <sys/errno.h> 40117845Ssam#include <sys/malloc.h> 41117845Ssam#include <sys/kernel.h> 42117845Ssam#include <sys/mbuf.h> 43129879Sphk#include <sys/module.h> 44117845Ssam#include <sys/lock.h> 45117845Ssam#include <sys/mutex.h> 46117845Ssam#include <sys/sysctl.h> 47117845Ssam#include <sys/endian.h> 48117845Ssam 49117845Ssam#include <vm/vm.h> 50117845Ssam#include <vm/pmap.h> 51117845Ssam 52117845Ssam#include <machine/bus.h> 53117845Ssam#include <machine/resource.h> 54117845Ssam#include <sys/bus.h> 55117845Ssam#include <sys/rman.h> 56117845Ssam 57117845Ssam#include <crypto/sha1.h> 58117845Ssam#include <opencrypto/cryptodev.h> 59117845Ssam#include <opencrypto/cryptosoft.h> 60117845Ssam#include <sys/md5.h> 61117845Ssam#include <sys/random.h> 62167755Ssam#include <sys/kobj.h> 63117845Ssam 64167755Ssam#include "cryptodev_if.h" 65167755Ssam 66119287Simp#include <dev/pci/pcivar.h> 67119287Simp#include <dev/pci/pcireg.h> 68117845Ssam 69117845Ssam#ifdef SAFE_RNDTEST 70117845Ssam#include <dev/rndtest/rndtest.h> 71117845Ssam#endif 72117845Ssam#include <dev/safe/safereg.h> 73117845Ssam#include <dev/safe/safevar.h> 74117845Ssam 75117845Ssam#ifndef bswap32 76117845Ssam#define bswap32 NTOHL 77117845Ssam#endif 78117845Ssam 79117845Ssam/* 80117845Ssam * Prototypes and count for the pci_device structure 81117845Ssam */ 82117845Ssamstatic int safe_probe(device_t); 83117845Ssamstatic int safe_attach(device_t); 84117845Ssamstatic int safe_detach(device_t); 85117845Ssamstatic int safe_suspend(device_t); 86117845Ssamstatic int safe_resume(device_t); 87188178Simpstatic int safe_shutdown(device_t); 88117845Ssam 89167755Ssamstatic int safe_newsession(device_t, u_int32_t *, struct cryptoini *); 90167755Ssamstatic int safe_freesession(device_t, u_int64_t); 91167755Ssamstatic int safe_process(device_t, struct cryptop *, int); 92167755Ssam 93117845Ssamstatic device_method_t safe_methods[] = { 94117845Ssam /* Device interface */ 95117845Ssam DEVMETHOD(device_probe, safe_probe), 96117845Ssam DEVMETHOD(device_attach, safe_attach), 97117845Ssam DEVMETHOD(device_detach, safe_detach), 98117845Ssam DEVMETHOD(device_suspend, safe_suspend), 99117845Ssam DEVMETHOD(device_resume, safe_resume), 100117845Ssam DEVMETHOD(device_shutdown, safe_shutdown), 101117845Ssam 102167755Ssam /* crypto device methods */ 103167755Ssam DEVMETHOD(cryptodev_newsession, safe_newsession), 104167755Ssam DEVMETHOD(cryptodev_freesession,safe_freesession), 105167755Ssam DEVMETHOD(cryptodev_process, safe_process), 106167755Ssam 107227843Smarius DEVMETHOD_END 108117845Ssam}; 109117845Ssamstatic driver_t safe_driver = { 110117845Ssam "safe", 111117845Ssam safe_methods, 112117845Ssam sizeof (struct safe_softc) 113117845Ssam}; 114117845Ssamstatic devclass_t safe_devclass; 115117845Ssam 116117845SsamDRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 117117845SsamMODULE_DEPEND(safe, crypto, 1, 1, 1); 118117845Ssam#ifdef SAFE_RNDTEST 119117845SsamMODULE_DEPEND(safe, rndtest, 1, 1, 1); 120117845Ssam#endif 121117845Ssam 122117845Ssamstatic void safe_intr(void *); 123117845Ssamstatic void safe_callback(struct safe_softc *, struct safe_ringentry *); 124117845Ssamstatic void safe_feed(struct safe_softc *, struct safe_ringentry *); 125117845Ssamstatic void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 126117845Ssam#ifndef SAFE_NO_RNG 127117845Ssamstatic void safe_rng_init(struct safe_softc *); 128117845Ssamstatic void safe_rng(void *); 129117845Ssam#endif /* SAFE_NO_RNG */ 130117845Ssamstatic int safe_dma_malloc(struct safe_softc *, bus_size_t, 131117845Ssam struct safe_dma_alloc *, int); 132117845Ssam#define safe_dma_sync(_dma, _flags) \ 133117845Ssam bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 134117845Ssamstatic void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 135117845Ssamstatic int safe_dmamap_aligned(const struct safe_operand *); 136117845Ssamstatic int safe_dmamap_uniform(const struct safe_operand *); 137117845Ssam 138117845Ssamstatic void safe_reset_board(struct safe_softc *); 139117845Ssamstatic void safe_init_board(struct safe_softc *); 140117845Ssamstatic void safe_init_pciregs(device_t dev); 141117845Ssamstatic void safe_cleanchip(struct safe_softc *); 142117845Ssamstatic void safe_totalreset(struct safe_softc *); 143117845Ssam 144117845Ssamstatic int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 145117845Ssam 146227309Sedstatic SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, 147227309Sed "SafeNet driver parameters"); 148117845Ssam 149117845Ssam#ifdef SAFE_DEBUG 150117845Ssamstatic void safe_dump_dmastatus(struct safe_softc *, const char *); 151117845Ssamstatic void safe_dump_ringstate(struct safe_softc *, const char *); 152117845Ssamstatic void safe_dump_intrstate(struct safe_softc *, const char *); 153117845Ssamstatic void safe_dump_request(struct safe_softc *, const char *, 154117845Ssam struct safe_ringentry *); 155117845Ssam 156117845Ssamstatic struct safe_softc *safec; /* for use by hw.safe.dump */ 157117845Ssam 158117845Ssamstatic int safe_debug = 0; 159117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 160117845Ssam 0, "control debugging msgs"); 161117845Ssam#define DPRINTF(_x) if (safe_debug) printf _x 162117845Ssam#else 163117845Ssam#define DPRINTF(_x) 164117845Ssam#endif 165117845Ssam 166117845Ssam#define READ_REG(sc,r) \ 167117845Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 168117845Ssam 169117845Ssam#define WRITE_REG(sc,reg,val) \ 170117845Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 171117845Ssam 172117845Ssamstruct safe_stats safestats; 173117845SsamSYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 174117845Ssam safe_stats, "driver statistics"); 175117845Ssam#ifndef SAFE_NO_RNG 176117845Ssamstatic int safe_rnginterval = 1; /* poll once a second */ 177117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 178117845Ssam 0, "RNG polling interval (secs)"); 179117845Ssamstatic int safe_rngbufsize = 16; /* 64 bytes each poll */ 180117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 181117845Ssam 0, "RNG polling buffer size (32-bit words)"); 182117845Ssamstatic int safe_rngmaxalarm = 8; /* max alarms before reset */ 183117845SsamSYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 184117845Ssam 0, "RNG max alarms before reset"); 185117845Ssam#endif /* SAFE_NO_RNG */ 186117845Ssam 187117845Ssamstatic int 188117845Ssamsafe_probe(device_t dev) 189117845Ssam{ 190117845Ssam if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 191117845Ssam pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 192142890Simp return (BUS_PROBE_DEFAULT); 193117845Ssam return (ENXIO); 194117845Ssam} 195117845Ssam 196117845Ssamstatic const char* 197117845Ssamsafe_partname(struct safe_softc *sc) 198117845Ssam{ 199117845Ssam /* XXX sprintf numbers when not decoded */ 200117845Ssam switch (pci_get_vendor(sc->sc_dev)) { 201117845Ssam case PCI_VENDOR_SAFENET: 202117845Ssam switch (pci_get_device(sc->sc_dev)) { 203117845Ssam case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 204117845Ssam } 205117845Ssam return "SafeNet unknown-part"; 206117845Ssam } 207117845Ssam return "Unknown-vendor unknown-part"; 208117845Ssam} 209117845Ssam 210117845Ssam#ifndef SAFE_NO_RNG 211117845Ssamstatic void 212117845Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 213117845Ssam{ 214117845Ssam random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 215117845Ssam} 216117845Ssam#endif /* SAFE_NO_RNG */ 217117845Ssam 218117845Ssamstatic int 219117845Ssamsafe_attach(device_t dev) 220117845Ssam{ 221117845Ssam struct safe_softc *sc = device_get_softc(dev); 222117845Ssam u_int32_t raddr; 223117845Ssam u_int32_t cmd, i, devinfo; 224117845Ssam int rid; 225117845Ssam 226117845Ssam bzero(sc, sizeof (*sc)); 227117845Ssam sc->sc_dev = dev; 228117845Ssam 229117845Ssam /* XXX handle power management */ 230117845Ssam 231117845Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 232117845Ssam cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 233117845Ssam pci_write_config(dev, PCIR_COMMAND, cmd, 4); 234117845Ssam cmd = pci_read_config(dev, PCIR_COMMAND, 4); 235117845Ssam 236117845Ssam if (!(cmd & PCIM_CMD_MEMEN)) { 237117845Ssam device_printf(dev, "failed to enable memory mapping\n"); 238117845Ssam goto bad; 239117845Ssam } 240117845Ssam 241117845Ssam if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 242117845Ssam device_printf(dev, "failed to enable bus mastering\n"); 243117845Ssam goto bad; 244117845Ssam } 245117845Ssam 246117845Ssam /* 247117845Ssam * Setup memory-mapping of PCI registers. 248117845Ssam */ 249117845Ssam rid = BS_BAR; 250127135Snjl sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 251127135Snjl RF_ACTIVE); 252117845Ssam if (sc->sc_sr == NULL) { 253117845Ssam device_printf(dev, "cannot map register space\n"); 254117845Ssam goto bad; 255117845Ssam } 256117845Ssam sc->sc_st = rman_get_bustag(sc->sc_sr); 257117845Ssam sc->sc_sh = rman_get_bushandle(sc->sc_sr); 258117845Ssam 259117845Ssam /* 260117845Ssam * Arrange interrupt line. 261117845Ssam */ 262117845Ssam rid = 0; 263127135Snjl sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 264127135Snjl RF_SHAREABLE|RF_ACTIVE); 265117845Ssam if (sc->sc_irq == NULL) { 266117845Ssam device_printf(dev, "could not map interrupt\n"); 267117845Ssam goto bad1; 268117845Ssam } 269117845Ssam /* 270117845Ssam * NB: Network code assumes we are blocked with splimp() 271117845Ssam * so make sure the IRQ is mapped appropriately. 272117845Ssam */ 273117845Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 274166901Spiso NULL, safe_intr, sc, &sc->sc_ih)) { 275117845Ssam device_printf(dev, "could not establish interrupt\n"); 276117845Ssam goto bad2; 277117845Ssam } 278117845Ssam 279167755Ssam sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 280117845Ssam if (sc->sc_cid < 0) { 281117845Ssam device_printf(dev, "could not get crypto driver id\n"); 282117845Ssam goto bad3; 283117845Ssam } 284117845Ssam 285117845Ssam sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 286117845Ssam (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 287117845Ssam 288117845Ssam /* 289117845Ssam * Setup DMA descriptor area. 290117845Ssam */ 291232874Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 292117845Ssam 1, /* alignment */ 293117845Ssam SAFE_DMA_BOUNDARY, /* boundary */ 294117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 295117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 296117845Ssam NULL, NULL, /* filter, filterarg */ 297117845Ssam SAFE_MAX_DMA, /* maxsize */ 298117845Ssam SAFE_MAX_PART, /* nsegments */ 299117845Ssam SAFE_MAX_SSIZE, /* maxsegsize */ 300117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 301117845Ssam NULL, NULL, /* locking */ 302117845Ssam &sc->sc_srcdmat)) { 303117845Ssam device_printf(dev, "cannot allocate DMA tag\n"); 304117845Ssam goto bad4; 305117845Ssam } 306232874Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 307173307Ssam 1, /* alignment */ 308117845Ssam SAFE_MAX_DSIZE, /* boundary */ 309117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 310117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 311117845Ssam NULL, NULL, /* filter, filterarg */ 312117845Ssam SAFE_MAX_DMA, /* maxsize */ 313117845Ssam SAFE_MAX_PART, /* nsegments */ 314117845Ssam SAFE_MAX_DSIZE, /* maxsegsize */ 315117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 316117845Ssam NULL, NULL, /* locking */ 317117845Ssam &sc->sc_dstdmat)) { 318117845Ssam device_printf(dev, "cannot allocate DMA tag\n"); 319117845Ssam goto bad4; 320117845Ssam } 321117845Ssam 322117845Ssam /* 323117845Ssam * Allocate packet engine descriptors. 324117845Ssam */ 325117845Ssam if (safe_dma_malloc(sc, 326117845Ssam SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 327117845Ssam &sc->sc_ringalloc, 0)) { 328117845Ssam device_printf(dev, "cannot allocate PE descriptor ring\n"); 329117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 330117845Ssam goto bad4; 331117845Ssam } 332117845Ssam /* 333117845Ssam * Hookup the static portion of all our data structures. 334117845Ssam */ 335117845Ssam sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 336117845Ssam sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 337117845Ssam sc->sc_front = sc->sc_ring; 338117845Ssam sc->sc_back = sc->sc_ring; 339117845Ssam raddr = sc->sc_ringalloc.dma_paddr; 340117845Ssam bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 341117845Ssam for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 342117845Ssam struct safe_ringentry *re = &sc->sc_ring[i]; 343117845Ssam 344117845Ssam re->re_desc.d_sa = raddr + 345117845Ssam offsetof(struct safe_ringentry, re_sa); 346117845Ssam re->re_sa.sa_staterec = raddr + 347117845Ssam offsetof(struct safe_ringentry, re_sastate); 348117845Ssam 349117845Ssam raddr += sizeof (struct safe_ringentry); 350117845Ssam } 351117845Ssam mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 352117845Ssam "packet engine ring", MTX_DEF); 353117845Ssam 354117845Ssam /* 355117845Ssam * Allocate scatter and gather particle descriptors. 356117845Ssam */ 357117845Ssam if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 358117845Ssam &sc->sc_spalloc, 0)) { 359117845Ssam device_printf(dev, "cannot allocate source particle " 360117845Ssam "descriptor ring\n"); 361117845Ssam mtx_destroy(&sc->sc_ringmtx); 362117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 363117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 364117845Ssam goto bad4; 365117845Ssam } 366117845Ssam sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 367117845Ssam sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 368117845Ssam sc->sc_spfree = sc->sc_spring; 369117845Ssam bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 370117845Ssam 371117845Ssam if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 372117845Ssam &sc->sc_dpalloc, 0)) { 373117845Ssam device_printf(dev, "cannot allocate destination particle " 374117845Ssam "descriptor ring\n"); 375117845Ssam mtx_destroy(&sc->sc_ringmtx); 376117845Ssam safe_dma_free(sc, &sc->sc_spalloc); 377117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 378117845Ssam bus_dma_tag_destroy(sc->sc_dstdmat); 379117845Ssam goto bad4; 380117845Ssam } 381117845Ssam sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 382117845Ssam sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 383117845Ssam sc->sc_dpfree = sc->sc_dpring; 384117845Ssam bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 385117845Ssam 386117845Ssam device_printf(sc->sc_dev, "%s", safe_partname(sc)); 387117845Ssam 388117845Ssam devinfo = READ_REG(sc, SAFE_DEVINFO); 389117845Ssam if (devinfo & SAFE_DEVINFO_RNG) { 390117845Ssam sc->sc_flags |= SAFE_FLAGS_RNG; 391117845Ssam printf(" rng"); 392117845Ssam } 393117845Ssam if (devinfo & SAFE_DEVINFO_PKEY) { 394117845Ssam#if 0 395117845Ssam printf(" key"); 396117845Ssam sc->sc_flags |= SAFE_FLAGS_KEY; 397167755Ssam crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); 398167755Ssam crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); 399117845Ssam#endif 400117845Ssam } 401117845Ssam if (devinfo & SAFE_DEVINFO_DES) { 402117845Ssam printf(" des/3des"); 403167755Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 404167755Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 405117845Ssam } 406117845Ssam if (devinfo & SAFE_DEVINFO_AES) { 407117845Ssam printf(" aes"); 408167755Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 409117845Ssam } 410117845Ssam if (devinfo & SAFE_DEVINFO_MD5) { 411117845Ssam printf(" md5"); 412167755Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 413117845Ssam } 414117845Ssam if (devinfo & SAFE_DEVINFO_SHA1) { 415117845Ssam printf(" sha1"); 416167755Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 417117845Ssam } 418117845Ssam printf(" null"); 419167755Ssam crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); 420167755Ssam crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); 421117845Ssam /* XXX other supported algorithms */ 422117845Ssam printf("\n"); 423117845Ssam 424117845Ssam safe_reset_board(sc); /* reset h/w */ 425117845Ssam safe_init_pciregs(dev); /* init pci settings */ 426117845Ssam safe_init_board(sc); /* init h/w */ 427117845Ssam 428117845Ssam#ifndef SAFE_NO_RNG 429117845Ssam if (sc->sc_flags & SAFE_FLAGS_RNG) { 430117845Ssam#ifdef SAFE_RNDTEST 431117845Ssam sc->sc_rndtest = rndtest_attach(dev); 432117845Ssam if (sc->sc_rndtest) 433117845Ssam sc->sc_harvest = rndtest_harvest; 434117845Ssam else 435117845Ssam sc->sc_harvest = default_harvest; 436117845Ssam#else 437117845Ssam sc->sc_harvest = default_harvest; 438117845Ssam#endif 439117845Ssam safe_rng_init(sc); 440117845Ssam 441119137Ssam callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 442117845Ssam callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 443117845Ssam } 444117845Ssam#endif /* SAFE_NO_RNG */ 445117845Ssam#ifdef SAFE_DEBUG 446117845Ssam safec = sc; /* for use by hw.safe.dump */ 447117845Ssam#endif 448117845Ssam return (0); 449117845Ssambad4: 450117845Ssam crypto_unregister_all(sc->sc_cid); 451117845Ssambad3: 452117845Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 453117845Ssambad2: 454117845Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 455117845Ssambad1: 456117845Ssam bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 457117845Ssambad: 458117845Ssam return (ENXIO); 459117845Ssam} 460117845Ssam 461117845Ssam/* 462117845Ssam * Detach a device that successfully probed. 463117845Ssam */ 464117845Ssamstatic int 465117845Ssamsafe_detach(device_t dev) 466117845Ssam{ 467117845Ssam struct safe_softc *sc = device_get_softc(dev); 468117845Ssam 469117845Ssam /* XXX wait/abort active ops */ 470117845Ssam 471117845Ssam WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 472117845Ssam 473117845Ssam callout_stop(&sc->sc_rngto); 474117845Ssam 475117845Ssam crypto_unregister_all(sc->sc_cid); 476117845Ssam 477117845Ssam#ifdef SAFE_RNDTEST 478117845Ssam if (sc->sc_rndtest) 479117845Ssam rndtest_detach(sc->sc_rndtest); 480117845Ssam#endif 481117845Ssam 482117845Ssam safe_cleanchip(sc); 483117845Ssam safe_dma_free(sc, &sc->sc_dpalloc); 484117845Ssam safe_dma_free(sc, &sc->sc_spalloc); 485117845Ssam mtx_destroy(&sc->sc_ringmtx); 486117845Ssam safe_dma_free(sc, &sc->sc_ringalloc); 487117845Ssam 488117845Ssam bus_generic_detach(dev); 489117845Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 490117845Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 491117845Ssam 492117845Ssam bus_dma_tag_destroy(sc->sc_srcdmat); 493117845Ssam bus_dma_tag_destroy(sc->sc_dstdmat); 494117845Ssam bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 495117845Ssam 496117845Ssam return (0); 497117845Ssam} 498117845Ssam 499117845Ssam/* 500117845Ssam * Stop all chip i/o so that the kernel's probe routines don't 501117845Ssam * get confused by errant DMAs when rebooting. 502117845Ssam */ 503188178Simpstatic int 504117845Ssamsafe_shutdown(device_t dev) 505117845Ssam{ 506117845Ssam#ifdef notyet 507117845Ssam safe_stop(device_get_softc(dev)); 508117845Ssam#endif 509188178Simp return (0); 510117845Ssam} 511117845Ssam 512117845Ssam/* 513117845Ssam * Device suspend routine. 514117845Ssam */ 515117845Ssamstatic int 516117845Ssamsafe_suspend(device_t dev) 517117845Ssam{ 518117845Ssam struct safe_softc *sc = device_get_softc(dev); 519117845Ssam 520117845Ssam#ifdef notyet 521117845Ssam /* XXX stop the device and save PCI settings */ 522117845Ssam#endif 523117845Ssam sc->sc_suspended = 1; 524117845Ssam 525117845Ssam return (0); 526117845Ssam} 527117845Ssam 528117845Ssamstatic int 529117845Ssamsafe_resume(device_t dev) 530117845Ssam{ 531117845Ssam struct safe_softc *sc = device_get_softc(dev); 532117845Ssam 533117845Ssam#ifdef notyet 534117845Ssam /* XXX retore PCI settings and start the device */ 535117845Ssam#endif 536117845Ssam sc->sc_suspended = 0; 537117845Ssam return (0); 538117845Ssam} 539117845Ssam 540117845Ssam/* 541117845Ssam * SafeXcel Interrupt routine 542117845Ssam */ 543117845Ssamstatic void 544117845Ssamsafe_intr(void *arg) 545117845Ssam{ 546117845Ssam struct safe_softc *sc = arg; 547117845Ssam volatile u_int32_t stat; 548117845Ssam 549117845Ssam stat = READ_REG(sc, SAFE_HM_STAT); 550117845Ssam if (stat == 0) /* shared irq, not for us */ 551117845Ssam return; 552117845Ssam 553117845Ssam WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 554117845Ssam 555117845Ssam if ((stat & SAFE_INT_PE_DDONE)) { 556117845Ssam /* 557117845Ssam * Descriptor(s) done; scan the ring and 558117845Ssam * process completed operations. 559117845Ssam */ 560117845Ssam mtx_lock(&sc->sc_ringmtx); 561117845Ssam while (sc->sc_back != sc->sc_front) { 562117845Ssam struct safe_ringentry *re = sc->sc_back; 563117845Ssam#ifdef SAFE_DEBUG 564117845Ssam if (safe_debug) { 565117845Ssam safe_dump_ringstate(sc, __func__); 566117845Ssam safe_dump_request(sc, __func__, re); 567117845Ssam } 568117845Ssam#endif 569117845Ssam /* 570117845Ssam * safe_process marks ring entries that were allocated 571117845Ssam * but not used with a csr of zero. This insures the 572117845Ssam * ring front pointer never needs to be set backwards 573117845Ssam * in the event that an entry is allocated but not used 574117845Ssam * because of a setup error. 575117845Ssam */ 576117845Ssam if (re->re_desc.d_csr != 0) { 577117845Ssam if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 578117845Ssam break; 579117845Ssam if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 580117845Ssam break; 581117845Ssam sc->sc_nqchip--; 582117845Ssam safe_callback(sc, re); 583117845Ssam } 584117845Ssam if (++(sc->sc_back) == sc->sc_ringtop) 585117845Ssam sc->sc_back = sc->sc_ring; 586117845Ssam } 587117845Ssam mtx_unlock(&sc->sc_ringmtx); 588117845Ssam } 589117845Ssam 590117845Ssam /* 591117845Ssam * Check to see if we got any DMA Error 592117845Ssam */ 593117845Ssam if (stat & SAFE_INT_PE_ERROR) { 594117845Ssam DPRINTF(("dmaerr dmastat %08x\n", 595117845Ssam READ_REG(sc, SAFE_PE_DMASTAT))); 596117845Ssam safestats.st_dmaerr++; 597117845Ssam safe_totalreset(sc); 598117845Ssam#if 0 599117845Ssam safe_feed(sc); 600117845Ssam#endif 601117845Ssam } 602117845Ssam 603117845Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 604117845Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 605117845Ssam DPRINTF(("%s: wakeup crypto %x\n", __func__, 606117845Ssam sc->sc_needwakeup)); 607117845Ssam sc->sc_needwakeup &= ~wakeup; 608117845Ssam crypto_unblock(sc->sc_cid, wakeup); 609117845Ssam } 610117845Ssam} 611117845Ssam 612117845Ssam/* 613117845Ssam * safe_feed() - post a request to chip 614117845Ssam */ 615117845Ssamstatic void 616117845Ssamsafe_feed(struct safe_softc *sc, struct safe_ringentry *re) 617117845Ssam{ 618117845Ssam bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 619117845Ssam if (re->re_dst_map != NULL) 620117845Ssam bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 621117845Ssam BUS_DMASYNC_PREREAD); 622117845Ssam /* XXX have no smaller granularity */ 623117845Ssam safe_dma_sync(&sc->sc_ringalloc, 624117845Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 625117845Ssam safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 626117845Ssam safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 627117845Ssam 628117845Ssam#ifdef SAFE_DEBUG 629117845Ssam if (safe_debug) { 630117845Ssam safe_dump_ringstate(sc, __func__); 631117845Ssam safe_dump_request(sc, __func__, re); 632117845Ssam } 633117845Ssam#endif 634117845Ssam sc->sc_nqchip++; 635117845Ssam if (sc->sc_nqchip > safestats.st_maxqchip) 636117845Ssam safestats.st_maxqchip = sc->sc_nqchip; 637117845Ssam /* poke h/w to check descriptor ring, any value can be written */ 638117845Ssam WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 639117845Ssam} 640117845Ssam 641159226Spjd#define N(a) (sizeof(a) / sizeof (a[0])) 642159226Spjdstatic void 643159226Spjdsafe_setup_enckey(struct safe_session *ses, caddr_t key) 644159226Spjd{ 645159226Spjd int i; 646159226Spjd 647159226Spjd bcopy(key, ses->ses_key, ses->ses_klen / 8); 648159226Spjd 649159226Spjd /* PE is little-endian, insure proper byte order */ 650159226Spjd for (i = 0; i < N(ses->ses_key); i++) 651159226Spjd ses->ses_key[i] = htole32(ses->ses_key[i]); 652159226Spjd} 653159226Spjd 654159226Spjdstatic void 655159226Spjdsafe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) 656159226Spjd{ 657159226Spjd MD5_CTX md5ctx; 658159226Spjd SHA1_CTX sha1ctx; 659159226Spjd int i; 660159226Spjd 661159226Spjd 662159226Spjd for (i = 0; i < klen; i++) 663159226Spjd key[i] ^= HMAC_IPAD_VAL; 664159226Spjd 665159226Spjd if (algo == CRYPTO_MD5_HMAC) { 666159226Spjd MD5Init(&md5ctx); 667159226Spjd MD5Update(&md5ctx, key, klen); 668159232Spjd MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 669159226Spjd bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 670159226Spjd } else { 671159226Spjd SHA1Init(&sha1ctx); 672159226Spjd SHA1Update(&sha1ctx, key, klen); 673159232Spjd SHA1Update(&sha1ctx, hmac_ipad_buffer, 674159232Spjd SHA1_HMAC_BLOCK_LEN - klen); 675159226Spjd bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 676159226Spjd } 677159226Spjd 678159226Spjd for (i = 0; i < klen; i++) 679159226Spjd key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 680159226Spjd 681159226Spjd if (algo == CRYPTO_MD5_HMAC) { 682159226Spjd MD5Init(&md5ctx); 683159226Spjd MD5Update(&md5ctx, key, klen); 684159232Spjd MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 685159226Spjd bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 686159226Spjd } else { 687159226Spjd SHA1Init(&sha1ctx); 688159226Spjd SHA1Update(&sha1ctx, key, klen); 689159232Spjd SHA1Update(&sha1ctx, hmac_opad_buffer, 690159232Spjd SHA1_HMAC_BLOCK_LEN - klen); 691159226Spjd bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 692159226Spjd } 693159226Spjd 694159226Spjd for (i = 0; i < klen; i++) 695159226Spjd key[i] ^= HMAC_OPAD_VAL; 696159226Spjd 697159226Spjd /* PE is little-endian, insure proper byte order */ 698159226Spjd for (i = 0; i < N(ses->ses_hminner); i++) { 699159226Spjd ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 700159226Spjd ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 701159226Spjd } 702159226Spjd} 703159226Spjd#undef N 704159226Spjd 705117845Ssam/* 706117845Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 707117845Ssam * contains our registration id, and should contain an encoded session 708117845Ssam * id on successful allocation. 709117845Ssam */ 710117845Ssamstatic int 711167755Ssamsafe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 712117845Ssam{ 713167755Ssam struct safe_softc *sc = device_get_softc(dev); 714117845Ssam struct cryptoini *c, *encini = NULL, *macini = NULL; 715117845Ssam struct safe_session *ses = NULL; 716159226Spjd int sesn; 717117845Ssam 718117845Ssam if (sidp == NULL || cri == NULL || sc == NULL) 719117845Ssam return (EINVAL); 720117845Ssam 721117845Ssam for (c = cri; c != NULL; c = c->cri_next) { 722117845Ssam if (c->cri_alg == CRYPTO_MD5_HMAC || 723117845Ssam c->cri_alg == CRYPTO_SHA1_HMAC || 724117845Ssam c->cri_alg == CRYPTO_NULL_HMAC) { 725117845Ssam if (macini) 726117845Ssam return (EINVAL); 727117845Ssam macini = c; 728117845Ssam } else if (c->cri_alg == CRYPTO_DES_CBC || 729117845Ssam c->cri_alg == CRYPTO_3DES_CBC || 730117845Ssam c->cri_alg == CRYPTO_AES_CBC || 731117845Ssam c->cri_alg == CRYPTO_NULL_CBC) { 732117845Ssam if (encini) 733117845Ssam return (EINVAL); 734117845Ssam encini = c; 735117845Ssam } else 736117845Ssam return (EINVAL); 737117845Ssam } 738117845Ssam if (encini == NULL && macini == NULL) 739117845Ssam return (EINVAL); 740117845Ssam if (encini) { /* validate key length */ 741117845Ssam switch (encini->cri_alg) { 742117845Ssam case CRYPTO_DES_CBC: 743117845Ssam if (encini->cri_klen != 64) 744117845Ssam return (EINVAL); 745117845Ssam break; 746117845Ssam case CRYPTO_3DES_CBC: 747117845Ssam if (encini->cri_klen != 192) 748117845Ssam return (EINVAL); 749117845Ssam break; 750117845Ssam case CRYPTO_AES_CBC: 751117845Ssam if (encini->cri_klen != 128 && 752117845Ssam encini->cri_klen != 192 && 753117845Ssam encini->cri_klen != 256) 754117845Ssam return (EINVAL); 755117845Ssam break; 756117845Ssam } 757117845Ssam } 758117845Ssam 759117845Ssam if (sc->sc_sessions == NULL) { 760117845Ssam ses = sc->sc_sessions = (struct safe_session *)malloc( 761117845Ssam sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 762117845Ssam if (ses == NULL) 763117845Ssam return (ENOMEM); 764117845Ssam sesn = 0; 765117845Ssam sc->sc_nsessions = 1; 766117845Ssam } else { 767117845Ssam for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 768117845Ssam if (sc->sc_sessions[sesn].ses_used == 0) { 769117845Ssam ses = &sc->sc_sessions[sesn]; 770117845Ssam break; 771117845Ssam } 772117845Ssam } 773117845Ssam 774117845Ssam if (ses == NULL) { 775117845Ssam sesn = sc->sc_nsessions; 776117845Ssam ses = (struct safe_session *)malloc((sesn + 1) * 777117845Ssam sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 778117845Ssam if (ses == NULL) 779117845Ssam return (ENOMEM); 780117845Ssam bcopy(sc->sc_sessions, ses, sesn * 781117845Ssam sizeof(struct safe_session)); 782117845Ssam bzero(sc->sc_sessions, sesn * 783117845Ssam sizeof(struct safe_session)); 784117845Ssam free(sc->sc_sessions, M_DEVBUF); 785117845Ssam sc->sc_sessions = ses; 786117845Ssam ses = &sc->sc_sessions[sesn]; 787117845Ssam sc->sc_nsessions++; 788117845Ssam } 789117845Ssam } 790117845Ssam 791117845Ssam bzero(ses, sizeof(struct safe_session)); 792117845Ssam ses->ses_used = 1; 793117845Ssam 794117845Ssam if (encini) { 795117845Ssam /* get an IV */ 796117845Ssam /* XXX may read fewer than requested */ 797117845Ssam read_random(ses->ses_iv, sizeof(ses->ses_iv)); 798117845Ssam 799117845Ssam ses->ses_klen = encini->cri_klen; 800159226Spjd if (encini->cri_key != NULL) 801159226Spjd safe_setup_enckey(ses, encini->cri_key); 802117845Ssam } 803117845Ssam 804117845Ssam if (macini) { 805158705Spjd ses->ses_mlen = macini->cri_mlen; 806158705Spjd if (ses->ses_mlen == 0) { 807158705Spjd if (macini->cri_alg == CRYPTO_MD5_HMAC) 808159233Spjd ses->ses_mlen = MD5_HASH_LEN; 809158705Spjd else 810159233Spjd ses->ses_mlen = SHA1_HASH_LEN; 811158705Spjd } 812158705Spjd 813159226Spjd if (macini->cri_key != NULL) { 814159226Spjd safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, 815117845Ssam macini->cri_klen / 8); 816117845Ssam } 817117845Ssam } 818117845Ssam 819117845Ssam *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 820117845Ssam return (0); 821117845Ssam} 822117845Ssam 823117845Ssam/* 824117845Ssam * Deallocate a session. 825117845Ssam */ 826117845Ssamstatic int 827167755Ssamsafe_freesession(device_t dev, u_int64_t tid) 828117845Ssam{ 829167755Ssam struct safe_softc *sc = device_get_softc(dev); 830117845Ssam int session, ret; 831117845Ssam u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 832117845Ssam 833117845Ssam if (sc == NULL) 834117845Ssam return (EINVAL); 835117845Ssam 836117845Ssam session = SAFE_SESSION(sid); 837117845Ssam if (session < sc->sc_nsessions) { 838117845Ssam bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 839117845Ssam ret = 0; 840117845Ssam } else 841117845Ssam ret = EINVAL; 842117845Ssam return (ret); 843117845Ssam} 844117845Ssam 845117845Ssamstatic void 846117845Ssamsafe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 847117845Ssam{ 848117845Ssam struct safe_operand *op = arg; 849117845Ssam 850117845Ssam DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 851117845Ssam (u_int) mapsize, nsegs, error)); 852117845Ssam if (error != 0) 853117845Ssam return; 854117845Ssam op->mapsize = mapsize; 855117845Ssam op->nsegs = nsegs; 856117845Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 857117845Ssam} 858117845Ssam 859117845Ssamstatic int 860167755Ssamsafe_process(device_t dev, struct cryptop *crp, int hint) 861117845Ssam{ 862167755Ssam struct safe_softc *sc = device_get_softc(dev); 863117845Ssam int err = 0, i, nicealign, uniform; 864117845Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 865117845Ssam int bypass, oplen, ivsize; 866117845Ssam caddr_t iv; 867117845Ssam int16_t coffset; 868117845Ssam struct safe_session *ses; 869117845Ssam struct safe_ringentry *re; 870117845Ssam struct safe_sarec *sa; 871117845Ssam struct safe_pdesc *pd; 872117845Ssam u_int32_t cmd0, cmd1, staterec; 873117845Ssam 874117845Ssam if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 875117845Ssam safestats.st_invalid++; 876117845Ssam return (EINVAL); 877117845Ssam } 878117845Ssam if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 879117845Ssam safestats.st_badsession++; 880117845Ssam return (EINVAL); 881117845Ssam } 882117845Ssam 883117845Ssam mtx_lock(&sc->sc_ringmtx); 884117845Ssam if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 885117845Ssam safestats.st_ringfull++; 886117845Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 887117845Ssam mtx_unlock(&sc->sc_ringmtx); 888117845Ssam return (ERESTART); 889117845Ssam } 890117845Ssam re = sc->sc_front; 891117845Ssam 892117845Ssam staterec = re->re_sa.sa_staterec; /* save */ 893117845Ssam /* NB: zero everything but the PE descriptor */ 894117845Ssam bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 895117845Ssam re->re_sa.sa_staterec = staterec; /* restore */ 896117845Ssam 897117845Ssam re->re_crp = crp; 898117845Ssam re->re_sesn = SAFE_SESSION(crp->crp_sid); 899117845Ssam 900117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 901117845Ssam re->re_src_m = (struct mbuf *)crp->crp_buf; 902117845Ssam re->re_dst_m = (struct mbuf *)crp->crp_buf; 903117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 904117845Ssam re->re_src_io = (struct uio *)crp->crp_buf; 905117845Ssam re->re_dst_io = (struct uio *)crp->crp_buf; 906117845Ssam } else { 907117845Ssam safestats.st_badflags++; 908117845Ssam err = EINVAL; 909117845Ssam goto errout; /* XXX we don't handle contiguous blocks! */ 910117845Ssam } 911117845Ssam 912117845Ssam sa = &re->re_sa; 913117845Ssam ses = &sc->sc_sessions[re->re_sesn]; 914117845Ssam 915117845Ssam crd1 = crp->crp_desc; 916117845Ssam if (crd1 == NULL) { 917117845Ssam safestats.st_nodesc++; 918117845Ssam err = EINVAL; 919117845Ssam goto errout; 920117845Ssam } 921117845Ssam crd2 = crd1->crd_next; 922117845Ssam 923117845Ssam cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 924117845Ssam cmd1 = 0; 925117845Ssam if (crd2 == NULL) { 926117845Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 927117845Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 928117845Ssam crd1->crd_alg == CRYPTO_NULL_HMAC) { 929117845Ssam maccrd = crd1; 930117845Ssam enccrd = NULL; 931117845Ssam cmd0 |= SAFE_SA_CMD0_OP_HASH; 932117845Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 933117845Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 934117845Ssam crd1->crd_alg == CRYPTO_AES_CBC || 935117845Ssam crd1->crd_alg == CRYPTO_NULL_CBC) { 936117845Ssam maccrd = NULL; 937117845Ssam enccrd = crd1; 938117845Ssam cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 939117845Ssam } else { 940117845Ssam safestats.st_badalg++; 941117845Ssam err = EINVAL; 942117845Ssam goto errout; 943117845Ssam } 944117845Ssam } else { 945117845Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 946117845Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 947117845Ssam crd1->crd_alg == CRYPTO_NULL_HMAC) && 948117845Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 949117845Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 950117845Ssam crd2->crd_alg == CRYPTO_AES_CBC || 951117845Ssam crd2->crd_alg == CRYPTO_NULL_CBC) && 952117845Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 953117845Ssam maccrd = crd1; 954117845Ssam enccrd = crd2; 955117845Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 956117845Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 957117845Ssam crd1->crd_alg == CRYPTO_AES_CBC || 958117845Ssam crd1->crd_alg == CRYPTO_NULL_CBC) && 959117845Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 960117845Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 961117845Ssam crd2->crd_alg == CRYPTO_NULL_HMAC) && 962117845Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 963117845Ssam enccrd = crd1; 964117845Ssam maccrd = crd2; 965117845Ssam } else { 966117845Ssam safestats.st_badalg++; 967117845Ssam err = EINVAL; 968117845Ssam goto errout; 969117845Ssam } 970117845Ssam cmd0 |= SAFE_SA_CMD0_OP_BOTH; 971117845Ssam } 972117845Ssam 973117845Ssam if (enccrd) { 974159226Spjd if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 975159226Spjd safe_setup_enckey(ses, enccrd->crd_key); 976159226Spjd 977117845Ssam if (enccrd->crd_alg == CRYPTO_DES_CBC) { 978117845Ssam cmd0 |= SAFE_SA_CMD0_DES; 979117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 980117845Ssam ivsize = 2*sizeof(u_int32_t); 981117845Ssam } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 982117845Ssam cmd0 |= SAFE_SA_CMD0_3DES; 983117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 984117845Ssam ivsize = 2*sizeof(u_int32_t); 985117845Ssam } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 986117845Ssam cmd0 |= SAFE_SA_CMD0_AES; 987117845Ssam cmd1 |= SAFE_SA_CMD1_CBC; 988117845Ssam if (ses->ses_klen == 128) 989117845Ssam cmd1 |= SAFE_SA_CMD1_AES128; 990117845Ssam else if (ses->ses_klen == 192) 991117845Ssam cmd1 |= SAFE_SA_CMD1_AES192; 992117845Ssam else 993117845Ssam cmd1 |= SAFE_SA_CMD1_AES256; 994117845Ssam ivsize = 4*sizeof(u_int32_t); 995117845Ssam } else { 996117845Ssam cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 997117845Ssam ivsize = 0; 998117845Ssam } 999117845Ssam 1000117845Ssam /* 1001117845Ssam * Setup encrypt/decrypt state. When using basic ops 1002117845Ssam * we can't use an inline IV because hash/crypt offset 1003117845Ssam * must be from the end of the IV to the start of the 1004117845Ssam * crypt data and this leaves out the preceding header 1005117845Ssam * from the hash calculation. Instead we place the IV 1006117845Ssam * in the state record and set the hash/crypt offset to 1007117845Ssam * copy both the header+IV. 1008117845Ssam */ 1009117845Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1010117845Ssam cmd0 |= SAFE_SA_CMD0_OUTBOUND; 1011117845Ssam 1012117845Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1013117845Ssam iv = enccrd->crd_iv; 1014117845Ssam else 1015117845Ssam iv = (caddr_t) ses->ses_iv; 1016117845Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1017159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 1018159242Spjd enccrd->crd_inject, ivsize, iv); 1019117845Ssam } 1020117845Ssam bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1021117845Ssam cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1022117845Ssam re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1023117845Ssam } else { 1024117845Ssam cmd0 |= SAFE_SA_CMD0_INBOUND; 1025117845Ssam 1026159242Spjd if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { 1027117845Ssam bcopy(enccrd->crd_iv, 1028117845Ssam re->re_sastate.sa_saved_iv, ivsize); 1029159242Spjd } else { 1030159242Spjd crypto_copydata(crp->crp_flags, crp->crp_buf, 1031159242Spjd enccrd->crd_inject, ivsize, 1032159242Spjd (caddr_t)re->re_sastate.sa_saved_iv); 1033159242Spjd } 1034117845Ssam cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1035117845Ssam } 1036117845Ssam /* 1037117845Ssam * For basic encryption use the zero pad algorithm. 1038117845Ssam * This pads results to an 8-byte boundary and 1039117845Ssam * suppresses padding verification for inbound (i.e. 1040117845Ssam * decrypt) operations. 1041117845Ssam * 1042117845Ssam * NB: Not sure if the 8-byte pad boundary is a problem. 1043117845Ssam */ 1044117845Ssam cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1045117845Ssam 1046117845Ssam /* XXX assert key bufs have the same size */ 1047117845Ssam bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1048117845Ssam } 1049117845Ssam 1050117845Ssam if (maccrd) { 1051159226Spjd if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1052159226Spjd safe_setup_mackey(ses, maccrd->crd_alg, 1053159226Spjd maccrd->crd_key, maccrd->crd_klen / 8); 1054159226Spjd } 1055159226Spjd 1056117845Ssam if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1057117845Ssam cmd0 |= SAFE_SA_CMD0_MD5; 1058117845Ssam cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1059117845Ssam } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1060117845Ssam cmd0 |= SAFE_SA_CMD0_SHA1; 1061117845Ssam cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1062117845Ssam } else { 1063117845Ssam cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1064117845Ssam } 1065117845Ssam /* 1066117845Ssam * Digest data is loaded from the SA and the hash 1067117845Ssam * result is saved to the state block where we 1068117845Ssam * retrieve it for return to the caller. 1069117845Ssam */ 1070117845Ssam /* XXX assert digest bufs have the same size */ 1071117845Ssam bcopy(ses->ses_hminner, sa->sa_indigest, 1072117845Ssam sizeof(sa->sa_indigest)); 1073117845Ssam bcopy(ses->ses_hmouter, sa->sa_outdigest, 1074117845Ssam sizeof(sa->sa_outdigest)); 1075117845Ssam 1076117845Ssam cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1077117845Ssam re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1078117845Ssam } 1079117845Ssam 1080117845Ssam if (enccrd && maccrd) { 1081117845Ssam /* 1082117845Ssam * The offset from hash data to the start of 1083117845Ssam * crypt data is the difference in the skips. 1084117845Ssam */ 1085117845Ssam bypass = maccrd->crd_skip; 1086117845Ssam coffset = enccrd->crd_skip - maccrd->crd_skip; 1087117845Ssam if (coffset < 0) { 1088117845Ssam DPRINTF(("%s: hash does not precede crypt; " 1089117845Ssam "mac skip %u enc skip %u\n", 1090117845Ssam __func__, maccrd->crd_skip, enccrd->crd_skip)); 1091117845Ssam safestats.st_skipmismatch++; 1092117845Ssam err = EINVAL; 1093117845Ssam goto errout; 1094117845Ssam } 1095117845Ssam oplen = enccrd->crd_skip + enccrd->crd_len; 1096117845Ssam if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1097117845Ssam DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1098117845Ssam __func__, maccrd->crd_skip + maccrd->crd_len, 1099117845Ssam oplen)); 1100117845Ssam safestats.st_lenmismatch++; 1101117845Ssam err = EINVAL; 1102117845Ssam goto errout; 1103117845Ssam } 1104117845Ssam#ifdef SAFE_DEBUG 1105117845Ssam if (safe_debug) { 1106117845Ssam printf("mac: skip %d, len %d, inject %d\n", 1107117845Ssam maccrd->crd_skip, maccrd->crd_len, 1108117845Ssam maccrd->crd_inject); 1109117845Ssam printf("enc: skip %d, len %d, inject %d\n", 1110117845Ssam enccrd->crd_skip, enccrd->crd_len, 1111117845Ssam enccrd->crd_inject); 1112117845Ssam printf("bypass %d coffset %d oplen %d\n", 1113117845Ssam bypass, coffset, oplen); 1114117845Ssam } 1115117845Ssam#endif 1116117845Ssam if (coffset & 3) { /* offset must be 32-bit aligned */ 1117117845Ssam DPRINTF(("%s: coffset %u misaligned\n", 1118117845Ssam __func__, coffset)); 1119117845Ssam safestats.st_coffmisaligned++; 1120117845Ssam err = EINVAL; 1121117845Ssam goto errout; 1122117845Ssam } 1123117845Ssam coffset >>= 2; 1124117845Ssam if (coffset > 255) { /* offset must be <256 dwords */ 1125117845Ssam DPRINTF(("%s: coffset %u too big\n", 1126117845Ssam __func__, coffset)); 1127117845Ssam safestats.st_cofftoobig++; 1128117845Ssam err = EINVAL; 1129117845Ssam goto errout; 1130117845Ssam } 1131117845Ssam /* 1132117845Ssam * Tell the hardware to copy the header to the output. 1133117845Ssam * The header is defined as the data from the end of 1134117845Ssam * the bypass to the start of data to be encrypted. 1135117845Ssam * Typically this is the inline IV. Note that you need 1136117845Ssam * to do this even if src+dst are the same; it appears 1137117845Ssam * that w/o this bit the crypted data is written 1138117845Ssam * immediately after the bypass data. 1139117845Ssam */ 1140117845Ssam cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1141117845Ssam /* 1142117845Ssam * Disable IP header mutable bit handling. This is 1143117845Ssam * needed to get correct HMAC calculations. 1144117845Ssam */ 1145117845Ssam cmd1 |= SAFE_SA_CMD1_MUTABLE; 1146117845Ssam } else { 1147117845Ssam if (enccrd) { 1148117845Ssam bypass = enccrd->crd_skip; 1149117845Ssam oplen = bypass + enccrd->crd_len; 1150117845Ssam } else { 1151117845Ssam bypass = maccrd->crd_skip; 1152117845Ssam oplen = bypass + maccrd->crd_len; 1153117845Ssam } 1154117845Ssam coffset = 0; 1155117845Ssam } 1156117845Ssam /* XXX verify multiple of 4 when using s/g */ 1157117845Ssam if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1158117845Ssam DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1159117845Ssam safestats.st_bypasstoobig++; 1160117845Ssam err = EINVAL; 1161117845Ssam goto errout; 1162117845Ssam } 1163117845Ssam 1164117845Ssam if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1165117845Ssam safestats.st_nomap++; 1166117845Ssam err = ENOMEM; 1167117845Ssam goto errout; 1168117845Ssam } 1169117845Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1170117845Ssam if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1171117845Ssam re->re_src_m, safe_op_cb, 1172117845Ssam &re->re_src, BUS_DMA_NOWAIT) != 0) { 1173117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1174117845Ssam re->re_src_map = NULL; 1175117845Ssam safestats.st_noload++; 1176117845Ssam err = ENOMEM; 1177117845Ssam goto errout; 1178117845Ssam } 1179117845Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1180117845Ssam if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1181117845Ssam re->re_src_io, safe_op_cb, 1182117845Ssam &re->re_src, BUS_DMA_NOWAIT) != 0) { 1183117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1184117845Ssam re->re_src_map = NULL; 1185117845Ssam safestats.st_noload++; 1186117845Ssam err = ENOMEM; 1187117845Ssam goto errout; 1188117845Ssam } 1189117845Ssam } 1190117845Ssam nicealign = safe_dmamap_aligned(&re->re_src); 1191117845Ssam uniform = safe_dmamap_uniform(&re->re_src); 1192117845Ssam 1193117845Ssam DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1194117845Ssam nicealign, uniform, re->re_src.nsegs)); 1195117845Ssam if (re->re_src.nsegs > 1) { 1196117845Ssam re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1197117845Ssam ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1198117845Ssam for (i = 0; i < re->re_src_nsegs; i++) { 1199117845Ssam /* NB: no need to check if there's space */ 1200117845Ssam pd = sc->sc_spfree; 1201117845Ssam if (++(sc->sc_spfree) == sc->sc_springtop) 1202117845Ssam sc->sc_spfree = sc->sc_spring; 1203117845Ssam 1204117845Ssam KASSERT((pd->pd_flags&3) == 0 || 1205117845Ssam (pd->pd_flags&3) == SAFE_PD_DONE, 1206117845Ssam ("bogus source particle descriptor; flags %x", 1207117845Ssam pd->pd_flags)); 1208117845Ssam pd->pd_addr = re->re_src_segs[i].ds_addr; 1209117845Ssam pd->pd_size = re->re_src_segs[i].ds_len; 1210117845Ssam pd->pd_flags = SAFE_PD_READY; 1211117845Ssam } 1212117845Ssam cmd0 |= SAFE_SA_CMD0_IGATHER; 1213117845Ssam } else { 1214117845Ssam /* 1215117845Ssam * No need for gather, reference the operand directly. 1216117845Ssam */ 1217117845Ssam re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1218117845Ssam } 1219117845Ssam 1220117845Ssam if (enccrd == NULL && maccrd != NULL) { 1221117845Ssam /* 1222117845Ssam * Hash op; no destination needed. 1223117845Ssam */ 1224117845Ssam } else { 1225117845Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1226117845Ssam if (!nicealign) { 1227117845Ssam safestats.st_iovmisaligned++; 1228117845Ssam err = EINVAL; 1229117845Ssam goto errout; 1230117845Ssam } 1231117845Ssam if (uniform != 1) { 1232117845Ssam /* 1233117845Ssam * Source is not suitable for direct use as 1234117845Ssam * the destination. Create a new scatter/gather 1235117845Ssam * list based on the destination requirements 1236117845Ssam * and check if that's ok. 1237117845Ssam */ 1238117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1239117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map)) { 1240117845Ssam safestats.st_nomap++; 1241117845Ssam err = ENOMEM; 1242117845Ssam goto errout; 1243117845Ssam } 1244117845Ssam if (bus_dmamap_load_uio(sc->sc_dstdmat, 1245117845Ssam re->re_dst_map, re->re_dst_io, 1246117845Ssam safe_op_cb, &re->re_dst, 1247117845Ssam BUS_DMA_NOWAIT) != 0) { 1248117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1249117845Ssam re->re_dst_map); 1250117845Ssam re->re_dst_map = NULL; 1251117845Ssam safestats.st_noload++; 1252117845Ssam err = ENOMEM; 1253117845Ssam goto errout; 1254117845Ssam } 1255117845Ssam uniform = safe_dmamap_uniform(&re->re_dst); 1256117845Ssam if (!uniform) { 1257117845Ssam /* 1258117845Ssam * There's no way to handle the DMA 1259117845Ssam * requirements with this uio. We 1260117845Ssam * could create a separate DMA area for 1261117845Ssam * the result and then copy it back, 1262117845Ssam * but for now we just bail and return 1263117845Ssam * an error. Note that uio requests 1264117845Ssam * > SAFE_MAX_DSIZE are handled because 1265117845Ssam * the DMA map and segment list for the 1266117845Ssam * destination wil result in a 1267117845Ssam * destination particle list that does 1268117845Ssam * the necessary scatter DMA. 1269117845Ssam */ 1270117845Ssam safestats.st_iovnotuniform++; 1271117845Ssam err = EINVAL; 1272117845Ssam goto errout; 1273117845Ssam } 1274118882Ssam } else 1275118882Ssam re->re_dst = re->re_src; 1276117845Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1277117845Ssam if (nicealign && uniform == 1) { 1278117845Ssam /* 1279117845Ssam * Source layout is suitable for direct 1280117845Ssam * sharing of the DMA map and segment list. 1281117845Ssam */ 1282117845Ssam re->re_dst = re->re_src; 1283117845Ssam } else if (nicealign && uniform == 2) { 1284117845Ssam /* 1285117845Ssam * The source is properly aligned but requires a 1286117845Ssam * different particle list to handle DMA of the 1287117845Ssam * result. Create a new map and do the load to 1288117845Ssam * create the segment list. The particle 1289117845Ssam * descriptor setup code below will handle the 1290117845Ssam * rest. 1291117845Ssam */ 1292117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1293117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map)) { 1294117845Ssam safestats.st_nomap++; 1295117845Ssam err = ENOMEM; 1296117845Ssam goto errout; 1297117845Ssam } 1298117845Ssam if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1299117845Ssam re->re_dst_map, re->re_dst_m, 1300117845Ssam safe_op_cb, &re->re_dst, 1301117845Ssam BUS_DMA_NOWAIT) != 0) { 1302117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1303117845Ssam re->re_dst_map); 1304117845Ssam re->re_dst_map = NULL; 1305117845Ssam safestats.st_noload++; 1306117845Ssam err = ENOMEM; 1307117845Ssam goto errout; 1308117845Ssam } 1309117845Ssam } else { /* !(aligned and/or uniform) */ 1310117845Ssam int totlen, len; 1311117845Ssam struct mbuf *m, *top, **mp; 1312117845Ssam 1313117845Ssam /* 1314117845Ssam * DMA constraints require that we allocate a 1315117845Ssam * new mbuf chain for the destination. We 1316117845Ssam * allocate an entire new set of mbufs of 1317117845Ssam * optimal/required size and then tell the 1318117845Ssam * hardware to copy any bits that are not 1319117845Ssam * created as a byproduct of the operation. 1320117845Ssam */ 1321117845Ssam if (!nicealign) 1322117845Ssam safestats.st_unaligned++; 1323117845Ssam if (!uniform) 1324117845Ssam safestats.st_notuniform++; 1325117845Ssam totlen = re->re_src_mapsize; 1326117845Ssam if (re->re_src_m->m_flags & M_PKTHDR) { 1327117845Ssam len = MHLEN; 1328117845Ssam MGETHDR(m, M_DONTWAIT, MT_DATA); 1329117845Ssam if (m && !m_dup_pkthdr(m, re->re_src_m, 1330117845Ssam M_DONTWAIT)) { 1331117845Ssam m_free(m); 1332117845Ssam m = NULL; 1333117845Ssam } 1334117845Ssam } else { 1335117845Ssam len = MLEN; 1336117845Ssam MGET(m, M_DONTWAIT, MT_DATA); 1337117845Ssam } 1338117845Ssam if (m == NULL) { 1339117845Ssam safestats.st_nombuf++; 1340117845Ssam err = sc->sc_nqchip ? ERESTART : ENOMEM; 1341117845Ssam goto errout; 1342117845Ssam } 1343117845Ssam if (totlen >= MINCLSIZE) { 1344117845Ssam MCLGET(m, M_DONTWAIT); 1345117845Ssam if ((m->m_flags & M_EXT) == 0) { 1346117845Ssam m_free(m); 1347117845Ssam safestats.st_nomcl++; 1348117845Ssam err = sc->sc_nqchip ? 1349117845Ssam ERESTART : ENOMEM; 1350117845Ssam goto errout; 1351117845Ssam } 1352117845Ssam len = MCLBYTES; 1353117845Ssam } 1354117845Ssam m->m_len = len; 1355117845Ssam top = NULL; 1356117845Ssam mp = ⊤ 1357117845Ssam 1358117845Ssam while (totlen > 0) { 1359117845Ssam if (top) { 1360117845Ssam MGET(m, M_DONTWAIT, MT_DATA); 1361117845Ssam if (m == NULL) { 1362117845Ssam m_freem(top); 1363117845Ssam safestats.st_nombuf++; 1364117845Ssam err = sc->sc_nqchip ? 1365117845Ssam ERESTART : ENOMEM; 1366117845Ssam goto errout; 1367117845Ssam } 1368117845Ssam len = MLEN; 1369117845Ssam } 1370117845Ssam if (top && totlen >= MINCLSIZE) { 1371117845Ssam MCLGET(m, M_DONTWAIT); 1372117845Ssam if ((m->m_flags & M_EXT) == 0) { 1373117845Ssam *mp = m; 1374117845Ssam m_freem(top); 1375117845Ssam safestats.st_nomcl++; 1376117845Ssam err = sc->sc_nqchip ? 1377117845Ssam ERESTART : ENOMEM; 1378117845Ssam goto errout; 1379117845Ssam } 1380117845Ssam len = MCLBYTES; 1381117845Ssam } 1382117845Ssam m->m_len = len = min(totlen, len); 1383117845Ssam totlen -= len; 1384117845Ssam *mp = m; 1385117845Ssam mp = &m->m_next; 1386117845Ssam } 1387117845Ssam re->re_dst_m = top; 1388117845Ssam if (bus_dmamap_create(sc->sc_dstdmat, 1389117845Ssam BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1390117845Ssam safestats.st_nomap++; 1391117845Ssam err = ENOMEM; 1392117845Ssam goto errout; 1393117845Ssam } 1394117845Ssam if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1395117845Ssam re->re_dst_map, re->re_dst_m, 1396117845Ssam safe_op_cb, &re->re_dst, 1397117845Ssam BUS_DMA_NOWAIT) != 0) { 1398117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, 1399117845Ssam re->re_dst_map); 1400117845Ssam re->re_dst_map = NULL; 1401117845Ssam safestats.st_noload++; 1402117845Ssam err = ENOMEM; 1403117845Ssam goto errout; 1404117845Ssam } 1405117845Ssam if (re->re_src.mapsize > oplen) { 1406117845Ssam /* 1407117845Ssam * There's data following what the 1408117845Ssam * hardware will copy for us. If this 1409117845Ssam * isn't just the ICV (that's going to 1410117845Ssam * be written on completion), copy it 1411117845Ssam * to the new mbufs 1412117845Ssam */ 1413117845Ssam if (!(maccrd && 1414117845Ssam (re->re_src.mapsize-oplen) == 12 && 1415117845Ssam maccrd->crd_inject == oplen)) 1416117845Ssam safe_mcopy(re->re_src_m, 1417117845Ssam re->re_dst_m, 1418117845Ssam oplen); 1419117845Ssam else 1420117845Ssam safestats.st_noicvcopy++; 1421117845Ssam } 1422117845Ssam } 1423117845Ssam } else { 1424117845Ssam safestats.st_badflags++; 1425117845Ssam err = EINVAL; 1426117845Ssam goto errout; 1427117845Ssam } 1428117845Ssam 1429117845Ssam if (re->re_dst.nsegs > 1) { 1430117845Ssam re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1431117845Ssam ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1432117845Ssam for (i = 0; i < re->re_dst_nsegs; i++) { 1433117845Ssam pd = sc->sc_dpfree; 1434117845Ssam KASSERT((pd->pd_flags&3) == 0 || 1435117845Ssam (pd->pd_flags&3) == SAFE_PD_DONE, 1436117845Ssam ("bogus dest particle descriptor; flags %x", 1437117845Ssam pd->pd_flags)); 1438117845Ssam if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1439117845Ssam sc->sc_dpfree = sc->sc_dpring; 1440117845Ssam pd->pd_addr = re->re_dst_segs[i].ds_addr; 1441117845Ssam pd->pd_flags = SAFE_PD_READY; 1442117845Ssam } 1443117845Ssam cmd0 |= SAFE_SA_CMD0_OSCATTER; 1444117845Ssam } else { 1445117845Ssam /* 1446117845Ssam * No need for scatter, reference the operand directly. 1447117845Ssam */ 1448117845Ssam re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1449117845Ssam } 1450117845Ssam } 1451117845Ssam 1452117845Ssam /* 1453117845Ssam * All done with setup; fillin the SA command words 1454117845Ssam * and the packet engine descriptor. The operation 1455117845Ssam * is now ready for submission to the hardware. 1456117845Ssam */ 1457117845Ssam sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1458117845Ssam sa->sa_cmd1 = cmd1 1459117845Ssam | (coffset << SAFE_SA_CMD1_OFFSET_S) 1460117845Ssam | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1461117845Ssam | SAFE_SA_CMD1_SRPCI 1462117845Ssam ; 1463117845Ssam /* 1464117845Ssam * NB: the order of writes is important here. In case the 1465117845Ssam * chip is scanning the ring because of an outstanding request 1466117845Ssam * it might nab this one too. In that case we need to make 1467117845Ssam * sure the setup is complete before we write the length 1468117845Ssam * field of the descriptor as it signals the descriptor is 1469117845Ssam * ready for processing. 1470117845Ssam */ 1471117845Ssam re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1472117845Ssam if (maccrd) 1473117845Ssam re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1474117845Ssam re->re_desc.d_len = oplen 1475117845Ssam | SAFE_PE_LEN_READY 1476117845Ssam | (bypass << SAFE_PE_LEN_BYPASS_S) 1477117845Ssam ; 1478117845Ssam 1479117845Ssam safestats.st_ipackets++; 1480117845Ssam safestats.st_ibytes += oplen; 1481117845Ssam 1482117845Ssam if (++(sc->sc_front) == sc->sc_ringtop) 1483117845Ssam sc->sc_front = sc->sc_ring; 1484117845Ssam 1485117845Ssam /* XXX honor batching */ 1486117845Ssam safe_feed(sc, re); 1487117845Ssam mtx_unlock(&sc->sc_ringmtx); 1488117845Ssam return (0); 1489117845Ssam 1490117845Ssamerrout: 1491117845Ssam if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1492117845Ssam m_freem(re->re_dst_m); 1493117845Ssam 1494117845Ssam if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1495117845Ssam bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1496117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1497117845Ssam } 1498117845Ssam if (re->re_src_map != NULL) { 1499117845Ssam bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1500117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1501117845Ssam } 1502117845Ssam mtx_unlock(&sc->sc_ringmtx); 1503117845Ssam if (err != ERESTART) { 1504117845Ssam crp->crp_etype = err; 1505117845Ssam crypto_done(crp); 1506117845Ssam } else { 1507117845Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 1508117845Ssam } 1509117845Ssam return (err); 1510117845Ssam} 1511117845Ssam 1512117845Ssamstatic void 1513117845Ssamsafe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1514117845Ssam{ 1515117845Ssam struct cryptop *crp = (struct cryptop *)re->re_crp; 1516117845Ssam struct cryptodesc *crd; 1517117845Ssam 1518117845Ssam safestats.st_opackets++; 1519117845Ssam safestats.st_obytes += re->re_dst.mapsize; 1520117845Ssam 1521117845Ssam safe_dma_sync(&sc->sc_ringalloc, 1522117845Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1523117845Ssam if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1524117845Ssam device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1525117845Ssam re->re_desc.d_csr, 1526117845Ssam re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1527117845Ssam safestats.st_peoperr++; 1528117845Ssam crp->crp_etype = EIO; /* something more meaningful? */ 1529117845Ssam } 1530117845Ssam if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1531117845Ssam bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1532117845Ssam BUS_DMASYNC_POSTREAD); 1533117845Ssam bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1534117845Ssam bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1535117845Ssam } 1536117845Ssam bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1537117845Ssam bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1538117845Ssam bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1539117845Ssam 1540117845Ssam /* 1541117845Ssam * If result was written to a differet mbuf chain, swap 1542117845Ssam * it in as the return value and reclaim the original. 1543117845Ssam */ 1544117845Ssam if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1545117845Ssam m_freem(re->re_src_m); 1546117845Ssam crp->crp_buf = (caddr_t)re->re_dst_m; 1547117845Ssam } 1548117845Ssam 1549117845Ssam if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1550117845Ssam /* copy out IV for future use */ 1551117845Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1552117845Ssam int ivsize; 1553117845Ssam 1554117845Ssam if (crd->crd_alg == CRYPTO_DES_CBC || 1555117845Ssam crd->crd_alg == CRYPTO_3DES_CBC) { 1556117845Ssam ivsize = 2*sizeof(u_int32_t); 1557117845Ssam } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1558117845Ssam ivsize = 4*sizeof(u_int32_t); 1559117845Ssam } else 1560117845Ssam continue; 1561159242Spjd crypto_copydata(crp->crp_flags, crp->crp_buf, 1562159242Spjd crd->crd_skip + crd->crd_len - ivsize, ivsize, 1563159242Spjd (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1564117845Ssam break; 1565117845Ssam } 1566117845Ssam } 1567117845Ssam 1568117845Ssam if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1569117845Ssam /* copy out ICV result */ 1570117845Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1571117845Ssam if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1572117845Ssam crd->crd_alg == CRYPTO_SHA1_HMAC || 1573117845Ssam crd->crd_alg == CRYPTO_NULL_HMAC)) 1574117845Ssam continue; 1575117845Ssam if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1576117845Ssam /* 1577117845Ssam * SHA-1 ICV's are byte-swapped; fix 'em up 1578117845Ssam * before copy them to their destination. 1579117845Ssam */ 1580223026Sdelphij re->re_sastate.sa_saved_indigest[0] = 1581223026Sdelphij bswap32(re->re_sastate.sa_saved_indigest[0]); 1582223026Sdelphij re->re_sastate.sa_saved_indigest[1] = 1583223026Sdelphij bswap32(re->re_sastate.sa_saved_indigest[1]); 1584223026Sdelphij re->re_sastate.sa_saved_indigest[2] = 1585223026Sdelphij bswap32(re->re_sastate.sa_saved_indigest[2]); 1586117845Ssam } 1587159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 1588159242Spjd crd->crd_inject, 1589159242Spjd sc->sc_sessions[re->re_sesn].ses_mlen, 1590159242Spjd (caddr_t)re->re_sastate.sa_saved_indigest); 1591117845Ssam break; 1592117845Ssam } 1593117845Ssam } 1594117845Ssam crypto_done(crp); 1595117845Ssam} 1596117845Ssam 1597117845Ssam/* 1598117845Ssam * Copy all data past offset from srcm to dstm. 1599117845Ssam */ 1600117845Ssamstatic void 1601117845Ssamsafe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1602117845Ssam{ 1603117845Ssam u_int j, dlen, slen; 1604117845Ssam caddr_t dptr, sptr; 1605117845Ssam 1606117845Ssam /* 1607117845Ssam * Advance src and dst to offset. 1608117845Ssam */ 1609117845Ssam j = offset; 1610117845Ssam while (j >= 0) { 1611117845Ssam if (srcm->m_len > j) 1612117845Ssam break; 1613117845Ssam j -= srcm->m_len; 1614117845Ssam srcm = srcm->m_next; 1615117845Ssam if (srcm == NULL) 1616117845Ssam return; 1617117845Ssam } 1618117845Ssam sptr = mtod(srcm, caddr_t) + j; 1619117845Ssam slen = srcm->m_len - j; 1620117845Ssam 1621117845Ssam j = offset; 1622117845Ssam while (j >= 0) { 1623117845Ssam if (dstm->m_len > j) 1624117845Ssam break; 1625117845Ssam j -= dstm->m_len; 1626117845Ssam dstm = dstm->m_next; 1627117845Ssam if (dstm == NULL) 1628117845Ssam return; 1629117845Ssam } 1630117845Ssam dptr = mtod(dstm, caddr_t) + j; 1631117845Ssam dlen = dstm->m_len - j; 1632117845Ssam 1633117845Ssam /* 1634117845Ssam * Copy everything that remains. 1635117845Ssam */ 1636117845Ssam for (;;) { 1637117845Ssam j = min(slen, dlen); 1638117845Ssam bcopy(sptr, dptr, j); 1639117845Ssam if (slen == j) { 1640117845Ssam srcm = srcm->m_next; 1641117845Ssam if (srcm == NULL) 1642117845Ssam return; 1643117845Ssam sptr = srcm->m_data; 1644117845Ssam slen = srcm->m_len; 1645117845Ssam } else 1646117845Ssam sptr += j, slen -= j; 1647117845Ssam if (dlen == j) { 1648117845Ssam dstm = dstm->m_next; 1649117845Ssam if (dstm == NULL) 1650117845Ssam return; 1651117845Ssam dptr = dstm->m_data; 1652117845Ssam dlen = dstm->m_len; 1653117845Ssam } else 1654117845Ssam dptr += j, dlen -= j; 1655117845Ssam } 1656117845Ssam} 1657117845Ssam 1658117845Ssam#ifndef SAFE_NO_RNG 1659117845Ssam#define SAFE_RNG_MAXWAIT 1000 1660117845Ssam 1661117845Ssamstatic void 1662117845Ssamsafe_rng_init(struct safe_softc *sc) 1663117845Ssam{ 1664117845Ssam u_int32_t w, v; 1665117845Ssam int i; 1666117845Ssam 1667117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1668117845Ssam /* use default value according to the manual */ 1669117845Ssam WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1670117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1671117845Ssam 1672117845Ssam /* 1673117845Ssam * There is a bug in rev 1.0 of the 1140 that when the RNG 1674117845Ssam * is brought out of reset the ready status flag does not 1675117845Ssam * work until the RNG has finished its internal initialization. 1676117845Ssam * 1677117845Ssam * So in order to determine the device is through its 1678117845Ssam * initialization we must read the data register, using the 1679117845Ssam * status reg in the read in case it is initialized. Then read 1680117845Ssam * the data register until it changes from the first read. 1681117845Ssam * Once it changes read the data register until it changes 1682117845Ssam * again. At this time the RNG is considered initialized. 1683117845Ssam * This could take between 750ms - 1000ms in time. 1684117845Ssam */ 1685117845Ssam i = 0; 1686117845Ssam w = READ_REG(sc, SAFE_RNG_OUT); 1687117845Ssam do { 1688117845Ssam v = READ_REG(sc, SAFE_RNG_OUT); 1689117845Ssam if (v != w) { 1690117845Ssam w = v; 1691117845Ssam break; 1692117845Ssam } 1693117845Ssam DELAY(10); 1694117845Ssam } while (++i < SAFE_RNG_MAXWAIT); 1695117845Ssam 1696117845Ssam /* Wait Until data changes again */ 1697117845Ssam i = 0; 1698117845Ssam do { 1699117845Ssam v = READ_REG(sc, SAFE_RNG_OUT); 1700117845Ssam if (v != w) 1701117845Ssam break; 1702117845Ssam DELAY(10); 1703117845Ssam } while (++i < SAFE_RNG_MAXWAIT); 1704117845Ssam} 1705117845Ssam 1706117845Ssamstatic __inline void 1707117845Ssamsafe_rng_disable_short_cycle(struct safe_softc *sc) 1708117845Ssam{ 1709117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 1710117845Ssam READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1711117845Ssam} 1712117845Ssam 1713117845Ssamstatic __inline void 1714117845Ssamsafe_rng_enable_short_cycle(struct safe_softc *sc) 1715117845Ssam{ 1716117845Ssam WRITE_REG(sc, SAFE_RNG_CTRL, 1717117845Ssam READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1718117845Ssam} 1719117845Ssam 1720117845Ssamstatic __inline u_int32_t 1721117845Ssamsafe_rng_read(struct safe_softc *sc) 1722117845Ssam{ 1723117845Ssam int i; 1724117845Ssam 1725117845Ssam i = 0; 1726117845Ssam while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1727117845Ssam ; 1728117845Ssam return READ_REG(sc, SAFE_RNG_OUT); 1729117845Ssam} 1730117845Ssam 1731117845Ssamstatic void 1732117845Ssamsafe_rng(void *arg) 1733117845Ssam{ 1734117845Ssam struct safe_softc *sc = arg; 1735117845Ssam u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1736117845Ssam u_int maxwords; 1737117845Ssam int i; 1738117845Ssam 1739117845Ssam safestats.st_rng++; 1740117845Ssam /* 1741117845Ssam * Fetch the next block of data. 1742117845Ssam */ 1743117845Ssam maxwords = safe_rngbufsize; 1744117845Ssam if (maxwords > SAFE_RNG_MAXBUFSIZ) 1745117845Ssam maxwords = SAFE_RNG_MAXBUFSIZ; 1746117845Ssamretry: 1747117845Ssam for (i = 0; i < maxwords; i++) 1748117845Ssam buf[i] = safe_rng_read(sc); 1749117845Ssam /* 1750117845Ssam * Check the comparator alarm count and reset the h/w if 1751117845Ssam * it exceeds our threshold. This guards against the 1752117845Ssam * hardware oscillators resonating with external signals. 1753117845Ssam */ 1754117845Ssam if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1755117845Ssam u_int32_t freq_inc, w; 1756117845Ssam 1757117845Ssam DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1758117845Ssam READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1759117845Ssam safestats.st_rngalarm++; 1760117845Ssam safe_rng_enable_short_cycle(sc); 1761117845Ssam freq_inc = 18; 1762117845Ssam for (i = 0; i < 64; i++) { 1763117845Ssam w = READ_REG(sc, SAFE_RNG_CNFG); 1764117845Ssam freq_inc = ((w + freq_inc) & 0x3fL); 1765117845Ssam w = ((w & ~0x3fL) | freq_inc); 1766117845Ssam WRITE_REG(sc, SAFE_RNG_CNFG, w); 1767117845Ssam 1768117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1769117845Ssam 1770117845Ssam (void) safe_rng_read(sc); 1771117845Ssam DELAY(25); 1772117845Ssam 1773117845Ssam if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1774117845Ssam safe_rng_disable_short_cycle(sc); 1775117845Ssam goto retry; 1776117845Ssam } 1777117845Ssam freq_inc = 1; 1778117845Ssam } 1779117845Ssam safe_rng_disable_short_cycle(sc); 1780117845Ssam } else 1781117845Ssam WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1782117845Ssam 1783117845Ssam (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1784117845Ssam callout_reset(&sc->sc_rngto, 1785117845Ssam hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1786117845Ssam} 1787117845Ssam#endif /* SAFE_NO_RNG */ 1788117845Ssam 1789117845Ssamstatic void 1790117845Ssamsafe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1791117845Ssam{ 1792117845Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 1793117845Ssam *paddr = segs->ds_addr; 1794117845Ssam} 1795117845Ssam 1796117845Ssamstatic int 1797117845Ssamsafe_dma_malloc( 1798117845Ssam struct safe_softc *sc, 1799117845Ssam bus_size_t size, 1800117845Ssam struct safe_dma_alloc *dma, 1801117845Ssam int mapflags 1802117845Ssam) 1803117845Ssam{ 1804117845Ssam int r; 1805117845Ssam 1806232874Sscottl r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1807117845Ssam sizeof(u_int32_t), 0, /* alignment, bounds */ 1808117845Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1809117845Ssam BUS_SPACE_MAXADDR, /* highaddr */ 1810117845Ssam NULL, NULL, /* filter, filterarg */ 1811117845Ssam size, /* maxsize */ 1812117845Ssam 1, /* nsegments */ 1813117845Ssam size, /* maxsegsize */ 1814117845Ssam BUS_DMA_ALLOCNOW, /* flags */ 1815117845Ssam NULL, NULL, /* locking */ 1816117845Ssam &dma->dma_tag); 1817117845Ssam if (r != 0) { 1818117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1819117845Ssam "bus_dma_tag_create failed; error %u\n", r); 1820117845Ssam goto fail_0; 1821117845Ssam } 1822117845Ssam 1823117845Ssam r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1824117845Ssam if (r != 0) { 1825117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1826117845Ssam "bus_dmamap_create failed; error %u\n", r); 1827117845Ssam goto fail_1; 1828117845Ssam } 1829117845Ssam 1830117845Ssam r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1831117845Ssam BUS_DMA_NOWAIT, &dma->dma_map); 1832117845Ssam if (r != 0) { 1833117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1834117845Ssam "bus_dmammem_alloc failed; size %zu, error %u\n", 1835117845Ssam size, r); 1836117845Ssam goto fail_2; 1837117845Ssam } 1838117845Ssam 1839117845Ssam r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1840117845Ssam size, 1841117845Ssam safe_dmamap_cb, 1842117845Ssam &dma->dma_paddr, 1843117845Ssam mapflags | BUS_DMA_NOWAIT); 1844117845Ssam if (r != 0) { 1845117845Ssam device_printf(sc->sc_dev, "safe_dma_malloc: " 1846117845Ssam "bus_dmamap_load failed; error %u\n", r); 1847117845Ssam goto fail_3; 1848117845Ssam } 1849117845Ssam 1850117845Ssam dma->dma_size = size; 1851117845Ssam return (0); 1852117845Ssam 1853117845Ssamfail_3: 1854117845Ssam bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1855117845Ssamfail_2: 1856117845Ssam bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1857117845Ssamfail_1: 1858117845Ssam bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1859117845Ssam bus_dma_tag_destroy(dma->dma_tag); 1860117845Ssamfail_0: 1861117845Ssam dma->dma_map = NULL; 1862117845Ssam dma->dma_tag = NULL; 1863117845Ssam return (r); 1864117845Ssam} 1865117845Ssam 1866117845Ssamstatic void 1867117845Ssamsafe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1868117845Ssam{ 1869117845Ssam bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1870117845Ssam bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1871117845Ssam bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1872117845Ssam bus_dma_tag_destroy(dma->dma_tag); 1873117845Ssam} 1874117845Ssam 1875117845Ssam/* 1876117845Ssam * Resets the board. Values in the regesters are left as is 1877117845Ssam * from the reset (i.e. initial values are assigned elsewhere). 1878117845Ssam */ 1879117845Ssamstatic void 1880117845Ssamsafe_reset_board(struct safe_softc *sc) 1881117845Ssam{ 1882117845Ssam u_int32_t v; 1883117845Ssam /* 1884117845Ssam * Reset the device. The manual says no delay 1885117845Ssam * is needed between marking and clearing reset. 1886117845Ssam */ 1887117845Ssam v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1888117845Ssam (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1889117845Ssam SAFE_PE_DMACFG_SGRESET); 1890117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v 1891117845Ssam | SAFE_PE_DMACFG_PERESET 1892117845Ssam | SAFE_PE_DMACFG_PDRRESET 1893117845Ssam | SAFE_PE_DMACFG_SGRESET); 1894117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v); 1895117845Ssam} 1896117845Ssam 1897117845Ssam/* 1898117845Ssam * Initialize registers we need to touch only once. 1899117845Ssam */ 1900117845Ssamstatic void 1901117845Ssamsafe_init_board(struct safe_softc *sc) 1902117845Ssam{ 1903117845Ssam u_int32_t v, dwords; 1904117845Ssam 1905201758Smbr v = READ_REG(sc, SAFE_PE_DMACFG); 1906117845Ssam v &=~ SAFE_PE_DMACFG_PEMODE; 1907117845Ssam v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1908117845Ssam | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1909117845Ssam | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1910117845Ssam | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1911117845Ssam | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1912117845Ssam | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1913117845Ssam ; 1914117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v); 1915117845Ssam#if 0 1916117845Ssam /* XXX select byte swap based on host byte order */ 1917117845Ssam WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1918117845Ssam#endif 1919117845Ssam if (sc->sc_chiprev == SAFE_REV(1,0)) { 1920117845Ssam /* 1921117845Ssam * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1922117845Ssam * "target mode transfers" done while the chip is DMA'ing 1923117845Ssam * >1020 bytes cause the hardware to lockup. To avoid this 1924117845Ssam * we reduce the max PCI transfer size and use small source 1925117845Ssam * particle descriptors (<= 256 bytes). 1926117845Ssam */ 1927117845Ssam WRITE_REG(sc, SAFE_DMA_CFG, 256); 1928117845Ssam device_printf(sc->sc_dev, 1929117845Ssam "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1930117845Ssam (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1931117845Ssam SAFE_REV_MAJ(sc->sc_chiprev), 1932117845Ssam SAFE_REV_MIN(sc->sc_chiprev)); 1933117845Ssam } 1934117845Ssam 1935117845Ssam /* NB: operands+results are overlaid */ 1936117845Ssam WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1937117845Ssam WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1938117845Ssam /* 1939117845Ssam * Configure ring entry size and number of items in the ring. 1940117845Ssam */ 1941117845Ssam KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1942117845Ssam ("PE ring entry not 32-bit aligned!")); 1943117845Ssam dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1944117845Ssam WRITE_REG(sc, SAFE_PE_RINGCFG, 1945117845Ssam (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1946117845Ssam WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1947117845Ssam 1948117845Ssam WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1949117845Ssam WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1950117845Ssam WRITE_REG(sc, SAFE_PE_PARTSIZE, 1951117845Ssam (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1952117845Ssam /* 1953117845Ssam * NB: destination particles are fixed size. We use 1954117845Ssam * an mbuf cluster and require all results go to 1955117845Ssam * clusters or smaller. 1956117845Ssam */ 1957117845Ssam WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1958117845Ssam 1959117845Ssam /* it's now safe to enable PE mode, do it */ 1960117845Ssam WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1961117845Ssam 1962117845Ssam /* 1963117845Ssam * Configure hardware to use level-triggered interrupts and 1964117845Ssam * to interrupt after each descriptor is processed. 1965117845Ssam */ 1966117845Ssam WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1967117845Ssam WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1968117845Ssam WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1969117845Ssam} 1970117845Ssam 1971117845Ssam/* 1972117845Ssam * Init PCI registers 1973117845Ssam */ 1974117845Ssamstatic void 1975117845Ssamsafe_init_pciregs(device_t dev) 1976117845Ssam{ 1977117845Ssam} 1978117845Ssam 1979117845Ssam/* 1980117845Ssam * Clean up after a chip crash. 1981117845Ssam * It is assumed that the caller in splimp() 1982117845Ssam */ 1983117845Ssamstatic void 1984117845Ssamsafe_cleanchip(struct safe_softc *sc) 1985117845Ssam{ 1986117845Ssam 1987117845Ssam if (sc->sc_nqchip != 0) { 1988117845Ssam struct safe_ringentry *re = sc->sc_back; 1989117845Ssam 1990117845Ssam while (re != sc->sc_front) { 1991117845Ssam if (re->re_desc.d_csr != 0) 1992117845Ssam safe_free_entry(sc, re); 1993117845Ssam if (++re == sc->sc_ringtop) 1994117845Ssam re = sc->sc_ring; 1995117845Ssam } 1996117845Ssam sc->sc_back = re; 1997117845Ssam sc->sc_nqchip = 0; 1998117845Ssam } 1999117845Ssam} 2000117845Ssam 2001117845Ssam/* 2002117845Ssam * free a safe_q 2003117845Ssam * It is assumed that the caller is within splimp(). 2004117845Ssam */ 2005117845Ssamstatic int 2006117845Ssamsafe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 2007117845Ssam{ 2008117845Ssam struct cryptop *crp; 2009117845Ssam 2010117845Ssam /* 2011117845Ssam * Free header MCR 2012117845Ssam */ 2013117845Ssam if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2014117845Ssam m_freem(re->re_dst_m); 2015117845Ssam 2016117845Ssam crp = (struct cryptop *)re->re_crp; 2017117845Ssam 2018117845Ssam re->re_desc.d_csr = 0; 2019117845Ssam 2020117845Ssam crp->crp_etype = EFAULT; 2021117845Ssam crypto_done(crp); 2022117845Ssam return(0); 2023117845Ssam} 2024117845Ssam 2025117845Ssam/* 2026117845Ssam * Routine to reset the chip and clean up. 2027117845Ssam * It is assumed that the caller is in splimp() 2028117845Ssam */ 2029117845Ssamstatic void 2030117845Ssamsafe_totalreset(struct safe_softc *sc) 2031117845Ssam{ 2032117845Ssam safe_reset_board(sc); 2033117845Ssam safe_init_board(sc); 2034117845Ssam safe_cleanchip(sc); 2035117845Ssam} 2036117845Ssam 2037117845Ssam/* 2038117845Ssam * Is the operand suitable aligned for direct DMA. Each 2039117845Ssam * segment must be aligned on a 32-bit boundary and all 2040117845Ssam * but the last segment must be a multiple of 4 bytes. 2041117845Ssam */ 2042117845Ssamstatic int 2043117845Ssamsafe_dmamap_aligned(const struct safe_operand *op) 2044117845Ssam{ 2045117845Ssam int i; 2046117845Ssam 2047117845Ssam for (i = 0; i < op->nsegs; i++) { 2048117845Ssam if (op->segs[i].ds_addr & 3) 2049117845Ssam return (0); 2050117845Ssam if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2051117845Ssam return (0); 2052117845Ssam } 2053117845Ssam return (1); 2054117845Ssam} 2055117845Ssam 2056117845Ssam/* 2057117845Ssam * Is the operand suitable for direct DMA as the destination 2058117845Ssam * of an operation. The hardware requires that each ``particle'' 2059117845Ssam * but the last in an operation result have the same size. We 2060117845Ssam * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2061117845Ssam * 0 if some segment is not a multiple of of this size, 1 if all 2062117845Ssam * segments are exactly this size, or 2 if segments are at worst 2063117845Ssam * a multple of this size. 2064117845Ssam */ 2065117845Ssamstatic int 2066117845Ssamsafe_dmamap_uniform(const struct safe_operand *op) 2067117845Ssam{ 2068117845Ssam int result = 1; 2069117845Ssam 2070117845Ssam if (op->nsegs > 0) { 2071117845Ssam int i; 2072117845Ssam 2073118882Ssam for (i = 0; i < op->nsegs-1; i++) { 2074117845Ssam if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2075117845Ssam return (0); 2076117845Ssam if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2077117845Ssam result = 2; 2078118882Ssam } 2079117845Ssam } 2080117845Ssam return (result); 2081117845Ssam} 2082117845Ssam 2083117845Ssam#ifdef SAFE_DEBUG 2084117845Ssamstatic void 2085117845Ssamsafe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2086117845Ssam{ 2087117845Ssam printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2088117845Ssam , tag 2089117845Ssam , READ_REG(sc, SAFE_DMA_ENDIAN) 2090117845Ssam , READ_REG(sc, SAFE_DMA_SRCADDR) 2091117845Ssam , READ_REG(sc, SAFE_DMA_DSTADDR) 2092117845Ssam , READ_REG(sc, SAFE_DMA_STAT) 2093117845Ssam ); 2094117845Ssam} 2095117845Ssam 2096117845Ssamstatic void 2097117845Ssamsafe_dump_intrstate(struct safe_softc *sc, const char *tag) 2098117845Ssam{ 2099117845Ssam printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2100117845Ssam , tag 2101117845Ssam , READ_REG(sc, SAFE_HI_CFG) 2102117845Ssam , READ_REG(sc, SAFE_HI_MASK) 2103117845Ssam , READ_REG(sc, SAFE_HI_DESC_CNT) 2104117845Ssam , READ_REG(sc, SAFE_HU_STAT) 2105117845Ssam , READ_REG(sc, SAFE_HM_STAT) 2106117845Ssam ); 2107117845Ssam} 2108117845Ssam 2109117845Ssamstatic void 2110117845Ssamsafe_dump_ringstate(struct safe_softc *sc, const char *tag) 2111117845Ssam{ 2112117845Ssam u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2113117845Ssam 2114117845Ssam /* NB: assume caller has lock on ring */ 2115125466Speter printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2116117845Ssam tag, 2117117845Ssam estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2118125466Speter (unsigned long)(sc->sc_back - sc->sc_ring), 2119125466Speter (unsigned long)(sc->sc_front - sc->sc_ring)); 2120117845Ssam} 2121117845Ssam 2122117845Ssamstatic void 2123117845Ssamsafe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2124117845Ssam{ 2125117845Ssam int ix, nsegs; 2126117845Ssam 2127117845Ssam ix = re - sc->sc_ring; 2128117845Ssam printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2129117845Ssam , tag 2130117845Ssam , re, ix 2131117845Ssam , re->re_desc.d_csr 2132117845Ssam , re->re_desc.d_src 2133117845Ssam , re->re_desc.d_dst 2134117845Ssam , re->re_desc.d_sa 2135117845Ssam , re->re_desc.d_len 2136117845Ssam ); 2137117845Ssam if (re->re_src.nsegs > 1) { 2138117845Ssam ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2139117845Ssam sizeof(struct safe_pdesc); 2140117845Ssam for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2141117845Ssam printf(" spd[%u] %p: %p size %u flags %x" 2142117845Ssam , ix, &sc->sc_spring[ix] 2143125466Speter , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2144117845Ssam , sc->sc_spring[ix].pd_size 2145117845Ssam , sc->sc_spring[ix].pd_flags 2146117845Ssam ); 2147117845Ssam if (sc->sc_spring[ix].pd_size == 0) 2148117845Ssam printf(" (zero!)"); 2149117845Ssam printf("\n"); 2150117845Ssam if (++ix == SAFE_TOTAL_SPART) 2151117845Ssam ix = 0; 2152117845Ssam } 2153117845Ssam } 2154117845Ssam if (re->re_dst.nsegs > 1) { 2155117845Ssam ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2156117845Ssam sizeof(struct safe_pdesc); 2157117845Ssam for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2158117845Ssam printf(" dpd[%u] %p: %p flags %x\n" 2159117845Ssam , ix, &sc->sc_dpring[ix] 2160125466Speter , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2161117845Ssam , sc->sc_dpring[ix].pd_flags 2162117845Ssam ); 2163117845Ssam if (++ix == SAFE_TOTAL_DPART) 2164117845Ssam ix = 0; 2165117845Ssam } 2166117845Ssam } 2167117845Ssam printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2168117845Ssam re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2169117845Ssam printf("sa: key %x %x %x %x %x %x %x %x\n" 2170117845Ssam , re->re_sa.sa_key[0] 2171117845Ssam , re->re_sa.sa_key[1] 2172117845Ssam , re->re_sa.sa_key[2] 2173117845Ssam , re->re_sa.sa_key[3] 2174117845Ssam , re->re_sa.sa_key[4] 2175117845Ssam , re->re_sa.sa_key[5] 2176117845Ssam , re->re_sa.sa_key[6] 2177117845Ssam , re->re_sa.sa_key[7] 2178117845Ssam ); 2179117845Ssam printf("sa: indigest %x %x %x %x %x\n" 2180117845Ssam , re->re_sa.sa_indigest[0] 2181117845Ssam , re->re_sa.sa_indigest[1] 2182117845Ssam , re->re_sa.sa_indigest[2] 2183117845Ssam , re->re_sa.sa_indigest[3] 2184117845Ssam , re->re_sa.sa_indigest[4] 2185117845Ssam ); 2186117845Ssam printf("sa: outdigest %x %x %x %x %x\n" 2187117845Ssam , re->re_sa.sa_outdigest[0] 2188117845Ssam , re->re_sa.sa_outdigest[1] 2189117845Ssam , re->re_sa.sa_outdigest[2] 2190117845Ssam , re->re_sa.sa_outdigest[3] 2191117845Ssam , re->re_sa.sa_outdigest[4] 2192117845Ssam ); 2193117845Ssam printf("sr: iv %x %x %x %x\n" 2194117845Ssam , re->re_sastate.sa_saved_iv[0] 2195117845Ssam , re->re_sastate.sa_saved_iv[1] 2196117845Ssam , re->re_sastate.sa_saved_iv[2] 2197117845Ssam , re->re_sastate.sa_saved_iv[3] 2198117845Ssam ); 2199117845Ssam printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2200117845Ssam , re->re_sastate.sa_saved_hashbc 2201117845Ssam , re->re_sastate.sa_saved_indigest[0] 2202117845Ssam , re->re_sastate.sa_saved_indigest[1] 2203117845Ssam , re->re_sastate.sa_saved_indigest[2] 2204117845Ssam , re->re_sastate.sa_saved_indigest[3] 2205117845Ssam , re->re_sastate.sa_saved_indigest[4] 2206117845Ssam ); 2207117845Ssam} 2208117845Ssam 2209117845Ssamstatic void 2210117845Ssamsafe_dump_ring(struct safe_softc *sc, const char *tag) 2211117845Ssam{ 2212117845Ssam mtx_lock(&sc->sc_ringmtx); 2213117845Ssam printf("\nSafeNet Ring State:\n"); 2214117845Ssam safe_dump_intrstate(sc, tag); 2215117845Ssam safe_dump_dmastatus(sc, tag); 2216117845Ssam safe_dump_ringstate(sc, tag); 2217117845Ssam if (sc->sc_nqchip) { 2218117845Ssam struct safe_ringentry *re = sc->sc_back; 2219117845Ssam do { 2220117845Ssam safe_dump_request(sc, tag, re); 2221117845Ssam if (++re == sc->sc_ringtop) 2222117845Ssam re = sc->sc_ring; 2223117845Ssam } while (re != sc->sc_front); 2224117845Ssam } 2225117845Ssam mtx_unlock(&sc->sc_ringmtx); 2226117845Ssam} 2227117845Ssam 2228117845Ssamstatic int 2229117845Ssamsysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2230117845Ssam{ 2231117845Ssam char dmode[64]; 2232117845Ssam int error; 2233117845Ssam 2234117845Ssam strncpy(dmode, "", sizeof(dmode) - 1); 2235117845Ssam dmode[sizeof(dmode) - 1] = '\0'; 2236117845Ssam error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2237117845Ssam 2238117845Ssam if (error == 0 && req->newptr != NULL) { 2239117845Ssam struct safe_softc *sc = safec; 2240117845Ssam 2241117845Ssam if (!sc) 2242117845Ssam return EINVAL; 2243117845Ssam if (strncmp(dmode, "dma", 3) == 0) 2244117845Ssam safe_dump_dmastatus(sc, "safe0"); 2245117845Ssam else if (strncmp(dmode, "int", 3) == 0) 2246117845Ssam safe_dump_intrstate(sc, "safe0"); 2247117845Ssam else if (strncmp(dmode, "ring", 4) == 0) 2248117845Ssam safe_dump_ring(sc, "safe0"); 2249117845Ssam else 2250117845Ssam return EINVAL; 2251117845Ssam } 2252117845Ssam return error; 2253117845Ssam} 2254117845SsamSYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2255117845Ssam 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2256117845Ssam#endif /* SAFE_DEBUG */ 2257