if_rl.c revision 184524
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 184524 2008-11-01 17:02:01Z imp $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#ifdef HAVE_KERNEL_OPTION_HEADERS 87#include "opt_device_polling.h" 88#include "opt_rl.h" 89#endif 90 91#include <sys/param.h> 92#include <sys/endian.h> 93#include <sys/systm.h> 94#include <sys/sockio.h> 95#include <sys/mbuf.h> 96#include <sys/malloc.h> 97#include <sys/kernel.h> 98#include <sys/module.h> 99#include <sys/socket.h> 100 101#include <net/if.h> 102#include <net/if_arp.h> 103#include <net/ethernet.h> 104#include <net/if_dl.h> 105#include <net/if_media.h> 106#include <net/if_types.h> 107 108#include <net/bpf.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/miivar.h> 117 118#include <dev/pci/pcireg.h> 119#include <dev/pci/pcivar.h> 120 121MODULE_DEPEND(rl, pci, 1, 1, 1); 122MODULE_DEPEND(rl, ether, 1, 1, 1); 123MODULE_DEPEND(rl, miibus, 1, 1, 1); 124 125/* "device miibus" required. See GENERIC if you get errors here. */ 126#include "miibus_if.h" 127 128/* 129 * Default to using PIO access for this driver. On SMP systems, 130 * there appear to be problems with memory mapped mode: it looks like 131 * doing too many memory mapped access back to back in rapid succession 132 * can hang the bus. I'm inclined to blame this on crummy design/construction 133 * on the part of RealTek. Memory mapped mode does appear to work on 134 * uniprocessor systems though. 135 */ 136#define RL_USEIOSPACE 137 138#include <pci/if_rlreg.h> 139 140/* 141 * Various supported device vendors/types and their names. 142 */ 143static struct rl_type rl_devs[] = { 144 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 145 "RealTek 8129 10/100BaseTX" }, 146 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 147 "RealTek 8139 10/100BaseTX" }, 148 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139, 149 "RealTek 8139 10/100BaseTX" }, 150 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 151 "RealTek 8139 10/100BaseTX CardBus" }, 152 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 153 "RealTek 8100 10/100BaseTX" }, 154 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 155 "Accton MPX 5030/5038 10/100BaseTX" }, 156 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 157 "Delta Electronics 8139 10/100BaseTX" }, 158 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 159 "Addtron Technology 8139 10/100BaseTX" }, 160 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 161 "D-Link DFE-530TX+ 10/100BaseTX" }, 162 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 163 "D-Link DFE-690TXD 10/100BaseTX" }, 164 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 165 "Nortel Networks 10/100BaseTX" }, 166 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 167 "Corega FEther CB-TXD" }, 168 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 169 "Corega FEtherII CB-TXD" }, 170 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 171 "Peppercon AG ROL-F" }, 172 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139, 173 "Planex FNW-3603-TX" }, 174 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 175 "Planex FNW-3800-TX" }, 176 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 177 "Compaq HNE-300" }, 178 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 179 "LevelOne FPC-0106TX" }, 180 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 181 "Edimax EP-4103DL CardBus" } 182}; 183 184static int rl_attach(device_t); 185static int rl_detach(device_t); 186static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int); 187static int rl_dma_alloc(struct rl_softc *); 188static void rl_dma_free(struct rl_softc *); 189static void rl_eeprom_putbyte(struct rl_softc *, int); 190static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 191static int rl_encap(struct rl_softc *, struct mbuf **); 192static int rl_list_tx_init(struct rl_softc *); 193static int rl_list_rx_init(struct rl_softc *); 194static int rl_ifmedia_upd(struct ifnet *); 195static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 196static int rl_ioctl(struct ifnet *, u_long, caddr_t); 197static void rl_intr(void *); 198static void rl_init(void *); 199static void rl_init_locked(struct rl_softc *sc); 200static void rl_mii_send(struct rl_softc *, uint32_t, int); 201static void rl_mii_sync(struct rl_softc *); 202static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 203static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 204static int rl_miibus_readreg(device_t, int, int); 205static void rl_miibus_statchg(device_t); 206static int rl_miibus_writereg(device_t, int, int, int); 207#ifdef DEVICE_POLLING 208static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 209static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 210#endif 211static int rl_probe(device_t); 212static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 213static void rl_reset(struct rl_softc *); 214static int rl_resume(device_t); 215static void rl_rxeof(struct rl_softc *); 216static void rl_setmulti(struct rl_softc *); 217static int rl_shutdown(device_t); 218static void rl_start(struct ifnet *); 219static void rl_start_locked(struct ifnet *); 220static void rl_stop(struct rl_softc *); 221static int rl_suspend(device_t); 222static void rl_tick(void *); 223static void rl_txeof(struct rl_softc *); 224static void rl_watchdog(struct rl_softc *); 225 226#ifdef RL_USEIOSPACE 227#define RL_RES SYS_RES_IOPORT 228#define RL_RID RL_PCI_LOIO 229#else 230#define RL_RES SYS_RES_MEMORY 231#define RL_RID RL_PCI_LOMEM 232#endif 233 234static device_method_t rl_methods[] = { 235 /* Device interface */ 236 DEVMETHOD(device_probe, rl_probe), 237 DEVMETHOD(device_attach, rl_attach), 238 DEVMETHOD(device_detach, rl_detach), 239 DEVMETHOD(device_suspend, rl_suspend), 240 DEVMETHOD(device_resume, rl_resume), 241 DEVMETHOD(device_shutdown, rl_shutdown), 242 243 /* bus interface */ 244 DEVMETHOD(bus_print_child, bus_generic_print_child), 245 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 246 247 /* MII interface */ 248 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 249 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 250 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 251 252 { 0, 0 } 253}; 254 255static driver_t rl_driver = { 256 "rl", 257 rl_methods, 258 sizeof(struct rl_softc) 259}; 260 261static devclass_t rl_devclass; 262 263DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 264DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 265DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 266 267#define EE_SET(x) \ 268 CSR_WRITE_1(sc, RL_EECMD, \ 269 CSR_READ_1(sc, RL_EECMD) | x) 270 271#define EE_CLR(x) \ 272 CSR_WRITE_1(sc, RL_EECMD, \ 273 CSR_READ_1(sc, RL_EECMD) & ~x) 274 275/* 276 * Send a read command and address to the EEPROM, check for ACK. 277 */ 278static void 279rl_eeprom_putbyte(struct rl_softc *sc, int addr) 280{ 281 register int d, i; 282 283 d = addr | sc->rl_eecmd_read; 284 285 /* 286 * Feed in each bit and strobe the clock. 287 */ 288 for (i = 0x400; i; i >>= 1) { 289 if (d & i) { 290 EE_SET(RL_EE_DATAIN); 291 } else { 292 EE_CLR(RL_EE_DATAIN); 293 } 294 DELAY(100); 295 EE_SET(RL_EE_CLK); 296 DELAY(150); 297 EE_CLR(RL_EE_CLK); 298 DELAY(100); 299 } 300} 301 302/* 303 * Read a word of data stored in the EEPROM at address 'addr.' 304 */ 305static void 306rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 307{ 308 register int i; 309 uint16_t word = 0; 310 311 /* Enter EEPROM access mode. */ 312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 313 314 /* 315 * Send address of word we want to read. 316 */ 317 rl_eeprom_putbyte(sc, addr); 318 319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 320 321 /* 322 * Start reading bits from EEPROM. 323 */ 324 for (i = 0x8000; i; i >>= 1) { 325 EE_SET(RL_EE_CLK); 326 DELAY(100); 327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 328 word |= i; 329 EE_CLR(RL_EE_CLK); 330 DELAY(100); 331 } 332 333 /* Turn off EEPROM access mode. */ 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 335 336 *dest = word; 337} 338 339/* 340 * Read a sequence of words from the EEPROM. 341 */ 342static void 343rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 344{ 345 int i; 346 uint16_t word = 0, *ptr; 347 348 for (i = 0; i < cnt; i++) { 349 rl_eeprom_getword(sc, off + i, &word); 350 ptr = (uint16_t *)(dest + (i * 2)); 351 if (swap) 352 *ptr = ntohs(word); 353 else 354 *ptr = word; 355 } 356} 357 358/* 359 * MII access routines are provided for the 8129, which 360 * doesn't have a built-in PHY. For the 8139, we fake things 361 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 362 * direct access PHY registers. 363 */ 364#define MII_SET(x) \ 365 CSR_WRITE_1(sc, RL_MII, \ 366 CSR_READ_1(sc, RL_MII) | (x)) 367 368#define MII_CLR(x) \ 369 CSR_WRITE_1(sc, RL_MII, \ 370 CSR_READ_1(sc, RL_MII) & ~(x)) 371 372/* 373 * Sync the PHYs by setting data bit and strobing the clock 32 times. 374 */ 375static void 376rl_mii_sync(struct rl_softc *sc) 377{ 378 register int i; 379 380 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 381 382 for (i = 0; i < 32; i++) { 383 MII_SET(RL_MII_CLK); 384 DELAY(1); 385 MII_CLR(RL_MII_CLK); 386 DELAY(1); 387 } 388} 389 390/* 391 * Clock a series of bits through the MII. 392 */ 393static void 394rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 395{ 396 int i; 397 398 MII_CLR(RL_MII_CLK); 399 400 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 401 if (bits & i) { 402 MII_SET(RL_MII_DATAOUT); 403 } else { 404 MII_CLR(RL_MII_DATAOUT); 405 } 406 DELAY(1); 407 MII_CLR(RL_MII_CLK); 408 DELAY(1); 409 MII_SET(RL_MII_CLK); 410 } 411} 412 413/* 414 * Read an PHY register through the MII. 415 */ 416static int 417rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 418{ 419 int i, ack; 420 421 /* Set up frame for RX. */ 422 frame->mii_stdelim = RL_MII_STARTDELIM; 423 frame->mii_opcode = RL_MII_READOP; 424 frame->mii_turnaround = 0; 425 frame->mii_data = 0; 426 427 CSR_WRITE_2(sc, RL_MII, 0); 428 429 /* Turn on data xmit. */ 430 MII_SET(RL_MII_DIR); 431 432 rl_mii_sync(sc); 433 434 /* Send command/address info. */ 435 rl_mii_send(sc, frame->mii_stdelim, 2); 436 rl_mii_send(sc, frame->mii_opcode, 2); 437 rl_mii_send(sc, frame->mii_phyaddr, 5); 438 rl_mii_send(sc, frame->mii_regaddr, 5); 439 440 /* Idle bit */ 441 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 442 DELAY(1); 443 MII_SET(RL_MII_CLK); 444 DELAY(1); 445 446 /* Turn off xmit. */ 447 MII_CLR(RL_MII_DIR); 448 449 /* Check for ack */ 450 MII_CLR(RL_MII_CLK); 451 DELAY(1); 452 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 453 MII_SET(RL_MII_CLK); 454 DELAY(1); 455 456 /* 457 * Now try reading data bits. If the ack failed, we still 458 * need to clock through 16 cycles to keep the PHY(s) in sync. 459 */ 460 if (ack) { 461 for(i = 0; i < 16; i++) { 462 MII_CLR(RL_MII_CLK); 463 DELAY(1); 464 MII_SET(RL_MII_CLK); 465 DELAY(1); 466 } 467 goto fail; 468 } 469 470 for (i = 0x8000; i; i >>= 1) { 471 MII_CLR(RL_MII_CLK); 472 DELAY(1); 473 if (!ack) { 474 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 475 frame->mii_data |= i; 476 DELAY(1); 477 } 478 MII_SET(RL_MII_CLK); 479 DELAY(1); 480 } 481 482fail: 483 MII_CLR(RL_MII_CLK); 484 DELAY(1); 485 MII_SET(RL_MII_CLK); 486 DELAY(1); 487 488 return (ack ? 1 : 0); 489} 490 491/* 492 * Write to a PHY register through the MII. 493 */ 494static int 495rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 496{ 497 498 /* Set up frame for TX. */ 499 frame->mii_stdelim = RL_MII_STARTDELIM; 500 frame->mii_opcode = RL_MII_WRITEOP; 501 frame->mii_turnaround = RL_MII_TURNAROUND; 502 503 /* Turn on data output. */ 504 MII_SET(RL_MII_DIR); 505 506 rl_mii_sync(sc); 507 508 rl_mii_send(sc, frame->mii_stdelim, 2); 509 rl_mii_send(sc, frame->mii_opcode, 2); 510 rl_mii_send(sc, frame->mii_phyaddr, 5); 511 rl_mii_send(sc, frame->mii_regaddr, 5); 512 rl_mii_send(sc, frame->mii_turnaround, 2); 513 rl_mii_send(sc, frame->mii_data, 16); 514 515 /* Idle bit. */ 516 MII_SET(RL_MII_CLK); 517 DELAY(1); 518 MII_CLR(RL_MII_CLK); 519 DELAY(1); 520 521 /* Turn off xmit. */ 522 MII_CLR(RL_MII_DIR); 523 524 return (0); 525} 526 527static int 528rl_miibus_readreg(device_t dev, int phy, int reg) 529{ 530 struct rl_softc *sc; 531 struct rl_mii_frame frame; 532 uint16_t rval = 0; 533 uint16_t rl8139_reg = 0; 534 535 sc = device_get_softc(dev); 536 537 if (sc->rl_type == RL_8139) { 538 /* Pretend the internal PHY is only at address 0 */ 539 if (phy) { 540 return (0); 541 } 542 switch (reg) { 543 case MII_BMCR: 544 rl8139_reg = RL_BMCR; 545 break; 546 case MII_BMSR: 547 rl8139_reg = RL_BMSR; 548 break; 549 case MII_ANAR: 550 rl8139_reg = RL_ANAR; 551 break; 552 case MII_ANER: 553 rl8139_reg = RL_ANER; 554 break; 555 case MII_ANLPAR: 556 rl8139_reg = RL_LPAR; 557 break; 558 case MII_PHYIDR1: 559 case MII_PHYIDR2: 560 return (0); 561 /* 562 * Allow the rlphy driver to read the media status 563 * register. If we have a link partner which does not 564 * support NWAY, this is the register which will tell 565 * us the results of parallel detection. 566 */ 567 case RL_MEDIASTAT: 568 rval = CSR_READ_1(sc, RL_MEDIASTAT); 569 return (rval); 570 default: 571 device_printf(sc->rl_dev, "bad phy register\n"); 572 return (0); 573 } 574 rval = CSR_READ_2(sc, rl8139_reg); 575 return (rval); 576 } 577 578 bzero((char *)&frame, sizeof(frame)); 579 frame.mii_phyaddr = phy; 580 frame.mii_regaddr = reg; 581 rl_mii_readreg(sc, &frame); 582 583 return (frame.mii_data); 584} 585 586static int 587rl_miibus_writereg(device_t dev, int phy, int reg, int data) 588{ 589 struct rl_softc *sc; 590 struct rl_mii_frame frame; 591 uint16_t rl8139_reg = 0; 592 593 sc = device_get_softc(dev); 594 595 if (sc->rl_type == RL_8139) { 596 /* Pretend the internal PHY is only at address 0 */ 597 if (phy) { 598 return (0); 599 } 600 switch (reg) { 601 case MII_BMCR: 602 rl8139_reg = RL_BMCR; 603 break; 604 case MII_BMSR: 605 rl8139_reg = RL_BMSR; 606 break; 607 case MII_ANAR: 608 rl8139_reg = RL_ANAR; 609 break; 610 case MII_ANER: 611 rl8139_reg = RL_ANER; 612 break; 613 case MII_ANLPAR: 614 rl8139_reg = RL_LPAR; 615 break; 616 case MII_PHYIDR1: 617 case MII_PHYIDR2: 618 return (0); 619 break; 620 default: 621 device_printf(sc->rl_dev, "bad phy register\n"); 622 return (0); 623 } 624 CSR_WRITE_2(sc, rl8139_reg, data); 625 return (0); 626 } 627 628 bzero((char *)&frame, sizeof(frame)); 629 frame.mii_phyaddr = phy; 630 frame.mii_regaddr = reg; 631 frame.mii_data = data; 632 rl_mii_writereg(sc, &frame); 633 634 return (0); 635} 636 637static void 638rl_miibus_statchg(device_t dev) 639{ 640 struct rl_softc *sc; 641 struct ifnet *ifp; 642 struct mii_data *mii; 643 644 sc = device_get_softc(dev); 645 mii = device_get_softc(sc->rl_miibus); 646 ifp = sc->rl_ifp; 647 if (mii == NULL || ifp == NULL || 648 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 649 return; 650 651 sc->rl_flags &= ~RL_FLAG_LINK; 652 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 653 (IFM_ACTIVE | IFM_AVALID)) { 654 switch (IFM_SUBTYPE(mii->mii_media_active)) { 655 case IFM_10_T: 656 case IFM_100_TX: 657 sc->rl_flags |= RL_FLAG_LINK; 658 break; 659 default: 660 break; 661 } 662 } 663 /* 664 * RealTek controllers do not provide any interface to 665 * Tx/Rx MACs for resolved speed, duplex and flow-control 666 * parameters. 667 */ 668} 669 670/* 671 * Program the 64-bit multicast hash filter. 672 */ 673static void 674rl_setmulti(struct rl_softc *sc) 675{ 676 struct ifnet *ifp = sc->rl_ifp; 677 int h = 0; 678 uint32_t hashes[2] = { 0, 0 }; 679 struct ifmultiaddr *ifma; 680 uint32_t rxfilt; 681 int mcnt = 0; 682 683 RL_LOCK_ASSERT(sc); 684 685 rxfilt = CSR_READ_4(sc, RL_RXCFG); 686 687 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 688 rxfilt |= RL_RXCFG_RX_MULTI; 689 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 690 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 691 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 692 return; 693 } 694 695 /* first, zot all the existing hash bits */ 696 CSR_WRITE_4(sc, RL_MAR0, 0); 697 CSR_WRITE_4(sc, RL_MAR4, 0); 698 699 /* now program new ones */ 700 IF_ADDR_LOCK(ifp); 701 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 702 if (ifma->ifma_addr->sa_family != AF_LINK) 703 continue; 704 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 705 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 706 if (h < 32) 707 hashes[0] |= (1 << h); 708 else 709 hashes[1] |= (1 << (h - 32)); 710 mcnt++; 711 } 712 IF_ADDR_UNLOCK(ifp); 713 714 if (mcnt) 715 rxfilt |= RL_RXCFG_RX_MULTI; 716 else 717 rxfilt &= ~RL_RXCFG_RX_MULTI; 718 719 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 720 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 721 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 722} 723 724static void 725rl_reset(struct rl_softc *sc) 726{ 727 register int i; 728 729 RL_LOCK_ASSERT(sc); 730 731 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 732 733 for (i = 0; i < RL_TIMEOUT; i++) { 734 DELAY(10); 735 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 736 break; 737 } 738 if (i == RL_TIMEOUT) 739 device_printf(sc->rl_dev, "reset never completed!\n"); 740} 741 742/* 743 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 744 * IDs against our list and return a device name if we find a match. 745 */ 746static int 747rl_probe(device_t dev) 748{ 749 struct rl_type *t; 750 uint16_t devid, revid, vendor; 751 int i; 752 753 vendor = pci_get_vendor(dev); 754 devid = pci_get_device(dev); 755 revid = pci_get_revid(dev); 756 757 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 758 if (revid == 0x20) { 759 /* 8139C+, let re(4) take care of this device. */ 760 return (ENXIO); 761 } 762 } 763 t = rl_devs; 764 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) { 765 if (vendor == t->rl_vid && devid == t->rl_did) { 766 device_set_desc(dev, t->rl_name); 767 return (BUS_PROBE_DEFAULT); 768 } 769 } 770 771 return (ENXIO); 772} 773 774struct rl_dmamap_arg { 775 bus_addr_t rl_busaddr; 776}; 777 778static void 779rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 780{ 781 struct rl_dmamap_arg *ctx; 782 783 if (error != 0) 784 return; 785 786 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 787 788 ctx = (struct rl_dmamap_arg *)arg; 789 ctx->rl_busaddr = segs[0].ds_addr; 790} 791 792/* 793 * Attach the interface. Allocate softc structures, do ifmedia 794 * setup and ethernet/BPF attach. 795 */ 796static int 797rl_attach(device_t dev) 798{ 799 uint8_t eaddr[ETHER_ADDR_LEN]; 800 uint16_t as[3]; 801 struct ifnet *ifp; 802 struct rl_softc *sc; 803 struct rl_type *t; 804 int error = 0, i, rid; 805 int unit; 806 uint16_t rl_did = 0; 807 808 sc = device_get_softc(dev); 809 unit = device_get_unit(dev); 810 sc->rl_dev = dev; 811 812 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 813 MTX_DEF); 814 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 815 816 pci_enable_busmaster(dev); 817 818 /* Map control/status registers. */ 819 rid = RL_RID; 820 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 821 822 if (sc->rl_res == NULL) { 823 device_printf(dev, "couldn't map ports/memory\n"); 824 error = ENXIO; 825 goto fail; 826 } 827 828#ifdef notdef 829 /* 830 * Detect the Realtek 8139B. For some reason, this chip is very 831 * unstable when left to autoselect the media 832 * The best workaround is to set the device to the required 833 * media type or to set it to the 10 Meg speed. 834 */ 835 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 836 device_printf(dev, 837"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 838#endif 839 840 sc->rl_btag = rman_get_bustag(sc->rl_res); 841 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 842 843 /* Allocate interrupt */ 844 rid = 0; 845 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 846 RF_SHAREABLE | RF_ACTIVE); 847 848 if (sc->rl_irq[0] == NULL) { 849 device_printf(dev, "couldn't map interrupt\n"); 850 error = ENXIO; 851 goto fail; 852 } 853 854 /* 855 * Reset the adapter. Only take the lock here as it's needed in 856 * order to call rl_reset(). 857 */ 858 RL_LOCK(sc); 859 rl_reset(sc); 860 RL_UNLOCK(sc); 861 862 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 863 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 864 if (rl_did != 0x8129) 865 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 866 867 /* 868 * Get station address from the EEPROM. 869 */ 870 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 871 for (i = 0; i < 3; i++) { 872 eaddr[(i * 2) + 0] = as[i] & 0xff; 873 eaddr[(i * 2) + 1] = as[i] >> 8; 874 } 875 876 /* 877 * Now read the exact device type from the EEPROM to find 878 * out if it's an 8129 or 8139. 879 */ 880 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 881 882 t = rl_devs; 883 sc->rl_type = 0; 884 while(t->rl_name != NULL) { 885 if (rl_did == t->rl_did) { 886 sc->rl_type = t->rl_basetype; 887 break; 888 } 889 t++; 890 } 891 892 if (sc->rl_type == 0) { 893 device_printf(dev, "unknown device ID: %x\n", rl_did); 894 error = ENXIO; 895 goto fail; 896 } 897 898 if ((error = rl_dma_alloc(sc)) != 0) 899 goto fail; 900 901 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 902 if (ifp == NULL) { 903 device_printf(dev, "can not if_alloc()\n"); 904 error = ENOSPC; 905 goto fail; 906 } 907 908 /* Do MII setup */ 909 if (mii_phy_probe(dev, &sc->rl_miibus, 910 rl_ifmedia_upd, rl_ifmedia_sts)) { 911 device_printf(dev, "MII without any phy!\n"); 912 error = ENXIO; 913 goto fail; 914 } 915 916 ifp->if_softc = sc; 917 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 918 ifp->if_mtu = ETHERMTU; 919 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 920 ifp->if_ioctl = rl_ioctl; 921 ifp->if_start = rl_start; 922 ifp->if_init = rl_init; 923 ifp->if_capabilities = IFCAP_VLAN_MTU; 924 ifp->if_capenable = ifp->if_capabilities; 925#ifdef DEVICE_POLLING 926 ifp->if_capabilities |= IFCAP_POLLING; 927#endif 928 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 929 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 930 IFQ_SET_READY(&ifp->if_snd); 931 932 /* 933 * Call MI attach routine. 934 */ 935 ether_ifattach(ifp, eaddr); 936 937 /* Hook interrupt last to avoid having to lock softc */ 938 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE, 939 NULL, rl_intr, sc, &sc->rl_intrhand[0]); 940 if (error) { 941 device_printf(sc->rl_dev, "couldn't set up irq\n"); 942 ether_ifdetach(ifp); 943 } 944 945fail: 946 if (error) 947 rl_detach(dev); 948 949 return (error); 950} 951 952/* 953 * Shutdown hardware and free up resources. This can be called any 954 * time after the mutex has been initialized. It is called in both 955 * the error case in attach and the normal detach case so it needs 956 * to be careful about only freeing resources that have actually been 957 * allocated. 958 */ 959static int 960rl_detach(device_t dev) 961{ 962 struct rl_softc *sc; 963 struct ifnet *ifp; 964 965 sc = device_get_softc(dev); 966 ifp = sc->rl_ifp; 967 968 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 969 970#ifdef DEVICE_POLLING 971 if (ifp->if_capenable & IFCAP_POLLING) 972 ether_poll_deregister(ifp); 973#endif 974 /* These should only be active if attach succeeded */ 975 if (device_is_attached(dev)) { 976 RL_LOCK(sc); 977 rl_stop(sc); 978 RL_UNLOCK(sc); 979 callout_drain(&sc->rl_stat_callout); 980 ether_ifdetach(ifp); 981 } 982#if 0 983 sc->suspended = 1; 984#endif 985 if (sc->rl_miibus) 986 device_delete_child(dev, sc->rl_miibus); 987 bus_generic_detach(dev); 988 989 if (sc->rl_intrhand[0]) 990 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 991 if (sc->rl_irq[0]) 992 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]); 993 if (sc->rl_res) 994 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 995 996 if (ifp) 997 if_free(ifp); 998 999 rl_dma_free(sc); 1000 1001 mtx_destroy(&sc->rl_mtx); 1002 1003 return (0); 1004} 1005 1006static int 1007rl_dma_alloc(struct rl_softc *sc) 1008{ 1009 struct rl_dmamap_arg ctx; 1010 int error, i; 1011 1012 /* 1013 * Allocate the parent bus DMA tag appropriate for PCI. 1014 */ 1015 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */ 1016 1, 0, /* alignment, boundary */ 1017 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1018 BUS_SPACE_MAXADDR, /* highaddr */ 1019 NULL, NULL, /* filter, filterarg */ 1020 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 1021 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1022 0, /* flags */ 1023 NULL, NULL, /* lockfunc, lockarg */ 1024 &sc->rl_parent_tag); 1025 if (error) { 1026 device_printf(sc->rl_dev, 1027 "failed to create parent DMA tag.\n"); 1028 goto fail; 1029 } 1030 /* Create DMA tag for Rx memory block. */ 1031 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1032 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 1033 BUS_SPACE_MAXADDR, /* lowaddr */ 1034 BUS_SPACE_MAXADDR, /* highaddr */ 1035 NULL, NULL, /* filter, filterarg */ 1036 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */ 1037 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */ 1038 0, /* flags */ 1039 NULL, NULL, /* lockfunc, lockarg */ 1040 &sc->rl_cdata.rl_rx_tag); 1041 if (error) { 1042 device_printf(sc->rl_dev, 1043 "failed to create Rx memory block DMA tag.\n"); 1044 goto fail; 1045 } 1046 /* Create DMA tag for Tx buffer. */ 1047 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1048 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 1049 BUS_SPACE_MAXADDR, /* lowaddr */ 1050 BUS_SPACE_MAXADDR, /* highaddr */ 1051 NULL, NULL, /* filter, filterarg */ 1052 MCLBYTES, 1, /* maxsize, nsegments */ 1053 MCLBYTES, /* maxsegsize */ 1054 0, /* flags */ 1055 NULL, NULL, /* lockfunc, lockarg */ 1056 &sc->rl_cdata.rl_tx_tag); 1057 if (error) { 1058 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n"); 1059 goto fail; 1060 } 1061 1062 /* 1063 * Allocate DMA'able memory and load DMA map for Rx memory block. 1064 */ 1065 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag, 1066 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK | 1067 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap); 1068 if (error != 0) { 1069 device_printf(sc->rl_dev, 1070 "failed to allocate Rx DMA memory block.\n"); 1071 goto fail; 1072 } 1073 ctx.rl_busaddr = 0; 1074 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag, 1075 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf, 1076 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx, 1077 BUS_DMA_NOWAIT); 1078 if (error != 0 || ctx.rl_busaddr == 0) { 1079 device_printf(sc->rl_dev, 1080 "could not load Rx DMA memory block.\n"); 1081 goto fail; 1082 } 1083 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr; 1084 1085 /* Create DMA maps for Tx buffers. */ 1086 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1087 sc->rl_cdata.rl_tx_chain[i] = NULL; 1088 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 1089 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0, 1090 &sc->rl_cdata.rl_tx_dmamap[i]); 1091 if (error != 0) { 1092 device_printf(sc->rl_dev, 1093 "could not create Tx dmamap.\n"); 1094 goto fail; 1095 } 1096 } 1097 1098 /* Leave a few bytes before the start of the RX ring buffer. */ 1099 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1100 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE; 1101 1102fail: 1103 return (error); 1104} 1105 1106static void 1107rl_dma_free(struct rl_softc *sc) 1108{ 1109 int i; 1110 1111 /* Rx memory block. */ 1112 if (sc->rl_cdata.rl_rx_tag != NULL) { 1113 if (sc->rl_cdata.rl_rx_dmamap != NULL) 1114 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1115 sc->rl_cdata.rl_rx_dmamap); 1116 if (sc->rl_cdata.rl_rx_dmamap != NULL && 1117 sc->rl_cdata.rl_rx_buf_ptr != NULL) 1118 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1119 sc->rl_cdata.rl_rx_buf_ptr, 1120 sc->rl_cdata.rl_rx_dmamap); 1121 sc->rl_cdata.rl_rx_buf_ptr = NULL; 1122 sc->rl_cdata.rl_rx_buf = NULL; 1123 sc->rl_cdata.rl_rx_dmamap = NULL; 1124 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1125 sc->rl_cdata.rl_tx_tag = NULL; 1126 } 1127 1128 /* Tx buffers. */ 1129 if (sc->rl_cdata.rl_tx_tag != NULL) { 1130 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1131 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) { 1132 bus_dmamap_destroy( 1133 sc->rl_cdata.rl_tx_tag, 1134 sc->rl_cdata.rl_tx_dmamap[i]); 1135 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 1136 } 1137 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1138 sc->rl_cdata.rl_tx_tag = NULL; 1139 } 1140 } 1141 1142 if (sc->rl_parent_tag != NULL) { 1143 bus_dma_tag_destroy(sc->rl_parent_tag); 1144 sc->rl_parent_tag = NULL; 1145 } 1146} 1147 1148/* 1149 * Initialize the transmit descriptors. 1150 */ 1151static int 1152rl_list_tx_init(struct rl_softc *sc) 1153{ 1154 struct rl_chain_data *cd; 1155 int i; 1156 1157 RL_LOCK_ASSERT(sc); 1158 1159 cd = &sc->rl_cdata; 1160 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1161 cd->rl_tx_chain[i] = NULL; 1162 CSR_WRITE_4(sc, 1163 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1164 } 1165 1166 sc->rl_cdata.cur_tx = 0; 1167 sc->rl_cdata.last_tx = 0; 1168 1169 return (0); 1170} 1171 1172static int 1173rl_list_rx_init(struct rl_softc *sc) 1174{ 1175 1176 RL_LOCK_ASSERT(sc); 1177 1178 bzero(sc->rl_cdata.rl_rx_buf_ptr, 1179 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ); 1180 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap, 1181 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1182 1183 return (0); 1184} 1185 1186/* 1187 * A frame has been uploaded: pass the resulting mbuf chain up to 1188 * the higher level protocols. 1189 * 1190 * You know there's something wrong with a PCI bus-master chip design 1191 * when you have to use m_devget(). 1192 * 1193 * The receive operation is badly documented in the datasheet, so I'll 1194 * attempt to document it here. The driver provides a buffer area and 1195 * places its base address in the RX buffer start address register. 1196 * The chip then begins copying frames into the RX buffer. Each frame 1197 * is preceded by a 32-bit RX status word which specifies the length 1198 * of the frame and certain other status bits. Each frame (starting with 1199 * the status word) is also 32-bit aligned. The frame length is in the 1200 * first 16 bits of the status word; the lower 15 bits correspond with 1201 * the 'rx status register' mentioned in the datasheet. 1202 * 1203 * Note: to make the Alpha happy, the frame payload needs to be aligned 1204 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1205 * as the offset argument to m_devget(). 1206 */ 1207static void 1208rl_rxeof(struct rl_softc *sc) 1209{ 1210 struct mbuf *m; 1211 struct ifnet *ifp = sc->rl_ifp; 1212 uint8_t *rxbufpos; 1213 int total_len = 0; 1214 int wrap = 0; 1215 uint32_t rxstat; 1216 uint16_t cur_rx; 1217 uint16_t limit; 1218 uint16_t max_bytes, rx_bytes = 0; 1219 1220 RL_LOCK_ASSERT(sc); 1221 1222 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap, 1223 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1224 1225 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1226 1227 /* Do not try to read past this point. */ 1228 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1229 1230 if (limit < cur_rx) 1231 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1232 else 1233 max_bytes = limit - cur_rx; 1234 1235 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1236#ifdef DEVICE_POLLING 1237 if (ifp->if_capenable & IFCAP_POLLING) { 1238 if (sc->rxcycles <= 0) 1239 break; 1240 sc->rxcycles--; 1241 } 1242#endif 1243 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1244 rxstat = le32toh(*(uint32_t *)rxbufpos); 1245 1246 /* 1247 * Here's a totally undocumented fact for you. When the 1248 * RealTek chip is in the process of copying a packet into 1249 * RAM for you, the length will be 0xfff0. If you spot a 1250 * packet header with this value, you need to stop. The 1251 * datasheet makes absolutely no mention of this and 1252 * RealTek should be shot for this. 1253 */ 1254 total_len = rxstat >> 16; 1255 if (total_len == RL_RXSTAT_UNFINISHED) 1256 break; 1257 1258 if (!(rxstat & RL_RXSTAT_RXOK) || 1259 total_len < ETHER_MIN_LEN || 1260 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 1261 ifp->if_ierrors++; 1262 rl_init_locked(sc); 1263 return; 1264 } 1265 1266 /* No errors; receive the packet. */ 1267 rx_bytes += total_len + 4; 1268 1269 /* 1270 * XXX The RealTek chip includes the CRC with every 1271 * received frame, and there's no way to turn this 1272 * behavior off (at least, I can't find anything in 1273 * the manual that explains how to do it) so we have 1274 * to trim off the CRC manually. 1275 */ 1276 total_len -= ETHER_CRC_LEN; 1277 1278 /* 1279 * Avoid trying to read more bytes than we know 1280 * the chip has prepared for us. 1281 */ 1282 if (rx_bytes > max_bytes) 1283 break; 1284 1285 rxbufpos = sc->rl_cdata.rl_rx_buf + 1286 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1287 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1288 rxbufpos = sc->rl_cdata.rl_rx_buf; 1289 1290 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1291 if (total_len > wrap) { 1292 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1293 NULL); 1294 if (m == NULL) { 1295 ifp->if_ierrors++; 1296 } else { 1297 m_copyback(m, wrap, total_len - wrap, 1298 sc->rl_cdata.rl_rx_buf); 1299 } 1300 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1301 } else { 1302 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1303 NULL); 1304 if (m == NULL) 1305 ifp->if_ierrors++; 1306 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1307 } 1308 1309 /* Round up to 32-bit boundary. */ 1310 cur_rx = (cur_rx + 3) & ~3; 1311 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1312 1313 if (m == NULL) 1314 continue; 1315 1316 ifp->if_ipackets++; 1317 RL_UNLOCK(sc); 1318 (*ifp->if_input)(ifp, m); 1319 RL_LOCK(sc); 1320 } 1321 1322 /* No need to sync Rx memory block as we didn't modify it. */ 1323} 1324 1325/* 1326 * A frame was downloaded to the chip. It's safe for us to clean up 1327 * the list buffers. 1328 */ 1329static void 1330rl_txeof(struct rl_softc *sc) 1331{ 1332 struct ifnet *ifp = sc->rl_ifp; 1333 uint32_t txstat; 1334 1335 RL_LOCK_ASSERT(sc); 1336 1337 /* 1338 * Go through our tx list and free mbufs for those 1339 * frames that have been uploaded. 1340 */ 1341 do { 1342 if (RL_LAST_TXMBUF(sc) == NULL) 1343 break; 1344 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1345 if (!(txstat & (RL_TXSTAT_TX_OK| 1346 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1347 break; 1348 1349 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1350 1351 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc), 1352 BUS_DMASYNC_POSTWRITE); 1353 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1354 m_freem(RL_LAST_TXMBUF(sc)); 1355 RL_LAST_TXMBUF(sc) = NULL; 1356 /* 1357 * If there was a transmit underrun, bump the TX threshold. 1358 * Make sure not to overflow the 63 * 32byte we can address 1359 * with the 6 available bit. 1360 */ 1361 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1362 (sc->rl_txthresh < 2016)) 1363 sc->rl_txthresh += 32; 1364 if (txstat & RL_TXSTAT_TX_OK) 1365 ifp->if_opackets++; 1366 else { 1367 int oldthresh; 1368 ifp->if_oerrors++; 1369 if ((txstat & RL_TXSTAT_TXABRT) || 1370 (txstat & RL_TXSTAT_OUTOFWIN)) 1371 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1372 oldthresh = sc->rl_txthresh; 1373 /* error recovery */ 1374 rl_init_locked(sc); 1375 /* restore original threshold */ 1376 sc->rl_txthresh = oldthresh; 1377 return; 1378 } 1379 RL_INC(sc->rl_cdata.last_tx); 1380 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1381 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1382 1383 if (RL_LAST_TXMBUF(sc) == NULL) 1384 sc->rl_watchdog_timer = 0; 1385} 1386 1387#ifdef RL_TWISTER_ENABLE 1388static void 1389rl_twister_update(struct rl_softc *sc) 1390{ 1391 uint16_t linktest; 1392 /* 1393 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for 1394 * Linux driver. Values undocumented otherwise. 1395 */ 1396 static const uint32_t param[4][4] = { 1397 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1398 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1399 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1400 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1401 }; 1402 1403 /* 1404 * Tune the so-called twister registers of the RTL8139. These 1405 * are used to compensate for impedance mismatches. The 1406 * method for tuning these registers is undocumented and the 1407 * following procedure is collected from public sources. 1408 */ 1409 switch (sc->rl_twister) 1410 { 1411 case CHK_LINK: 1412 /* 1413 * If we have a sufficient link, then we can proceed in 1414 * the state machine to the next stage. If not, then 1415 * disable further tuning after writing sane defaults. 1416 */ 1417 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { 1418 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD); 1419 sc->rl_twister = FIND_ROW; 1420 } else { 1421 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD); 1422 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1423 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1424 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1425 sc->rl_twister = DONE; 1426 } 1427 break; 1428 case FIND_ROW: 1429 /* 1430 * Read how long it took to see the echo to find the tuning 1431 * row to use. 1432 */ 1433 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1434 if (linktest == RL_CSCFG_ROW3) 1435 sc->rl_twist_row = 3; 1436 else if (linktest == RL_CSCFG_ROW2) 1437 sc->rl_twist_row = 2; 1438 else if (linktest == RL_CSCFG_ROW1) 1439 sc->rl_twist_row = 1; 1440 else 1441 sc->rl_twist_row = 0; 1442 sc->rl_twist_col = 0; 1443 sc->rl_twister = SET_PARAM; 1444 break; 1445 case SET_PARAM: 1446 if (sc->rl_twist_col == 0) 1447 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1448 CSR_WRITE_4(sc, RL_PARA7C, 1449 param[sc->rl_twist_row][sc->rl_twist_col]); 1450 if (++sc->rl_twist_col == 4) { 1451 if (sc->rl_twist_row == 3) 1452 sc->rl_twister = RECHK_LONG; 1453 else 1454 sc->rl_twister = DONE; 1455 } 1456 break; 1457 case RECHK_LONG: 1458 /* 1459 * For long cables, we have to double check to make sure we 1460 * don't mistune. 1461 */ 1462 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1463 if (linktest == RL_CSCFG_ROW3) 1464 sc->rl_twister = DONE; 1465 else { 1466 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE); 1467 sc->rl_twister = RETUNE; 1468 } 1469 break; 1470 case RETUNE: 1471 /* Retune for a shorter cable (try column 2) */ 1472 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1473 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1474 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1475 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1476 sc->rl_twist_row--; 1477 sc->rl_twist_col = 0; 1478 sc->rl_twister = SET_PARAM; 1479 break; 1480 1481 case DONE: 1482 break; 1483 } 1484 1485} 1486#endif 1487 1488static void 1489rl_tick(void *xsc) 1490{ 1491 struct rl_softc *sc = xsc; 1492 struct mii_data *mii; 1493 int ticks; 1494 1495 RL_LOCK_ASSERT(sc); 1496 /* 1497 * If we're doing the twister cable calibration, then we need to defer 1498 * watchdog timeouts. This is a no-op in normal operations, but 1499 * can falsely trigger when the cable calibration takes a while and 1500 * there was traffic ready to go when rl was started. 1501 * 1502 * We don't defer mii_tick since that updates the mii status, which 1503 * helps the twister process, at least according to similar patches 1504 * for the Linux driver I found online while doing the fixes. Worst 1505 * case is a few extra mii reads during calibration. 1506 */ 1507 mii = device_get_softc(sc->rl_miibus); 1508 mii_tick(mii); 1509#ifdef RL_TWISTER_ENABLE 1510 if (sc->rl_twister == DONE) 1511 rl_watchdog(sc); 1512 else 1513 rl_twister_update(sc); 1514 if (sc->rl_twister == DONE) 1515 ticks = hz; 1516 else 1517 ticks = hz / 10; 1518#else 1519 rl_watchdog(sc); 1520 ticks = hz; 1521#endif 1522 1523 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc); 1524} 1525 1526#ifdef DEVICE_POLLING 1527static void 1528rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1529{ 1530 struct rl_softc *sc = ifp->if_softc; 1531 1532 RL_LOCK(sc); 1533 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1534 rl_poll_locked(ifp, cmd, count); 1535 RL_UNLOCK(sc); 1536} 1537 1538static void 1539rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1540{ 1541 struct rl_softc *sc = ifp->if_softc; 1542 1543 RL_LOCK_ASSERT(sc); 1544 1545 sc->rxcycles = count; 1546 rl_rxeof(sc); 1547 rl_txeof(sc); 1548 1549 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1550 rl_start_locked(ifp); 1551 1552 if (cmd == POLL_AND_CHECK_STATUS) { 1553 uint16_t status; 1554 1555 /* We should also check the status register. */ 1556 status = CSR_READ_2(sc, RL_ISR); 1557 if (status == 0xffff) 1558 return; 1559 if (status != 0) 1560 CSR_WRITE_2(sc, RL_ISR, status); 1561 1562 /* XXX We should check behaviour on receiver stalls. */ 1563 1564 if (status & RL_ISR_SYSTEM_ERR) 1565 rl_init_locked(sc); 1566 } 1567} 1568#endif /* DEVICE_POLLING */ 1569 1570static void 1571rl_intr(void *arg) 1572{ 1573 struct rl_softc *sc = arg; 1574 struct ifnet *ifp = sc->rl_ifp; 1575 uint16_t status; 1576 1577 RL_LOCK(sc); 1578 1579 if (sc->suspended) 1580 goto done_locked; 1581 1582#ifdef DEVICE_POLLING 1583 if (ifp->if_capenable & IFCAP_POLLING) 1584 goto done_locked; 1585#endif 1586 1587 for (;;) { 1588 status = CSR_READ_2(sc, RL_ISR); 1589 /* If the card has gone away, the read returns 0xffff. */ 1590 if (status == 0xffff) 1591 break; 1592 if (status != 0) 1593 CSR_WRITE_2(sc, RL_ISR, status); 1594 if ((status & RL_INTRS) == 0) 1595 break; 1596 if (status & RL_ISR_RX_OK) 1597 rl_rxeof(sc); 1598 if (status & RL_ISR_RX_ERR) 1599 rl_rxeof(sc); 1600 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1601 rl_txeof(sc); 1602 if (status & RL_ISR_SYSTEM_ERR) 1603 rl_init_locked(sc); 1604 } 1605 1606 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1607 rl_start_locked(ifp); 1608 1609done_locked: 1610 RL_UNLOCK(sc); 1611} 1612 1613/* 1614 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1615 * pointers to the fragment pointers. 1616 */ 1617static int 1618rl_encap(struct rl_softc *sc, struct mbuf **m_head) 1619{ 1620 struct mbuf *m; 1621 bus_dma_segment_t txsegs[1]; 1622 int error, nsegs, padlen; 1623 1624 RL_LOCK_ASSERT(sc); 1625 1626 m = *m_head; 1627 padlen = 0; 1628 /* 1629 * Hardware doesn't auto-pad, so we have to make sure 1630 * pad short frames out to the minimum frame length. 1631 */ 1632 if (m->m_pkthdr.len < RL_MIN_FRAMELEN) 1633 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len; 1634 /* 1635 * The RealTek is brain damaged and wants longword-aligned 1636 * TX buffers, plus we can only have one fragment buffer 1637 * per packet. We have to copy pretty much all the time. 1638 */ 1639 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 || 1640 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) { 1641 m = m_defrag(*m_head, M_DONTWAIT); 1642 if (m == NULL) { 1643 m_freem(*m_head); 1644 *m_head = NULL; 1645 return (ENOMEM); 1646 } 1647 } 1648 *m_head = m; 1649 1650 if (padlen > 0) { 1651 /* 1652 * Make security-conscious people happy: zero out the 1653 * bytes in the pad area, since we don't know what 1654 * this mbuf cluster buffer's previous user might 1655 * have left in it. 1656 */ 1657 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1658 m->m_pkthdr.len += padlen; 1659 m->m_len = m->m_pkthdr.len; 1660 } 1661 1662 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag, 1663 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0); 1664 if (error != 0) 1665 return (error); 1666 if (nsegs == 0) { 1667 m_freem(*m_head); 1668 *m_head = NULL; 1669 return (EIO); 1670 } 1671 1672 RL_CUR_TXMBUF(sc) = m; 1673 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1674 BUS_DMASYNC_PREWRITE); 1675 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr)); 1676 1677 return (0); 1678} 1679 1680/* 1681 * Main transmit routine. 1682 */ 1683static void 1684rl_start(struct ifnet *ifp) 1685{ 1686 struct rl_softc *sc = ifp->if_softc; 1687 1688 RL_LOCK(sc); 1689 rl_start_locked(ifp); 1690 RL_UNLOCK(sc); 1691} 1692 1693static void 1694rl_start_locked(struct ifnet *ifp) 1695{ 1696 struct rl_softc *sc = ifp->if_softc; 1697 struct mbuf *m_head = NULL; 1698 1699 RL_LOCK_ASSERT(sc); 1700 1701 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1702 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 1703 return; 1704 1705 while (RL_CUR_TXMBUF(sc) == NULL) { 1706 1707 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1708 1709 if (m_head == NULL) 1710 break; 1711 1712 if (rl_encap(sc, &m_head)) { 1713 if (m_head == NULL) 1714 break; 1715 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1716 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1717 break; 1718 } 1719 1720 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1721 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1722 1723 /* Transmit the frame. */ 1724 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1725 RL_TXTHRESH(sc->rl_txthresh) | 1726 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1727 1728 RL_INC(sc->rl_cdata.cur_tx); 1729 1730 /* Set a timeout in case the chip goes out to lunch. */ 1731 sc->rl_watchdog_timer = 5; 1732 } 1733 1734 /* 1735 * We broke out of the loop because all our TX slots are 1736 * full. Mark the NIC as busy until it drains some of the 1737 * packets from the queue. 1738 */ 1739 if (RL_CUR_TXMBUF(sc) != NULL) 1740 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1741} 1742 1743static void 1744rl_init(void *xsc) 1745{ 1746 struct rl_softc *sc = xsc; 1747 1748 RL_LOCK(sc); 1749 rl_init_locked(sc); 1750 RL_UNLOCK(sc); 1751} 1752 1753static void 1754rl_init_locked(struct rl_softc *sc) 1755{ 1756 struct ifnet *ifp = sc->rl_ifp; 1757 struct mii_data *mii; 1758 uint32_t rxcfg = 0; 1759 uint32_t eaddr[2]; 1760 1761 RL_LOCK_ASSERT(sc); 1762 1763 mii = device_get_softc(sc->rl_miibus); 1764 1765 /* 1766 * Cancel pending I/O and free all RX/TX buffers. 1767 */ 1768 rl_stop(sc); 1769 1770 rl_reset(sc); 1771#ifdef RL_TWISTER_ENABLE 1772 /* 1773 * Reset twister register tuning state. The twister registers 1774 * and their tuning are undocumented, but are necessary to cope 1775 * with bad links. rl_twister = DONE here will disable this entirely. 1776 */ 1777 sc->rl_twister = CHK_LINK; 1778#endif 1779 1780 /* 1781 * Init our MAC address. Even though the chipset 1782 * documentation doesn't mention it, we need to enter "Config 1783 * register write enable" mode to modify the ID registers. 1784 */ 1785 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1786 bzero(eaddr, sizeof(eaddr)); 1787 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN); 1788 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]); 1789 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]); 1790 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1791 1792 /* Init the RX memory block pointer register. */ 1793 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr + 1794 RL_RX_8139_BUF_RESERVE); 1795 /* Init TX descriptors. */ 1796 rl_list_tx_init(sc); 1797 /* Init Rx memory block. */ 1798 rl_list_rx_init(sc); 1799 1800 /* 1801 * Enable transmit and receive. 1802 */ 1803 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1804 1805 /* 1806 * Set the initial TX and RX configuration. 1807 */ 1808 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1809 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1810 1811 /* Set the individual bit to receive frames for this host only. */ 1812 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1813 rxcfg |= RL_RXCFG_RX_INDIV; 1814 1815 /* If we want promiscuous mode, set the allframes bit. */ 1816 if (ifp->if_flags & IFF_PROMISC) { 1817 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1818 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1819 } else { 1820 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1821 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1822 } 1823 1824 /* Set capture broadcast bit to capture broadcast frames. */ 1825 if (ifp->if_flags & IFF_BROADCAST) { 1826 rxcfg |= RL_RXCFG_RX_BROAD; 1827 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1828 } else { 1829 rxcfg &= ~RL_RXCFG_RX_BROAD; 1830 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1831 } 1832 1833 /* Program the multicast filter, if necessary. */ 1834 rl_setmulti(sc); 1835 1836#ifdef DEVICE_POLLING 1837 /* Disable interrupts if we are polling. */ 1838 if (ifp->if_capenable & IFCAP_POLLING) 1839 CSR_WRITE_2(sc, RL_IMR, 0); 1840 else 1841#endif 1842 /* Enable interrupts. */ 1843 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1844 1845 /* Set initial TX threshold */ 1846 sc->rl_txthresh = RL_TX_THRESH_INIT; 1847 1848 /* Start RX/TX process. */ 1849 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1850 1851 /* Enable receiver and transmitter. */ 1852 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1853 1854 sc->rl_flags &= ~RL_FLAG_LINK; 1855 mii_mediachg(mii); 1856 1857 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1858 1859 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1860 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1861 1862 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1863} 1864 1865/* 1866 * Set media options. 1867 */ 1868static int 1869rl_ifmedia_upd(struct ifnet *ifp) 1870{ 1871 struct rl_softc *sc = ifp->if_softc; 1872 struct mii_data *mii; 1873 1874 mii = device_get_softc(sc->rl_miibus); 1875 1876 RL_LOCK(sc); 1877 mii_mediachg(mii); 1878 RL_UNLOCK(sc); 1879 1880 return (0); 1881} 1882 1883/* 1884 * Report current media status. 1885 */ 1886static void 1887rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1888{ 1889 struct rl_softc *sc = ifp->if_softc; 1890 struct mii_data *mii; 1891 1892 mii = device_get_softc(sc->rl_miibus); 1893 1894 RL_LOCK(sc); 1895 mii_pollstat(mii); 1896 RL_UNLOCK(sc); 1897 ifmr->ifm_active = mii->mii_media_active; 1898 ifmr->ifm_status = mii->mii_media_status; 1899} 1900 1901static int 1902rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1903{ 1904 struct ifreq *ifr = (struct ifreq *)data; 1905 struct mii_data *mii; 1906 struct rl_softc *sc = ifp->if_softc; 1907 int error = 0; 1908 1909 switch (command) { 1910 case SIOCSIFFLAGS: 1911 RL_LOCK(sc); 1912 if (ifp->if_flags & IFF_UP) { 1913 rl_init_locked(sc); 1914 } else { 1915 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1916 rl_stop(sc); 1917 } 1918 RL_UNLOCK(sc); 1919 error = 0; 1920 break; 1921 case SIOCADDMULTI: 1922 case SIOCDELMULTI: 1923 RL_LOCK(sc); 1924 rl_setmulti(sc); 1925 RL_UNLOCK(sc); 1926 error = 0; 1927 break; 1928 case SIOCGIFMEDIA: 1929 case SIOCSIFMEDIA: 1930 mii = device_get_softc(sc->rl_miibus); 1931 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1932 break; 1933 case SIOCSIFCAP: 1934#ifdef DEVICE_POLLING 1935 if (ifr->ifr_reqcap & IFCAP_POLLING && 1936 !(ifp->if_capenable & IFCAP_POLLING)) { 1937 error = ether_poll_register(rl_poll, ifp); 1938 if (error) 1939 return(error); 1940 RL_LOCK(sc); 1941 /* Disable interrupts */ 1942 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1943 ifp->if_capenable |= IFCAP_POLLING; 1944 RL_UNLOCK(sc); 1945 return (error); 1946 1947 } 1948 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1949 ifp->if_capenable & IFCAP_POLLING) { 1950 error = ether_poll_deregister(ifp); 1951 /* Enable interrupts. */ 1952 RL_LOCK(sc); 1953 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1954 ifp->if_capenable &= ~IFCAP_POLLING; 1955 RL_UNLOCK(sc); 1956 return (error); 1957 } 1958#endif /* DEVICE_POLLING */ 1959 break; 1960 default: 1961 error = ether_ioctl(ifp, command, data); 1962 break; 1963 } 1964 1965 return (error); 1966} 1967 1968static void 1969rl_watchdog(struct rl_softc *sc) 1970{ 1971 1972 RL_LOCK_ASSERT(sc); 1973 1974 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0) 1975 return; 1976 1977 device_printf(sc->rl_dev, "watchdog timeout\n"); 1978 sc->rl_ifp->if_oerrors++; 1979 1980 rl_txeof(sc); 1981 rl_rxeof(sc); 1982 rl_init_locked(sc); 1983} 1984 1985/* 1986 * Stop the adapter and free any mbufs allocated to the 1987 * RX and TX lists. 1988 */ 1989static void 1990rl_stop(struct rl_softc *sc) 1991{ 1992 register int i; 1993 struct ifnet *ifp = sc->rl_ifp; 1994 1995 RL_LOCK_ASSERT(sc); 1996 1997 sc->rl_watchdog_timer = 0; 1998 callout_stop(&sc->rl_stat_callout); 1999 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2000 sc->rl_flags &= ~RL_FLAG_LINK; 2001 2002 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2003 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2004 for (i = 0; i < RL_TIMEOUT; i++) { 2005 DELAY(10); 2006 if ((CSR_READ_1(sc, RL_COMMAND) & 2007 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0) 2008 break; 2009 } 2010 if (i == RL_TIMEOUT) 2011 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n"); 2012 2013 /* 2014 * Free the TX list buffers. 2015 */ 2016 for (i = 0; i < RL_TX_LIST_CNT; i++) { 2017 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 2018 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 2019 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, 2020 sc->rl_cdata.rl_tx_dmamap[i], 2021 BUS_DMASYNC_POSTWRITE); 2022 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 2023 sc->rl_cdata.rl_tx_dmamap[i]); 2024 m_freem(sc->rl_cdata.rl_tx_chain[i]); 2025 sc->rl_cdata.rl_tx_chain[i] = NULL; 2026 } 2027 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 2028 0x0000000); 2029 } 2030 } 2031} 2032 2033/* 2034 * Device suspend routine. Stop the interface and save some PCI 2035 * settings in case the BIOS doesn't restore them properly on 2036 * resume. 2037 */ 2038static int 2039rl_suspend(device_t dev) 2040{ 2041 struct rl_softc *sc; 2042 2043 sc = device_get_softc(dev); 2044 2045 RL_LOCK(sc); 2046 rl_stop(sc); 2047 sc->suspended = 1; 2048 RL_UNLOCK(sc); 2049 2050 return (0); 2051} 2052 2053/* 2054 * Device resume routine. Restore some PCI settings in case the BIOS 2055 * doesn't, re-enable busmastering, and restart the interface if 2056 * appropriate. 2057 */ 2058static int 2059rl_resume(device_t dev) 2060{ 2061 struct rl_softc *sc; 2062 struct ifnet *ifp; 2063 2064 sc = device_get_softc(dev); 2065 ifp = sc->rl_ifp; 2066 2067 RL_LOCK(sc); 2068 2069 /* reinitialize interface if necessary */ 2070 if (ifp->if_flags & IFF_UP) 2071 rl_init_locked(sc); 2072 2073 sc->suspended = 0; 2074 2075 RL_UNLOCK(sc); 2076 2077 return (0); 2078} 2079 2080/* 2081 * Stop all chip I/O so that the kernel's probe routines don't 2082 * get confused by errant DMAs when rebooting. 2083 */ 2084static int 2085rl_shutdown(device_t dev) 2086{ 2087 struct rl_softc *sc; 2088 2089 sc = device_get_softc(dev); 2090 2091 RL_LOCK(sc); 2092 rl_stop(sc); 2093 RL_UNLOCK(sc); 2094 2095 return (0); 2096} 2097