if_rl.c revision 111381
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8129/8139 PCI NIC driver 35 * 36 * Supports several extremely cheap PCI 10/100 adapters based on 37 * the RealTek chipset. Datasheets can be obtained from 38 * www.realtek.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 47 * probably the worst PCI ethernet controller ever made, with the possible 48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 49 * DMA, but it has a terrible interface that nullifies any performance 50 * gains that bus-master DMA usually offers. 51 * 52 * For transmission, the chip offers a series of four TX descriptor 53 * registers. Each transmit frame must be in a contiguous buffer, aligned 54 * on a longword (32-bit) boundary. This means we almost always have to 55 * do mbuf copies in order to transmit a frame, except in the unlikely 56 * case where a) the packet fits into a single mbuf, and b) the packet 57 * is 32-bit aligned within the mbuf's data area. The presence of only 58 * four descriptor registers means that we can never have more than four 59 * packets queued for transmission at any one time. 60 * 61 * Reception is not much better. The driver has to allocate a single large 62 * buffer area (up to 64K in size) into which the chip will DMA received 63 * frames. Because we don't know where within this region received packets 64 * will begin or end, we have no choice but to copy data from the buffer 65 * area into mbufs in order to pass the packets up to the higher protocol 66 * levels. 67 * 68 * It's impossible given this rotten design to really achieve decent 69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 70 * some equally overmuscled CPU to drive it. 71 * 72 * On the bright side, the 8139 does have a built-in PHY, although 73 * rather than using an MDIO serial interface like most other NICs, the 74 * PHY registers are directly accessible through the 8139's register 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 */ 83 84#include <sys/param.h> 85#include <sys/endian.h> 86#include <sys/systm.h> 87#include <sys/sockio.h> 88#include <sys/mbuf.h> 89#include <sys/malloc.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98 99#include <net/bpf.h> 100 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111#include <pci/pcireg.h> 112#include <pci/pcivar.h> 113 114MODULE_DEPEND(rl, miibus, 1, 1, 1); 115 116/* "controller miibus0" required. See GENERIC if you get errors here. */ 117#include "miibus_if.h" 118 119/* 120 * Default to using PIO access for this driver. On SMP systems, 121 * there appear to be problems with memory mapped mode: it looks like 122 * doing too many memory mapped access back to back in rapid succession 123 * can hang the bus. I'm inclined to blame this on crummy design/construction 124 * on the part of RealTek. Memory mapped mode does appear to work on 125 * uniprocessor systems though. 126 */ 127#define RL_USEIOSPACE 128 129#include <pci/if_rlreg.h> 130 131__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 111381 2003-02-23 23:35:35Z dan $"); 132 133/* 134 * Various supported device vendors/types and their names. 135 */ 136static struct rl_type rl_devs[] = { 137 { RT_VENDORID, RT_DEVICEID_8129, 138 "RealTek 8129 10/100BaseTX" }, 139 { RT_VENDORID, RT_DEVICEID_8139, 140 "RealTek 8139 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8138, 142 "RealTek 8139 10/100BaseTX CardBus" }, 143 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 144 "Accton MPX 5030/5038 10/100BaseTX" }, 145 { DELTA_VENDORID, DELTA_DEVICEID_8139, 146 "Delta Electronics 8139 10/100BaseTX" }, 147 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 148 "Addtron Technolgy 8139 10/100BaseTX" }, 149 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 150 "D-Link DFE-530TX+ 10/100BaseTX" }, 151 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 152 "D-Link DFE-690TXD 10/100BaseTX" }, 153 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 154 "Nortel Networks 10/100BaseTX" }, 155 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 156 "Corega FEther CB-TXD" }, 157 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 158 "Corega FEtherII CB-TXD" }, 159 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 160 "Peppercon AG ROL-F" }, 161 { 0, 0, NULL } 162}; 163 164static int rl_probe (device_t); 165static int rl_attach (device_t); 166static int rl_detach (device_t); 167 168static int rl_encap (struct rl_softc *, struct mbuf * ); 169 170static void rl_rxeof (struct rl_softc *); 171static void rl_txeof (struct rl_softc *); 172static void rl_intr (void *); 173static void rl_tick (void *); 174static void rl_start (struct ifnet *); 175static int rl_ioctl (struct ifnet *, u_long, caddr_t); 176static void rl_init (void *); 177static void rl_stop (struct rl_softc *); 178static void rl_watchdog (struct ifnet *); 179static int rl_suspend (device_t); 180static int rl_resume (device_t); 181static void rl_shutdown (device_t); 182static int rl_ifmedia_upd (struct ifnet *); 183static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 184 185static void rl_eeprom_putbyte (struct rl_softc *, int); 186static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 187static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 188static void rl_mii_sync (struct rl_softc *); 189static void rl_mii_send (struct rl_softc *, u_int32_t, int); 190static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 191static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 192 193static int rl_miibus_readreg (device_t, int, int); 194static int rl_miibus_writereg (device_t, int, int, int); 195static void rl_miibus_statchg (device_t); 196 197static u_int8_t rl_calchash (caddr_t); 198static void rl_setmulti (struct rl_softc *); 199static void rl_reset (struct rl_softc *); 200static int rl_list_tx_init (struct rl_softc *); 201 202static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 203static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 204 205#ifdef RL_USEIOSPACE 206#define RL_RES SYS_RES_IOPORT 207#define RL_RID RL_PCI_LOIO 208#else 209#define RL_RES SYS_RES_MEMORY 210#define RL_RID RL_PCI_LOMEM 211#endif 212 213static device_method_t rl_methods[] = { 214 /* Device interface */ 215 DEVMETHOD(device_probe, rl_probe), 216 DEVMETHOD(device_attach, rl_attach), 217 DEVMETHOD(device_detach, rl_detach), 218 DEVMETHOD(device_suspend, rl_suspend), 219 DEVMETHOD(device_resume, rl_resume), 220 DEVMETHOD(device_shutdown, rl_shutdown), 221 222 /* bus interface */ 223 DEVMETHOD(bus_print_child, bus_generic_print_child), 224 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 225 226 /* MII interface */ 227 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 228 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 229 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 230 231 { 0, 0 } 232}; 233 234static driver_t rl_driver = { 235 "rl", 236 rl_methods, 237 sizeof(struct rl_softc) 238}; 239 240static devclass_t rl_devclass; 241 242DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 243DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 244DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 245 246#define EE_SET(x) \ 247 CSR_WRITE_1(sc, RL_EECMD, \ 248 CSR_READ_1(sc, RL_EECMD) | x) 249 250#define EE_CLR(x) \ 251 CSR_WRITE_1(sc, RL_EECMD, \ 252 CSR_READ_1(sc, RL_EECMD) & ~x) 253 254static void 255rl_dma_map_rxbuf(arg, segs, nseg, error) 256 void *arg; 257 bus_dma_segment_t *segs; 258 int nseg, error; 259{ 260 struct rl_softc *sc; 261 262 sc = arg; 263 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 264 265 return; 266} 267 268static void 269rl_dma_map_txbuf(arg, segs, nseg, error) 270 void *arg; 271 bus_dma_segment_t *segs; 272 int nseg, error; 273{ 274 struct rl_softc *sc; 275 276 sc = arg; 277 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 278 279 return; 280} 281 282/* 283 * Send a read command and address to the EEPROM, check for ACK. 284 */ 285static void 286rl_eeprom_putbyte(sc, addr) 287 struct rl_softc *sc; 288 int addr; 289{ 290 register int d, i; 291 292 d = addr | sc->rl_eecmd_read; 293 294 /* 295 * Feed in each bit and strobe the clock. 296 */ 297 for (i = 0x400; i; i >>= 1) { 298 if (d & i) { 299 EE_SET(RL_EE_DATAIN); 300 } else { 301 EE_CLR(RL_EE_DATAIN); 302 } 303 DELAY(100); 304 EE_SET(RL_EE_CLK); 305 DELAY(150); 306 EE_CLR(RL_EE_CLK); 307 DELAY(100); 308 } 309 310 return; 311} 312 313/* 314 * Read a word of data stored in the EEPROM at address 'addr.' 315 */ 316static void 317rl_eeprom_getword(sc, addr, dest) 318 struct rl_softc *sc; 319 int addr; 320 u_int16_t *dest; 321{ 322 register int i; 323 u_int16_t word = 0; 324 325 /* Enter EEPROM access mode. */ 326 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 327 328 /* 329 * Send address of word we want to read. 330 */ 331 rl_eeprom_putbyte(sc, addr); 332 333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 334 335 /* 336 * Start reading bits from EEPROM. 337 */ 338 for (i = 0x8000; i; i >>= 1) { 339 EE_SET(RL_EE_CLK); 340 DELAY(100); 341 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 342 word |= i; 343 EE_CLR(RL_EE_CLK); 344 DELAY(100); 345 } 346 347 /* Turn off EEPROM access mode. */ 348 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 349 350 *dest = word; 351 352 return; 353} 354 355/* 356 * Read a sequence of words from the EEPROM. 357 */ 358static void 359rl_read_eeprom(sc, dest, off, cnt, swap) 360 struct rl_softc *sc; 361 caddr_t dest; 362 int off; 363 int cnt; 364 int swap; 365{ 366 int i; 367 u_int16_t word = 0, *ptr; 368 369 for (i = 0; i < cnt; i++) { 370 rl_eeprom_getword(sc, off + i, &word); 371 ptr = (u_int16_t *)(dest + (i * 2)); 372 if (swap) 373 *ptr = ntohs(word); 374 else 375 *ptr = word; 376 } 377 378 return; 379} 380 381 382/* 383 * MII access routines are provided for the 8129, which 384 * doesn't have a built-in PHY. For the 8139, we fake things 385 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 386 * direct access PHY registers. 387 */ 388#define MII_SET(x) \ 389 CSR_WRITE_1(sc, RL_MII, \ 390 CSR_READ_1(sc, RL_MII) | (x)) 391 392#define MII_CLR(x) \ 393 CSR_WRITE_1(sc, RL_MII, \ 394 CSR_READ_1(sc, RL_MII) & ~(x)) 395 396/* 397 * Sync the PHYs by setting data bit and strobing the clock 32 times. 398 */ 399static void 400rl_mii_sync(sc) 401 struct rl_softc *sc; 402{ 403 register int i; 404 405 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 406 407 for (i = 0; i < 32; i++) { 408 MII_SET(RL_MII_CLK); 409 DELAY(1); 410 MII_CLR(RL_MII_CLK); 411 DELAY(1); 412 } 413 414 return; 415} 416 417/* 418 * Clock a series of bits through the MII. 419 */ 420static void 421rl_mii_send(sc, bits, cnt) 422 struct rl_softc *sc; 423 u_int32_t bits; 424 int cnt; 425{ 426 int i; 427 428 MII_CLR(RL_MII_CLK); 429 430 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 431 if (bits & i) { 432 MII_SET(RL_MII_DATAOUT); 433 } else { 434 MII_CLR(RL_MII_DATAOUT); 435 } 436 DELAY(1); 437 MII_CLR(RL_MII_CLK); 438 DELAY(1); 439 MII_SET(RL_MII_CLK); 440 } 441} 442 443/* 444 * Read an PHY register through the MII. 445 */ 446static int 447rl_mii_readreg(sc, frame) 448 struct rl_softc *sc; 449 struct rl_mii_frame *frame; 450 451{ 452 int i, ack; 453 454 RL_LOCK(sc); 455 456 /* 457 * Set up frame for RX. 458 */ 459 frame->mii_stdelim = RL_MII_STARTDELIM; 460 frame->mii_opcode = RL_MII_READOP; 461 frame->mii_turnaround = 0; 462 frame->mii_data = 0; 463 464 CSR_WRITE_2(sc, RL_MII, 0); 465 466 /* 467 * Turn on data xmit. 468 */ 469 MII_SET(RL_MII_DIR); 470 471 rl_mii_sync(sc); 472 473 /* 474 * Send command/address info. 475 */ 476 rl_mii_send(sc, frame->mii_stdelim, 2); 477 rl_mii_send(sc, frame->mii_opcode, 2); 478 rl_mii_send(sc, frame->mii_phyaddr, 5); 479 rl_mii_send(sc, frame->mii_regaddr, 5); 480 481 /* Idle bit */ 482 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 483 DELAY(1); 484 MII_SET(RL_MII_CLK); 485 DELAY(1); 486 487 /* Turn off xmit. */ 488 MII_CLR(RL_MII_DIR); 489 490 /* Check for ack */ 491 MII_CLR(RL_MII_CLK); 492 DELAY(1); 493 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 494 MII_SET(RL_MII_CLK); 495 DELAY(1); 496 497 /* 498 * Now try reading data bits. If the ack failed, we still 499 * need to clock through 16 cycles to keep the PHY(s) in sync. 500 */ 501 if (ack) { 502 for(i = 0; i < 16; i++) { 503 MII_CLR(RL_MII_CLK); 504 DELAY(1); 505 MII_SET(RL_MII_CLK); 506 DELAY(1); 507 } 508 goto fail; 509 } 510 511 for (i = 0x8000; i; i >>= 1) { 512 MII_CLR(RL_MII_CLK); 513 DELAY(1); 514 if (!ack) { 515 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 516 frame->mii_data |= i; 517 DELAY(1); 518 } 519 MII_SET(RL_MII_CLK); 520 DELAY(1); 521 } 522 523fail: 524 525 MII_CLR(RL_MII_CLK); 526 DELAY(1); 527 MII_SET(RL_MII_CLK); 528 DELAY(1); 529 530 RL_UNLOCK(sc); 531 532 if (ack) 533 return(1); 534 return(0); 535} 536 537/* 538 * Write to a PHY register through the MII. 539 */ 540static int 541rl_mii_writereg(sc, frame) 542 struct rl_softc *sc; 543 struct rl_mii_frame *frame; 544 545{ 546 RL_LOCK(sc); 547 548 /* 549 * Set up frame for TX. 550 */ 551 552 frame->mii_stdelim = RL_MII_STARTDELIM; 553 frame->mii_opcode = RL_MII_WRITEOP; 554 frame->mii_turnaround = RL_MII_TURNAROUND; 555 556 /* 557 * Turn on data output. 558 */ 559 MII_SET(RL_MII_DIR); 560 561 rl_mii_sync(sc); 562 563 rl_mii_send(sc, frame->mii_stdelim, 2); 564 rl_mii_send(sc, frame->mii_opcode, 2); 565 rl_mii_send(sc, frame->mii_phyaddr, 5); 566 rl_mii_send(sc, frame->mii_regaddr, 5); 567 rl_mii_send(sc, frame->mii_turnaround, 2); 568 rl_mii_send(sc, frame->mii_data, 16); 569 570 /* Idle bit. */ 571 MII_SET(RL_MII_CLK); 572 DELAY(1); 573 MII_CLR(RL_MII_CLK); 574 DELAY(1); 575 576 /* 577 * Turn off xmit. 578 */ 579 MII_CLR(RL_MII_DIR); 580 581 RL_UNLOCK(sc); 582 583 return(0); 584} 585 586static int 587rl_miibus_readreg(dev, phy, reg) 588 device_t dev; 589 int phy, reg; 590{ 591 struct rl_softc *sc; 592 struct rl_mii_frame frame; 593 u_int16_t rval = 0; 594 u_int16_t rl8139_reg = 0; 595 596 sc = device_get_softc(dev); 597 RL_LOCK(sc); 598 599 if (sc->rl_type == RL_8139) { 600 /* Pretend the internal PHY is only at address 0 */ 601 if (phy) { 602 RL_UNLOCK(sc); 603 return(0); 604 } 605 switch(reg) { 606 case MII_BMCR: 607 rl8139_reg = RL_BMCR; 608 break; 609 case MII_BMSR: 610 rl8139_reg = RL_BMSR; 611 break; 612 case MII_ANAR: 613 rl8139_reg = RL_ANAR; 614 break; 615 case MII_ANER: 616 rl8139_reg = RL_ANER; 617 break; 618 case MII_ANLPAR: 619 rl8139_reg = RL_LPAR; 620 break; 621 case MII_PHYIDR1: 622 case MII_PHYIDR2: 623 RL_UNLOCK(sc); 624 return(0); 625 break; 626 /* 627 * Allow the rlphy driver to read the media status 628 * register. If we have a link partner which does not 629 * support NWAY, this is the register which will tell 630 * us the results of parallel detection. 631 */ 632 case RL_MEDIASTAT: 633 rval = CSR_READ_1(sc, RL_MEDIASTAT); 634 RL_UNLOCK(sc); 635 return(rval); 636 break; 637 default: 638 printf("rl%d: bad phy register\n", sc->rl_unit); 639 RL_UNLOCK(sc); 640 return(0); 641 } 642 rval = CSR_READ_2(sc, rl8139_reg); 643 RL_UNLOCK(sc); 644 return(rval); 645 } 646 647 bzero((char *)&frame, sizeof(frame)); 648 649 frame.mii_phyaddr = phy; 650 frame.mii_regaddr = reg; 651 rl_mii_readreg(sc, &frame); 652 RL_UNLOCK(sc); 653 654 return(frame.mii_data); 655} 656 657static int 658rl_miibus_writereg(dev, phy, reg, data) 659 device_t dev; 660 int phy, reg, data; 661{ 662 struct rl_softc *sc; 663 struct rl_mii_frame frame; 664 u_int16_t rl8139_reg = 0; 665 666 sc = device_get_softc(dev); 667 RL_LOCK(sc); 668 669 if (sc->rl_type == RL_8139) { 670 /* Pretend the internal PHY is only at address 0 */ 671 if (phy) { 672 RL_UNLOCK(sc); 673 return(0); 674 } 675 switch(reg) { 676 case MII_BMCR: 677 rl8139_reg = RL_BMCR; 678 break; 679 case MII_BMSR: 680 rl8139_reg = RL_BMSR; 681 break; 682 case MII_ANAR: 683 rl8139_reg = RL_ANAR; 684 break; 685 case MII_ANER: 686 rl8139_reg = RL_ANER; 687 break; 688 case MII_ANLPAR: 689 rl8139_reg = RL_LPAR; 690 break; 691 case MII_PHYIDR1: 692 case MII_PHYIDR2: 693 RL_UNLOCK(sc); 694 return(0); 695 break; 696 default: 697 printf("rl%d: bad phy register\n", sc->rl_unit); 698 RL_UNLOCK(sc); 699 return(0); 700 } 701 CSR_WRITE_2(sc, rl8139_reg, data); 702 RL_UNLOCK(sc); 703 return(0); 704 } 705 706 bzero((char *)&frame, sizeof(frame)); 707 708 frame.mii_phyaddr = phy; 709 frame.mii_regaddr = reg; 710 frame.mii_data = data; 711 712 rl_mii_writereg(sc, &frame); 713 714 RL_UNLOCK(sc); 715 return(0); 716} 717 718static void 719rl_miibus_statchg(dev) 720 device_t dev; 721{ 722 return; 723} 724 725/* 726 * Calculate CRC of a multicast group address, return the upper 6 bits. 727 */ 728static u_int8_t 729rl_calchash(addr) 730 caddr_t addr; 731{ 732 u_int32_t crc, carry; 733 int i, j; 734 u_int8_t c; 735 736 /* Compute CRC for the address value. */ 737 crc = 0xFFFFFFFF; /* initial value */ 738 739 for (i = 0; i < 6; i++) { 740 c = *(addr + i); 741 for (j = 0; j < 8; j++) { 742 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 743 crc <<= 1; 744 c >>= 1; 745 if (carry) 746 crc = (crc ^ 0x04c11db6) | carry; 747 } 748 } 749 750 /* return the filter bit position */ 751 return(crc >> 26); 752} 753 754/* 755 * Program the 64-bit multicast hash filter. 756 */ 757static void 758rl_setmulti(sc) 759 struct rl_softc *sc; 760{ 761 struct ifnet *ifp; 762 int h = 0; 763 u_int32_t hashes[2] = { 0, 0 }; 764 struct ifmultiaddr *ifma; 765 u_int32_t rxfilt; 766 int mcnt = 0; 767 768 ifp = &sc->arpcom.ac_if; 769 770 rxfilt = CSR_READ_4(sc, RL_RXCFG); 771 772 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 773 rxfilt |= RL_RXCFG_RX_MULTI; 774 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 775 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 776 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 777 return; 778 } 779 780 /* first, zot all the existing hash bits */ 781 CSR_WRITE_4(sc, RL_MAR0, 0); 782 CSR_WRITE_4(sc, RL_MAR4, 0); 783 784 /* now program new ones */ 785 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 786 if (ifma->ifma_addr->sa_family != AF_LINK) 787 continue; 788 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 789 if (h < 32) 790 hashes[0] |= (1 << h); 791 else 792 hashes[1] |= (1 << (h - 32)); 793 mcnt++; 794 } 795 796 if (mcnt) 797 rxfilt |= RL_RXCFG_RX_MULTI; 798 else 799 rxfilt &= ~RL_RXCFG_RX_MULTI; 800 801 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 802 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 803 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 804 805 return; 806} 807 808static void 809rl_reset(sc) 810 struct rl_softc *sc; 811{ 812 register int i; 813 814 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 815 816 for (i = 0; i < RL_TIMEOUT; i++) { 817 DELAY(10); 818 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 819 break; 820 } 821 if (i == RL_TIMEOUT) 822 printf("rl%d: reset never completed!\n", sc->rl_unit); 823 824 return; 825} 826 827/* 828 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 829 * IDs against our list and return a device name if we find a match. 830 */ 831static int 832rl_probe(dev) 833 device_t dev; 834{ 835 struct rl_type *t; 836 837 t = rl_devs; 838 839 while(t->rl_name != NULL) { 840 if ((pci_get_vendor(dev) == t->rl_vid) && 841 (pci_get_device(dev) == t->rl_did)) { 842 device_set_desc(dev, t->rl_name); 843 return(0); 844 } 845 t++; 846 } 847 848 return(ENXIO); 849} 850 851/* 852 * Attach the interface. Allocate softc structures, do ifmedia 853 * setup and ethernet/BPF attach. 854 */ 855static int 856rl_attach(dev) 857 device_t dev; 858{ 859 u_char eaddr[ETHER_ADDR_LEN]; 860 u_int32_t command; 861 u_int16_t as[3]; 862 struct rl_softc *sc; 863 struct ifnet *ifp; 864 u_int16_t rl_did = 0; 865 int unit, error = 0, rid, i; 866 867 sc = device_get_softc(dev); 868 unit = device_get_unit(dev); 869 bzero(sc, sizeof(struct rl_softc)); 870 871 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 872 MTX_DEF | MTX_RECURSE); 873 874 /* 875 * Handle power management nonsense. 876 */ 877 878 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 879 u_int32_t iobase, membase, irq; 880 881 /* Save important PCI config data. */ 882 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 883 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 884 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 885 886 /* Reset the power state. */ 887 printf("rl%d: chip is is in D%d power mode " 888 "-- setting to D0\n", unit, 889 pci_get_powerstate(dev)); 890 891 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 892 893 /* Restore PCI config data. */ 894 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 895 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 896 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 897 } 898 899 /* 900 * Map control/status registers. 901 */ 902 pci_enable_busmaster(dev); 903 pci_enable_io(dev, SYS_RES_IOPORT); 904 pci_enable_io(dev, SYS_RES_MEMORY); 905 command = pci_read_config(dev, PCIR_COMMAND, 4); 906 907#ifdef RL_USEIOSPACE 908 if (!(command & PCIM_CMD_PORTEN)) { 909 printf("rl%d: failed to enable I/O ports!\n", unit); 910 error = ENXIO; 911 goto fail; 912 } 913#else 914 if (!(command & PCIM_CMD_MEMEN)) { 915 printf("rl%d: failed to enable memory mapping!\n", unit); 916 error = ENXIO; 917 goto fail; 918 } 919#endif 920 921 rid = RL_RID; 922 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 923 0, ~0, 1, RF_ACTIVE); 924 925 if (sc->rl_res == NULL) { 926 printf ("rl%d: couldn't map ports/memory\n", unit); 927 error = ENXIO; 928 goto fail; 929 } 930 931 /* Detect the Realtek 8139B. For some reason, this chip is very 932 * unstable when left to autoselect the media 933 * The best workaround is to set the device to the required 934 * media type or to set it to the 10 Meg speed. 935 */ 936 937 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 938 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 939 } 940 941 sc->rl_btag = rman_get_bustag(sc->rl_res); 942 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 943 944 rid = 0; 945 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 946 RF_SHAREABLE | RF_ACTIVE); 947 948 if (sc->rl_irq == NULL) { 949 printf("rl%d: couldn't map interrupt\n", unit); 950 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 951 error = ENXIO; 952 goto fail; 953 } 954 955 /* Reset the adapter. */ 956 rl_reset(sc); 957 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 958 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 959 if (rl_did != 0x8129) 960 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 961 962 /* 963 * Get station address from the EEPROM. 964 */ 965 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 966 for (i = 0; i < 3; i++) { 967 eaddr[(i * 2) + 0] = as[i] & 0xff; 968 eaddr[(i * 2) + 1] = as[i] >> 8; 969 } 970 971 /* 972 * A RealTek chip was detected. Inform the world. 973 */ 974 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 975 976 sc->rl_unit = unit; 977 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 978 979 /* 980 * Now read the exact device type from the EEPROM to find 981 * out if it's an 8129 or 8139. 982 */ 983 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 984 985 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 986 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 987 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 988 rl_did == DLINK_DEVICEID_690TXD || 989 rl_did == COREGA_DEVICEID_FETHERCBTXD || 990 rl_did == COREGA_DEVICEID_FETHERIICBTXD) 991 sc->rl_type = RL_8139; 992 else if (rl_did == RT_DEVICEID_8129) 993 sc->rl_type = RL_8129; 994 else { 995 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 996 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 997 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 998 error = ENXIO; 999 goto fail; 1000 } 1001 1002 /* 1003 * Allocate the parent bus DMA tag appropriate for PCI. 1004 */ 1005#define RL_NSEG_NEW 32 1006 error = bus_dma_tag_create(NULL, /* parent */ 1007 1, 0, /* alignment, boundary */ 1008 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1009 BUS_SPACE_MAXADDR, /* highaddr */ 1010 NULL, NULL, /* filter, filterarg */ 1011 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1012 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1013 BUS_DMA_ALLOCNOW, /* flags */ 1014 &sc->rl_parent_tag); 1015 1016 /* 1017 * Now allocate a tag for the DMA descriptor lists. 1018 * All of our lists are allocated as a contiguous block 1019 * of memory. 1020 */ 1021 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1022 1, 0, /* alignment, boundary */ 1023 BUS_SPACE_MAXADDR, /* lowaddr */ 1024 BUS_SPACE_MAXADDR, /* highaddr */ 1025 NULL, NULL, /* filter, filterarg */ 1026 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1027 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1028 0, /* flags */ 1029 &sc->rl_tag); 1030 1031 /* 1032 * Now allocate a chunk of DMA-able memory based on the 1033 * tag we just created. 1034 */ 1035 error = bus_dmamem_alloc(sc->rl_tag, 1036 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1037 &sc->rl_cdata.rl_rx_dmamap); 1038 1039 if (sc->rl_cdata.rl_rx_buf == NULL) { 1040 printf("rl%d: no memory for list buffers!\n", unit); 1041 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1042 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1043 bus_dma_tag_destroy(sc->rl_tag); 1044 error = ENXIO; 1045 goto fail; 1046 } 1047 1048 /* Leave a few bytes before the start of the RX ring buffer. */ 1049 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1050 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1051 1052 /* Do MII setup */ 1053 if (mii_phy_probe(dev, &sc->rl_miibus, 1054 rl_ifmedia_upd, rl_ifmedia_sts)) { 1055 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1056 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1057 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1058 bus_dmamem_free(sc->rl_tag, 1059 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1060 bus_dma_tag_destroy(sc->rl_tag); 1061 error = ENXIO; 1062 goto fail; 1063 } 1064 1065 ifp = &sc->arpcom.ac_if; 1066 ifp->if_softc = sc; 1067 ifp->if_unit = unit; 1068 ifp->if_name = "rl"; 1069 ifp->if_mtu = ETHERMTU; 1070 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1071 ifp->if_ioctl = rl_ioctl; 1072 ifp->if_output = ether_output; 1073 ifp->if_start = rl_start; 1074 ifp->if_watchdog = rl_watchdog; 1075 ifp->if_init = rl_init; 1076 ifp->if_baudrate = 10000000; 1077 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1078 1079 /* 1080 * Call MI attach routine. 1081 */ 1082 ether_ifattach(ifp, eaddr); 1083 1084 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1085 rl_intr, sc, &sc->rl_intrhand); 1086 1087 if (error) { 1088 printf("rl%d: couldn't set up irq\n", unit); 1089 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1090 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1091 bus_dmamem_free(sc->rl_tag, 1092 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1093 bus_dma_tag_destroy(sc->rl_tag); 1094 goto fail; 1095 } 1096 1097 callout_handle_init(&sc->rl_stat_ch); 1098fail: 1099 if (error != 0) 1100 mtx_destroy(&sc->rl_mtx); 1101 return (error); 1102} 1103 1104static int 1105rl_detach(dev) 1106 device_t dev; 1107{ 1108 struct rl_softc *sc; 1109 struct ifnet *ifp; 1110 1111 sc = device_get_softc(dev); 1112 RL_LOCK(sc); 1113 ifp = &sc->arpcom.ac_if; 1114 1115 ether_ifdetach(ifp); 1116 rl_stop(sc); 1117 1118 bus_generic_detach(dev); 1119 device_delete_child(dev, sc->rl_miibus); 1120 1121 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1122 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1123 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1124 1125 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1126 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1127 sc->rl_cdata.rl_rx_dmamap); 1128 bus_dma_tag_destroy(sc->rl_tag); 1129 bus_dma_tag_destroy(sc->rl_parent_tag); 1130 1131 RL_UNLOCK(sc); 1132 mtx_destroy(&sc->rl_mtx); 1133 1134 return(0); 1135} 1136 1137/* 1138 * Initialize the transmit descriptors. 1139 */ 1140static int 1141rl_list_tx_init(sc) 1142 struct rl_softc *sc; 1143{ 1144 struct rl_chain_data *cd; 1145 int i; 1146 1147 cd = &sc->rl_cdata; 1148 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1149 cd->rl_tx_chain[i] = NULL; 1150 CSR_WRITE_4(sc, 1151 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1152 } 1153 1154 sc->rl_cdata.cur_tx = 0; 1155 sc->rl_cdata.last_tx = 0; 1156 1157 return(0); 1158} 1159 1160/* 1161 * A frame has been uploaded: pass the resulting mbuf chain up to 1162 * the higher level protocols. 1163 * 1164 * You know there's something wrong with a PCI bus-master chip design 1165 * when you have to use m_devget(). 1166 * 1167 * The receive operation is badly documented in the datasheet, so I'll 1168 * attempt to document it here. The driver provides a buffer area and 1169 * places its base address in the RX buffer start address register. 1170 * The chip then begins copying frames into the RX buffer. Each frame 1171 * is preceded by a 32-bit RX status word which specifies the length 1172 * of the frame and certain other status bits. Each frame (starting with 1173 * the status word) is also 32-bit aligned. The frame length is in the 1174 * first 16 bits of the status word; the lower 15 bits correspond with 1175 * the 'rx status register' mentioned in the datasheet. 1176 * 1177 * Note: to make the Alpha happy, the frame payload needs to be aligned 1178 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1179 * as the offset argument to m_devget(). 1180 */ 1181static void 1182rl_rxeof(sc) 1183 struct rl_softc *sc; 1184{ 1185 struct mbuf *m; 1186 struct ifnet *ifp; 1187 int total_len = 0; 1188 u_int32_t rxstat; 1189 caddr_t rxbufpos; 1190 int wrap = 0; 1191 u_int16_t cur_rx; 1192 u_int16_t limit; 1193 u_int16_t rx_bytes = 0, max_bytes; 1194 1195 ifp = &sc->arpcom.ac_if; 1196 1197 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1198 BUS_DMASYNC_POSTREAD); 1199 1200 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1201 1202 /* Do not try to read past this point. */ 1203 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1204 1205 if (limit < cur_rx) 1206 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1207 else 1208 max_bytes = limit - cur_rx; 1209 1210 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1211#ifdef DEVICE_POLLING 1212 if (ifp->if_flags & IFF_POLLING) { 1213 if (sc->rxcycles <= 0) 1214 break; 1215 sc->rxcycles--; 1216 } 1217#endif /* DEVICE_POLLING */ 1218 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1219 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1220 1221 /* 1222 * Here's a totally undocumented fact for you. When the 1223 * RealTek chip is in the process of copying a packet into 1224 * RAM for you, the length will be 0xfff0. If you spot a 1225 * packet header with this value, you need to stop. The 1226 * datasheet makes absolutely no mention of this and 1227 * RealTek should be shot for this. 1228 */ 1229 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1230 break; 1231 1232 if (!(rxstat & RL_RXSTAT_RXOK)) { 1233 ifp->if_ierrors++; 1234 rl_init(sc); 1235 return; 1236 } 1237 1238 /* No errors; receive the packet. */ 1239 total_len = rxstat >> 16; 1240 rx_bytes += total_len + 4; 1241 1242 /* 1243 * XXX The RealTek chip includes the CRC with every 1244 * received frame, and there's no way to turn this 1245 * behavior off (at least, I can't find anything in 1246 * the manual that explains how to do it) so we have 1247 * to trim off the CRC manually. 1248 */ 1249 total_len -= ETHER_CRC_LEN; 1250 1251 /* 1252 * Avoid trying to read more bytes than we know 1253 * the chip has prepared for us. 1254 */ 1255 if (rx_bytes > max_bytes) 1256 break; 1257 1258 rxbufpos = sc->rl_cdata.rl_rx_buf + 1259 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1260 1261 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1262 rxbufpos = sc->rl_cdata.rl_rx_buf; 1263 1264 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1265 1266 if (total_len > wrap) { 1267 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1268 NULL); 1269 if (m == NULL) { 1270 ifp->if_ierrors++; 1271 } else { 1272 m_copyback(m, wrap, total_len - wrap, 1273 sc->rl_cdata.rl_rx_buf); 1274 } 1275 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1276 } else { 1277 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1278 NULL); 1279 if (m == NULL) { 1280 ifp->if_ierrors++; 1281 } 1282 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1283 } 1284 1285 /* 1286 * Round up to 32-bit boundary. 1287 */ 1288 cur_rx = (cur_rx + 3) & ~3; 1289 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1290 1291 if (m == NULL) 1292 continue; 1293 1294 ifp->if_ipackets++; 1295 (*ifp->if_input)(ifp, m); 1296 } 1297 1298 return; 1299} 1300 1301/* 1302 * A frame was downloaded to the chip. It's safe for us to clean up 1303 * the list buffers. 1304 */ 1305static void 1306rl_txeof(sc) 1307 struct rl_softc *sc; 1308{ 1309 struct ifnet *ifp; 1310 u_int32_t txstat; 1311 1312 ifp = &sc->arpcom.ac_if; 1313 1314 /* 1315 * Go through our tx list and free mbufs for those 1316 * frames that have been uploaded. 1317 */ 1318 do { 1319 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1320 if (!(txstat & (RL_TXSTAT_TX_OK| 1321 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1322 break; 1323 1324 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1325 1326 if (RL_LAST_TXMBUF(sc) != NULL) { 1327 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1328 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1329 m_freem(RL_LAST_TXMBUF(sc)); 1330 RL_LAST_TXMBUF(sc) = NULL; 1331 } 1332 if (txstat & RL_TXSTAT_TX_OK) 1333 ifp->if_opackets++; 1334 else { 1335 int oldthresh; 1336 ifp->if_oerrors++; 1337 if ((txstat & RL_TXSTAT_TXABRT) || 1338 (txstat & RL_TXSTAT_OUTOFWIN)) 1339 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1340 oldthresh = sc->rl_txthresh; 1341 /* error recovery */ 1342 rl_reset(sc); 1343 rl_init(sc); 1344 /* 1345 * If there was a transmit underrun, 1346 * bump the TX threshold. 1347 */ 1348 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1349 sc->rl_txthresh = oldthresh + 32; 1350 return; 1351 } 1352 RL_INC(sc->rl_cdata.last_tx); 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1355 1356 ifp->if_timer = 1357 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1358 1359 return; 1360} 1361 1362static void 1363rl_tick(xsc) 1364 void *xsc; 1365{ 1366 struct rl_softc *sc; 1367 struct mii_data *mii; 1368 1369 sc = xsc; 1370 RL_LOCK(sc); 1371 mii = device_get_softc(sc->rl_miibus); 1372 1373 mii_tick(mii); 1374 1375 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1376 RL_UNLOCK(sc); 1377 1378 return; 1379} 1380 1381#ifdef DEVICE_POLLING 1382static void 1383rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1384{ 1385 struct rl_softc *sc = ifp->if_softc; 1386 1387 RL_LOCK(sc); 1388 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1389 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1390 goto done; 1391 } 1392 1393 sc->rxcycles = count; 1394 rl_rxeof(sc); 1395 rl_txeof(sc); 1396 if (ifp->if_snd.ifq_head != NULL) 1397 rl_start(ifp); 1398 1399 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1400 u_int16_t status; 1401 1402 status = CSR_READ_2(sc, RL_ISR); 1403 if (status == 0xffff) 1404 goto done; 1405 if (status) 1406 CSR_WRITE_2(sc, RL_ISR, status); 1407 1408 /* 1409 * XXX check behaviour on receiver stalls. 1410 */ 1411 1412 if (status & RL_ISR_SYSTEM_ERR) { 1413 rl_reset(sc); 1414 rl_init(sc); 1415 } 1416 } 1417done: 1418 RL_UNLOCK(sc); 1419} 1420#endif /* DEVICE_POLLING */ 1421 1422static void 1423rl_intr(arg) 1424 void *arg; 1425{ 1426 struct rl_softc *sc; 1427 struct ifnet *ifp; 1428 u_int16_t status; 1429 1430 sc = arg; 1431 1432 if (sc->suspended) { 1433 return; 1434 } 1435 1436 RL_LOCK(sc); 1437 ifp = &sc->arpcom.ac_if; 1438 1439#ifdef DEVICE_POLLING 1440 if (ifp->if_flags & IFF_POLLING) 1441 goto done; 1442 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1443 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1444 rl_poll(ifp, 0, 1); 1445 goto done; 1446 } 1447#endif /* DEVICE_POLLING */ 1448 1449 for (;;) { 1450 1451 status = CSR_READ_2(sc, RL_ISR); 1452 /* If the card has gone away the read returns 0xffff. */ 1453 if (status == 0xffff) 1454 break; 1455 if (status) 1456 CSR_WRITE_2(sc, RL_ISR, status); 1457 1458 if ((status & RL_INTRS) == 0) 1459 break; 1460 1461 if (status & RL_ISR_RX_OK) 1462 rl_rxeof(sc); 1463 1464 if (status & RL_ISR_RX_ERR) 1465 rl_rxeof(sc); 1466 1467 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1468 rl_txeof(sc); 1469 1470 if (status & RL_ISR_SYSTEM_ERR) { 1471 rl_reset(sc); 1472 rl_init(sc); 1473 } 1474 1475 } 1476 1477 if (ifp->if_snd.ifq_head != NULL) 1478 rl_start(ifp); 1479 1480#ifdef DEVICE_POLLING 1481done: 1482#endif 1483 RL_UNLOCK(sc); 1484 1485 return; 1486} 1487 1488/* 1489 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1490 * pointers to the fragment pointers. 1491 */ 1492static int 1493rl_encap(sc, m_head) 1494 struct rl_softc *sc; 1495 struct mbuf *m_head; 1496{ 1497 struct mbuf *m_new = NULL; 1498 1499 /* 1500 * The RealTek is brain damaged and wants longword-aligned 1501 * TX buffers, plus we can only have one fragment buffer 1502 * per packet. We have to copy pretty much all the time. 1503 */ 1504 1505 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1506 if (m_new == NULL) 1507 return(1); 1508 if (m_head->m_pkthdr.len > MHLEN) { 1509 MCLGET(m_new, M_DONTWAIT); 1510 if (!(m_new->m_flags & M_EXT)) { 1511 m_freem(m_new); 1512 return(1); 1513 } 1514 } 1515 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1516 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1517 m_freem(m_head); 1518 m_head = m_new; 1519 1520 /* Pad frames to at least 60 bytes. */ 1521 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1522 /* 1523 * Make security concious people happy: zero out the 1524 * bytes in the pad area, since we don't know what 1525 * this mbuf cluster buffer's previous user might 1526 * have left in it. 1527 */ 1528 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1529 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1530 m_head->m_pkthdr.len += 1531 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1532 m_head->m_len = m_head->m_pkthdr.len; 1533 } 1534 1535 RL_CUR_TXMBUF(sc) = m_head; 1536 1537 return(0); 1538} 1539 1540/* 1541 * Main transmit routine. 1542 */ 1543 1544static void 1545rl_start(ifp) 1546 struct ifnet *ifp; 1547{ 1548 struct rl_softc *sc; 1549 struct mbuf *m_head = NULL; 1550 1551 sc = ifp->if_softc; 1552 RL_LOCK(sc); 1553 1554 while(RL_CUR_TXMBUF(sc) == NULL) { 1555 IF_DEQUEUE(&ifp->if_snd, m_head); 1556 if (m_head == NULL) 1557 break; 1558 1559 if (rl_encap(sc, m_head)) { 1560 IF_PREPEND(&ifp->if_snd, m_head); 1561 ifp->if_flags |= IFF_OACTIVE; 1562 break; 1563 } 1564 1565 /* 1566 * If there's a BPF listener, bounce a copy of this frame 1567 * to him. 1568 */ 1569 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1570 1571 /* 1572 * Transmit the frame. 1573 */ 1574 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1575 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1576 mtod(RL_CUR_TXMBUF(sc), void *), 1577 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1578 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1579 BUS_DMASYNC_PREREAD); 1580 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1581 RL_TXTHRESH(sc->rl_txthresh) | 1582 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1583 1584 RL_INC(sc->rl_cdata.cur_tx); 1585 } 1586 1587 /* 1588 * We broke out of the loop because all our TX slots are 1589 * full. Mark the NIC as busy until it drains some of the 1590 * packets from the queue. 1591 */ 1592 if (RL_CUR_TXMBUF(sc) != NULL) 1593 ifp->if_flags |= IFF_OACTIVE; 1594 1595 /* 1596 * Set a timeout in case the chip goes out to lunch. 1597 */ 1598 ifp->if_timer = 5; 1599 RL_UNLOCK(sc); 1600 1601 return; 1602} 1603 1604static void 1605rl_init(xsc) 1606 void *xsc; 1607{ 1608 struct rl_softc *sc = xsc; 1609 struct ifnet *ifp = &sc->arpcom.ac_if; 1610 struct mii_data *mii; 1611 int i; 1612 u_int32_t rxcfg = 0; 1613 1614 RL_LOCK(sc); 1615 mii = device_get_softc(sc->rl_miibus); 1616 1617 /* 1618 * Cancel pending I/O and free all RX/TX buffers. 1619 */ 1620 rl_stop(sc); 1621 1622 /* Init our MAC address */ 1623 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1624 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1625 } 1626 1627 /* Init the RX buffer pointer register. */ 1628 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1629 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1630 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1631 BUS_DMASYNC_PREWRITE); 1632 1633 /* Init TX descriptors. */ 1634 rl_list_tx_init(sc); 1635 1636 /* 1637 * Enable transmit and receive. 1638 */ 1639 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1640 1641 /* 1642 * Set the initial TX and RX configuration. 1643 */ 1644 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1645 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1646 1647 /* Set the individual bit to receive frames for this host only. */ 1648 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1649 rxcfg |= RL_RXCFG_RX_INDIV; 1650 1651 /* If we want promiscuous mode, set the allframes bit. */ 1652 if (ifp->if_flags & IFF_PROMISC) { 1653 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1654 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1655 } else { 1656 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1657 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1658 } 1659 1660 /* 1661 * Set capture broadcast bit to capture broadcast frames. 1662 */ 1663 if (ifp->if_flags & IFF_BROADCAST) { 1664 rxcfg |= RL_RXCFG_RX_BROAD; 1665 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1666 } else { 1667 rxcfg &= ~RL_RXCFG_RX_BROAD; 1668 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1669 } 1670 1671 /* 1672 * Program the multicast filter, if necessary. 1673 */ 1674 rl_setmulti(sc); 1675 1676#ifdef DEVICE_POLLING 1677 /* 1678 * Disable interrupts if we are polling. 1679 */ 1680 if (ifp->if_flags & IFF_POLLING) 1681 CSR_WRITE_2(sc, RL_IMR, 0); 1682 else /* otherwise ... */ 1683#endif /* DEVICE_POLLING */ 1684 /* 1685 * Enable interrupts. 1686 */ 1687 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1688 1689 /* Set initial TX threshold */ 1690 sc->rl_txthresh = RL_TX_THRESH_INIT; 1691 1692 /* Start RX/TX process. */ 1693 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1694 1695 /* Enable receiver and transmitter. */ 1696 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1697 1698 mii_mediachg(mii); 1699 1700 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1701 1702 ifp->if_flags |= IFF_RUNNING; 1703 ifp->if_flags &= ~IFF_OACTIVE; 1704 1705 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1706 RL_UNLOCK(sc); 1707 1708 return; 1709} 1710 1711/* 1712 * Set media options. 1713 */ 1714static int 1715rl_ifmedia_upd(ifp) 1716 struct ifnet *ifp; 1717{ 1718 struct rl_softc *sc; 1719 struct mii_data *mii; 1720 1721 sc = ifp->if_softc; 1722 mii = device_get_softc(sc->rl_miibus); 1723 mii_mediachg(mii); 1724 1725 return(0); 1726} 1727 1728/* 1729 * Report current media status. 1730 */ 1731static void 1732rl_ifmedia_sts(ifp, ifmr) 1733 struct ifnet *ifp; 1734 struct ifmediareq *ifmr; 1735{ 1736 struct rl_softc *sc; 1737 struct mii_data *mii; 1738 1739 sc = ifp->if_softc; 1740 mii = device_get_softc(sc->rl_miibus); 1741 1742 mii_pollstat(mii); 1743 ifmr->ifm_active = mii->mii_media_active; 1744 ifmr->ifm_status = mii->mii_media_status; 1745 1746 return; 1747} 1748 1749static int 1750rl_ioctl(ifp, command, data) 1751 struct ifnet *ifp; 1752 u_long command; 1753 caddr_t data; 1754{ 1755 struct rl_softc *sc = ifp->if_softc; 1756 struct ifreq *ifr = (struct ifreq *) data; 1757 struct mii_data *mii; 1758 int error = 0; 1759 1760 RL_LOCK(sc); 1761 1762 switch(command) { 1763 case SIOCSIFFLAGS: 1764 if (ifp->if_flags & IFF_UP) { 1765 rl_init(sc); 1766 } else { 1767 if (ifp->if_flags & IFF_RUNNING) 1768 rl_stop(sc); 1769 } 1770 error = 0; 1771 break; 1772 case SIOCADDMULTI: 1773 case SIOCDELMULTI: 1774 rl_setmulti(sc); 1775 error = 0; 1776 break; 1777 case SIOCGIFMEDIA: 1778 case SIOCSIFMEDIA: 1779 mii = device_get_softc(sc->rl_miibus); 1780 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1781 break; 1782 default: 1783 error = ether_ioctl(ifp, command, data); 1784 break; 1785 } 1786 1787 RL_UNLOCK(sc); 1788 1789 return(error); 1790} 1791 1792static void 1793rl_watchdog(ifp) 1794 struct ifnet *ifp; 1795{ 1796 struct rl_softc *sc; 1797 1798 sc = ifp->if_softc; 1799 RL_LOCK(sc); 1800 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1801 ifp->if_oerrors++; 1802 1803 rl_txeof(sc); 1804 rl_rxeof(sc); 1805 rl_init(sc); 1806 RL_UNLOCK(sc); 1807 1808 return; 1809} 1810 1811/* 1812 * Stop the adapter and free any mbufs allocated to the 1813 * RX and TX lists. 1814 */ 1815static void 1816rl_stop(sc) 1817 struct rl_softc *sc; 1818{ 1819 register int i; 1820 struct ifnet *ifp; 1821 1822 RL_LOCK(sc); 1823 ifp = &sc->arpcom.ac_if; 1824 ifp->if_timer = 0; 1825 1826 untimeout(rl_tick, sc, sc->rl_stat_ch); 1827 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1828#ifdef DEVICE_POLLING 1829 ether_poll_deregister(ifp); 1830#endif /* DEVICE_POLLING */ 1831 1832 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1833 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1834 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1835 1836 /* 1837 * Free the TX list buffers. 1838 */ 1839 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1840 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1841 bus_dmamap_unload(sc->rl_tag, 1842 sc->rl_cdata.rl_tx_dmamap[i]); 1843 bus_dmamap_destroy(sc->rl_tag, 1844 sc->rl_cdata.rl_tx_dmamap[i]); 1845 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1846 sc->rl_cdata.rl_tx_chain[i] = NULL; 1847 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1848 } 1849 } 1850 1851 RL_UNLOCK(sc); 1852 return; 1853} 1854 1855/* 1856 * Device suspend routine. Stop the interface and save some PCI 1857 * settings in case the BIOS doesn't restore them properly on 1858 * resume. 1859 */ 1860static int 1861rl_suspend(dev) 1862 device_t dev; 1863{ 1864 register int i; 1865 struct rl_softc *sc; 1866 1867 sc = device_get_softc(dev); 1868 1869 rl_stop(sc); 1870 1871 for (i = 0; i < 5; i++) 1872 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1873 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1874 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1875 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1876 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1877 1878 sc->suspended = 1; 1879 1880 return (0); 1881} 1882 1883/* 1884 * Device resume routine. Restore some PCI settings in case the BIOS 1885 * doesn't, re-enable busmastering, and restart the interface if 1886 * appropriate. 1887 */ 1888static int 1889rl_resume(dev) 1890 device_t dev; 1891{ 1892 register int i; 1893 struct rl_softc *sc; 1894 struct ifnet *ifp; 1895 1896 sc = device_get_softc(dev); 1897 ifp = &sc->arpcom.ac_if; 1898 1899 /* better way to do this? */ 1900 for (i = 0; i < 5; i++) 1901 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1902 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1903 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1904 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1905 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1906 1907 /* reenable busmastering */ 1908 pci_enable_busmaster(dev); 1909 pci_enable_io(dev, RL_RES); 1910 1911 /* reinitialize interface if necessary */ 1912 if (ifp->if_flags & IFF_UP) 1913 rl_init(sc); 1914 1915 sc->suspended = 0; 1916 1917 return (0); 1918} 1919 1920/* 1921 * Stop all chip I/O so that the kernel's probe routines don't 1922 * get confused by errant DMAs when rebooting. 1923 */ 1924static void 1925rl_shutdown(dev) 1926 device_t dev; 1927{ 1928 struct rl_softc *sc; 1929 1930 sc = device_get_softc(dev); 1931 1932 rl_stop(sc); 1933 1934 return; 1935} 1936