if_rl.c revision 99165
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 99165 2002-06-30 22:16:22Z luigi $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 8740516Swpaul#include <sys/systm.h> 8840516Swpaul#include <sys/sockio.h> 8940516Swpaul#include <sys/mbuf.h> 9040516Swpaul#include <sys/malloc.h> 9140516Swpaul#include <sys/kernel.h> 9240516Swpaul#include <sys/socket.h> 9340516Swpaul 9440516Swpaul#include <net/if.h> 9540516Swpaul#include <net/if_arp.h> 9640516Swpaul#include <net/ethernet.h> 9740516Swpaul#include <net/if_dl.h> 9840516Swpaul#include <net/if_media.h> 9940516Swpaul 10040516Swpaul#include <net/bpf.h> 10140516Swpaul 10241569Swpaul#include <machine/bus_pio.h> 10341569Swpaul#include <machine/bus_memio.h> 10441569Swpaul#include <machine/bus.h> 10550703Swpaul#include <machine/resource.h> 10650703Swpaul#include <sys/bus.h> 10750703Swpaul#include <sys/rman.h> 10840516Swpaul 10950703Swpaul#include <dev/mii/mii.h> 11050703Swpaul#include <dev/mii/miivar.h> 11150703Swpaul 11240516Swpaul#include <pci/pcireg.h> 11340516Swpaul#include <pci/pcivar.h> 11440516Swpaul 11559758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11659758Speter 11751089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11850703Swpaul#include "miibus_if.h" 11950703Swpaul 12040516Swpaul/* 12140516Swpaul * Default to using PIO access for this driver. On SMP systems, 12240516Swpaul * there appear to be problems with memory mapped mode: it looks like 12340516Swpaul * doing too many memory mapped access back to back in rapid succession 12440516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12540516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12640516Swpaul * uniprocessor systems though. 12740516Swpaul */ 12840516Swpaul#define RL_USEIOSPACE 12940516Swpaul 13040516Swpaul#include <pci/if_rlreg.h> 13140516Swpaul 13240516Swpaul#ifndef lint 13341591Sarchiestatic const char rcsid[] = 13450477Speter "$FreeBSD: head/sys/pci/if_rl.c 99165 2002-06-30 22:16:22Z luigi $"; 13540516Swpaul#endif 13640516Swpaul 13740516Swpaul/* 13840516Swpaul * Various supported device vendors/types and their names. 13940516Swpaul */ 14040516Swpaulstatic struct rl_type rl_devs[] = { 14140516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14240516Swpaul "RealTek 8129 10/100BaseTX" }, 14340516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14440516Swpaul "RealTek 8139 10/100BaseTX" }, 14567771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14667771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14741243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14841243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14944238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15044238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15144238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15244238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15372813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15472813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15596112Sjhb { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 15696112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 15794400Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 15894400Swpaul "Nortel Networks 10/100BaseTX" }, 15940516Swpaul { 0, 0, NULL } 16040516Swpaul}; 16140516Swpaul 16292739Salfredstatic int rl_probe (device_t); 16392739Salfredstatic int rl_attach (device_t); 16492739Salfredstatic int rl_detach (device_t); 16540516Swpaul 16692739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 16740516Swpaul 16892739Salfredstatic void rl_rxeof (struct rl_softc *); 16992739Salfredstatic void rl_txeof (struct rl_softc *); 17092739Salfredstatic void rl_intr (void *); 17192739Salfredstatic void rl_tick (void *); 17292739Salfredstatic void rl_start (struct ifnet *); 17392739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17492739Salfredstatic void rl_init (void *); 17592739Salfredstatic void rl_stop (struct rl_softc *); 17692739Salfredstatic void rl_watchdog (struct ifnet *); 17792739Salfredstatic int rl_suspend (device_t); 17892739Salfredstatic int rl_resume (device_t); 17992739Salfredstatic void rl_shutdown (device_t); 18092739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 18192739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 18240516Swpaul 18392739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18492739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 18592739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 18692739Salfredstatic void rl_mii_sync (struct rl_softc *); 18792739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 18892739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 18992739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 19040516Swpaul 19192739Salfredstatic int rl_miibus_readreg (device_t, int, int); 19292739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 19392739Salfredstatic void rl_miibus_statchg (device_t); 19440516Swpaul 19592739Salfredstatic u_int8_t rl_calchash (caddr_t); 19692739Salfredstatic void rl_setmulti (struct rl_softc *); 19792739Salfredstatic void rl_reset (struct rl_softc *); 19892739Salfredstatic int rl_list_tx_init (struct rl_softc *); 19940516Swpaul 20092739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 20192739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 20281713Swpaul 20350703Swpaul#ifdef RL_USEIOSPACE 20450703Swpaul#define RL_RES SYS_RES_IOPORT 20550703Swpaul#define RL_RID RL_PCI_LOIO 20650703Swpaul#else 20750703Swpaul#define RL_RES SYS_RES_MEMORY 20850703Swpaul#define RL_RID RL_PCI_LOMEM 20950703Swpaul#endif 21050703Swpaul 21150703Swpaulstatic device_method_t rl_methods[] = { 21250703Swpaul /* Device interface */ 21350703Swpaul DEVMETHOD(device_probe, rl_probe), 21450703Swpaul DEVMETHOD(device_attach, rl_attach), 21550703Swpaul DEVMETHOD(device_detach, rl_detach), 21686822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 21786822Siwasaki DEVMETHOD(device_resume, rl_resume), 21850703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 21950703Swpaul 22050703Swpaul /* bus interface */ 22150703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22250703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22350703Swpaul 22450703Swpaul /* MII interface */ 22550703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 22650703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 22750703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 22850703Swpaul 22950703Swpaul { 0, 0 } 23050703Swpaul}; 23150703Swpaul 23250703Swpaulstatic driver_t rl_driver = { 23351455Swpaul "rl", 23450703Swpaul rl_methods, 23550703Swpaul sizeof(struct rl_softc) 23650703Swpaul}; 23750703Swpaul 23850703Swpaulstatic devclass_t rl_devclass; 23950703Swpaul 24051533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 24167931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 24251473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 24350703Swpaul 24440516Swpaul#define EE_SET(x) \ 24540516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24640516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 24740516Swpaul 24840516Swpaul#define EE_CLR(x) \ 24940516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25040516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 25140516Swpaul 25281713Swpaulstatic void 25381713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25481713Swpaul void *arg; 25581713Swpaul bus_dma_segment_t *segs; 25681713Swpaul int nseg, error; 25781713Swpaul{ 25881713Swpaul struct rl_softc *sc; 25981713Swpaul 26081713Swpaul sc = arg; 26181713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 26281713Swpaul 26381713Swpaul return; 26481713Swpaul} 26581713Swpaul 26681713Swpaulstatic void 26781713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 26881713Swpaul void *arg; 26981713Swpaul bus_dma_segment_t *segs; 27081713Swpaul int nseg, error; 27181713Swpaul{ 27281713Swpaul struct rl_softc *sc; 27381713Swpaul 27481713Swpaul sc = arg; 27581713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 27681713Swpaul 27781713Swpaul return; 27881713Swpaul} 27981713Swpaul 28040516Swpaul/* 28140516Swpaul * Send a read command and address to the EEPROM, check for ACK. 28240516Swpaul */ 28340516Swpaulstatic void rl_eeprom_putbyte(sc, addr) 28440516Swpaul struct rl_softc *sc; 28541656Swpaul int addr; 28640516Swpaul{ 28740516Swpaul register int d, i; 28840516Swpaul 28967931Swpaul d = addr | sc->rl_eecmd_read; 29040516Swpaul 29140516Swpaul /* 29255170Sbillf * Feed in each bit and strobe the clock. 29340516Swpaul */ 29440516Swpaul for (i = 0x400; i; i >>= 1) { 29540516Swpaul if (d & i) { 29640516Swpaul EE_SET(RL_EE_DATAIN); 29740516Swpaul } else { 29840516Swpaul EE_CLR(RL_EE_DATAIN); 29940516Swpaul } 30040516Swpaul DELAY(100); 30140516Swpaul EE_SET(RL_EE_CLK); 30240516Swpaul DELAY(150); 30340516Swpaul EE_CLR(RL_EE_CLK); 30440516Swpaul DELAY(100); 30540516Swpaul } 30640516Swpaul 30740516Swpaul return; 30840516Swpaul} 30940516Swpaul 31040516Swpaul/* 31140516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 31240516Swpaul */ 31340516Swpaulstatic void rl_eeprom_getword(sc, addr, dest) 31440516Swpaul struct rl_softc *sc; 31541656Swpaul int addr; 31640516Swpaul u_int16_t *dest; 31740516Swpaul{ 31840516Swpaul register int i; 31940516Swpaul u_int16_t word = 0; 32040516Swpaul 32140516Swpaul /* Enter EEPROM access mode. */ 32240516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32340516Swpaul 32440516Swpaul /* 32540516Swpaul * Send address of word we want to read. 32640516Swpaul */ 32740516Swpaul rl_eeprom_putbyte(sc, addr); 32840516Swpaul 32940516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33040516Swpaul 33140516Swpaul /* 33240516Swpaul * Start reading bits from EEPROM. 33340516Swpaul */ 33440516Swpaul for (i = 0x8000; i; i >>= 1) { 33540516Swpaul EE_SET(RL_EE_CLK); 33640516Swpaul DELAY(100); 33740516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 33840516Swpaul word |= i; 33940516Swpaul EE_CLR(RL_EE_CLK); 34040516Swpaul DELAY(100); 34140516Swpaul } 34240516Swpaul 34340516Swpaul /* Turn off EEPROM access mode. */ 34440516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 34540516Swpaul 34640516Swpaul *dest = word; 34740516Swpaul 34840516Swpaul return; 34940516Swpaul} 35040516Swpaul 35140516Swpaul/* 35240516Swpaul * Read a sequence of words from the EEPROM. 35340516Swpaul */ 35440516Swpaulstatic void rl_read_eeprom(sc, dest, off, cnt, swap) 35540516Swpaul struct rl_softc *sc; 35640516Swpaul caddr_t dest; 35740516Swpaul int off; 35840516Swpaul int cnt; 35940516Swpaul int swap; 36040516Swpaul{ 36140516Swpaul int i; 36240516Swpaul u_int16_t word = 0, *ptr; 36340516Swpaul 36440516Swpaul for (i = 0; i < cnt; i++) { 36540516Swpaul rl_eeprom_getword(sc, off + i, &word); 36640516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 36740516Swpaul if (swap) 36840516Swpaul *ptr = ntohs(word); 36940516Swpaul else 37040516Swpaul *ptr = word; 37140516Swpaul } 37240516Swpaul 37340516Swpaul return; 37440516Swpaul} 37540516Swpaul 37640516Swpaul 37740516Swpaul/* 37840516Swpaul * MII access routines are provided for the 8129, which 37940516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 38040516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 38140516Swpaul * direct access PHY registers. 38240516Swpaul */ 38340516Swpaul#define MII_SET(x) \ 38440516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38540516Swpaul CSR_READ_1(sc, RL_MII) | x) 38640516Swpaul 38740516Swpaul#define MII_CLR(x) \ 38840516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38940516Swpaul CSR_READ_1(sc, RL_MII) & ~x) 39040516Swpaul 39140516Swpaul/* 39240516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 39340516Swpaul */ 39440516Swpaulstatic void rl_mii_sync(sc) 39540516Swpaul struct rl_softc *sc; 39640516Swpaul{ 39740516Swpaul register int i; 39840516Swpaul 39940516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 40040516Swpaul 40140516Swpaul for (i = 0; i < 32; i++) { 40240516Swpaul MII_SET(RL_MII_CLK); 40340516Swpaul DELAY(1); 40440516Swpaul MII_CLR(RL_MII_CLK); 40540516Swpaul DELAY(1); 40640516Swpaul } 40740516Swpaul 40840516Swpaul return; 40940516Swpaul} 41040516Swpaul 41140516Swpaul/* 41240516Swpaul * Clock a series of bits through the MII. 41340516Swpaul */ 41440516Swpaulstatic void rl_mii_send(sc, bits, cnt) 41540516Swpaul struct rl_softc *sc; 41640516Swpaul u_int32_t bits; 41740516Swpaul int cnt; 41840516Swpaul{ 41940516Swpaul int i; 42040516Swpaul 42140516Swpaul MII_CLR(RL_MII_CLK); 42240516Swpaul 42340516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 42440516Swpaul if (bits & i) { 42540516Swpaul MII_SET(RL_MII_DATAOUT); 42640516Swpaul } else { 42740516Swpaul MII_CLR(RL_MII_DATAOUT); 42840516Swpaul } 42940516Swpaul DELAY(1); 43040516Swpaul MII_CLR(RL_MII_CLK); 43140516Swpaul DELAY(1); 43240516Swpaul MII_SET(RL_MII_CLK); 43340516Swpaul } 43440516Swpaul} 43540516Swpaul 43640516Swpaul/* 43740516Swpaul * Read an PHY register through the MII. 43840516Swpaul */ 43940516Swpaulstatic int rl_mii_readreg(sc, frame) 44040516Swpaul struct rl_softc *sc; 44140516Swpaul struct rl_mii_frame *frame; 44240516Swpaul 44340516Swpaul{ 44467087Swpaul int i, ack; 44540516Swpaul 44667087Swpaul RL_LOCK(sc); 44740516Swpaul 44840516Swpaul /* 44940516Swpaul * Set up frame for RX. 45040516Swpaul */ 45140516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 45240516Swpaul frame->mii_opcode = RL_MII_READOP; 45340516Swpaul frame->mii_turnaround = 0; 45440516Swpaul frame->mii_data = 0; 45540516Swpaul 45640516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 45740516Swpaul 45840516Swpaul /* 45940516Swpaul * Turn on data xmit. 46040516Swpaul */ 46140516Swpaul MII_SET(RL_MII_DIR); 46240516Swpaul 46340516Swpaul rl_mii_sync(sc); 46440516Swpaul 46540516Swpaul /* 46640516Swpaul * Send command/address info. 46740516Swpaul */ 46840516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 46940516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 47040516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 47140516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 47240516Swpaul 47340516Swpaul /* Idle bit */ 47440516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 47540516Swpaul DELAY(1); 47640516Swpaul MII_SET(RL_MII_CLK); 47740516Swpaul DELAY(1); 47840516Swpaul 47940516Swpaul /* Turn off xmit. */ 48040516Swpaul MII_CLR(RL_MII_DIR); 48140516Swpaul 48240516Swpaul /* Check for ack */ 48340516Swpaul MII_CLR(RL_MII_CLK); 48440516Swpaul DELAY(1); 48540516Swpaul MII_SET(RL_MII_CLK); 48640516Swpaul DELAY(1); 48740516Swpaul ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 48840516Swpaul 48940516Swpaul /* 49040516Swpaul * Now try reading data bits. If the ack failed, we still 49140516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 49240516Swpaul */ 49340516Swpaul if (ack) { 49440516Swpaul for(i = 0; i < 16; i++) { 49540516Swpaul MII_CLR(RL_MII_CLK); 49640516Swpaul DELAY(1); 49740516Swpaul MII_SET(RL_MII_CLK); 49840516Swpaul DELAY(1); 49940516Swpaul } 50040516Swpaul goto fail; 50140516Swpaul } 50240516Swpaul 50340516Swpaul for (i = 0x8000; i; i >>= 1) { 50440516Swpaul MII_CLR(RL_MII_CLK); 50540516Swpaul DELAY(1); 50640516Swpaul if (!ack) { 50740516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 50840516Swpaul frame->mii_data |= i; 50940516Swpaul DELAY(1); 51040516Swpaul } 51140516Swpaul MII_SET(RL_MII_CLK); 51240516Swpaul DELAY(1); 51340516Swpaul } 51440516Swpaul 51540516Swpaulfail: 51640516Swpaul 51740516Swpaul MII_CLR(RL_MII_CLK); 51840516Swpaul DELAY(1); 51940516Swpaul MII_SET(RL_MII_CLK); 52040516Swpaul DELAY(1); 52140516Swpaul 52267087Swpaul RL_UNLOCK(sc); 52340516Swpaul 52440516Swpaul if (ack) 52540516Swpaul return(1); 52640516Swpaul return(0); 52740516Swpaul} 52840516Swpaul 52940516Swpaul/* 53040516Swpaul * Write to a PHY register through the MII. 53140516Swpaul */ 53240516Swpaulstatic int rl_mii_writereg(sc, frame) 53340516Swpaul struct rl_softc *sc; 53440516Swpaul struct rl_mii_frame *frame; 53540516Swpaul 53640516Swpaul{ 53767087Swpaul RL_LOCK(sc); 53840516Swpaul 53940516Swpaul /* 54040516Swpaul * Set up frame for TX. 54140516Swpaul */ 54240516Swpaul 54340516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 54440516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 54540516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 54640516Swpaul 54740516Swpaul /* 54840516Swpaul * Turn on data output. 54940516Swpaul */ 55040516Swpaul MII_SET(RL_MII_DIR); 55140516Swpaul 55240516Swpaul rl_mii_sync(sc); 55340516Swpaul 55440516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 55540516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 55640516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 55740516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 55840516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 55940516Swpaul rl_mii_send(sc, frame->mii_data, 16); 56040516Swpaul 56140516Swpaul /* Idle bit. */ 56240516Swpaul MII_SET(RL_MII_CLK); 56340516Swpaul DELAY(1); 56440516Swpaul MII_CLR(RL_MII_CLK); 56540516Swpaul DELAY(1); 56640516Swpaul 56740516Swpaul /* 56840516Swpaul * Turn off xmit. 56940516Swpaul */ 57040516Swpaul MII_CLR(RL_MII_DIR); 57140516Swpaul 57267087Swpaul RL_UNLOCK(sc); 57340516Swpaul 57440516Swpaul return(0); 57540516Swpaul} 57640516Swpaul 57750703Swpaulstatic int rl_miibus_readreg(dev, phy, reg) 57850703Swpaul device_t dev; 57950703Swpaul int phy, reg; 58050703Swpaul{ 58140516Swpaul struct rl_softc *sc; 58240516Swpaul struct rl_mii_frame frame; 58340516Swpaul u_int16_t rval = 0; 58440516Swpaul u_int16_t rl8139_reg = 0; 58540516Swpaul 58650703Swpaul sc = device_get_softc(dev); 58767087Swpaul RL_LOCK(sc); 58850703Swpaul 58940516Swpaul if (sc->rl_type == RL_8139) { 59050703Swpaul /* Pretend the internal PHY is only at address 0 */ 59167087Swpaul if (phy) { 59267087Swpaul RL_UNLOCK(sc); 59350703Swpaul return(0); 59467087Swpaul } 59540516Swpaul switch(reg) { 59650703Swpaul case MII_BMCR: 59740516Swpaul rl8139_reg = RL_BMCR; 59840516Swpaul break; 59950703Swpaul case MII_BMSR: 60040516Swpaul rl8139_reg = RL_BMSR; 60140516Swpaul break; 60250703Swpaul case MII_ANAR: 60340516Swpaul rl8139_reg = RL_ANAR; 60440516Swpaul break; 60550703Swpaul case MII_ANER: 60650703Swpaul rl8139_reg = RL_ANER; 60750703Swpaul break; 60850703Swpaul case MII_ANLPAR: 60940516Swpaul rl8139_reg = RL_LPAR; 61040516Swpaul break; 61150703Swpaul case MII_PHYIDR1: 61250703Swpaul case MII_PHYIDR2: 61367087Swpaul RL_UNLOCK(sc); 61450703Swpaul return(0); 61550703Swpaul break; 61694149Swpaul /* 61794149Swpaul * Allow the rlphy driver to read the media status 61894149Swpaul * register. If we have a link partner which does not 61994149Swpaul * support NWAY, this is the register which will tell 62094149Swpaul * us the results of parallel detection. 62194149Swpaul */ 62294149Swpaul case RL_MEDIASTAT: 62394149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 62494149Swpaul RL_UNLOCK(sc); 62594149Swpaul return(rval); 62694149Swpaul break; 62740516Swpaul default: 62840516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 62967087Swpaul RL_UNLOCK(sc); 63040516Swpaul return(0); 63140516Swpaul } 63240516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 63367087Swpaul RL_UNLOCK(sc); 63440516Swpaul return(rval); 63540516Swpaul } 63640516Swpaul 63740516Swpaul bzero((char *)&frame, sizeof(frame)); 63840516Swpaul 63950703Swpaul frame.mii_phyaddr = phy; 64040516Swpaul frame.mii_regaddr = reg; 64140516Swpaul rl_mii_readreg(sc, &frame); 64267087Swpaul RL_UNLOCK(sc); 64340516Swpaul 64440516Swpaul return(frame.mii_data); 64540516Swpaul} 64640516Swpaul 64750703Swpaulstatic int rl_miibus_writereg(dev, phy, reg, data) 64850703Swpaul device_t dev; 64950703Swpaul int phy, reg, data; 65050703Swpaul{ 65140516Swpaul struct rl_softc *sc; 65240516Swpaul struct rl_mii_frame frame; 65340516Swpaul u_int16_t rl8139_reg = 0; 65440516Swpaul 65550703Swpaul sc = device_get_softc(dev); 65667087Swpaul RL_LOCK(sc); 65750703Swpaul 65840516Swpaul if (sc->rl_type == RL_8139) { 65950703Swpaul /* Pretend the internal PHY is only at address 0 */ 66067087Swpaul if (phy) { 66167087Swpaul RL_UNLOCK(sc); 66250703Swpaul return(0); 66367087Swpaul } 66440516Swpaul switch(reg) { 66550703Swpaul case MII_BMCR: 66640516Swpaul rl8139_reg = RL_BMCR; 66740516Swpaul break; 66850703Swpaul case MII_BMSR: 66940516Swpaul rl8139_reg = RL_BMSR; 67040516Swpaul break; 67150703Swpaul case MII_ANAR: 67240516Swpaul rl8139_reg = RL_ANAR; 67340516Swpaul break; 67450703Swpaul case MII_ANER: 67550703Swpaul rl8139_reg = RL_ANER; 67650703Swpaul break; 67750703Swpaul case MII_ANLPAR: 67840516Swpaul rl8139_reg = RL_LPAR; 67940516Swpaul break; 68050703Swpaul case MII_PHYIDR1: 68150703Swpaul case MII_PHYIDR2: 68267087Swpaul RL_UNLOCK(sc); 68350703Swpaul return(0); 68450703Swpaul break; 68540516Swpaul default: 68640516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 68767087Swpaul RL_UNLOCK(sc); 68850703Swpaul return(0); 68940516Swpaul } 69040516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 69167087Swpaul RL_UNLOCK(sc); 69250703Swpaul return(0); 69340516Swpaul } 69440516Swpaul 69540516Swpaul bzero((char *)&frame, sizeof(frame)); 69640516Swpaul 69750703Swpaul frame.mii_phyaddr = phy; 69840516Swpaul frame.mii_regaddr = reg; 69940516Swpaul frame.mii_data = data; 70040516Swpaul 70140516Swpaul rl_mii_writereg(sc, &frame); 70240516Swpaul 70367087Swpaul RL_UNLOCK(sc); 70450703Swpaul return(0); 70550703Swpaul} 70650703Swpaul 70750703Swpaulstatic void rl_miibus_statchg(dev) 70850703Swpaul device_t dev; 70950703Swpaul{ 71040516Swpaul return; 71140516Swpaul} 71240516Swpaul 71340516Swpaul/* 71443062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 71540516Swpaul */ 71640516Swpaulstatic u_int8_t rl_calchash(addr) 71741656Swpaul caddr_t addr; 71840516Swpaul{ 71940516Swpaul u_int32_t crc, carry; 72040516Swpaul int i, j; 72140516Swpaul u_int8_t c; 72240516Swpaul 72340516Swpaul /* Compute CRC for the address value. */ 72440516Swpaul crc = 0xFFFFFFFF; /* initial value */ 72540516Swpaul 72640516Swpaul for (i = 0; i < 6; i++) { 72740516Swpaul c = *(addr + i); 72840516Swpaul for (j = 0; j < 8; j++) { 72940516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 73040516Swpaul crc <<= 1; 73140516Swpaul c >>= 1; 73240516Swpaul if (carry) 73340516Swpaul crc = (crc ^ 0x04c11db6) | carry; 73440516Swpaul } 73540516Swpaul } 73640516Swpaul 73740516Swpaul /* return the filter bit position */ 73843062Swpaul return(crc >> 26); 73940516Swpaul} 74040516Swpaul 74140516Swpaul/* 74240516Swpaul * Program the 64-bit multicast hash filter. 74340516Swpaul */ 74440516Swpaulstatic void rl_setmulti(sc) 74540516Swpaul struct rl_softc *sc; 74640516Swpaul{ 74740516Swpaul struct ifnet *ifp; 74840516Swpaul int h = 0; 74940516Swpaul u_int32_t hashes[2] = { 0, 0 }; 75040516Swpaul struct ifmultiaddr *ifma; 75140516Swpaul u_int32_t rxfilt; 75240516Swpaul int mcnt = 0; 75340516Swpaul 75440516Swpaul ifp = &sc->arpcom.ac_if; 75540516Swpaul 75640516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 75740516Swpaul 75843062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 75940516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 76040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 76140516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 76240516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 76340516Swpaul return; 76440516Swpaul } 76540516Swpaul 76640516Swpaul /* first, zot all the existing hash bits */ 76740516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 76840516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 76940516Swpaul 77040516Swpaul /* now program new ones */ 77172084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 77240516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 77340516Swpaul continue; 77440516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 77540516Swpaul if (h < 32) 77640516Swpaul hashes[0] |= (1 << h); 77740516Swpaul else 77840516Swpaul hashes[1] |= (1 << (h - 32)); 77940516Swpaul mcnt++; 78040516Swpaul } 78140516Swpaul 78240516Swpaul if (mcnt) 78340516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 78440516Swpaul else 78540516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 78640516Swpaul 78740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 78840516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 78940516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 79040516Swpaul 79140516Swpaul return; 79240516Swpaul} 79340516Swpaul 79440516Swpaulstatic void rl_reset(sc) 79540516Swpaul struct rl_softc *sc; 79640516Swpaul{ 79740516Swpaul register int i; 79840516Swpaul 79940516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 80040516Swpaul 80140516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 80240516Swpaul DELAY(10); 80340516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 80440516Swpaul break; 80540516Swpaul } 80640516Swpaul if (i == RL_TIMEOUT) 80740516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 80840516Swpaul 80940516Swpaul return; 81040516Swpaul} 81140516Swpaul 81240516Swpaul/* 81340516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 81440516Swpaul * IDs against our list and return a device name if we find a match. 81540516Swpaul */ 81650703Swpaulstatic int rl_probe(dev) 81750703Swpaul device_t dev; 81840516Swpaul{ 81940516Swpaul struct rl_type *t; 82040516Swpaul 82140516Swpaul t = rl_devs; 82240516Swpaul 82340516Swpaul while(t->rl_name != NULL) { 82450703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 82550703Swpaul (pci_get_device(dev) == t->rl_did)) { 82650703Swpaul device_set_desc(dev, t->rl_name); 82750703Swpaul return(0); 82840516Swpaul } 82940516Swpaul t++; 83040516Swpaul } 83140516Swpaul 83250703Swpaul return(ENXIO); 83340516Swpaul} 83440516Swpaul 83540516Swpaul/* 83640516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 83740516Swpaul * setup and ethernet/BPF attach. 83840516Swpaul */ 83950703Swpaulstatic int rl_attach(dev) 84050703Swpaul device_t dev; 84140516Swpaul{ 84240516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 84340516Swpaul u_int32_t command; 84440516Swpaul struct rl_softc *sc; 84540516Swpaul struct ifnet *ifp; 84640516Swpaul u_int16_t rl_did = 0; 84750703Swpaul int unit, error = 0, rid; 84840516Swpaul 84950703Swpaul sc = device_get_softc(dev); 85050703Swpaul unit = device_get_unit(dev); 85140516Swpaul bzero(sc, sizeof(struct rl_softc)); 85240516Swpaul 85393818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 85493818Sjhb MTX_DEF | MTX_RECURSE); 85569583Swpaul RL_LOCK(sc); 85669583Swpaul 85740516Swpaul /* 85840516Swpaul * Handle power management nonsense. 85940516Swpaul */ 86040516Swpaul 86170167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 86270167Swpaul u_int32_t iobase, membase, irq; 86340516Swpaul 86470167Swpaul /* Save important PCI config data. */ 86570167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 86670167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 86770167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 86840516Swpaul 86970167Swpaul /* Reset the power state. */ 87070167Swpaul printf("rl%d: chip is is in D%d power mode " 87170167Swpaul "-- setting to D0\n", unit, 87270167Swpaul pci_get_powerstate(dev)); 87340516Swpaul 87470167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 87540516Swpaul 87670167Swpaul /* Restore PCI config data. */ 87770167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 87870167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 87970167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 88040516Swpaul } 88140516Swpaul 88240516Swpaul /* 88340516Swpaul * Map control/status registers. 88440516Swpaul */ 88572813Swpaul pci_enable_busmaster(dev); 88679472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 88779472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 88861041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 88940516Swpaul 89040516Swpaul#ifdef RL_USEIOSPACE 89140516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 89240516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 89350703Swpaul error = ENXIO; 89440516Swpaul goto fail; 89540516Swpaul } 89640516Swpaul#else 89740516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 89840516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 89950703Swpaul error = ENXIO; 90040516Swpaul goto fail; 90140516Swpaul } 90250703Swpaul#endif 90340516Swpaul 90450703Swpaul rid = RL_RID; 90550703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 90650703Swpaul 0, ~0, 1, RF_ACTIVE); 90750703Swpaul 90850703Swpaul if (sc->rl_res == NULL) { 90950703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 91050703Swpaul error = ENXIO; 91140516Swpaul goto fail; 91240516Swpaul } 91340516Swpaul 91469127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 91569127Sroger * unstable when left to autoselect the media 91669127Sroger * The best workaround is to set the device to the required 91769127Sroger * media type or to set it to the 10 Meg speed. 91869127Sroger */ 91969127Sroger 92069127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 92169127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 92269127Sroger } 92369127Sroger 92450703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 92550703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 92650703Swpaul 92750703Swpaul rid = 0; 92850703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 92950703Swpaul RF_SHAREABLE | RF_ACTIVE); 93050703Swpaul 93150703Swpaul if (sc->rl_irq == NULL) { 93240516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 93350703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 93450703Swpaul error = ENXIO; 93540516Swpaul goto fail; 93640516Swpaul } 93740516Swpaul 93850703Swpaul error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 93950703Swpaul rl_intr, sc, &sc->rl_intrhand); 94050703Swpaul 94150703Swpaul if (error) { 94268215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 94350703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 94450703Swpaul printf("rl%d: couldn't set up irq\n", unit); 94550703Swpaul goto fail; 94650703Swpaul } 94750703Swpaul 94850703Swpaul callout_handle_init(&sc->rl_stat_ch); 94950703Swpaul 95040516Swpaul /* Reset the adapter. */ 95140516Swpaul rl_reset(sc); 95267931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 95367931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 95468215Swpaul if (rl_did != 0x8129) 95567931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 95640516Swpaul 95740516Swpaul /* 95840516Swpaul * Get station address from the EEPROM. 95940516Swpaul */ 96040516Swpaul rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 96140516Swpaul 96240516Swpaul /* 96340516Swpaul * A RealTek chip was detected. Inform the world. 96440516Swpaul */ 96540516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 96640516Swpaul 96740516Swpaul sc->rl_unit = unit; 96840516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 96940516Swpaul 97040516Swpaul /* 97140516Swpaul * Now read the exact device type from the EEPROM to find 97240516Swpaul * out if it's an 8129 or 8139. 97340516Swpaul */ 97440516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 97540516Swpaul 97644238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 97767771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 97896112Sjhb rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 97996112Sjhb rl_did == DLINK_DEVICEID_690TXD) 98040516Swpaul sc->rl_type = RL_8139; 98140516Swpaul else if (rl_did == RT_DEVICEID_8129) 98240516Swpaul sc->rl_type = RL_8129; 98340516Swpaul else { 98440516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 98550703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 98668215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 98750703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 98850703Swpaul error = ENXIO; 98940516Swpaul goto fail; 99040516Swpaul } 99140516Swpaul 99281713Swpaul /* 99381713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 99481713Swpaul */ 99581713Swpaul#define RL_NSEG_NEW 32 99681713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 99781713Swpaul 1, 0, /* alignment, boundary */ 99881713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 99981713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 100081713Swpaul NULL, NULL, /* filter, filterarg */ 100181713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 100281713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 100381713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 100481713Swpaul &sc->rl_parent_tag); 100540516Swpaul 100681713Swpaul /* 100781713Swpaul * Now allocate a tag for the DMA descriptor lists. 100881713Swpaul * All of our lists are allocated as a contiguous block 100981713Swpaul * of memory. 101081713Swpaul */ 101181713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 101281713Swpaul 1, 0, /* alignment, boundary */ 101381713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 101481713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 101581713Swpaul NULL, NULL, /* filter, filterarg */ 101681713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 101781713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 101881713Swpaul 0, /* flags */ 101981713Swpaul &sc->rl_tag); 102081713Swpaul 102181713Swpaul /* 102281713Swpaul * Now allocate a chunk of DMA-able memory based on the 102381713Swpaul * tag we just created. 102481713Swpaul */ 102581713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 102681713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 102781713Swpaul &sc->rl_cdata.rl_rx_dmamap); 102881713Swpaul 102940516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 103040516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 103150703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 103268215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 103350703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 103481713Swpaul bus_dma_tag_destroy(sc->rl_tag); 103550703Swpaul error = ENXIO; 103640516Swpaul goto fail; 103740516Swpaul } 103840516Swpaul 103948028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 104048028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 104148028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 104248028Swpaul 104350703Swpaul /* Do MII setup */ 104450703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 104550703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 104650703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 104750703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 104868215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 104950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 105081713Swpaul bus_dmamem_free(sc->rl_tag, 105181713Swpaul sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 105281713Swpaul bus_dma_tag_destroy(sc->rl_tag); 105350703Swpaul error = ENXIO; 105450703Swpaul goto fail; 105550703Swpaul } 105650703Swpaul 105740516Swpaul ifp = &sc->arpcom.ac_if; 105840516Swpaul ifp->if_softc = sc; 105940516Swpaul ifp->if_unit = unit; 106040516Swpaul ifp->if_name = "rl"; 106140516Swpaul ifp->if_mtu = ETHERMTU; 106240516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 106340516Swpaul ifp->if_ioctl = rl_ioctl; 106440516Swpaul ifp->if_output = ether_output; 106540516Swpaul ifp->if_start = rl_start; 106640516Swpaul ifp->if_watchdog = rl_watchdog; 106740516Swpaul ifp->if_init = rl_init; 106840516Swpaul ifp->if_baudrate = 10000000; 106945633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 107040516Swpaul 107140516Swpaul /* 107263090Sarchie * Call MI attach routine. 107340516Swpaul */ 107463090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 107567087Swpaul RL_UNLOCK(sc); 107667087Swpaul return(0); 107740516Swpaul 107840516Swpaulfail: 107967087Swpaul RL_UNLOCK(sc); 108067087Swpaul mtx_destroy(&sc->rl_mtx); 108150703Swpaul return(error); 108240516Swpaul} 108340516Swpaul 108450703Swpaulstatic int rl_detach(dev) 108550703Swpaul device_t dev; 108650703Swpaul{ 108750703Swpaul struct rl_softc *sc; 108850703Swpaul struct ifnet *ifp; 108950703Swpaul 109050703Swpaul sc = device_get_softc(dev); 109167087Swpaul RL_LOCK(sc); 109250703Swpaul ifp = &sc->arpcom.ac_if; 109350703Swpaul 109463090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 109550703Swpaul rl_stop(sc); 109650703Swpaul 109750703Swpaul bus_generic_detach(dev); 109850703Swpaul device_delete_child(dev, sc->rl_miibus); 109950703Swpaul 110050703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 110168215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 110250703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 110350703Swpaul 110481713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 110581713Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 110681713Swpaul sc->rl_cdata.rl_rx_dmamap); 110781713Swpaul bus_dma_tag_destroy(sc->rl_tag); 110881713Swpaul bus_dma_tag_destroy(sc->rl_parent_tag); 110950703Swpaul 111067087Swpaul RL_UNLOCK(sc); 111167087Swpaul mtx_destroy(&sc->rl_mtx); 111250703Swpaul 111350703Swpaul return(0); 111450703Swpaul} 111550703Swpaul 111640516Swpaul/* 111740516Swpaul * Initialize the transmit descriptors. 111840516Swpaul */ 111940516Swpaulstatic int rl_list_tx_init(sc) 112040516Swpaul struct rl_softc *sc; 112140516Swpaul{ 112240516Swpaul struct rl_chain_data *cd; 112340516Swpaul int i; 112440516Swpaul 112540516Swpaul cd = &sc->rl_cdata; 112640516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 112745633Swpaul cd->rl_tx_chain[i] = NULL; 112848028Swpaul CSR_WRITE_4(sc, 112948028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 113040516Swpaul } 113140516Swpaul 113245633Swpaul sc->rl_cdata.cur_tx = 0; 113345633Swpaul sc->rl_cdata.last_tx = 0; 113440516Swpaul 113540516Swpaul return(0); 113640516Swpaul} 113740516Swpaul 113840516Swpaul/* 113940516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 114040516Swpaul * the higher level protocols. 114140516Swpaul * 114240516Swpaul * You know there's something wrong with a PCI bus-master chip design 114340516Swpaul * when you have to use m_devget(). 114440516Swpaul * 114540516Swpaul * The receive operation is badly documented in the datasheet, so I'll 114640516Swpaul * attempt to document it here. The driver provides a buffer area and 114740516Swpaul * places its base address in the RX buffer start address register. 114840516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 114972645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 115040516Swpaul * of the frame and certain other status bits. Each frame (starting with 115140516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 115240516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 115340516Swpaul * the 'rx status register' mentioned in the datasheet. 115448028Swpaul * 115548028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 115678508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 115778508Sbmilekic * as the offset argument to m_devget(). 115840516Swpaul */ 115940516Swpaulstatic void rl_rxeof(sc) 116040516Swpaul struct rl_softc *sc; 116140516Swpaul{ 116240516Swpaul struct ether_header *eh; 116340516Swpaul struct mbuf *m; 116440516Swpaul struct ifnet *ifp; 116540516Swpaul int total_len = 0; 116640516Swpaul u_int32_t rxstat; 116740516Swpaul caddr_t rxbufpos; 116840516Swpaul int wrap = 0; 116940516Swpaul u_int16_t cur_rx; 117040516Swpaul u_int16_t limit; 117140516Swpaul u_int16_t rx_bytes = 0, max_bytes; 117240516Swpaul 117340516Swpaul ifp = &sc->arpcom.ac_if; 117440516Swpaul 117581713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 117681713Swpaul BUS_DMASYNC_POSTWRITE); 117781713Swpaul 117840516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 117940516Swpaul 118040516Swpaul /* Do not try to read past this point. */ 118140516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 118240516Swpaul 118340516Swpaul if (limit < cur_rx) 118440516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 118540516Swpaul else 118640516Swpaul max_bytes = limit - cur_rx; 118740516Swpaul 118842738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 118994883Sluigi#ifdef DEVICE_POLLING 119094883Sluigi if (ifp->if_ipending & IFF_POLLING) { 119194883Sluigi if (sc->rxcycles <= 0) 119294883Sluigi break; 119394883Sluigi sc->rxcycles--; 119494883Sluigi } 119594883Sluigi#endif /* DEVICE_POLLING */ 119640516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 119740516Swpaul rxstat = *(u_int32_t *)rxbufpos; 119840516Swpaul 119940516Swpaul /* 120040516Swpaul * Here's a totally undocumented fact for you. When the 120140516Swpaul * RealTek chip is in the process of copying a packet into 120240516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 120340516Swpaul * packet header with this value, you need to stop. The 120440516Swpaul * datasheet makes absolutely no mention of this and 120540516Swpaul * RealTek should be shot for this. 120640516Swpaul */ 120740516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 120840516Swpaul break; 120940516Swpaul 121040516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 121140516Swpaul ifp->if_ierrors++; 121250703Swpaul rl_init(sc); 121350703Swpaul return; 121440516Swpaul } 121540516Swpaul 121640516Swpaul /* No errors; receive the packet. */ 121740516Swpaul total_len = rxstat >> 16; 121840516Swpaul rx_bytes += total_len + 4; 121940516Swpaul 122040516Swpaul /* 122142051Swpaul * XXX The RealTek chip includes the CRC with every 122242051Swpaul * received frame, and there's no way to turn this 122342051Swpaul * behavior off (at least, I can't find anything in 122442051Swpaul * the manual that explains how to do it) so we have 122542051Swpaul * to trim off the CRC manually. 122642051Swpaul */ 122742051Swpaul total_len -= ETHER_CRC_LEN; 122842051Swpaul 122942051Swpaul /* 123040516Swpaul * Avoid trying to read more bytes than we know 123140516Swpaul * the chip has prepared for us. 123240516Swpaul */ 123340516Swpaul if (rx_bytes > max_bytes) 123440516Swpaul break; 123540516Swpaul 123640516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 123740516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 123840516Swpaul 123940516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 124040516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 124140516Swpaul 124240516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 124340516Swpaul 124440516Swpaul if (total_len > wrap) { 124578508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 124678508Sbmilekic NULL); 124740516Swpaul if (m == NULL) { 124840516Swpaul ifp->if_ierrors++; 124952426Swpaul } else { 125040516Swpaul m_copyback(m, wrap, total_len - wrap, 125140516Swpaul sc->rl_cdata.rl_rx_buf); 125248028Swpaul } 125342051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 125440516Swpaul } else { 125578508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 125678508Sbmilekic NULL); 125740516Swpaul if (m == NULL) { 125840516Swpaul ifp->if_ierrors++; 125978508Sbmilekic } 126042051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 126140516Swpaul } 126240516Swpaul 126340516Swpaul /* 126440516Swpaul * Round up to 32-bit boundary. 126540516Swpaul */ 126640516Swpaul cur_rx = (cur_rx + 3) & ~3; 126740516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 126840516Swpaul 126940516Swpaul if (m == NULL) 127040516Swpaul continue; 127140516Swpaul 127240516Swpaul eh = mtod(m, struct ether_header *); 127340516Swpaul ifp->if_ipackets++; 127440516Swpaul 127540516Swpaul /* Remove header from mbuf and pass it on. */ 127640516Swpaul m_adj(m, sizeof(struct ether_header)); 127740516Swpaul ether_input(ifp, eh, m); 127840516Swpaul } 127940516Swpaul 128040516Swpaul return; 128140516Swpaul} 128240516Swpaul 128340516Swpaul/* 128440516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 128540516Swpaul * the list buffers. 128640516Swpaul */ 128740516Swpaulstatic void rl_txeof(sc) 128840516Swpaul struct rl_softc *sc; 128940516Swpaul{ 129040516Swpaul struct ifnet *ifp; 129140516Swpaul u_int32_t txstat; 129240516Swpaul 129340516Swpaul ifp = &sc->arpcom.ac_if; 129440516Swpaul 129540516Swpaul /* 129640516Swpaul * Go through our tx list and free mbufs for those 129740516Swpaul * frames that have been uploaded. 129840516Swpaul */ 129945633Swpaul do { 130045633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 130145633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 130245633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 130340516Swpaul break; 130440516Swpaul 130545633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 130640516Swpaul 130745633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 130881713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 130981713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 131045633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 131145633Swpaul RL_LAST_TXMBUF(sc) = NULL; 131245633Swpaul } 131345633Swpaul if (txstat & RL_TXSTAT_TX_OK) 131445633Swpaul ifp->if_opackets++; 131545633Swpaul else { 131652426Swpaul int oldthresh; 131745633Swpaul ifp->if_oerrors++; 131845633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 131945633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 132045633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 132152426Swpaul oldthresh = sc->rl_txthresh; 132252426Swpaul /* error recovery */ 132352426Swpaul rl_reset(sc); 132452426Swpaul rl_init(sc); 132552426Swpaul /* 132652426Swpaul * If there was a transmit underrun, 132752426Swpaul * bump the TX threshold. 132852426Swpaul */ 132952426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 133052426Swpaul sc->rl_txthresh = oldthresh + 32; 133152426Swpaul return; 133245633Swpaul } 133345633Swpaul RL_INC(sc->rl_cdata.last_tx); 133445633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 133545633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 133640516Swpaul 133799165Sluigi ifp->if_timer = 133899165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 133999165Sluigi 134050703Swpaul return; 134150703Swpaul} 134240516Swpaul 134350703Swpaulstatic void rl_tick(xsc) 134450703Swpaul void *xsc; 134550703Swpaul{ 134650703Swpaul struct rl_softc *sc; 134750703Swpaul struct mii_data *mii; 134850703Swpaul 134950703Swpaul sc = xsc; 135067087Swpaul RL_LOCK(sc); 135150703Swpaul mii = device_get_softc(sc->rl_miibus); 135250703Swpaul 135350703Swpaul mii_tick(mii); 135450703Swpaul 135550703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 135667087Swpaul RL_UNLOCK(sc); 135750703Swpaul 135840516Swpaul return; 135940516Swpaul} 136040516Swpaul 136194883Sluigi#ifdef DEVICE_POLLING 136294883Sluigistatic void 136394883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 136494883Sluigi{ 136594883Sluigi struct rl_softc *sc = ifp->if_softc; 136694883Sluigi 136794883Sluigi RL_LOCK(sc); 136894883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 136994883Sluigi CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 137094883Sluigi goto done; 137194883Sluigi } 137294883Sluigi 137394883Sluigi sc->rxcycles = count; 137494883Sluigi rl_rxeof(sc); 137594883Sluigi rl_txeof(sc); 137694883Sluigi if (ifp->if_snd.ifq_head != NULL) 137794883Sluigi rl_start(ifp); 137894883Sluigi 137994883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 138094883Sluigi u_int16_t status; 138194883Sluigi 138294883Sluigi status = CSR_READ_2(sc, RL_ISR); 138394883Sluigi if (status) 138494883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 138594883Sluigi 138694883Sluigi /* 138794883Sluigi * XXX check behaviour on receiver stalls. 138894883Sluigi */ 138994883Sluigi 139094883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 139194883Sluigi rl_reset(sc); 139294883Sluigi rl_init(sc); 139394883Sluigi } 139494883Sluigi } 139594883Sluigidone: 139694883Sluigi RL_UNLOCK(sc); 139794883Sluigi} 139894883Sluigi#endif /* DEVICE_POLLING */ 139994883Sluigi 140040516Swpaulstatic void rl_intr(arg) 140140516Swpaul void *arg; 140240516Swpaul{ 140340516Swpaul struct rl_softc *sc; 140440516Swpaul struct ifnet *ifp; 140540516Swpaul u_int16_t status; 140640516Swpaul 140740516Swpaul sc = arg; 140886822Siwasaki 140986822Siwasaki if (sc->suspended) { 141086822Siwasaki return; 141186822Siwasaki } 141286822Siwasaki 141367087Swpaul RL_LOCK(sc); 141440516Swpaul ifp = &sc->arpcom.ac_if; 141540516Swpaul 141694883Sluigi#ifdef DEVICE_POLLING 141794883Sluigi if (ifp->if_ipending & IFF_POLLING) 141894883Sluigi goto done; 141994883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 142094883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 142194883Sluigi rl_poll(ifp, 0, 1); 142294883Sluigi goto done; 142394883Sluigi } 142494883Sluigi#endif /* DEVICE_POLLING */ 142540516Swpaul 142640516Swpaul for (;;) { 142740516Swpaul 142840516Swpaul status = CSR_READ_2(sc, RL_ISR); 142940516Swpaul if (status) 143040516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 143140516Swpaul 143240516Swpaul if ((status & RL_INTRS) == 0) 143340516Swpaul break; 143440516Swpaul 143540516Swpaul if (status & RL_ISR_RX_OK) 143640516Swpaul rl_rxeof(sc); 143740516Swpaul 143840516Swpaul if (status & RL_ISR_RX_ERR) 143940516Swpaul rl_rxeof(sc); 144040516Swpaul 144145633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 144240516Swpaul rl_txeof(sc); 144340516Swpaul 144440516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 144540516Swpaul rl_reset(sc); 144640516Swpaul rl_init(sc); 144740516Swpaul } 144840516Swpaul 144940516Swpaul } 145040516Swpaul 145152426Swpaul if (ifp->if_snd.ifq_head != NULL) 145240516Swpaul rl_start(ifp); 145340516Swpaul 145494883Sluigi#ifdef DEVICE_POLLING 145594883Sluigidone: 145694883Sluigi#endif 145767087Swpaul RL_UNLOCK(sc); 145867087Swpaul 145940516Swpaul return; 146040516Swpaul} 146140516Swpaul 146240516Swpaul/* 146340516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 146440516Swpaul * pointers to the fragment pointers. 146540516Swpaul */ 146645633Swpaulstatic int rl_encap(sc, m_head) 146740516Swpaul struct rl_softc *sc; 146840516Swpaul struct mbuf *m_head; 146940516Swpaul{ 147041243Swpaul struct mbuf *m_new = NULL; 147140516Swpaul 147240516Swpaul /* 147345633Swpaul * The RealTek is brain damaged and wants longword-aligned 147445633Swpaul * TX buffers, plus we can only have one fragment buffer 147545633Swpaul * per packet. We have to copy pretty much all the time. 147640516Swpaul */ 147740516Swpaul 147841243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 147987846Sluigi if (m_new == NULL) 148041243Swpaul return(1); 148141243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 148241243Swpaul MCLGET(m_new, M_DONTWAIT); 148341243Swpaul if (!(m_new->m_flags & M_EXT)) { 148441243Swpaul m_freem(m_new); 148540516Swpaul return(1); 148640516Swpaul } 148740516Swpaul } 148852426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 148941243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 149041243Swpaul m_freem(m_head); 149141243Swpaul m_head = m_new; 149240516Swpaul 149340516Swpaul /* Pad frames to at least 60 bytes. */ 149441243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 149555058Swpaul /* 149655058Swpaul * Make security concious people happy: zero out the 149755058Swpaul * bytes in the pad area, since we don't know what 149855058Swpaul * this mbuf cluster buffer's previous user might 149955058Swpaul * have left in it. 150055058Swpaul */ 150155058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 150255058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 150340516Swpaul m_head->m_pkthdr.len += 150452426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 150541243Swpaul m_head->m_len = m_head->m_pkthdr.len; 150641243Swpaul } 150740516Swpaul 150845633Swpaul RL_CUR_TXMBUF(sc) = m_head; 150940516Swpaul 151040516Swpaul return(0); 151140516Swpaul} 151240516Swpaul 151340516Swpaul/* 151440516Swpaul * Main transmit routine. 151540516Swpaul */ 151640516Swpaul 151740516Swpaulstatic void rl_start(ifp) 151840516Swpaul struct ifnet *ifp; 151940516Swpaul{ 152040516Swpaul struct rl_softc *sc; 152140516Swpaul struct mbuf *m_head = NULL; 152240516Swpaul 152340516Swpaul sc = ifp->if_softc; 152467087Swpaul RL_LOCK(sc); 152540516Swpaul 152645633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 152740516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 152840516Swpaul if (m_head == NULL) 152940516Swpaul break; 153040516Swpaul 153158801Swpaul if (rl_encap(sc, m_head)) { 153258801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 153358801Swpaul ifp->if_flags |= IFF_OACTIVE; 153458801Swpaul break; 153558801Swpaul } 153640516Swpaul 153740516Swpaul /* 153840516Swpaul * If there's a BPF listener, bounce a copy of this frame 153940516Swpaul * to him. 154040516Swpaul */ 154140516Swpaul if (ifp->if_bpf) 154245633Swpaul bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 154351583Swpaul 154440516Swpaul /* 154540516Swpaul * Transmit the frame. 154640516Swpaul */ 154781713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 154881713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 154981713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 155081713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 155181713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 155281713Swpaul BUS_DMASYNC_PREREAD); 155345633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 155452426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 155552426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 155645633Swpaul 155745633Swpaul RL_INC(sc->rl_cdata.cur_tx); 155840516Swpaul } 155940516Swpaul 156040516Swpaul /* 156145633Swpaul * We broke out of the loop because all our TX slots are 156245633Swpaul * full. Mark the NIC as busy until it drains some of the 156345633Swpaul * packets from the queue. 156445633Swpaul */ 156545633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 156645633Swpaul ifp->if_flags |= IFF_OACTIVE; 156745633Swpaul 156845633Swpaul /* 156940516Swpaul * Set a timeout in case the chip goes out to lunch. 157040516Swpaul */ 157140516Swpaul ifp->if_timer = 5; 157267087Swpaul RL_UNLOCK(sc); 157340516Swpaul 157440516Swpaul return; 157540516Swpaul} 157640516Swpaul 157740516Swpaulstatic void rl_init(xsc) 157840516Swpaul void *xsc; 157940516Swpaul{ 158040516Swpaul struct rl_softc *sc = xsc; 158140516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 158250703Swpaul struct mii_data *mii; 158367087Swpaul int i; 158440516Swpaul u_int32_t rxcfg = 0; 158540516Swpaul 158667087Swpaul RL_LOCK(sc); 158750703Swpaul mii = device_get_softc(sc->rl_miibus); 158840516Swpaul 158940516Swpaul /* 159040516Swpaul * Cancel pending I/O and free all RX/TX buffers. 159140516Swpaul */ 159240516Swpaul rl_stop(sc); 159340516Swpaul 159440516Swpaul /* Init our MAC address */ 159540516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 159640516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 159740516Swpaul } 159840516Swpaul 159940516Swpaul /* Init the RX buffer pointer register. */ 160081713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 160181713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 160281713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 160381713Swpaul BUS_DMASYNC_PREWRITE); 160440516Swpaul 160540516Swpaul /* Init TX descriptors. */ 160640516Swpaul rl_list_tx_init(sc); 160740516Swpaul 160840516Swpaul /* 160940516Swpaul * Enable transmit and receive. 161040516Swpaul */ 161140516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 161240516Swpaul 161340516Swpaul /* 161445633Swpaul * Set the initial TX and RX configuration. 161540516Swpaul */ 161645633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 161740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 161840516Swpaul 161940516Swpaul /* Set the individual bit to receive frames for this host only. */ 162040516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 162140516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 162240516Swpaul 162340516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 162440516Swpaul if (ifp->if_flags & IFF_PROMISC) { 162540516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 162640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 162740516Swpaul } else { 162840516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 162940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 163040516Swpaul } 163140516Swpaul 163240516Swpaul /* 163340516Swpaul * Set capture broadcast bit to capture broadcast frames. 163440516Swpaul */ 163540516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 163640516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 163740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 163840516Swpaul } else { 163940516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 164040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 164140516Swpaul } 164240516Swpaul 164340516Swpaul /* 164440516Swpaul * Program the multicast filter, if necessary. 164540516Swpaul */ 164640516Swpaul rl_setmulti(sc); 164740516Swpaul 164894883Sluigi#ifdef DEVICE_POLLING 164940516Swpaul /* 165094883Sluigi * Disable interrupts if we are polling. 165194883Sluigi */ 165294883Sluigi if (ifp->if_ipending & IFF_POLLING) 165394883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 165494883Sluigi else /* otherwise ... */ 165594883Sluigi#endif /* DEVICE_POLLING */ 165694883Sluigi /* 165740516Swpaul * Enable interrupts. 165840516Swpaul */ 165940516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 166040516Swpaul 166152426Swpaul /* Set initial TX threshold */ 166252426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 166352426Swpaul 166440516Swpaul /* Start RX/TX process. */ 166540516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 166640516Swpaul 166740516Swpaul /* Enable receiver and transmitter. */ 166840516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 166940516Swpaul 167050703Swpaul mii_mediachg(mii); 167140516Swpaul 167240516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 167340516Swpaul 167440516Swpaul ifp->if_flags |= IFF_RUNNING; 167540516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 167640516Swpaul 167750703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 167867087Swpaul RL_UNLOCK(sc); 167950703Swpaul 168040516Swpaul return; 168140516Swpaul} 168240516Swpaul 168340516Swpaul/* 168440516Swpaul * Set media options. 168540516Swpaul */ 168640516Swpaulstatic int rl_ifmedia_upd(ifp) 168740516Swpaul struct ifnet *ifp; 168840516Swpaul{ 168940516Swpaul struct rl_softc *sc; 169050703Swpaul struct mii_data *mii; 169140516Swpaul 169240516Swpaul sc = ifp->if_softc; 169350703Swpaul mii = device_get_softc(sc->rl_miibus); 169450703Swpaul mii_mediachg(mii); 169540516Swpaul 169640516Swpaul return(0); 169740516Swpaul} 169840516Swpaul 169940516Swpaul/* 170040516Swpaul * Report current media status. 170140516Swpaul */ 170240516Swpaulstatic void rl_ifmedia_sts(ifp, ifmr) 170340516Swpaul struct ifnet *ifp; 170440516Swpaul struct ifmediareq *ifmr; 170540516Swpaul{ 170640516Swpaul struct rl_softc *sc; 170750703Swpaul struct mii_data *mii; 170840516Swpaul 170940516Swpaul sc = ifp->if_softc; 171050703Swpaul mii = device_get_softc(sc->rl_miibus); 171140516Swpaul 171250703Swpaul mii_pollstat(mii); 171350703Swpaul ifmr->ifm_active = mii->mii_media_active; 171450703Swpaul ifmr->ifm_status = mii->mii_media_status; 171540516Swpaul 171640516Swpaul return; 171740516Swpaul} 171840516Swpaul 171940516Swpaulstatic int rl_ioctl(ifp, command, data) 172040516Swpaul struct ifnet *ifp; 172140516Swpaul u_long command; 172240516Swpaul caddr_t data; 172340516Swpaul{ 172440516Swpaul struct rl_softc *sc = ifp->if_softc; 172540516Swpaul struct ifreq *ifr = (struct ifreq *) data; 172650703Swpaul struct mii_data *mii; 172767087Swpaul int error = 0; 172840516Swpaul 172967087Swpaul RL_LOCK(sc); 173040516Swpaul 173140516Swpaul switch(command) { 173240516Swpaul case SIOCSIFADDR: 173340516Swpaul case SIOCGIFADDR: 173440516Swpaul case SIOCSIFMTU: 173540516Swpaul error = ether_ioctl(ifp, command, data); 173640516Swpaul break; 173740516Swpaul case SIOCSIFFLAGS: 173840516Swpaul if (ifp->if_flags & IFF_UP) { 173940516Swpaul rl_init(sc); 174040516Swpaul } else { 174140516Swpaul if (ifp->if_flags & IFF_RUNNING) 174240516Swpaul rl_stop(sc); 174340516Swpaul } 174440516Swpaul error = 0; 174540516Swpaul break; 174640516Swpaul case SIOCADDMULTI: 174740516Swpaul case SIOCDELMULTI: 174840516Swpaul rl_setmulti(sc); 174940516Swpaul error = 0; 175040516Swpaul break; 175140516Swpaul case SIOCGIFMEDIA: 175240516Swpaul case SIOCSIFMEDIA: 175350703Swpaul mii = device_get_softc(sc->rl_miibus); 175450703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 175540516Swpaul break; 175640516Swpaul default: 175740516Swpaul error = EINVAL; 175840516Swpaul break; 175940516Swpaul } 176040516Swpaul 176167087Swpaul RL_UNLOCK(sc); 176240516Swpaul 176340516Swpaul return(error); 176440516Swpaul} 176540516Swpaul 176640516Swpaulstatic void rl_watchdog(ifp) 176740516Swpaul struct ifnet *ifp; 176840516Swpaul{ 176940516Swpaul struct rl_softc *sc; 177040516Swpaul 177140516Swpaul sc = ifp->if_softc; 177267087Swpaul RL_LOCK(sc); 177340516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 177440516Swpaul ifp->if_oerrors++; 177550703Swpaul 177640516Swpaul rl_txeof(sc); 177740516Swpaul rl_rxeof(sc); 177840516Swpaul rl_init(sc); 177967087Swpaul RL_UNLOCK(sc); 178040516Swpaul 178140516Swpaul return; 178240516Swpaul} 178340516Swpaul 178440516Swpaul/* 178540516Swpaul * Stop the adapter and free any mbufs allocated to the 178640516Swpaul * RX and TX lists. 178740516Swpaul */ 178840516Swpaulstatic void rl_stop(sc) 178940516Swpaul struct rl_softc *sc; 179040516Swpaul{ 179140516Swpaul register int i; 179240516Swpaul struct ifnet *ifp; 179340516Swpaul 179467087Swpaul RL_LOCK(sc); 179540516Swpaul ifp = &sc->arpcom.ac_if; 179640516Swpaul ifp->if_timer = 0; 179740516Swpaul 179850703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 179994883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 180094883Sluigi#ifdef DEVICE_POLLING 180194883Sluigi ether_poll_deregister(ifp); 180294883Sluigi#endif /* DEVICE_POLLING */ 180350703Swpaul 180440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 180540516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 180681713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 180740516Swpaul 180840516Swpaul /* 180940516Swpaul * Free the TX list buffers. 181040516Swpaul */ 181140516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 181245633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 181381713Swpaul bus_dmamap_unload(sc->rl_tag, 181481713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 181581713Swpaul bus_dmamap_destroy(sc->rl_tag, 181681713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 181745633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 181845633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 181945633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 182040516Swpaul } 182140516Swpaul } 182240516Swpaul 182367087Swpaul RL_UNLOCK(sc); 182440516Swpaul return; 182540516Swpaul} 182640516Swpaul 182740516Swpaul/* 182886822Siwasaki * Device suspend routine. Stop the interface and save some PCI 182986822Siwasaki * settings in case the BIOS doesn't restore them properly on 183086822Siwasaki * resume. 183186822Siwasaki */ 183286822Siwasakistatic int rl_suspend(dev) 183386822Siwasaki device_t dev; 183486822Siwasaki{ 183586822Siwasaki register int i; 183686822Siwasaki struct rl_softc *sc; 183786822Siwasaki 183886822Siwasaki sc = device_get_softc(dev); 183986822Siwasaki 184086822Siwasaki rl_stop(sc); 184186822Siwasaki 184286822Siwasaki for (i = 0; i < 5; i++) 184386822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 184486822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 184586822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 184686822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 184786822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 184886822Siwasaki 184986822Siwasaki sc->suspended = 1; 185086822Siwasaki 185186822Siwasaki return (0); 185286822Siwasaki} 185386822Siwasaki 185486822Siwasaki/* 185586822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 185686822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 185786822Siwasaki * appropriate. 185886822Siwasaki */ 185986822Siwasakistatic int rl_resume(dev) 186086822Siwasaki device_t dev; 186186822Siwasaki{ 186286822Siwasaki register int i; 186386822Siwasaki struct rl_softc *sc; 186486822Siwasaki struct ifnet *ifp; 186586822Siwasaki 186686822Siwasaki sc = device_get_softc(dev); 186786822Siwasaki ifp = &sc->arpcom.ac_if; 186886822Siwasaki 186986822Siwasaki /* better way to do this? */ 187086822Siwasaki for (i = 0; i < 5; i++) 187186822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 187286822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 187386822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 187486822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 187586822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 187686822Siwasaki 187786822Siwasaki /* reenable busmastering */ 187886822Siwasaki pci_enable_busmaster(dev); 187986822Siwasaki pci_enable_io(dev, RL_RES); 188086822Siwasaki 188186822Siwasaki /* reinitialize interface if necessary */ 188286822Siwasaki if (ifp->if_flags & IFF_UP) 188386822Siwasaki rl_init(sc); 188486822Siwasaki 188586822Siwasaki sc->suspended = 0; 188686822Siwasaki 188786822Siwasaki return (0); 188886822Siwasaki} 188986822Siwasaki 189086822Siwasaki/* 189140516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 189240516Swpaul * get confused by errant DMAs when rebooting. 189340516Swpaul */ 189450703Swpaulstatic void rl_shutdown(dev) 189550703Swpaul device_t dev; 189640516Swpaul{ 189750703Swpaul struct rl_softc *sc; 189840516Swpaul 189950703Swpaul sc = device_get_softc(dev); 190050703Swpaul 190140516Swpaul rl_stop(sc); 190240516Swpaul 190340516Swpaul return; 190440516Swpaul} 1905