if_rl.c revision 94149
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 94149 2002-04-07 20:55:50Z wpaul $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 8740516Swpaul#include <sys/systm.h> 8840516Swpaul#include <sys/sockio.h> 8940516Swpaul#include <sys/mbuf.h> 9040516Swpaul#include <sys/malloc.h> 9140516Swpaul#include <sys/kernel.h> 9240516Swpaul#include <sys/socket.h> 9340516Swpaul 9440516Swpaul#include <net/if.h> 9540516Swpaul#include <net/if_arp.h> 9640516Swpaul#include <net/ethernet.h> 9740516Swpaul#include <net/if_dl.h> 9840516Swpaul#include <net/if_media.h> 9940516Swpaul 10040516Swpaul#include <net/bpf.h> 10140516Swpaul 10241569Swpaul#include <machine/bus_pio.h> 10341569Swpaul#include <machine/bus_memio.h> 10441569Swpaul#include <machine/bus.h> 10550703Swpaul#include <machine/resource.h> 10650703Swpaul#include <sys/bus.h> 10750703Swpaul#include <sys/rman.h> 10840516Swpaul 10950703Swpaul#include <dev/mii/mii.h> 11050703Swpaul#include <dev/mii/miivar.h> 11150703Swpaul 11240516Swpaul#include <pci/pcireg.h> 11340516Swpaul#include <pci/pcivar.h> 11440516Swpaul 11559758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11659758Speter 11751089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11850703Swpaul#include "miibus_if.h" 11950703Swpaul 12040516Swpaul/* 12140516Swpaul * Default to using PIO access for this driver. On SMP systems, 12240516Swpaul * there appear to be problems with memory mapped mode: it looks like 12340516Swpaul * doing too many memory mapped access back to back in rapid succession 12440516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12540516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12640516Swpaul * uniprocessor systems though. 12740516Swpaul */ 12840516Swpaul#define RL_USEIOSPACE 12940516Swpaul 13040516Swpaul#include <pci/if_rlreg.h> 13140516Swpaul 13240516Swpaul#ifndef lint 13341591Sarchiestatic const char rcsid[] = 13450477Speter "$FreeBSD: head/sys/pci/if_rl.c 94149 2002-04-07 20:55:50Z wpaul $"; 13540516Swpaul#endif 13640516Swpaul 13740516Swpaul/* 13840516Swpaul * Various supported device vendors/types and their names. 13940516Swpaul */ 14040516Swpaulstatic struct rl_type rl_devs[] = { 14140516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14240516Swpaul "RealTek 8129 10/100BaseTX" }, 14340516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14440516Swpaul "RealTek 8139 10/100BaseTX" }, 14567771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14667771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14741243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14841243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14944238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15044238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15144238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15244238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15372813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15472813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15540516Swpaul { 0, 0, NULL } 15640516Swpaul}; 15740516Swpaul 15892739Salfredstatic int rl_probe (device_t); 15992739Salfredstatic int rl_attach (device_t); 16092739Salfredstatic int rl_detach (device_t); 16140516Swpaul 16292739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 16340516Swpaul 16492739Salfredstatic void rl_rxeof (struct rl_softc *); 16592739Salfredstatic void rl_txeof (struct rl_softc *); 16692739Salfredstatic void rl_intr (void *); 16792739Salfredstatic void rl_tick (void *); 16892739Salfredstatic void rl_start (struct ifnet *); 16992739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17092739Salfredstatic void rl_init (void *); 17192739Salfredstatic void rl_stop (struct rl_softc *); 17292739Salfredstatic void rl_watchdog (struct ifnet *); 17392739Salfredstatic int rl_suspend (device_t); 17492739Salfredstatic int rl_resume (device_t); 17592739Salfredstatic void rl_shutdown (device_t); 17692739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 17792739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 17840516Swpaul 17992739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18092739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 18192739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 18292739Salfredstatic void rl_mii_sync (struct rl_softc *); 18392739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 18492739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 18592739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 18640516Swpaul 18792739Salfredstatic int rl_miibus_readreg (device_t, int, int); 18892739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 18992739Salfredstatic void rl_miibus_statchg (device_t); 19040516Swpaul 19192739Salfredstatic u_int8_t rl_calchash (caddr_t); 19292739Salfredstatic void rl_setmulti (struct rl_softc *); 19392739Salfredstatic void rl_reset (struct rl_softc *); 19492739Salfredstatic int rl_list_tx_init (struct rl_softc *); 19540516Swpaul 19692739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 19792739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 19881713Swpaul 19950703Swpaul#ifdef RL_USEIOSPACE 20050703Swpaul#define RL_RES SYS_RES_IOPORT 20150703Swpaul#define RL_RID RL_PCI_LOIO 20250703Swpaul#else 20350703Swpaul#define RL_RES SYS_RES_MEMORY 20450703Swpaul#define RL_RID RL_PCI_LOMEM 20550703Swpaul#endif 20650703Swpaul 20750703Swpaulstatic device_method_t rl_methods[] = { 20850703Swpaul /* Device interface */ 20950703Swpaul DEVMETHOD(device_probe, rl_probe), 21050703Swpaul DEVMETHOD(device_attach, rl_attach), 21150703Swpaul DEVMETHOD(device_detach, rl_detach), 21286822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 21386822Siwasaki DEVMETHOD(device_resume, rl_resume), 21450703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 21550703Swpaul 21650703Swpaul /* bus interface */ 21750703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 21850703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 21950703Swpaul 22050703Swpaul /* MII interface */ 22150703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 22250703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 22350703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 22450703Swpaul 22550703Swpaul { 0, 0 } 22650703Swpaul}; 22750703Swpaul 22850703Swpaulstatic driver_t rl_driver = { 22951455Swpaul "rl", 23050703Swpaul rl_methods, 23150703Swpaul sizeof(struct rl_softc) 23250703Swpaul}; 23350703Swpaul 23450703Swpaulstatic devclass_t rl_devclass; 23550703Swpaul 23651533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 23767931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 23851473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 23950703Swpaul 24040516Swpaul#define EE_SET(x) \ 24140516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24240516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 24340516Swpaul 24440516Swpaul#define EE_CLR(x) \ 24540516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24640516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 24740516Swpaul 24881713Swpaulstatic void 24981713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25081713Swpaul void *arg; 25181713Swpaul bus_dma_segment_t *segs; 25281713Swpaul int nseg, error; 25381713Swpaul{ 25481713Swpaul struct rl_softc *sc; 25581713Swpaul 25681713Swpaul sc = arg; 25781713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 25881713Swpaul 25981713Swpaul return; 26081713Swpaul} 26181713Swpaul 26281713Swpaulstatic void 26381713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 26481713Swpaul void *arg; 26581713Swpaul bus_dma_segment_t *segs; 26681713Swpaul int nseg, error; 26781713Swpaul{ 26881713Swpaul struct rl_softc *sc; 26981713Swpaul 27081713Swpaul sc = arg; 27181713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 27281713Swpaul 27381713Swpaul return; 27481713Swpaul} 27581713Swpaul 27640516Swpaul/* 27740516Swpaul * Send a read command and address to the EEPROM, check for ACK. 27840516Swpaul */ 27940516Swpaulstatic void rl_eeprom_putbyte(sc, addr) 28040516Swpaul struct rl_softc *sc; 28141656Swpaul int addr; 28240516Swpaul{ 28340516Swpaul register int d, i; 28440516Swpaul 28567931Swpaul d = addr | sc->rl_eecmd_read; 28640516Swpaul 28740516Swpaul /* 28855170Sbillf * Feed in each bit and strobe the clock. 28940516Swpaul */ 29040516Swpaul for (i = 0x400; i; i >>= 1) { 29140516Swpaul if (d & i) { 29240516Swpaul EE_SET(RL_EE_DATAIN); 29340516Swpaul } else { 29440516Swpaul EE_CLR(RL_EE_DATAIN); 29540516Swpaul } 29640516Swpaul DELAY(100); 29740516Swpaul EE_SET(RL_EE_CLK); 29840516Swpaul DELAY(150); 29940516Swpaul EE_CLR(RL_EE_CLK); 30040516Swpaul DELAY(100); 30140516Swpaul } 30240516Swpaul 30340516Swpaul return; 30440516Swpaul} 30540516Swpaul 30640516Swpaul/* 30740516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 30840516Swpaul */ 30940516Swpaulstatic void rl_eeprom_getword(sc, addr, dest) 31040516Swpaul struct rl_softc *sc; 31141656Swpaul int addr; 31240516Swpaul u_int16_t *dest; 31340516Swpaul{ 31440516Swpaul register int i; 31540516Swpaul u_int16_t word = 0; 31640516Swpaul 31740516Swpaul /* Enter EEPROM access mode. */ 31840516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 31940516Swpaul 32040516Swpaul /* 32140516Swpaul * Send address of word we want to read. 32240516Swpaul */ 32340516Swpaul rl_eeprom_putbyte(sc, addr); 32440516Swpaul 32540516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32640516Swpaul 32740516Swpaul /* 32840516Swpaul * Start reading bits from EEPROM. 32940516Swpaul */ 33040516Swpaul for (i = 0x8000; i; i >>= 1) { 33140516Swpaul EE_SET(RL_EE_CLK); 33240516Swpaul DELAY(100); 33340516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 33440516Swpaul word |= i; 33540516Swpaul EE_CLR(RL_EE_CLK); 33640516Swpaul DELAY(100); 33740516Swpaul } 33840516Swpaul 33940516Swpaul /* Turn off EEPROM access mode. */ 34040516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 34140516Swpaul 34240516Swpaul *dest = word; 34340516Swpaul 34440516Swpaul return; 34540516Swpaul} 34640516Swpaul 34740516Swpaul/* 34840516Swpaul * Read a sequence of words from the EEPROM. 34940516Swpaul */ 35040516Swpaulstatic void rl_read_eeprom(sc, dest, off, cnt, swap) 35140516Swpaul struct rl_softc *sc; 35240516Swpaul caddr_t dest; 35340516Swpaul int off; 35440516Swpaul int cnt; 35540516Swpaul int swap; 35640516Swpaul{ 35740516Swpaul int i; 35840516Swpaul u_int16_t word = 0, *ptr; 35940516Swpaul 36040516Swpaul for (i = 0; i < cnt; i++) { 36140516Swpaul rl_eeprom_getword(sc, off + i, &word); 36240516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 36340516Swpaul if (swap) 36440516Swpaul *ptr = ntohs(word); 36540516Swpaul else 36640516Swpaul *ptr = word; 36740516Swpaul } 36840516Swpaul 36940516Swpaul return; 37040516Swpaul} 37140516Swpaul 37240516Swpaul 37340516Swpaul/* 37440516Swpaul * MII access routines are provided for the 8129, which 37540516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 37640516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 37740516Swpaul * direct access PHY registers. 37840516Swpaul */ 37940516Swpaul#define MII_SET(x) \ 38040516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38140516Swpaul CSR_READ_1(sc, RL_MII) | x) 38240516Swpaul 38340516Swpaul#define MII_CLR(x) \ 38440516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38540516Swpaul CSR_READ_1(sc, RL_MII) & ~x) 38640516Swpaul 38740516Swpaul/* 38840516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 38940516Swpaul */ 39040516Swpaulstatic void rl_mii_sync(sc) 39140516Swpaul struct rl_softc *sc; 39240516Swpaul{ 39340516Swpaul register int i; 39440516Swpaul 39540516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 39640516Swpaul 39740516Swpaul for (i = 0; i < 32; i++) { 39840516Swpaul MII_SET(RL_MII_CLK); 39940516Swpaul DELAY(1); 40040516Swpaul MII_CLR(RL_MII_CLK); 40140516Swpaul DELAY(1); 40240516Swpaul } 40340516Swpaul 40440516Swpaul return; 40540516Swpaul} 40640516Swpaul 40740516Swpaul/* 40840516Swpaul * Clock a series of bits through the MII. 40940516Swpaul */ 41040516Swpaulstatic void rl_mii_send(sc, bits, cnt) 41140516Swpaul struct rl_softc *sc; 41240516Swpaul u_int32_t bits; 41340516Swpaul int cnt; 41440516Swpaul{ 41540516Swpaul int i; 41640516Swpaul 41740516Swpaul MII_CLR(RL_MII_CLK); 41840516Swpaul 41940516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 42040516Swpaul if (bits & i) { 42140516Swpaul MII_SET(RL_MII_DATAOUT); 42240516Swpaul } else { 42340516Swpaul MII_CLR(RL_MII_DATAOUT); 42440516Swpaul } 42540516Swpaul DELAY(1); 42640516Swpaul MII_CLR(RL_MII_CLK); 42740516Swpaul DELAY(1); 42840516Swpaul MII_SET(RL_MII_CLK); 42940516Swpaul } 43040516Swpaul} 43140516Swpaul 43240516Swpaul/* 43340516Swpaul * Read an PHY register through the MII. 43440516Swpaul */ 43540516Swpaulstatic int rl_mii_readreg(sc, frame) 43640516Swpaul struct rl_softc *sc; 43740516Swpaul struct rl_mii_frame *frame; 43840516Swpaul 43940516Swpaul{ 44067087Swpaul int i, ack; 44140516Swpaul 44267087Swpaul RL_LOCK(sc); 44340516Swpaul 44440516Swpaul /* 44540516Swpaul * Set up frame for RX. 44640516Swpaul */ 44740516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 44840516Swpaul frame->mii_opcode = RL_MII_READOP; 44940516Swpaul frame->mii_turnaround = 0; 45040516Swpaul frame->mii_data = 0; 45140516Swpaul 45240516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 45340516Swpaul 45440516Swpaul /* 45540516Swpaul * Turn on data xmit. 45640516Swpaul */ 45740516Swpaul MII_SET(RL_MII_DIR); 45840516Swpaul 45940516Swpaul rl_mii_sync(sc); 46040516Swpaul 46140516Swpaul /* 46240516Swpaul * Send command/address info. 46340516Swpaul */ 46440516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 46540516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 46640516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 46740516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 46840516Swpaul 46940516Swpaul /* Idle bit */ 47040516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 47140516Swpaul DELAY(1); 47240516Swpaul MII_SET(RL_MII_CLK); 47340516Swpaul DELAY(1); 47440516Swpaul 47540516Swpaul /* Turn off xmit. */ 47640516Swpaul MII_CLR(RL_MII_DIR); 47740516Swpaul 47840516Swpaul /* Check for ack */ 47940516Swpaul MII_CLR(RL_MII_CLK); 48040516Swpaul DELAY(1); 48140516Swpaul MII_SET(RL_MII_CLK); 48240516Swpaul DELAY(1); 48340516Swpaul ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 48440516Swpaul 48540516Swpaul /* 48640516Swpaul * Now try reading data bits. If the ack failed, we still 48740516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 48840516Swpaul */ 48940516Swpaul if (ack) { 49040516Swpaul for(i = 0; i < 16; i++) { 49140516Swpaul MII_CLR(RL_MII_CLK); 49240516Swpaul DELAY(1); 49340516Swpaul MII_SET(RL_MII_CLK); 49440516Swpaul DELAY(1); 49540516Swpaul } 49640516Swpaul goto fail; 49740516Swpaul } 49840516Swpaul 49940516Swpaul for (i = 0x8000; i; i >>= 1) { 50040516Swpaul MII_CLR(RL_MII_CLK); 50140516Swpaul DELAY(1); 50240516Swpaul if (!ack) { 50340516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 50440516Swpaul frame->mii_data |= i; 50540516Swpaul DELAY(1); 50640516Swpaul } 50740516Swpaul MII_SET(RL_MII_CLK); 50840516Swpaul DELAY(1); 50940516Swpaul } 51040516Swpaul 51140516Swpaulfail: 51240516Swpaul 51340516Swpaul MII_CLR(RL_MII_CLK); 51440516Swpaul DELAY(1); 51540516Swpaul MII_SET(RL_MII_CLK); 51640516Swpaul DELAY(1); 51740516Swpaul 51867087Swpaul RL_UNLOCK(sc); 51940516Swpaul 52040516Swpaul if (ack) 52140516Swpaul return(1); 52240516Swpaul return(0); 52340516Swpaul} 52440516Swpaul 52540516Swpaul/* 52640516Swpaul * Write to a PHY register through the MII. 52740516Swpaul */ 52840516Swpaulstatic int rl_mii_writereg(sc, frame) 52940516Swpaul struct rl_softc *sc; 53040516Swpaul struct rl_mii_frame *frame; 53140516Swpaul 53240516Swpaul{ 53367087Swpaul RL_LOCK(sc); 53440516Swpaul 53540516Swpaul /* 53640516Swpaul * Set up frame for TX. 53740516Swpaul */ 53840516Swpaul 53940516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 54040516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 54140516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 54240516Swpaul 54340516Swpaul /* 54440516Swpaul * Turn on data output. 54540516Swpaul */ 54640516Swpaul MII_SET(RL_MII_DIR); 54740516Swpaul 54840516Swpaul rl_mii_sync(sc); 54940516Swpaul 55040516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 55140516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 55240516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 55340516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 55440516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 55540516Swpaul rl_mii_send(sc, frame->mii_data, 16); 55640516Swpaul 55740516Swpaul /* Idle bit. */ 55840516Swpaul MII_SET(RL_MII_CLK); 55940516Swpaul DELAY(1); 56040516Swpaul MII_CLR(RL_MII_CLK); 56140516Swpaul DELAY(1); 56240516Swpaul 56340516Swpaul /* 56440516Swpaul * Turn off xmit. 56540516Swpaul */ 56640516Swpaul MII_CLR(RL_MII_DIR); 56740516Swpaul 56867087Swpaul RL_UNLOCK(sc); 56940516Swpaul 57040516Swpaul return(0); 57140516Swpaul} 57240516Swpaul 57350703Swpaulstatic int rl_miibus_readreg(dev, phy, reg) 57450703Swpaul device_t dev; 57550703Swpaul int phy, reg; 57650703Swpaul{ 57740516Swpaul struct rl_softc *sc; 57840516Swpaul struct rl_mii_frame frame; 57940516Swpaul u_int16_t rval = 0; 58040516Swpaul u_int16_t rl8139_reg = 0; 58140516Swpaul 58250703Swpaul sc = device_get_softc(dev); 58367087Swpaul RL_LOCK(sc); 58450703Swpaul 58540516Swpaul if (sc->rl_type == RL_8139) { 58650703Swpaul /* Pretend the internal PHY is only at address 0 */ 58767087Swpaul if (phy) { 58867087Swpaul RL_UNLOCK(sc); 58950703Swpaul return(0); 59067087Swpaul } 59140516Swpaul switch(reg) { 59250703Swpaul case MII_BMCR: 59340516Swpaul rl8139_reg = RL_BMCR; 59440516Swpaul break; 59550703Swpaul case MII_BMSR: 59640516Swpaul rl8139_reg = RL_BMSR; 59740516Swpaul break; 59850703Swpaul case MII_ANAR: 59940516Swpaul rl8139_reg = RL_ANAR; 60040516Swpaul break; 60150703Swpaul case MII_ANER: 60250703Swpaul rl8139_reg = RL_ANER; 60350703Swpaul break; 60450703Swpaul case MII_ANLPAR: 60540516Swpaul rl8139_reg = RL_LPAR; 60640516Swpaul break; 60750703Swpaul case MII_PHYIDR1: 60850703Swpaul case MII_PHYIDR2: 60967087Swpaul RL_UNLOCK(sc); 61050703Swpaul return(0); 61150703Swpaul break; 61294149Swpaul /* 61394149Swpaul * Allow the rlphy driver to read the media status 61494149Swpaul * register. If we have a link partner which does not 61594149Swpaul * support NWAY, this is the register which will tell 61694149Swpaul * us the results of parallel detection. 61794149Swpaul */ 61894149Swpaul case RL_MEDIASTAT: 61994149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 62094149Swpaul RL_UNLOCK(sc); 62194149Swpaul return(rval); 62294149Swpaul break; 62340516Swpaul default: 62440516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 62567087Swpaul RL_UNLOCK(sc); 62640516Swpaul return(0); 62740516Swpaul } 62840516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 62967087Swpaul RL_UNLOCK(sc); 63040516Swpaul return(rval); 63140516Swpaul } 63240516Swpaul 63340516Swpaul bzero((char *)&frame, sizeof(frame)); 63440516Swpaul 63550703Swpaul frame.mii_phyaddr = phy; 63640516Swpaul frame.mii_regaddr = reg; 63740516Swpaul rl_mii_readreg(sc, &frame); 63867087Swpaul RL_UNLOCK(sc); 63940516Swpaul 64040516Swpaul return(frame.mii_data); 64140516Swpaul} 64240516Swpaul 64350703Swpaulstatic int rl_miibus_writereg(dev, phy, reg, data) 64450703Swpaul device_t dev; 64550703Swpaul int phy, reg, data; 64650703Swpaul{ 64740516Swpaul struct rl_softc *sc; 64840516Swpaul struct rl_mii_frame frame; 64940516Swpaul u_int16_t rl8139_reg = 0; 65040516Swpaul 65150703Swpaul sc = device_get_softc(dev); 65267087Swpaul RL_LOCK(sc); 65350703Swpaul 65440516Swpaul if (sc->rl_type == RL_8139) { 65550703Swpaul /* Pretend the internal PHY is only at address 0 */ 65667087Swpaul if (phy) { 65767087Swpaul RL_UNLOCK(sc); 65850703Swpaul return(0); 65967087Swpaul } 66040516Swpaul switch(reg) { 66150703Swpaul case MII_BMCR: 66240516Swpaul rl8139_reg = RL_BMCR; 66340516Swpaul break; 66450703Swpaul case MII_BMSR: 66540516Swpaul rl8139_reg = RL_BMSR; 66640516Swpaul break; 66750703Swpaul case MII_ANAR: 66840516Swpaul rl8139_reg = RL_ANAR; 66940516Swpaul break; 67050703Swpaul case MII_ANER: 67150703Swpaul rl8139_reg = RL_ANER; 67250703Swpaul break; 67350703Swpaul case MII_ANLPAR: 67440516Swpaul rl8139_reg = RL_LPAR; 67540516Swpaul break; 67650703Swpaul case MII_PHYIDR1: 67750703Swpaul case MII_PHYIDR2: 67867087Swpaul RL_UNLOCK(sc); 67950703Swpaul return(0); 68050703Swpaul break; 68140516Swpaul default: 68240516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 68367087Swpaul RL_UNLOCK(sc); 68450703Swpaul return(0); 68540516Swpaul } 68640516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 68767087Swpaul RL_UNLOCK(sc); 68850703Swpaul return(0); 68940516Swpaul } 69040516Swpaul 69140516Swpaul bzero((char *)&frame, sizeof(frame)); 69240516Swpaul 69350703Swpaul frame.mii_phyaddr = phy; 69440516Swpaul frame.mii_regaddr = reg; 69540516Swpaul frame.mii_data = data; 69640516Swpaul 69740516Swpaul rl_mii_writereg(sc, &frame); 69840516Swpaul 69967087Swpaul RL_UNLOCK(sc); 70050703Swpaul return(0); 70150703Swpaul} 70250703Swpaul 70350703Swpaulstatic void rl_miibus_statchg(dev) 70450703Swpaul device_t dev; 70550703Swpaul{ 70640516Swpaul return; 70740516Swpaul} 70840516Swpaul 70940516Swpaul/* 71043062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 71140516Swpaul */ 71240516Swpaulstatic u_int8_t rl_calchash(addr) 71341656Swpaul caddr_t addr; 71440516Swpaul{ 71540516Swpaul u_int32_t crc, carry; 71640516Swpaul int i, j; 71740516Swpaul u_int8_t c; 71840516Swpaul 71940516Swpaul /* Compute CRC for the address value. */ 72040516Swpaul crc = 0xFFFFFFFF; /* initial value */ 72140516Swpaul 72240516Swpaul for (i = 0; i < 6; i++) { 72340516Swpaul c = *(addr + i); 72440516Swpaul for (j = 0; j < 8; j++) { 72540516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 72640516Swpaul crc <<= 1; 72740516Swpaul c >>= 1; 72840516Swpaul if (carry) 72940516Swpaul crc = (crc ^ 0x04c11db6) | carry; 73040516Swpaul } 73140516Swpaul } 73240516Swpaul 73340516Swpaul /* return the filter bit position */ 73443062Swpaul return(crc >> 26); 73540516Swpaul} 73640516Swpaul 73740516Swpaul/* 73840516Swpaul * Program the 64-bit multicast hash filter. 73940516Swpaul */ 74040516Swpaulstatic void rl_setmulti(sc) 74140516Swpaul struct rl_softc *sc; 74240516Swpaul{ 74340516Swpaul struct ifnet *ifp; 74440516Swpaul int h = 0; 74540516Swpaul u_int32_t hashes[2] = { 0, 0 }; 74640516Swpaul struct ifmultiaddr *ifma; 74740516Swpaul u_int32_t rxfilt; 74840516Swpaul int mcnt = 0; 74940516Swpaul 75040516Swpaul ifp = &sc->arpcom.ac_if; 75140516Swpaul 75240516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 75340516Swpaul 75443062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 75540516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 75640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 75740516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 75840516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 75940516Swpaul return; 76040516Swpaul } 76140516Swpaul 76240516Swpaul /* first, zot all the existing hash bits */ 76340516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 76440516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 76540516Swpaul 76640516Swpaul /* now program new ones */ 76772084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 76840516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 76940516Swpaul continue; 77040516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 77140516Swpaul if (h < 32) 77240516Swpaul hashes[0] |= (1 << h); 77340516Swpaul else 77440516Swpaul hashes[1] |= (1 << (h - 32)); 77540516Swpaul mcnt++; 77640516Swpaul } 77740516Swpaul 77840516Swpaul if (mcnt) 77940516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 78040516Swpaul else 78140516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 78240516Swpaul 78340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 78440516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 78540516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 78640516Swpaul 78740516Swpaul return; 78840516Swpaul} 78940516Swpaul 79040516Swpaulstatic void rl_reset(sc) 79140516Swpaul struct rl_softc *sc; 79240516Swpaul{ 79340516Swpaul register int i; 79440516Swpaul 79540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 79640516Swpaul 79740516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 79840516Swpaul DELAY(10); 79940516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 80040516Swpaul break; 80140516Swpaul } 80240516Swpaul if (i == RL_TIMEOUT) 80340516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 80440516Swpaul 80540516Swpaul return; 80640516Swpaul} 80740516Swpaul 80840516Swpaul/* 80940516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 81040516Swpaul * IDs against our list and return a device name if we find a match. 81140516Swpaul */ 81250703Swpaulstatic int rl_probe(dev) 81350703Swpaul device_t dev; 81440516Swpaul{ 81540516Swpaul struct rl_type *t; 81640516Swpaul 81740516Swpaul t = rl_devs; 81840516Swpaul 81940516Swpaul while(t->rl_name != NULL) { 82050703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 82150703Swpaul (pci_get_device(dev) == t->rl_did)) { 82250703Swpaul device_set_desc(dev, t->rl_name); 82350703Swpaul return(0); 82440516Swpaul } 82540516Swpaul t++; 82640516Swpaul } 82740516Swpaul 82850703Swpaul return(ENXIO); 82940516Swpaul} 83040516Swpaul 83140516Swpaul/* 83240516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 83340516Swpaul * setup and ethernet/BPF attach. 83440516Swpaul */ 83550703Swpaulstatic int rl_attach(dev) 83650703Swpaul device_t dev; 83740516Swpaul{ 83840516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 83940516Swpaul u_int32_t command; 84040516Swpaul struct rl_softc *sc; 84140516Swpaul struct ifnet *ifp; 84240516Swpaul u_int16_t rl_did = 0; 84350703Swpaul int unit, error = 0, rid; 84440516Swpaul 84550703Swpaul sc = device_get_softc(dev); 84650703Swpaul unit = device_get_unit(dev); 84740516Swpaul bzero(sc, sizeof(struct rl_softc)); 84840516Swpaul 84993818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 85093818Sjhb MTX_DEF | MTX_RECURSE); 85169583Swpaul RL_LOCK(sc); 85269583Swpaul 85340516Swpaul /* 85440516Swpaul * Handle power management nonsense. 85540516Swpaul */ 85640516Swpaul 85770167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 85870167Swpaul u_int32_t iobase, membase, irq; 85940516Swpaul 86070167Swpaul /* Save important PCI config data. */ 86170167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 86270167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 86370167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 86440516Swpaul 86570167Swpaul /* Reset the power state. */ 86670167Swpaul printf("rl%d: chip is is in D%d power mode " 86770167Swpaul "-- setting to D0\n", unit, 86870167Swpaul pci_get_powerstate(dev)); 86940516Swpaul 87070167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 87140516Swpaul 87270167Swpaul /* Restore PCI config data. */ 87370167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 87470167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 87570167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 87640516Swpaul } 87740516Swpaul 87840516Swpaul /* 87940516Swpaul * Map control/status registers. 88040516Swpaul */ 88172813Swpaul pci_enable_busmaster(dev); 88279472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 88379472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 88461041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 88540516Swpaul 88640516Swpaul#ifdef RL_USEIOSPACE 88740516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 88840516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 88950703Swpaul error = ENXIO; 89040516Swpaul goto fail; 89140516Swpaul } 89240516Swpaul#else 89340516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 89440516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 89550703Swpaul error = ENXIO; 89640516Swpaul goto fail; 89740516Swpaul } 89850703Swpaul#endif 89940516Swpaul 90050703Swpaul rid = RL_RID; 90150703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 90250703Swpaul 0, ~0, 1, RF_ACTIVE); 90350703Swpaul 90450703Swpaul if (sc->rl_res == NULL) { 90550703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 90650703Swpaul error = ENXIO; 90740516Swpaul goto fail; 90840516Swpaul } 90940516Swpaul 91069127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 91169127Sroger * unstable when left to autoselect the media 91269127Sroger * The best workaround is to set the device to the required 91369127Sroger * media type or to set it to the 10 Meg speed. 91469127Sroger */ 91569127Sroger 91669127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 91769127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 91869127Sroger } 91969127Sroger 92050703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 92150703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 92250703Swpaul 92350703Swpaul rid = 0; 92450703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 92550703Swpaul RF_SHAREABLE | RF_ACTIVE); 92650703Swpaul 92750703Swpaul if (sc->rl_irq == NULL) { 92840516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 92950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 93050703Swpaul error = ENXIO; 93140516Swpaul goto fail; 93240516Swpaul } 93340516Swpaul 93450703Swpaul error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 93550703Swpaul rl_intr, sc, &sc->rl_intrhand); 93650703Swpaul 93750703Swpaul if (error) { 93868215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 93950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 94050703Swpaul printf("rl%d: couldn't set up irq\n", unit); 94150703Swpaul goto fail; 94250703Swpaul } 94350703Swpaul 94450703Swpaul callout_handle_init(&sc->rl_stat_ch); 94550703Swpaul 94640516Swpaul /* Reset the adapter. */ 94740516Swpaul rl_reset(sc); 94867931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 94967931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 95068215Swpaul if (rl_did != 0x8129) 95167931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 95240516Swpaul 95340516Swpaul /* 95440516Swpaul * Get station address from the EEPROM. 95540516Swpaul */ 95640516Swpaul rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 95740516Swpaul 95840516Swpaul /* 95940516Swpaul * A RealTek chip was detected. Inform the world. 96040516Swpaul */ 96140516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 96240516Swpaul 96340516Swpaul sc->rl_unit = unit; 96440516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 96540516Swpaul 96640516Swpaul /* 96740516Swpaul * Now read the exact device type from the EEPROM to find 96840516Swpaul * out if it's an 8129 or 8139. 96940516Swpaul */ 97040516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 97140516Swpaul 97244238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 97367771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 97472813Swpaul rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS) 97540516Swpaul sc->rl_type = RL_8139; 97640516Swpaul else if (rl_did == RT_DEVICEID_8129) 97740516Swpaul sc->rl_type = RL_8129; 97840516Swpaul else { 97940516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 98050703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 98168215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 98250703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 98350703Swpaul error = ENXIO; 98440516Swpaul goto fail; 98540516Swpaul } 98640516Swpaul 98781713Swpaul /* 98881713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 98981713Swpaul */ 99081713Swpaul#define RL_NSEG_NEW 32 99181713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 99281713Swpaul 1, 0, /* alignment, boundary */ 99381713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 99481713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 99581713Swpaul NULL, NULL, /* filter, filterarg */ 99681713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 99781713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 99881713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 99981713Swpaul &sc->rl_parent_tag); 100040516Swpaul 100181713Swpaul /* 100281713Swpaul * Now allocate a tag for the DMA descriptor lists. 100381713Swpaul * All of our lists are allocated as a contiguous block 100481713Swpaul * of memory. 100581713Swpaul */ 100681713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 100781713Swpaul 1, 0, /* alignment, boundary */ 100881713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 100981713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 101081713Swpaul NULL, NULL, /* filter, filterarg */ 101181713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 101281713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 101381713Swpaul 0, /* flags */ 101481713Swpaul &sc->rl_tag); 101581713Swpaul 101681713Swpaul /* 101781713Swpaul * Now allocate a chunk of DMA-able memory based on the 101881713Swpaul * tag we just created. 101981713Swpaul */ 102081713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 102181713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 102281713Swpaul &sc->rl_cdata.rl_rx_dmamap); 102381713Swpaul 102440516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 102540516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 102650703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 102768215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 102850703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 102981713Swpaul bus_dma_tag_destroy(sc->rl_tag); 103050703Swpaul error = ENXIO; 103140516Swpaul goto fail; 103240516Swpaul } 103340516Swpaul 103448028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 103548028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 103648028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 103748028Swpaul 103850703Swpaul /* Do MII setup */ 103950703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 104050703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 104150703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 104250703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 104368215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 104450703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 104581713Swpaul bus_dmamem_free(sc->rl_tag, 104681713Swpaul sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 104781713Swpaul bus_dma_tag_destroy(sc->rl_tag); 104850703Swpaul error = ENXIO; 104950703Swpaul goto fail; 105050703Swpaul } 105150703Swpaul 105240516Swpaul ifp = &sc->arpcom.ac_if; 105340516Swpaul ifp->if_softc = sc; 105440516Swpaul ifp->if_unit = unit; 105540516Swpaul ifp->if_name = "rl"; 105640516Swpaul ifp->if_mtu = ETHERMTU; 105740516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 105840516Swpaul ifp->if_ioctl = rl_ioctl; 105940516Swpaul ifp->if_output = ether_output; 106040516Swpaul ifp->if_start = rl_start; 106140516Swpaul ifp->if_watchdog = rl_watchdog; 106240516Swpaul ifp->if_init = rl_init; 106340516Swpaul ifp->if_baudrate = 10000000; 106445633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 106540516Swpaul 106640516Swpaul /* 106763090Sarchie * Call MI attach routine. 106840516Swpaul */ 106963090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 107067087Swpaul RL_UNLOCK(sc); 107167087Swpaul return(0); 107240516Swpaul 107340516Swpaulfail: 107467087Swpaul RL_UNLOCK(sc); 107567087Swpaul mtx_destroy(&sc->rl_mtx); 107650703Swpaul return(error); 107740516Swpaul} 107840516Swpaul 107950703Swpaulstatic int rl_detach(dev) 108050703Swpaul device_t dev; 108150703Swpaul{ 108250703Swpaul struct rl_softc *sc; 108350703Swpaul struct ifnet *ifp; 108450703Swpaul 108550703Swpaul sc = device_get_softc(dev); 108667087Swpaul RL_LOCK(sc); 108750703Swpaul ifp = &sc->arpcom.ac_if; 108850703Swpaul 108963090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 109050703Swpaul rl_stop(sc); 109150703Swpaul 109250703Swpaul bus_generic_detach(dev); 109350703Swpaul device_delete_child(dev, sc->rl_miibus); 109450703Swpaul 109550703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 109668215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 109750703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 109850703Swpaul 109981713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 110081713Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 110181713Swpaul sc->rl_cdata.rl_rx_dmamap); 110281713Swpaul bus_dma_tag_destroy(sc->rl_tag); 110381713Swpaul bus_dma_tag_destroy(sc->rl_parent_tag); 110450703Swpaul 110567087Swpaul RL_UNLOCK(sc); 110667087Swpaul mtx_destroy(&sc->rl_mtx); 110750703Swpaul 110850703Swpaul return(0); 110950703Swpaul} 111050703Swpaul 111140516Swpaul/* 111240516Swpaul * Initialize the transmit descriptors. 111340516Swpaul */ 111440516Swpaulstatic int rl_list_tx_init(sc) 111540516Swpaul struct rl_softc *sc; 111640516Swpaul{ 111740516Swpaul struct rl_chain_data *cd; 111840516Swpaul int i; 111940516Swpaul 112040516Swpaul cd = &sc->rl_cdata; 112140516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 112245633Swpaul cd->rl_tx_chain[i] = NULL; 112348028Swpaul CSR_WRITE_4(sc, 112448028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 112540516Swpaul } 112640516Swpaul 112745633Swpaul sc->rl_cdata.cur_tx = 0; 112845633Swpaul sc->rl_cdata.last_tx = 0; 112940516Swpaul 113040516Swpaul return(0); 113140516Swpaul} 113240516Swpaul 113340516Swpaul/* 113440516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 113540516Swpaul * the higher level protocols. 113640516Swpaul * 113740516Swpaul * You know there's something wrong with a PCI bus-master chip design 113840516Swpaul * when you have to use m_devget(). 113940516Swpaul * 114040516Swpaul * The receive operation is badly documented in the datasheet, so I'll 114140516Swpaul * attempt to document it here. The driver provides a buffer area and 114240516Swpaul * places its base address in the RX buffer start address register. 114340516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 114472645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 114540516Swpaul * of the frame and certain other status bits. Each frame (starting with 114640516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 114740516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 114840516Swpaul * the 'rx status register' mentioned in the datasheet. 114948028Swpaul * 115048028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 115178508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 115278508Sbmilekic * as the offset argument to m_devget(). 115340516Swpaul */ 115440516Swpaulstatic void rl_rxeof(sc) 115540516Swpaul struct rl_softc *sc; 115640516Swpaul{ 115740516Swpaul struct ether_header *eh; 115840516Swpaul struct mbuf *m; 115940516Swpaul struct ifnet *ifp; 116040516Swpaul int total_len = 0; 116140516Swpaul u_int32_t rxstat; 116240516Swpaul caddr_t rxbufpos; 116340516Swpaul int wrap = 0; 116440516Swpaul u_int16_t cur_rx; 116540516Swpaul u_int16_t limit; 116640516Swpaul u_int16_t rx_bytes = 0, max_bytes; 116740516Swpaul 116840516Swpaul ifp = &sc->arpcom.ac_if; 116940516Swpaul 117081713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 117181713Swpaul BUS_DMASYNC_POSTWRITE); 117281713Swpaul 117340516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 117440516Swpaul 117540516Swpaul /* Do not try to read past this point. */ 117640516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 117740516Swpaul 117840516Swpaul if (limit < cur_rx) 117940516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 118040516Swpaul else 118140516Swpaul max_bytes = limit - cur_rx; 118240516Swpaul 118342738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 118440516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 118540516Swpaul rxstat = *(u_int32_t *)rxbufpos; 118640516Swpaul 118740516Swpaul /* 118840516Swpaul * Here's a totally undocumented fact for you. When the 118940516Swpaul * RealTek chip is in the process of copying a packet into 119040516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 119140516Swpaul * packet header with this value, you need to stop. The 119240516Swpaul * datasheet makes absolutely no mention of this and 119340516Swpaul * RealTek should be shot for this. 119440516Swpaul */ 119540516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 119640516Swpaul break; 119740516Swpaul 119840516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 119940516Swpaul ifp->if_ierrors++; 120050703Swpaul rl_init(sc); 120150703Swpaul return; 120240516Swpaul } 120340516Swpaul 120440516Swpaul /* No errors; receive the packet. */ 120540516Swpaul total_len = rxstat >> 16; 120640516Swpaul rx_bytes += total_len + 4; 120740516Swpaul 120840516Swpaul /* 120942051Swpaul * XXX The RealTek chip includes the CRC with every 121042051Swpaul * received frame, and there's no way to turn this 121142051Swpaul * behavior off (at least, I can't find anything in 121242051Swpaul * the manual that explains how to do it) so we have 121342051Swpaul * to trim off the CRC manually. 121442051Swpaul */ 121542051Swpaul total_len -= ETHER_CRC_LEN; 121642051Swpaul 121742051Swpaul /* 121840516Swpaul * Avoid trying to read more bytes than we know 121940516Swpaul * the chip has prepared for us. 122040516Swpaul */ 122140516Swpaul if (rx_bytes > max_bytes) 122240516Swpaul break; 122340516Swpaul 122440516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 122540516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 122640516Swpaul 122740516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 122840516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 122940516Swpaul 123040516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 123140516Swpaul 123240516Swpaul if (total_len > wrap) { 123378508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 123478508Sbmilekic NULL); 123540516Swpaul if (m == NULL) { 123640516Swpaul ifp->if_ierrors++; 123752426Swpaul } else { 123840516Swpaul m_copyback(m, wrap, total_len - wrap, 123940516Swpaul sc->rl_cdata.rl_rx_buf); 124048028Swpaul } 124142051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 124240516Swpaul } else { 124378508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 124478508Sbmilekic NULL); 124540516Swpaul if (m == NULL) { 124640516Swpaul ifp->if_ierrors++; 124778508Sbmilekic } 124842051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 124940516Swpaul } 125040516Swpaul 125140516Swpaul /* 125240516Swpaul * Round up to 32-bit boundary. 125340516Swpaul */ 125440516Swpaul cur_rx = (cur_rx + 3) & ~3; 125540516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 125640516Swpaul 125740516Swpaul if (m == NULL) 125840516Swpaul continue; 125940516Swpaul 126040516Swpaul eh = mtod(m, struct ether_header *); 126140516Swpaul ifp->if_ipackets++; 126240516Swpaul 126340516Swpaul /* Remove header from mbuf and pass it on. */ 126440516Swpaul m_adj(m, sizeof(struct ether_header)); 126540516Swpaul ether_input(ifp, eh, m); 126640516Swpaul } 126740516Swpaul 126840516Swpaul return; 126940516Swpaul} 127040516Swpaul 127140516Swpaul/* 127240516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 127340516Swpaul * the list buffers. 127440516Swpaul */ 127540516Swpaulstatic void rl_txeof(sc) 127640516Swpaul struct rl_softc *sc; 127740516Swpaul{ 127840516Swpaul struct ifnet *ifp; 127940516Swpaul u_int32_t txstat; 128040516Swpaul 128140516Swpaul ifp = &sc->arpcom.ac_if; 128240516Swpaul 128340516Swpaul /* Clear the timeout timer. */ 128440516Swpaul ifp->if_timer = 0; 128540516Swpaul 128640516Swpaul /* 128740516Swpaul * Go through our tx list and free mbufs for those 128840516Swpaul * frames that have been uploaded. 128940516Swpaul */ 129045633Swpaul do { 129145633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 129245633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 129345633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 129440516Swpaul break; 129540516Swpaul 129645633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 129740516Swpaul 129845633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 129981713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 130081713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 130145633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 130245633Swpaul RL_LAST_TXMBUF(sc) = NULL; 130345633Swpaul } 130445633Swpaul if (txstat & RL_TXSTAT_TX_OK) 130545633Swpaul ifp->if_opackets++; 130645633Swpaul else { 130752426Swpaul int oldthresh; 130845633Swpaul ifp->if_oerrors++; 130945633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 131045633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 131145633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 131252426Swpaul oldthresh = sc->rl_txthresh; 131352426Swpaul /* error recovery */ 131452426Swpaul rl_reset(sc); 131552426Swpaul rl_init(sc); 131652426Swpaul /* 131752426Swpaul * If there was a transmit underrun, 131852426Swpaul * bump the TX threshold. 131952426Swpaul */ 132052426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 132152426Swpaul sc->rl_txthresh = oldthresh + 32; 132252426Swpaul return; 132345633Swpaul } 132445633Swpaul RL_INC(sc->rl_cdata.last_tx); 132545633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 132645633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 132740516Swpaul 132850703Swpaul return; 132950703Swpaul} 133040516Swpaul 133150703Swpaulstatic void rl_tick(xsc) 133250703Swpaul void *xsc; 133350703Swpaul{ 133450703Swpaul struct rl_softc *sc; 133550703Swpaul struct mii_data *mii; 133650703Swpaul 133750703Swpaul sc = xsc; 133867087Swpaul RL_LOCK(sc); 133950703Swpaul mii = device_get_softc(sc->rl_miibus); 134050703Swpaul 134150703Swpaul mii_tick(mii); 134250703Swpaul 134350703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 134467087Swpaul RL_UNLOCK(sc); 134550703Swpaul 134640516Swpaul return; 134740516Swpaul} 134840516Swpaul 134940516Swpaulstatic void rl_intr(arg) 135040516Swpaul void *arg; 135140516Swpaul{ 135240516Swpaul struct rl_softc *sc; 135340516Swpaul struct ifnet *ifp; 135440516Swpaul u_int16_t status; 135540516Swpaul 135640516Swpaul sc = arg; 135786822Siwasaki 135886822Siwasaki if (sc->suspended) { 135986822Siwasaki return; 136086822Siwasaki } 136186822Siwasaki 136267087Swpaul RL_LOCK(sc); 136340516Swpaul ifp = &sc->arpcom.ac_if; 136440516Swpaul 136540516Swpaul /* Disable interrupts. */ 136640516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 136740516Swpaul 136840516Swpaul for (;;) { 136940516Swpaul 137040516Swpaul status = CSR_READ_2(sc, RL_ISR); 137140516Swpaul if (status) 137240516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 137340516Swpaul 137440516Swpaul if ((status & RL_INTRS) == 0) 137540516Swpaul break; 137640516Swpaul 137740516Swpaul if (status & RL_ISR_RX_OK) 137840516Swpaul rl_rxeof(sc); 137940516Swpaul 138040516Swpaul if (status & RL_ISR_RX_ERR) 138140516Swpaul rl_rxeof(sc); 138240516Swpaul 138345633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 138440516Swpaul rl_txeof(sc); 138540516Swpaul 138640516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 138740516Swpaul rl_reset(sc); 138840516Swpaul rl_init(sc); 138940516Swpaul } 139040516Swpaul 139140516Swpaul } 139240516Swpaul 139340516Swpaul /* Re-enable interrupts. */ 139440516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 139540516Swpaul 139652426Swpaul if (ifp->if_snd.ifq_head != NULL) 139740516Swpaul rl_start(ifp); 139840516Swpaul 139967087Swpaul RL_UNLOCK(sc); 140067087Swpaul 140140516Swpaul return; 140240516Swpaul} 140340516Swpaul 140440516Swpaul/* 140540516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 140640516Swpaul * pointers to the fragment pointers. 140740516Swpaul */ 140845633Swpaulstatic int rl_encap(sc, m_head) 140940516Swpaul struct rl_softc *sc; 141040516Swpaul struct mbuf *m_head; 141140516Swpaul{ 141241243Swpaul struct mbuf *m_new = NULL; 141340516Swpaul 141440516Swpaul /* 141545633Swpaul * The RealTek is brain damaged and wants longword-aligned 141645633Swpaul * TX buffers, plus we can only have one fragment buffer 141745633Swpaul * per packet. We have to copy pretty much all the time. 141840516Swpaul */ 141940516Swpaul 142041243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 142187846Sluigi if (m_new == NULL) 142241243Swpaul return(1); 142341243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 142441243Swpaul MCLGET(m_new, M_DONTWAIT); 142541243Swpaul if (!(m_new->m_flags & M_EXT)) { 142641243Swpaul m_freem(m_new); 142740516Swpaul return(1); 142840516Swpaul } 142940516Swpaul } 143052426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 143141243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 143241243Swpaul m_freem(m_head); 143341243Swpaul m_head = m_new; 143440516Swpaul 143540516Swpaul /* Pad frames to at least 60 bytes. */ 143641243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 143755058Swpaul /* 143855058Swpaul * Make security concious people happy: zero out the 143955058Swpaul * bytes in the pad area, since we don't know what 144055058Swpaul * this mbuf cluster buffer's previous user might 144155058Swpaul * have left in it. 144255058Swpaul */ 144355058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 144455058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 144540516Swpaul m_head->m_pkthdr.len += 144652426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 144741243Swpaul m_head->m_len = m_head->m_pkthdr.len; 144841243Swpaul } 144940516Swpaul 145045633Swpaul RL_CUR_TXMBUF(sc) = m_head; 145140516Swpaul 145240516Swpaul return(0); 145340516Swpaul} 145440516Swpaul 145540516Swpaul/* 145640516Swpaul * Main transmit routine. 145740516Swpaul */ 145840516Swpaul 145940516Swpaulstatic void rl_start(ifp) 146040516Swpaul struct ifnet *ifp; 146140516Swpaul{ 146240516Swpaul struct rl_softc *sc; 146340516Swpaul struct mbuf *m_head = NULL; 146440516Swpaul 146540516Swpaul sc = ifp->if_softc; 146667087Swpaul RL_LOCK(sc); 146740516Swpaul 146845633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 146940516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 147040516Swpaul if (m_head == NULL) 147140516Swpaul break; 147240516Swpaul 147358801Swpaul if (rl_encap(sc, m_head)) { 147458801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 147558801Swpaul ifp->if_flags |= IFF_OACTIVE; 147658801Swpaul break; 147758801Swpaul } 147840516Swpaul 147940516Swpaul /* 148040516Swpaul * If there's a BPF listener, bounce a copy of this frame 148140516Swpaul * to him. 148240516Swpaul */ 148340516Swpaul if (ifp->if_bpf) 148445633Swpaul bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 148551583Swpaul 148640516Swpaul /* 148740516Swpaul * Transmit the frame. 148840516Swpaul */ 148981713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 149081713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 149181713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 149281713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 149381713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 149481713Swpaul BUS_DMASYNC_PREREAD); 149545633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 149652426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 149752426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 149845633Swpaul 149945633Swpaul RL_INC(sc->rl_cdata.cur_tx); 150040516Swpaul } 150140516Swpaul 150240516Swpaul /* 150345633Swpaul * We broke out of the loop because all our TX slots are 150445633Swpaul * full. Mark the NIC as busy until it drains some of the 150545633Swpaul * packets from the queue. 150645633Swpaul */ 150745633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 150845633Swpaul ifp->if_flags |= IFF_OACTIVE; 150945633Swpaul 151045633Swpaul /* 151140516Swpaul * Set a timeout in case the chip goes out to lunch. 151240516Swpaul */ 151340516Swpaul ifp->if_timer = 5; 151467087Swpaul RL_UNLOCK(sc); 151540516Swpaul 151640516Swpaul return; 151740516Swpaul} 151840516Swpaul 151940516Swpaulstatic void rl_init(xsc) 152040516Swpaul void *xsc; 152140516Swpaul{ 152240516Swpaul struct rl_softc *sc = xsc; 152340516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 152450703Swpaul struct mii_data *mii; 152567087Swpaul int i; 152640516Swpaul u_int32_t rxcfg = 0; 152740516Swpaul 152867087Swpaul RL_LOCK(sc); 152950703Swpaul mii = device_get_softc(sc->rl_miibus); 153040516Swpaul 153140516Swpaul /* 153240516Swpaul * Cancel pending I/O and free all RX/TX buffers. 153340516Swpaul */ 153440516Swpaul rl_stop(sc); 153540516Swpaul 153640516Swpaul /* Init our MAC address */ 153740516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 153840516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 153940516Swpaul } 154040516Swpaul 154140516Swpaul /* Init the RX buffer pointer register. */ 154281713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 154381713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 154481713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 154581713Swpaul BUS_DMASYNC_PREWRITE); 154640516Swpaul 154740516Swpaul /* Init TX descriptors. */ 154840516Swpaul rl_list_tx_init(sc); 154940516Swpaul 155040516Swpaul /* 155140516Swpaul * Enable transmit and receive. 155240516Swpaul */ 155340516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 155440516Swpaul 155540516Swpaul /* 155645633Swpaul * Set the initial TX and RX configuration. 155740516Swpaul */ 155845633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 155940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 156040516Swpaul 156140516Swpaul /* Set the individual bit to receive frames for this host only. */ 156240516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 156340516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 156440516Swpaul 156540516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 156640516Swpaul if (ifp->if_flags & IFF_PROMISC) { 156740516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 156840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 156940516Swpaul } else { 157040516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 157140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 157240516Swpaul } 157340516Swpaul 157440516Swpaul /* 157540516Swpaul * Set capture broadcast bit to capture broadcast frames. 157640516Swpaul */ 157740516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 157840516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 157940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 158040516Swpaul } else { 158140516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 158240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 158340516Swpaul } 158440516Swpaul 158540516Swpaul /* 158640516Swpaul * Program the multicast filter, if necessary. 158740516Swpaul */ 158840516Swpaul rl_setmulti(sc); 158940516Swpaul 159040516Swpaul /* 159140516Swpaul * Enable interrupts. 159240516Swpaul */ 159340516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 159440516Swpaul 159552426Swpaul /* Set initial TX threshold */ 159652426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 159752426Swpaul 159840516Swpaul /* Start RX/TX process. */ 159940516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 160040516Swpaul 160140516Swpaul /* Enable receiver and transmitter. */ 160240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 160340516Swpaul 160450703Swpaul mii_mediachg(mii); 160540516Swpaul 160640516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 160740516Swpaul 160840516Swpaul ifp->if_flags |= IFF_RUNNING; 160940516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 161040516Swpaul 161150703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 161267087Swpaul RL_UNLOCK(sc); 161350703Swpaul 161440516Swpaul return; 161540516Swpaul} 161640516Swpaul 161740516Swpaul/* 161840516Swpaul * Set media options. 161940516Swpaul */ 162040516Swpaulstatic int rl_ifmedia_upd(ifp) 162140516Swpaul struct ifnet *ifp; 162240516Swpaul{ 162340516Swpaul struct rl_softc *sc; 162450703Swpaul struct mii_data *mii; 162540516Swpaul 162640516Swpaul sc = ifp->if_softc; 162750703Swpaul mii = device_get_softc(sc->rl_miibus); 162850703Swpaul mii_mediachg(mii); 162940516Swpaul 163040516Swpaul return(0); 163140516Swpaul} 163240516Swpaul 163340516Swpaul/* 163440516Swpaul * Report current media status. 163540516Swpaul */ 163640516Swpaulstatic void rl_ifmedia_sts(ifp, ifmr) 163740516Swpaul struct ifnet *ifp; 163840516Swpaul struct ifmediareq *ifmr; 163940516Swpaul{ 164040516Swpaul struct rl_softc *sc; 164150703Swpaul struct mii_data *mii; 164240516Swpaul 164340516Swpaul sc = ifp->if_softc; 164450703Swpaul mii = device_get_softc(sc->rl_miibus); 164540516Swpaul 164650703Swpaul mii_pollstat(mii); 164750703Swpaul ifmr->ifm_active = mii->mii_media_active; 164850703Swpaul ifmr->ifm_status = mii->mii_media_status; 164940516Swpaul 165040516Swpaul return; 165140516Swpaul} 165240516Swpaul 165340516Swpaulstatic int rl_ioctl(ifp, command, data) 165440516Swpaul struct ifnet *ifp; 165540516Swpaul u_long command; 165640516Swpaul caddr_t data; 165740516Swpaul{ 165840516Swpaul struct rl_softc *sc = ifp->if_softc; 165940516Swpaul struct ifreq *ifr = (struct ifreq *) data; 166050703Swpaul struct mii_data *mii; 166167087Swpaul int error = 0; 166240516Swpaul 166367087Swpaul RL_LOCK(sc); 166440516Swpaul 166540516Swpaul switch(command) { 166640516Swpaul case SIOCSIFADDR: 166740516Swpaul case SIOCGIFADDR: 166840516Swpaul case SIOCSIFMTU: 166940516Swpaul error = ether_ioctl(ifp, command, data); 167040516Swpaul break; 167140516Swpaul case SIOCSIFFLAGS: 167240516Swpaul if (ifp->if_flags & IFF_UP) { 167340516Swpaul rl_init(sc); 167440516Swpaul } else { 167540516Swpaul if (ifp->if_flags & IFF_RUNNING) 167640516Swpaul rl_stop(sc); 167740516Swpaul } 167840516Swpaul error = 0; 167940516Swpaul break; 168040516Swpaul case SIOCADDMULTI: 168140516Swpaul case SIOCDELMULTI: 168240516Swpaul rl_setmulti(sc); 168340516Swpaul error = 0; 168440516Swpaul break; 168540516Swpaul case SIOCGIFMEDIA: 168640516Swpaul case SIOCSIFMEDIA: 168750703Swpaul mii = device_get_softc(sc->rl_miibus); 168850703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 168940516Swpaul break; 169040516Swpaul default: 169140516Swpaul error = EINVAL; 169240516Swpaul break; 169340516Swpaul } 169440516Swpaul 169567087Swpaul RL_UNLOCK(sc); 169640516Swpaul 169740516Swpaul return(error); 169840516Swpaul} 169940516Swpaul 170040516Swpaulstatic void rl_watchdog(ifp) 170140516Swpaul struct ifnet *ifp; 170240516Swpaul{ 170340516Swpaul struct rl_softc *sc; 170440516Swpaul 170540516Swpaul sc = ifp->if_softc; 170667087Swpaul RL_LOCK(sc); 170740516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 170840516Swpaul ifp->if_oerrors++; 170950703Swpaul 171040516Swpaul rl_txeof(sc); 171140516Swpaul rl_rxeof(sc); 171240516Swpaul rl_init(sc); 171367087Swpaul RL_UNLOCK(sc); 171440516Swpaul 171540516Swpaul return; 171640516Swpaul} 171740516Swpaul 171840516Swpaul/* 171940516Swpaul * Stop the adapter and free any mbufs allocated to the 172040516Swpaul * RX and TX lists. 172140516Swpaul */ 172240516Swpaulstatic void rl_stop(sc) 172340516Swpaul struct rl_softc *sc; 172440516Swpaul{ 172540516Swpaul register int i; 172640516Swpaul struct ifnet *ifp; 172740516Swpaul 172867087Swpaul RL_LOCK(sc); 172940516Swpaul ifp = &sc->arpcom.ac_if; 173040516Swpaul ifp->if_timer = 0; 173140516Swpaul 173250703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 173350703Swpaul 173440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 173540516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 173681713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 173740516Swpaul 173840516Swpaul /* 173940516Swpaul * Free the TX list buffers. 174040516Swpaul */ 174140516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 174245633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 174381713Swpaul bus_dmamap_unload(sc->rl_tag, 174481713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 174581713Swpaul bus_dmamap_destroy(sc->rl_tag, 174681713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 174745633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 174845633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 174945633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 175040516Swpaul } 175140516Swpaul } 175240516Swpaul 175340516Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 175467087Swpaul RL_UNLOCK(sc); 175540516Swpaul return; 175640516Swpaul} 175740516Swpaul 175840516Swpaul/* 175986822Siwasaki * Device suspend routine. Stop the interface and save some PCI 176086822Siwasaki * settings in case the BIOS doesn't restore them properly on 176186822Siwasaki * resume. 176286822Siwasaki */ 176386822Siwasakistatic int rl_suspend(dev) 176486822Siwasaki device_t dev; 176586822Siwasaki{ 176686822Siwasaki register int i; 176786822Siwasaki struct rl_softc *sc; 176886822Siwasaki 176986822Siwasaki sc = device_get_softc(dev); 177086822Siwasaki 177186822Siwasaki rl_stop(sc); 177286822Siwasaki 177386822Siwasaki for (i = 0; i < 5; i++) 177486822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 177586822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 177686822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 177786822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 177886822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 177986822Siwasaki 178086822Siwasaki sc->suspended = 1; 178186822Siwasaki 178286822Siwasaki return (0); 178386822Siwasaki} 178486822Siwasaki 178586822Siwasaki/* 178686822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 178786822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 178886822Siwasaki * appropriate. 178986822Siwasaki */ 179086822Siwasakistatic int rl_resume(dev) 179186822Siwasaki device_t dev; 179286822Siwasaki{ 179386822Siwasaki register int i; 179486822Siwasaki struct rl_softc *sc; 179586822Siwasaki struct ifnet *ifp; 179686822Siwasaki 179786822Siwasaki sc = device_get_softc(dev); 179886822Siwasaki ifp = &sc->arpcom.ac_if; 179986822Siwasaki 180086822Siwasaki /* better way to do this? */ 180186822Siwasaki for (i = 0; i < 5; i++) 180286822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 180386822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 180486822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 180586822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 180686822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 180786822Siwasaki 180886822Siwasaki /* reenable busmastering */ 180986822Siwasaki pci_enable_busmaster(dev); 181086822Siwasaki pci_enable_io(dev, RL_RES); 181186822Siwasaki 181286822Siwasaki /* reinitialize interface if necessary */ 181386822Siwasaki if (ifp->if_flags & IFF_UP) 181486822Siwasaki rl_init(sc); 181586822Siwasaki 181686822Siwasaki sc->suspended = 0; 181786822Siwasaki 181886822Siwasaki return (0); 181986822Siwasaki} 182086822Siwasaki 182186822Siwasaki/* 182240516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 182340516Swpaul * get confused by errant DMAs when rebooting. 182440516Swpaul */ 182550703Swpaulstatic void rl_shutdown(dev) 182650703Swpaul device_t dev; 182740516Swpaul{ 182850703Swpaul struct rl_softc *sc; 182940516Swpaul 183050703Swpaul sc = device_get_softc(dev); 183150703Swpaul 183240516Swpaul rl_stop(sc); 183340516Swpaul 183440516Swpaul return; 183540516Swpaul} 1836