if_rl.c revision 79472
11573Srgrimes/* 21573Srgrimes * Copyright (c) 1997, 1998 31573Srgrimes * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 41573Srgrimes * 51573Srgrimes * Redistribution and use in source and binary forms, with or without 61573Srgrimes * modification, are permitted provided that the following conditions 71573Srgrimes * are met: 81573Srgrimes * 1. Redistributions of source code must retain the above copyright 91573Srgrimes * notice, this list of conditions and the following disclaimer. 101573Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 111573Srgrimes * notice, this list of conditions and the following disclaimer in the 121573Srgrimes * documentation and/or other materials provided with the distribution. 131573Srgrimes * 3. All advertising materials mentioning features or use of this software 141573Srgrimes * must display the following acknowledgement: 151573Srgrimes * This product includes software developed by Bill Paul. 161573Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 171573Srgrimes * may be used to endorse or promote products derived from this software 181573Srgrimes * without specific prior written permission. 191573Srgrimes * 201573Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 211573Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221573Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231573Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 241573Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251573Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261573Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271573Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281573Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291573Srgrimes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 301573Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 311573Srgrimes * 321573Srgrimes * $FreeBSD: head/sys/pci/if_rl.c 79472 2001-07-09 17:58:42Z wpaul $ 331573Srgrimes */ 341573Srgrimes 351573Srgrimes/* 361573Srgrimes * RealTek 8129/8139 PCI NIC driver 371573Srgrimes * 381573Srgrimes * Supports several extremely cheap PCI 10/100 adapters based on 391573Srgrimes * the RealTek chipset. Datasheets can be obtained from 401573Srgrimes * www.realtek.com.tw. 411573Srgrimes * 421573Srgrimes * Written by Bill Paul <wpaul@ctr.columbia.edu> 431573Srgrimes * Electrical Engineering Department 441573Srgrimes * Columbia University, New York City 451573Srgrimes */ 461573Srgrimes 471573Srgrimes/* 481573Srgrimes * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 491573Srgrimes * probably the worst PCI ethernet controller ever made, with the possible 501573Srgrimes * exception of the FEAST chip made by SMC. The 8139 supports bus-master 511573Srgrimes * DMA, but it has a terrible interface that nullifies any performance 521573Srgrimes * gains that bus-master DMA usually offers. 531573Srgrimes * 541573Srgrimes * For transmission, the chip offers a series of four TX descriptor 551573Srgrimes * registers. Each transmit frame must be in a contiguous buffer, aligned 561573Srgrimes * on a longword (32-bit) boundary. This means we almost always have to 571573Srgrimes * do mbuf copies in order to transmit a frame, except in the unlikely 581573Srgrimes * case where a) the packet fits into a single mbuf, and b) the packet 591573Srgrimes * is 32-bit aligned within the mbuf's data area. The presence of only 601573Srgrimes * four descriptor registers means that we can never have more than four 611573Srgrimes * packets queued for transmission at any one time. 621573Srgrimes * 631573Srgrimes * Reception is not much better. The driver has to allocate a single large 641573Srgrimes * buffer area (up to 64K in size) into which the chip will DMA received 651573Srgrimes * frames. Because we don't know where within this region received packets 661573Srgrimes * will begin or end, we have no choice but to copy data from the buffer 671573Srgrimes * area into mbufs in order to pass the packets up to the higher protocol 681573Srgrimes * levels. 691573Srgrimes * 701573Srgrimes * It's impossible given this rotten design to really achieve decent 711573Srgrimes * performance at 100Mbps, unless you happen to have a 400Mhz PII or 721573Srgrimes * some equally overmuscled CPU to drive it. 731573Srgrimes * 741573Srgrimes * On the bright side, the 8139 does have a built-in PHY, although 751573Srgrimes * rather than using an MDIO serial interface like most other NICs, the 761573Srgrimes * PHY registers are directly accessible through the 8139's register 771573Srgrimes * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 781573Srgrimes * filter. 791573Srgrimes * 801573Srgrimes * The 8129 chip is an older version of the 8139 that uses an external PHY 811573Srgrimes * chip. The 8129 has a serial MDIO interface for accessing the MII where 821573Srgrimes * the 8139 lets you directly access the on-board PHY registers. We need 831573Srgrimes * to select which interface to use depending on the chip type. 841573Srgrimes */ 851573Srgrimes 861573Srgrimes#include <sys/param.h> 871573Srgrimes#include <sys/systm.h> 881573Srgrimes#include <sys/sockio.h> 891573Srgrimes#include <sys/mbuf.h> 901573Srgrimes#include <sys/malloc.h> 911573Srgrimes#include <sys/kernel.h> 921573Srgrimes#include <sys/socket.h> 931573Srgrimes 941573Srgrimes#include <net/if.h> 951573Srgrimes#include <net/if_arp.h> 961573Srgrimes#include <net/ethernet.h> 971573Srgrimes#include <net/if_dl.h> 981573Srgrimes#include <net/if_media.h> 991573Srgrimes 1001573Srgrimes#include <net/bpf.h> 1011573Srgrimes 1021573Srgrimes#include <vm/vm.h> /* for vtophys */ 1031573Srgrimes#include <vm/pmap.h> /* for vtophys */ 1041573Srgrimes#include <machine/bus_pio.h> 1051573Srgrimes#include <machine/bus_memio.h> 1061573Srgrimes#include <machine/bus.h> 1071573Srgrimes#include <machine/resource.h> 1081573Srgrimes#include <sys/bus.h> 1091573Srgrimes#include <sys/rman.h> 1101573Srgrimes 1111573Srgrimes#include <dev/mii/mii.h> 1121573Srgrimes#include <dev/mii/miivar.h> 1131573Srgrimes 1141573Srgrimes#include <pci/pcireg.h> 1151573Srgrimes#include <pci/pcivar.h> 1161573Srgrimes 1171573SrgrimesMODULE_DEPEND(rl, miibus, 1, 1, 1); 1181573Srgrimes 1191573Srgrimes/* "controller miibus0" required. See GENERIC if you get errors here. */ 1201573Srgrimes#include "miibus_if.h" 1211573Srgrimes 1221573Srgrimes/* 1231573Srgrimes * Default to using PIO access for this driver. On SMP systems, 1241573Srgrimes * there appear to be problems with memory mapped mode: it looks like 1251573Srgrimes * doing too many memory mapped access back to back in rapid succession 1261573Srgrimes * can hang the bus. I'm inclined to blame this on crummy design/construction 1271573Srgrimes * on the part of RealTek. Memory mapped mode does appear to work on 1281573Srgrimes * uniprocessor systems though. 1291573Srgrimes */ 1301573Srgrimes#define RL_USEIOSPACE 1311573Srgrimes 1321573Srgrimes#include <pci/if_rlreg.h> 1331573Srgrimes 1341573Srgrimes#ifndef lint 1351573Srgrimesstatic const char rcsid[] = 1361573Srgrimes "$FreeBSD: head/sys/pci/if_rl.c 79472 2001-07-09 17:58:42Z wpaul $"; 1371573Srgrimes#endif 1381573Srgrimes 1391573Srgrimes/* 1401573Srgrimes * Various supported device vendors/types and their names. 1411573Srgrimes */ 1421573Srgrimesstatic struct rl_type rl_devs[] = { 1431573Srgrimes { RT_VENDORID, RT_DEVICEID_8129, 1441573Srgrimes "RealTek 8129 10/100BaseTX" }, 1451573Srgrimes { RT_VENDORID, RT_DEVICEID_8139, 1461573Srgrimes "RealTek 8139 10/100BaseTX" }, 1471573Srgrimes { RT_VENDORID, RT_DEVICEID_8138, 1481573Srgrimes "RealTek 8139 10/100BaseTX CardBus" }, 1491573Srgrimes { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 1501573Srgrimes "Accton MPX 5030/5038 10/100BaseTX" }, 1511573Srgrimes { DELTA_VENDORID, DELTA_DEVICEID_8139, 1521573Srgrimes "Delta Electronics 8139 10/100BaseTX" }, 1531573Srgrimes { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 1541573Srgrimes "Addtron Technolgy 8139 10/100BaseTX" }, 1551573Srgrimes { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 1561573Srgrimes "D-Link DFE-530TX+ 10/100BaseTX" }, 1571573Srgrimes { 0, 0, NULL } 1581573Srgrimes}; 159 160static int rl_probe __P((device_t)); 161static int rl_attach __P((device_t)); 162static int rl_detach __P((device_t)); 163 164static int rl_encap __P((struct rl_softc *, struct mbuf * )); 165 166static void rl_rxeof __P((struct rl_softc *)); 167static void rl_txeof __P((struct rl_softc *)); 168static void rl_intr __P((void *)); 169static void rl_tick __P((void *)); 170static void rl_start __P((struct ifnet *)); 171static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 172static void rl_init __P((void *)); 173static void rl_stop __P((struct rl_softc *)); 174static void rl_watchdog __P((struct ifnet *)); 175static void rl_shutdown __P((device_t)); 176static int rl_ifmedia_upd __P((struct ifnet *)); 177static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 178 179static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 180static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 181static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 182 int, int, int)); 183static void rl_mii_sync __P((struct rl_softc *)); 184static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 185static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 186static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 187 188static int rl_miibus_readreg __P((device_t, int, int)); 189static int rl_miibus_writereg __P((device_t, int, int, int)); 190static void rl_miibus_statchg __P((device_t)); 191 192static u_int8_t rl_calchash __P((caddr_t)); 193static void rl_setmulti __P((struct rl_softc *)); 194static void rl_reset __P((struct rl_softc *)); 195static int rl_list_tx_init __P((struct rl_softc *)); 196 197#ifdef RL_USEIOSPACE 198#define RL_RES SYS_RES_IOPORT 199#define RL_RID RL_PCI_LOIO 200#else 201#define RL_RES SYS_RES_MEMORY 202#define RL_RID RL_PCI_LOMEM 203#endif 204 205static device_method_t rl_methods[] = { 206 /* Device interface */ 207 DEVMETHOD(device_probe, rl_probe), 208 DEVMETHOD(device_attach, rl_attach), 209 DEVMETHOD(device_detach, rl_detach), 210 DEVMETHOD(device_shutdown, rl_shutdown), 211 212 /* bus interface */ 213 DEVMETHOD(bus_print_child, bus_generic_print_child), 214 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 218 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 219 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 220 221 { 0, 0 } 222}; 223 224static driver_t rl_driver = { 225 "rl", 226 rl_methods, 227 sizeof(struct rl_softc) 228}; 229 230static devclass_t rl_devclass; 231 232DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 233DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 234DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 235 236#define EE_SET(x) \ 237 CSR_WRITE_1(sc, RL_EECMD, \ 238 CSR_READ_1(sc, RL_EECMD) | x) 239 240#define EE_CLR(x) \ 241 CSR_WRITE_1(sc, RL_EECMD, \ 242 CSR_READ_1(sc, RL_EECMD) & ~x) 243 244/* 245 * Send a read command and address to the EEPROM, check for ACK. 246 */ 247static void rl_eeprom_putbyte(sc, addr) 248 struct rl_softc *sc; 249 int addr; 250{ 251 register int d, i; 252 253 d = addr | sc->rl_eecmd_read; 254 255 /* 256 * Feed in each bit and strobe the clock. 257 */ 258 for (i = 0x400; i; i >>= 1) { 259 if (d & i) { 260 EE_SET(RL_EE_DATAIN); 261 } else { 262 EE_CLR(RL_EE_DATAIN); 263 } 264 DELAY(100); 265 EE_SET(RL_EE_CLK); 266 DELAY(150); 267 EE_CLR(RL_EE_CLK); 268 DELAY(100); 269 } 270 271 return; 272} 273 274/* 275 * Read a word of data stored in the EEPROM at address 'addr.' 276 */ 277static void rl_eeprom_getword(sc, addr, dest) 278 struct rl_softc *sc; 279 int addr; 280 u_int16_t *dest; 281{ 282 register int i; 283 u_int16_t word = 0; 284 285 /* Enter EEPROM access mode. */ 286 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 rl_eeprom_putbyte(sc, addr); 292 293 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 294 295 /* 296 * Start reading bits from EEPROM. 297 */ 298 for (i = 0x8000; i; i >>= 1) { 299 EE_SET(RL_EE_CLK); 300 DELAY(100); 301 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 302 word |= i; 303 EE_CLR(RL_EE_CLK); 304 DELAY(100); 305 } 306 307 /* Turn off EEPROM access mode. */ 308 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 309 310 *dest = word; 311 312 return; 313} 314 315/* 316 * Read a sequence of words from the EEPROM. 317 */ 318static void rl_read_eeprom(sc, dest, off, cnt, swap) 319 struct rl_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324{ 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 rl_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338} 339 340 341/* 342 * MII access routines are provided for the 8129, which 343 * doesn't have a built-in PHY. For the 8139, we fake things 344 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 345 * direct access PHY registers. 346 */ 347#define MII_SET(x) \ 348 CSR_WRITE_1(sc, RL_MII, \ 349 CSR_READ_1(sc, RL_MII) | x) 350 351#define MII_CLR(x) \ 352 CSR_WRITE_1(sc, RL_MII, \ 353 CSR_READ_1(sc, RL_MII) & ~x) 354 355/* 356 * Sync the PHYs by setting data bit and strobing the clock 32 times. 357 */ 358static void rl_mii_sync(sc) 359 struct rl_softc *sc; 360{ 361 register int i; 362 363 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 364 365 for (i = 0; i < 32; i++) { 366 MII_SET(RL_MII_CLK); 367 DELAY(1); 368 MII_CLR(RL_MII_CLK); 369 DELAY(1); 370 } 371 372 return; 373} 374 375/* 376 * Clock a series of bits through the MII. 377 */ 378static void rl_mii_send(sc, bits, cnt) 379 struct rl_softc *sc; 380 u_int32_t bits; 381 int cnt; 382{ 383 int i; 384 385 MII_CLR(RL_MII_CLK); 386 387 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 388 if (bits & i) { 389 MII_SET(RL_MII_DATAOUT); 390 } else { 391 MII_CLR(RL_MII_DATAOUT); 392 } 393 DELAY(1); 394 MII_CLR(RL_MII_CLK); 395 DELAY(1); 396 MII_SET(RL_MII_CLK); 397 } 398} 399 400/* 401 * Read an PHY register through the MII. 402 */ 403static int rl_mii_readreg(sc, frame) 404 struct rl_softc *sc; 405 struct rl_mii_frame *frame; 406 407{ 408 int i, ack; 409 410 RL_LOCK(sc); 411 412 /* 413 * Set up frame for RX. 414 */ 415 frame->mii_stdelim = RL_MII_STARTDELIM; 416 frame->mii_opcode = RL_MII_READOP; 417 frame->mii_turnaround = 0; 418 frame->mii_data = 0; 419 420 CSR_WRITE_2(sc, RL_MII, 0); 421 422 /* 423 * Turn on data xmit. 424 */ 425 MII_SET(RL_MII_DIR); 426 427 rl_mii_sync(sc); 428 429 /* 430 * Send command/address info. 431 */ 432 rl_mii_send(sc, frame->mii_stdelim, 2); 433 rl_mii_send(sc, frame->mii_opcode, 2); 434 rl_mii_send(sc, frame->mii_phyaddr, 5); 435 rl_mii_send(sc, frame->mii_regaddr, 5); 436 437 /* Idle bit */ 438 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 439 DELAY(1); 440 MII_SET(RL_MII_CLK); 441 DELAY(1); 442 443 /* Turn off xmit. */ 444 MII_CLR(RL_MII_DIR); 445 446 /* Check for ack */ 447 MII_CLR(RL_MII_CLK); 448 DELAY(1); 449 MII_SET(RL_MII_CLK); 450 DELAY(1); 451 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 452 453 /* 454 * Now try reading data bits. If the ack failed, we still 455 * need to clock through 16 cycles to keep the PHY(s) in sync. 456 */ 457 if (ack) { 458 for(i = 0; i < 16; i++) { 459 MII_CLR(RL_MII_CLK); 460 DELAY(1); 461 MII_SET(RL_MII_CLK); 462 DELAY(1); 463 } 464 goto fail; 465 } 466 467 for (i = 0x8000; i; i >>= 1) { 468 MII_CLR(RL_MII_CLK); 469 DELAY(1); 470 if (!ack) { 471 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 472 frame->mii_data |= i; 473 DELAY(1); 474 } 475 MII_SET(RL_MII_CLK); 476 DELAY(1); 477 } 478 479fail: 480 481 MII_CLR(RL_MII_CLK); 482 DELAY(1); 483 MII_SET(RL_MII_CLK); 484 DELAY(1); 485 486 RL_UNLOCK(sc); 487 488 if (ack) 489 return(1); 490 return(0); 491} 492 493/* 494 * Write to a PHY register through the MII. 495 */ 496static int rl_mii_writereg(sc, frame) 497 struct rl_softc *sc; 498 struct rl_mii_frame *frame; 499 500{ 501 RL_LOCK(sc); 502 503 /* 504 * Set up frame for TX. 505 */ 506 507 frame->mii_stdelim = RL_MII_STARTDELIM; 508 frame->mii_opcode = RL_MII_WRITEOP; 509 frame->mii_turnaround = RL_MII_TURNAROUND; 510 511 /* 512 * Turn on data output. 513 */ 514 MII_SET(RL_MII_DIR); 515 516 rl_mii_sync(sc); 517 518 rl_mii_send(sc, frame->mii_stdelim, 2); 519 rl_mii_send(sc, frame->mii_opcode, 2); 520 rl_mii_send(sc, frame->mii_phyaddr, 5); 521 rl_mii_send(sc, frame->mii_regaddr, 5); 522 rl_mii_send(sc, frame->mii_turnaround, 2); 523 rl_mii_send(sc, frame->mii_data, 16); 524 525 /* Idle bit. */ 526 MII_SET(RL_MII_CLK); 527 DELAY(1); 528 MII_CLR(RL_MII_CLK); 529 DELAY(1); 530 531 /* 532 * Turn off xmit. 533 */ 534 MII_CLR(RL_MII_DIR); 535 536 RL_UNLOCK(sc); 537 538 return(0); 539} 540 541static int rl_miibus_readreg(dev, phy, reg) 542 device_t dev; 543 int phy, reg; 544{ 545 struct rl_softc *sc; 546 struct rl_mii_frame frame; 547 u_int16_t rval = 0; 548 u_int16_t rl8139_reg = 0; 549 550 sc = device_get_softc(dev); 551 RL_LOCK(sc); 552 553 if (sc->rl_type == RL_8139) { 554 /* Pretend the internal PHY is only at address 0 */ 555 if (phy) { 556 RL_UNLOCK(sc); 557 return(0); 558 } 559 switch(reg) { 560 case MII_BMCR: 561 rl8139_reg = RL_BMCR; 562 break; 563 case MII_BMSR: 564 rl8139_reg = RL_BMSR; 565 break; 566 case MII_ANAR: 567 rl8139_reg = RL_ANAR; 568 break; 569 case MII_ANER: 570 rl8139_reg = RL_ANER; 571 break; 572 case MII_ANLPAR: 573 rl8139_reg = RL_LPAR; 574 break; 575 case MII_PHYIDR1: 576 case MII_PHYIDR2: 577 RL_UNLOCK(sc); 578 return(0); 579 break; 580 default: 581 printf("rl%d: bad phy register\n", sc->rl_unit); 582 RL_UNLOCK(sc); 583 return(0); 584 } 585 rval = CSR_READ_2(sc, rl8139_reg); 586 RL_UNLOCK(sc); 587 return(rval); 588 } 589 590 bzero((char *)&frame, sizeof(frame)); 591 592 frame.mii_phyaddr = phy; 593 frame.mii_regaddr = reg; 594 rl_mii_readreg(sc, &frame); 595 RL_UNLOCK(sc); 596 597 return(frame.mii_data); 598} 599 600static int rl_miibus_writereg(dev, phy, reg, data) 601 device_t dev; 602 int phy, reg, data; 603{ 604 struct rl_softc *sc; 605 struct rl_mii_frame frame; 606 u_int16_t rl8139_reg = 0; 607 608 sc = device_get_softc(dev); 609 RL_LOCK(sc); 610 611 if (sc->rl_type == RL_8139) { 612 /* Pretend the internal PHY is only at address 0 */ 613 if (phy) { 614 RL_UNLOCK(sc); 615 return(0); 616 } 617 switch(reg) { 618 case MII_BMCR: 619 rl8139_reg = RL_BMCR; 620 break; 621 case MII_BMSR: 622 rl8139_reg = RL_BMSR; 623 break; 624 case MII_ANAR: 625 rl8139_reg = RL_ANAR; 626 break; 627 case MII_ANER: 628 rl8139_reg = RL_ANER; 629 break; 630 case MII_ANLPAR: 631 rl8139_reg = RL_LPAR; 632 break; 633 case MII_PHYIDR1: 634 case MII_PHYIDR2: 635 RL_UNLOCK(sc); 636 return(0); 637 break; 638 default: 639 printf("rl%d: bad phy register\n", sc->rl_unit); 640 RL_UNLOCK(sc); 641 return(0); 642 } 643 CSR_WRITE_2(sc, rl8139_reg, data); 644 RL_UNLOCK(sc); 645 return(0); 646 } 647 648 bzero((char *)&frame, sizeof(frame)); 649 650 frame.mii_phyaddr = phy; 651 frame.mii_regaddr = reg; 652 frame.mii_data = data; 653 654 rl_mii_writereg(sc, &frame); 655 656 RL_UNLOCK(sc); 657 return(0); 658} 659 660static void rl_miibus_statchg(dev) 661 device_t dev; 662{ 663 return; 664} 665 666/* 667 * Calculate CRC of a multicast group address, return the upper 6 bits. 668 */ 669static u_int8_t rl_calchash(addr) 670 caddr_t addr; 671{ 672 u_int32_t crc, carry; 673 int i, j; 674 u_int8_t c; 675 676 /* Compute CRC for the address value. */ 677 crc = 0xFFFFFFFF; /* initial value */ 678 679 for (i = 0; i < 6; i++) { 680 c = *(addr + i); 681 for (j = 0; j < 8; j++) { 682 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 683 crc <<= 1; 684 c >>= 1; 685 if (carry) 686 crc = (crc ^ 0x04c11db6) | carry; 687 } 688 } 689 690 /* return the filter bit position */ 691 return(crc >> 26); 692} 693 694/* 695 * Program the 64-bit multicast hash filter. 696 */ 697static void rl_setmulti(sc) 698 struct rl_softc *sc; 699{ 700 struct ifnet *ifp; 701 int h = 0; 702 u_int32_t hashes[2] = { 0, 0 }; 703 struct ifmultiaddr *ifma; 704 u_int32_t rxfilt; 705 int mcnt = 0; 706 707 ifp = &sc->arpcom.ac_if; 708 709 rxfilt = CSR_READ_4(sc, RL_RXCFG); 710 711 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 712 rxfilt |= RL_RXCFG_RX_MULTI; 713 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 714 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 715 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 716 return; 717 } 718 719 /* first, zot all the existing hash bits */ 720 CSR_WRITE_4(sc, RL_MAR0, 0); 721 CSR_WRITE_4(sc, RL_MAR4, 0); 722 723 /* now program new ones */ 724 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 725 if (ifma->ifma_addr->sa_family != AF_LINK) 726 continue; 727 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 728 if (h < 32) 729 hashes[0] |= (1 << h); 730 else 731 hashes[1] |= (1 << (h - 32)); 732 mcnt++; 733 } 734 735 if (mcnt) 736 rxfilt |= RL_RXCFG_RX_MULTI; 737 else 738 rxfilt &= ~RL_RXCFG_RX_MULTI; 739 740 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 741 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 742 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 743 744 return; 745} 746 747static void rl_reset(sc) 748 struct rl_softc *sc; 749{ 750 register int i; 751 752 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 753 754 for (i = 0; i < RL_TIMEOUT; i++) { 755 DELAY(10); 756 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 757 break; 758 } 759 if (i == RL_TIMEOUT) 760 printf("rl%d: reset never completed!\n", sc->rl_unit); 761 762 return; 763} 764 765/* 766 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 767 * IDs against our list and return a device name if we find a match. 768 */ 769static int rl_probe(dev) 770 device_t dev; 771{ 772 struct rl_type *t; 773 774 t = rl_devs; 775 776 while(t->rl_name != NULL) { 777 if ((pci_get_vendor(dev) == t->rl_vid) && 778 (pci_get_device(dev) == t->rl_did)) { 779 device_set_desc(dev, t->rl_name); 780 return(0); 781 } 782 t++; 783 } 784 785 return(ENXIO); 786} 787 788/* 789 * Attach the interface. Allocate softc structures, do ifmedia 790 * setup and ethernet/BPF attach. 791 */ 792static int rl_attach(dev) 793 device_t dev; 794{ 795 u_char eaddr[ETHER_ADDR_LEN]; 796 u_int32_t command; 797 struct rl_softc *sc; 798 struct ifnet *ifp; 799 u_int16_t rl_did = 0; 800 int unit, error = 0, rid; 801 802 sc = device_get_softc(dev); 803 unit = device_get_unit(dev); 804 bzero(sc, sizeof(struct rl_softc)); 805 806 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 807 RL_LOCK(sc); 808 809 /* 810 * Handle power management nonsense. 811 */ 812 813 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 814 u_int32_t iobase, membase, irq; 815 816 /* Save important PCI config data. */ 817 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 818 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 819 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 820 821 /* Reset the power state. */ 822 printf("rl%d: chip is is in D%d power mode " 823 "-- setting to D0\n", unit, 824 pci_get_powerstate(dev)); 825 826 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 827 828 /* Restore PCI config data. */ 829 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 830 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 831 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 832 } 833 834 /* 835 * Map control/status registers. 836 */ 837 pci_enable_busmaster(dev); 838 pci_enable_io(dev, SYS_RES_IOPORT); 839 pci_enable_io(dev, SYS_RES_MEMORY); 840 command = pci_read_config(dev, PCIR_COMMAND, 4); 841 842#ifdef RL_USEIOSPACE 843 if (!(command & PCIM_CMD_PORTEN)) { 844 printf("rl%d: failed to enable I/O ports!\n", unit); 845 error = ENXIO; 846 goto fail; 847 } 848#else 849 if (!(command & PCIM_CMD_MEMEN)) { 850 printf("rl%d: failed to enable memory mapping!\n", unit); 851 error = ENXIO; 852 goto fail; 853 } 854#endif 855 856 rid = RL_RID; 857 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 858 0, ~0, 1, RF_ACTIVE); 859 860 if (sc->rl_res == NULL) { 861 printf ("rl%d: couldn't map ports/memory\n", unit); 862 error = ENXIO; 863 goto fail; 864 } 865 866 /* Detect the Realtek 8139B. For some reason, this chip is very 867 * unstable when left to autoselect the media 868 * The best workaround is to set the device to the required 869 * media type or to set it to the 10 Meg speed. 870 */ 871 872 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 873 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 874 } 875 876 sc->rl_btag = rman_get_bustag(sc->rl_res); 877 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 878 879 rid = 0; 880 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 881 RF_SHAREABLE | RF_ACTIVE); 882 883 if (sc->rl_irq == NULL) { 884 printf("rl%d: couldn't map interrupt\n", unit); 885 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 886 error = ENXIO; 887 goto fail; 888 } 889 890 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 891 rl_intr, sc, &sc->rl_intrhand); 892 893 if (error) { 894 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 895 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 896 printf("rl%d: couldn't set up irq\n", unit); 897 goto fail; 898 } 899 900 callout_handle_init(&sc->rl_stat_ch); 901 902 /* Reset the adapter. */ 903 rl_reset(sc); 904 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 905 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 906 if (rl_did != 0x8129) 907 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 908 909 /* 910 * Get station address from the EEPROM. 911 */ 912 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 913 914 /* 915 * A RealTek chip was detected. Inform the world. 916 */ 917 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 918 919 sc->rl_unit = unit; 920 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 921 922 /* 923 * Now read the exact device type from the EEPROM to find 924 * out if it's an 8129 or 8139. 925 */ 926 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 927 928 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 929 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 930 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS) 931 sc->rl_type = RL_8139; 932 else if (rl_did == RT_DEVICEID_8129) 933 sc->rl_type = RL_8129; 934 else { 935 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 936 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 938 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 939 error = ENXIO; 940 goto fail; 941 } 942 943 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF, 944 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 945 946 if (sc->rl_cdata.rl_rx_buf == NULL) { 947 printf("rl%d: no memory for list buffers!\n", unit); 948 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 949 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 950 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 951 error = ENXIO; 952 goto fail; 953 } 954 955 /* Leave a few bytes before the start of the RX ring buffer. */ 956 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 957 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 958 959 /* Do MII setup */ 960 if (mii_phy_probe(dev, &sc->rl_miibus, 961 rl_ifmedia_upd, rl_ifmedia_sts)) { 962 printf("rl%d: MII without any phy!\n", sc->rl_unit); 963 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 964 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 965 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 966 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 967 error = ENXIO; 968 goto fail; 969 } 970 971 ifp = &sc->arpcom.ac_if; 972 ifp->if_softc = sc; 973 ifp->if_unit = unit; 974 ifp->if_name = "rl"; 975 ifp->if_mtu = ETHERMTU; 976 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 977 ifp->if_ioctl = rl_ioctl; 978 ifp->if_output = ether_output; 979 ifp->if_start = rl_start; 980 ifp->if_watchdog = rl_watchdog; 981 ifp->if_init = rl_init; 982 ifp->if_baudrate = 10000000; 983 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 984 985 /* 986 * Call MI attach routine. 987 */ 988 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 989 RL_UNLOCK(sc); 990 return(0); 991 992fail: 993 RL_UNLOCK(sc); 994 mtx_destroy(&sc->rl_mtx); 995 return(error); 996} 997 998static int rl_detach(dev) 999 device_t dev; 1000{ 1001 struct rl_softc *sc; 1002 struct ifnet *ifp; 1003 1004 sc = device_get_softc(dev); 1005 RL_LOCK(sc); 1006 ifp = &sc->arpcom.ac_if; 1007 1008 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1009 rl_stop(sc); 1010 1011 bus_generic_detach(dev); 1012 device_delete_child(dev, sc->rl_miibus); 1013 1014 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1015 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1016 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1017 1018 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF); 1019 1020 RL_UNLOCK(sc); 1021 mtx_destroy(&sc->rl_mtx); 1022 1023 return(0); 1024} 1025 1026/* 1027 * Initialize the transmit descriptors. 1028 */ 1029static int rl_list_tx_init(sc) 1030 struct rl_softc *sc; 1031{ 1032 struct rl_chain_data *cd; 1033 int i; 1034 1035 cd = &sc->rl_cdata; 1036 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1037 cd->rl_tx_chain[i] = NULL; 1038 CSR_WRITE_4(sc, 1039 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1040 } 1041 1042 sc->rl_cdata.cur_tx = 0; 1043 sc->rl_cdata.last_tx = 0; 1044 1045 return(0); 1046} 1047 1048/* 1049 * A frame has been uploaded: pass the resulting mbuf chain up to 1050 * the higher level protocols. 1051 * 1052 * You know there's something wrong with a PCI bus-master chip design 1053 * when you have to use m_devget(). 1054 * 1055 * The receive operation is badly documented in the datasheet, so I'll 1056 * attempt to document it here. The driver provides a buffer area and 1057 * places its base address in the RX buffer start address register. 1058 * The chip then begins copying frames into the RX buffer. Each frame 1059 * is preceded by a 32-bit RX status word which specifies the length 1060 * of the frame and certain other status bits. Each frame (starting with 1061 * the status word) is also 32-bit aligned. The frame length is in the 1062 * first 16 bits of the status word; the lower 15 bits correspond with 1063 * the 'rx status register' mentioned in the datasheet. 1064 * 1065 * Note: to make the Alpha happy, the frame payload needs to be aligned 1066 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1067 * as the offset argument to m_devget(). 1068 */ 1069static void rl_rxeof(sc) 1070 struct rl_softc *sc; 1071{ 1072 struct ether_header *eh; 1073 struct mbuf *m; 1074 struct ifnet *ifp; 1075 int total_len = 0; 1076 u_int32_t rxstat; 1077 caddr_t rxbufpos; 1078 int wrap = 0; 1079 u_int16_t cur_rx; 1080 u_int16_t limit; 1081 u_int16_t rx_bytes = 0, max_bytes; 1082 1083 ifp = &sc->arpcom.ac_if; 1084 1085 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1086 1087 /* Do not try to read past this point. */ 1088 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1089 1090 if (limit < cur_rx) 1091 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1092 else 1093 max_bytes = limit - cur_rx; 1094 1095 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1096 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1097 rxstat = *(u_int32_t *)rxbufpos; 1098 1099 /* 1100 * Here's a totally undocumented fact for you. When the 1101 * RealTek chip is in the process of copying a packet into 1102 * RAM for you, the length will be 0xfff0. If you spot a 1103 * packet header with this value, you need to stop. The 1104 * datasheet makes absolutely no mention of this and 1105 * RealTek should be shot for this. 1106 */ 1107 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1108 break; 1109 1110 if (!(rxstat & RL_RXSTAT_RXOK)) { 1111 ifp->if_ierrors++; 1112 rl_init(sc); 1113 return; 1114 } 1115 1116 /* No errors; receive the packet. */ 1117 total_len = rxstat >> 16; 1118 rx_bytes += total_len + 4; 1119 1120 /* 1121 * XXX The RealTek chip includes the CRC with every 1122 * received frame, and there's no way to turn this 1123 * behavior off (at least, I can't find anything in 1124 * the manual that explains how to do it) so we have 1125 * to trim off the CRC manually. 1126 */ 1127 total_len -= ETHER_CRC_LEN; 1128 1129 /* 1130 * Avoid trying to read more bytes than we know 1131 * the chip has prepared for us. 1132 */ 1133 if (rx_bytes > max_bytes) 1134 break; 1135 1136 rxbufpos = sc->rl_cdata.rl_rx_buf + 1137 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1138 1139 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1140 rxbufpos = sc->rl_cdata.rl_rx_buf; 1141 1142 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1143 1144 if (total_len > wrap) { 1145 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1146 NULL); 1147 if (m == NULL) { 1148 ifp->if_ierrors++; 1149 printf("rl%d: out of mbufs, tried to " 1150 "copy %d bytes\n", sc->rl_unit, wrap); 1151 } else { 1152 m_copyback(m, wrap, total_len - wrap, 1153 sc->rl_cdata.rl_rx_buf); 1154 } 1155 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1156 } else { 1157 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1158 NULL); 1159 if (m == NULL) { 1160 ifp->if_ierrors++; 1161 printf("rl%d: out of mbufs, tried to " 1162 "copy %d bytes\n", sc->rl_unit, total_len); 1163 } 1164 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1165 } 1166 1167 /* 1168 * Round up to 32-bit boundary. 1169 */ 1170 cur_rx = (cur_rx + 3) & ~3; 1171 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1172 1173 if (m == NULL) 1174 continue; 1175 1176 eh = mtod(m, struct ether_header *); 1177 ifp->if_ipackets++; 1178 1179 /* Remove header from mbuf and pass it on. */ 1180 m_adj(m, sizeof(struct ether_header)); 1181 ether_input(ifp, eh, m); 1182 } 1183 1184 return; 1185} 1186 1187/* 1188 * A frame was downloaded to the chip. It's safe for us to clean up 1189 * the list buffers. 1190 */ 1191static void rl_txeof(sc) 1192 struct rl_softc *sc; 1193{ 1194 struct ifnet *ifp; 1195 u_int32_t txstat; 1196 1197 ifp = &sc->arpcom.ac_if; 1198 1199 /* Clear the timeout timer. */ 1200 ifp->if_timer = 0; 1201 1202 /* 1203 * Go through our tx list and free mbufs for those 1204 * frames that have been uploaded. 1205 */ 1206 do { 1207 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1208 if (!(txstat & (RL_TXSTAT_TX_OK| 1209 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1210 break; 1211 1212 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1213 1214 if (RL_LAST_TXMBUF(sc) != NULL) { 1215 m_freem(RL_LAST_TXMBUF(sc)); 1216 RL_LAST_TXMBUF(sc) = NULL; 1217 } 1218 if (txstat & RL_TXSTAT_TX_OK) 1219 ifp->if_opackets++; 1220 else { 1221 int oldthresh; 1222 ifp->if_oerrors++; 1223 if ((txstat & RL_TXSTAT_TXABRT) || 1224 (txstat & RL_TXSTAT_OUTOFWIN)) 1225 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1226 oldthresh = sc->rl_txthresh; 1227 /* error recovery */ 1228 rl_reset(sc); 1229 rl_init(sc); 1230 /* 1231 * If there was a transmit underrun, 1232 * bump the TX threshold. 1233 */ 1234 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1235 sc->rl_txthresh = oldthresh + 32; 1236 return; 1237 } 1238 RL_INC(sc->rl_cdata.last_tx); 1239 ifp->if_flags &= ~IFF_OACTIVE; 1240 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1241 1242 return; 1243} 1244 1245static void rl_tick(xsc) 1246 void *xsc; 1247{ 1248 struct rl_softc *sc; 1249 struct mii_data *mii; 1250 1251 sc = xsc; 1252 RL_LOCK(sc); 1253 mii = device_get_softc(sc->rl_miibus); 1254 1255 mii_tick(mii); 1256 1257 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1258 RL_UNLOCK(sc); 1259 1260 return; 1261} 1262 1263static void rl_intr(arg) 1264 void *arg; 1265{ 1266 struct rl_softc *sc; 1267 struct ifnet *ifp; 1268 u_int16_t status; 1269 1270 sc = arg; 1271 RL_LOCK(sc); 1272 ifp = &sc->arpcom.ac_if; 1273 1274 /* Disable interrupts. */ 1275 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1276 1277 for (;;) { 1278 1279 status = CSR_READ_2(sc, RL_ISR); 1280 if (status) 1281 CSR_WRITE_2(sc, RL_ISR, status); 1282 1283 if ((status & RL_INTRS) == 0) 1284 break; 1285 1286 if (status & RL_ISR_RX_OK) 1287 rl_rxeof(sc); 1288 1289 if (status & RL_ISR_RX_ERR) 1290 rl_rxeof(sc); 1291 1292 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1293 rl_txeof(sc); 1294 1295 if (status & RL_ISR_SYSTEM_ERR) { 1296 rl_reset(sc); 1297 rl_init(sc); 1298 } 1299 1300 } 1301 1302 /* Re-enable interrupts. */ 1303 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1304 1305 if (ifp->if_snd.ifq_head != NULL) 1306 rl_start(ifp); 1307 1308 RL_UNLOCK(sc); 1309 1310 return; 1311} 1312 1313/* 1314 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1315 * pointers to the fragment pointers. 1316 */ 1317static int rl_encap(sc, m_head) 1318 struct rl_softc *sc; 1319 struct mbuf *m_head; 1320{ 1321 struct mbuf *m_new = NULL; 1322 1323 /* 1324 * The RealTek is brain damaged and wants longword-aligned 1325 * TX buffers, plus we can only have one fragment buffer 1326 * per packet. We have to copy pretty much all the time. 1327 */ 1328 1329 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1330 if (m_new == NULL) { 1331 printf("rl%d: no memory for tx list", sc->rl_unit); 1332 return(1); 1333 } 1334 if (m_head->m_pkthdr.len > MHLEN) { 1335 MCLGET(m_new, M_DONTWAIT); 1336 if (!(m_new->m_flags & M_EXT)) { 1337 m_freem(m_new); 1338 printf("rl%d: no memory for tx list", 1339 sc->rl_unit); 1340 return(1); 1341 } 1342 } 1343 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1344 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1345 m_freem(m_head); 1346 m_head = m_new; 1347 1348 /* Pad frames to at least 60 bytes. */ 1349 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1350 /* 1351 * Make security concious people happy: zero out the 1352 * bytes in the pad area, since we don't know what 1353 * this mbuf cluster buffer's previous user might 1354 * have left in it. 1355 */ 1356 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1357 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1358 m_head->m_pkthdr.len += 1359 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1360 m_head->m_len = m_head->m_pkthdr.len; 1361 } 1362 1363 RL_CUR_TXMBUF(sc) = m_head; 1364 1365 return(0); 1366} 1367 1368/* 1369 * Main transmit routine. 1370 */ 1371 1372static void rl_start(ifp) 1373 struct ifnet *ifp; 1374{ 1375 struct rl_softc *sc; 1376 struct mbuf *m_head = NULL; 1377 1378 sc = ifp->if_softc; 1379 RL_LOCK(sc); 1380 1381 while(RL_CUR_TXMBUF(sc) == NULL) { 1382 IF_DEQUEUE(&ifp->if_snd, m_head); 1383 if (m_head == NULL) 1384 break; 1385 1386 if (rl_encap(sc, m_head)) { 1387 IF_PREPEND(&ifp->if_snd, m_head); 1388 ifp->if_flags |= IFF_OACTIVE; 1389 break; 1390 } 1391 1392 /* 1393 * If there's a BPF listener, bounce a copy of this frame 1394 * to him. 1395 */ 1396 if (ifp->if_bpf) 1397 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1398 1399 /* 1400 * Transmit the frame. 1401 */ 1402 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1403 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1404 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1405 RL_TXTHRESH(sc->rl_txthresh) | 1406 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1407 1408 RL_INC(sc->rl_cdata.cur_tx); 1409 } 1410 1411 /* 1412 * We broke out of the loop because all our TX slots are 1413 * full. Mark the NIC as busy until it drains some of the 1414 * packets from the queue. 1415 */ 1416 if (RL_CUR_TXMBUF(sc) != NULL) 1417 ifp->if_flags |= IFF_OACTIVE; 1418 1419 /* 1420 * Set a timeout in case the chip goes out to lunch. 1421 */ 1422 ifp->if_timer = 5; 1423 RL_UNLOCK(sc); 1424 1425 return; 1426} 1427 1428static void rl_init(xsc) 1429 void *xsc; 1430{ 1431 struct rl_softc *sc = xsc; 1432 struct ifnet *ifp = &sc->arpcom.ac_if; 1433 struct mii_data *mii; 1434 int i; 1435 u_int32_t rxcfg = 0; 1436 1437 RL_LOCK(sc); 1438 mii = device_get_softc(sc->rl_miibus); 1439 1440 /* 1441 * Cancel pending I/O and free all RX/TX buffers. 1442 */ 1443 rl_stop(sc); 1444 1445 /* Init our MAC address */ 1446 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1447 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1448 } 1449 1450 /* Init the RX buffer pointer register. */ 1451 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1452 1453 /* Init TX descriptors. */ 1454 rl_list_tx_init(sc); 1455 1456 /* 1457 * Enable transmit and receive. 1458 */ 1459 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1460 1461 /* 1462 * Set the initial TX and RX configuration. 1463 */ 1464 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1465 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1466 1467 /* Set the individual bit to receive frames for this host only. */ 1468 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1469 rxcfg |= RL_RXCFG_RX_INDIV; 1470 1471 /* If we want promiscuous mode, set the allframes bit. */ 1472 if (ifp->if_flags & IFF_PROMISC) { 1473 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1474 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1475 } else { 1476 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1477 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1478 } 1479 1480 /* 1481 * Set capture broadcast bit to capture broadcast frames. 1482 */ 1483 if (ifp->if_flags & IFF_BROADCAST) { 1484 rxcfg |= RL_RXCFG_RX_BROAD; 1485 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1486 } else { 1487 rxcfg &= ~RL_RXCFG_RX_BROAD; 1488 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1489 } 1490 1491 /* 1492 * Program the multicast filter, if necessary. 1493 */ 1494 rl_setmulti(sc); 1495 1496 /* 1497 * Enable interrupts. 1498 */ 1499 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1500 1501 /* Set initial TX threshold */ 1502 sc->rl_txthresh = RL_TX_THRESH_INIT; 1503 1504 /* Start RX/TX process. */ 1505 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1506 1507 /* Enable receiver and transmitter. */ 1508 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1509 1510 mii_mediachg(mii); 1511 1512 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1513 1514 ifp->if_flags |= IFF_RUNNING; 1515 ifp->if_flags &= ~IFF_OACTIVE; 1516 1517 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1518 RL_UNLOCK(sc); 1519 1520 return; 1521} 1522 1523/* 1524 * Set media options. 1525 */ 1526static int rl_ifmedia_upd(ifp) 1527 struct ifnet *ifp; 1528{ 1529 struct rl_softc *sc; 1530 struct mii_data *mii; 1531 1532 sc = ifp->if_softc; 1533 mii = device_get_softc(sc->rl_miibus); 1534 mii_mediachg(mii); 1535 1536 return(0); 1537} 1538 1539/* 1540 * Report current media status. 1541 */ 1542static void rl_ifmedia_sts(ifp, ifmr) 1543 struct ifnet *ifp; 1544 struct ifmediareq *ifmr; 1545{ 1546 struct rl_softc *sc; 1547 struct mii_data *mii; 1548 1549 sc = ifp->if_softc; 1550 mii = device_get_softc(sc->rl_miibus); 1551 1552 mii_pollstat(mii); 1553 ifmr->ifm_active = mii->mii_media_active; 1554 ifmr->ifm_status = mii->mii_media_status; 1555 1556 return; 1557} 1558 1559static int rl_ioctl(ifp, command, data) 1560 struct ifnet *ifp; 1561 u_long command; 1562 caddr_t data; 1563{ 1564 struct rl_softc *sc = ifp->if_softc; 1565 struct ifreq *ifr = (struct ifreq *) data; 1566 struct mii_data *mii; 1567 int error = 0; 1568 1569 RL_LOCK(sc); 1570 1571 switch(command) { 1572 case SIOCSIFADDR: 1573 case SIOCGIFADDR: 1574 case SIOCSIFMTU: 1575 error = ether_ioctl(ifp, command, data); 1576 break; 1577 case SIOCSIFFLAGS: 1578 if (ifp->if_flags & IFF_UP) { 1579 rl_init(sc); 1580 } else { 1581 if (ifp->if_flags & IFF_RUNNING) 1582 rl_stop(sc); 1583 } 1584 error = 0; 1585 break; 1586 case SIOCADDMULTI: 1587 case SIOCDELMULTI: 1588 rl_setmulti(sc); 1589 error = 0; 1590 break; 1591 case SIOCGIFMEDIA: 1592 case SIOCSIFMEDIA: 1593 mii = device_get_softc(sc->rl_miibus); 1594 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1595 break; 1596 default: 1597 error = EINVAL; 1598 break; 1599 } 1600 1601 RL_UNLOCK(sc); 1602 1603 return(error); 1604} 1605 1606static void rl_watchdog(ifp) 1607 struct ifnet *ifp; 1608{ 1609 struct rl_softc *sc; 1610 1611 sc = ifp->if_softc; 1612 RL_LOCK(sc); 1613 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1614 ifp->if_oerrors++; 1615 1616 rl_txeof(sc); 1617 rl_rxeof(sc); 1618 rl_init(sc); 1619 RL_UNLOCK(sc); 1620 1621 return; 1622} 1623 1624/* 1625 * Stop the adapter and free any mbufs allocated to the 1626 * RX and TX lists. 1627 */ 1628static void rl_stop(sc) 1629 struct rl_softc *sc; 1630{ 1631 register int i; 1632 struct ifnet *ifp; 1633 1634 RL_LOCK(sc); 1635 ifp = &sc->arpcom.ac_if; 1636 ifp->if_timer = 0; 1637 1638 untimeout(rl_tick, sc, sc->rl_stat_ch); 1639 1640 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1641 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1642 1643 /* 1644 * Free the TX list buffers. 1645 */ 1646 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1647 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1648 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1649 sc->rl_cdata.rl_tx_chain[i] = NULL; 1650 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1651 } 1652 } 1653 1654 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1655 RL_UNLOCK(sc); 1656 return; 1657} 1658 1659/* 1660 * Stop all chip I/O so that the kernel's probe routines don't 1661 * get confused by errant DMAs when rebooting. 1662 */ 1663static void rl_shutdown(dev) 1664 device_t dev; 1665{ 1666 struct rl_softc *sc; 1667 1668 sc = device_get_softc(dev); 1669 1670 rl_stop(sc); 1671 1672 return; 1673} 1674