if_rl.c revision 70167
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 70167 2000-12-18 21:53:05Z wpaul $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 8740516Swpaul#include <sys/systm.h> 8840516Swpaul#include <sys/sockio.h> 8940516Swpaul#include <sys/mbuf.h> 9040516Swpaul#include <sys/malloc.h> 9140516Swpaul#include <sys/kernel.h> 9240516Swpaul#include <sys/socket.h> 9340516Swpaul 9440516Swpaul#include <net/if.h> 9540516Swpaul#include <net/if_arp.h> 9640516Swpaul#include <net/ethernet.h> 9740516Swpaul#include <net/if_dl.h> 9840516Swpaul#include <net/if_media.h> 9940516Swpaul 10040516Swpaul#include <net/bpf.h> 10140516Swpaul 10240516Swpaul#include <vm/vm.h> /* for vtophys */ 10340516Swpaul#include <vm/pmap.h> /* for vtophys */ 10441569Swpaul#include <machine/bus_pio.h> 10541569Swpaul#include <machine/bus_memio.h> 10641569Swpaul#include <machine/bus.h> 10750703Swpaul#include <machine/resource.h> 10850703Swpaul#include <sys/bus.h> 10950703Swpaul#include <sys/rman.h> 11040516Swpaul 11150703Swpaul#include <dev/mii/mii.h> 11250703Swpaul#include <dev/mii/miivar.h> 11350703Swpaul 11440516Swpaul#include <pci/pcireg.h> 11540516Swpaul#include <pci/pcivar.h> 11640516Swpaul 11759758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11859758Speter 11951089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12050703Swpaul#include "miibus_if.h" 12150703Swpaul 12240516Swpaul/* 12340516Swpaul * Default to using PIO access for this driver. On SMP systems, 12440516Swpaul * there appear to be problems with memory mapped mode: it looks like 12540516Swpaul * doing too many memory mapped access back to back in rapid succession 12640516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12740516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12840516Swpaul * uniprocessor systems though. 12940516Swpaul */ 13040516Swpaul#define RL_USEIOSPACE 13140516Swpaul 13240516Swpaul#include <pci/if_rlreg.h> 13340516Swpaul 13440516Swpaul#ifndef lint 13541591Sarchiestatic const char rcsid[] = 13650477Speter "$FreeBSD: head/sys/pci/if_rl.c 70167 2000-12-18 21:53:05Z wpaul $"; 13740516Swpaul#endif 13840516Swpaul 13940516Swpaul/* 14040516Swpaul * Various supported device vendors/types and their names. 14140516Swpaul */ 14240516Swpaulstatic struct rl_type rl_devs[] = { 14340516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14440516Swpaul "RealTek 8129 10/100BaseTX" }, 14540516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14640516Swpaul "RealTek 8139 10/100BaseTX" }, 14767771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14867771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14941243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 15041243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 15144238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15244238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15344238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15444238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15540516Swpaul { 0, 0, NULL } 15640516Swpaul}; 15740516Swpaul 15850703Swpaulstatic int rl_probe __P((device_t)); 15950703Swpaulstatic int rl_attach __P((device_t)); 16050703Swpaulstatic int rl_detach __P((device_t)); 16140516Swpaul 16245633Swpaulstatic int rl_encap __P((struct rl_softc *, struct mbuf * )); 16340516Swpaul 16440516Swpaulstatic void rl_rxeof __P((struct rl_softc *)); 16540516Swpaulstatic void rl_txeof __P((struct rl_softc *)); 16640516Swpaulstatic void rl_intr __P((void *)); 16750703Swpaulstatic void rl_tick __P((void *)); 16840516Swpaulstatic void rl_start __P((struct ifnet *)); 16940516Swpaulstatic int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 17040516Swpaulstatic void rl_init __P((void *)); 17140516Swpaulstatic void rl_stop __P((struct rl_softc *)); 17240516Swpaulstatic void rl_watchdog __P((struct ifnet *)); 17350703Swpaulstatic void rl_shutdown __P((device_t)); 17440516Swpaulstatic int rl_ifmedia_upd __P((struct ifnet *)); 17540516Swpaulstatic void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17640516Swpaul 17741656Swpaulstatic void rl_eeprom_putbyte __P((struct rl_softc *, int)); 17841656Swpaulstatic void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 17940516Swpaulstatic void rl_read_eeprom __P((struct rl_softc *, caddr_t, 18040516Swpaul int, int, int)); 18140516Swpaulstatic void rl_mii_sync __P((struct rl_softc *)); 18240516Swpaulstatic void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 18340516Swpaulstatic int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 18440516Swpaulstatic int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 18540516Swpaul 18650703Swpaulstatic int rl_miibus_readreg __P((device_t, int, int)); 18750703Swpaulstatic int rl_miibus_writereg __P((device_t, int, int, int)); 18850703Swpaulstatic void rl_miibus_statchg __P((device_t)); 18940516Swpaul 19041656Swpaulstatic u_int8_t rl_calchash __P((caddr_t)); 19140516Swpaulstatic void rl_setmulti __P((struct rl_softc *)); 19240516Swpaulstatic void rl_reset __P((struct rl_softc *)); 19340516Swpaulstatic int rl_list_tx_init __P((struct rl_softc *)); 19440516Swpaul 19550703Swpaul#ifdef RL_USEIOSPACE 19650703Swpaul#define RL_RES SYS_RES_IOPORT 19750703Swpaul#define RL_RID RL_PCI_LOIO 19850703Swpaul#else 19950703Swpaul#define RL_RES SYS_RES_MEMORY 20050703Swpaul#define RL_RID RL_PCI_LOMEM 20150703Swpaul#endif 20250703Swpaul 20350703Swpaulstatic device_method_t rl_methods[] = { 20450703Swpaul /* Device interface */ 20550703Swpaul DEVMETHOD(device_probe, rl_probe), 20650703Swpaul DEVMETHOD(device_attach, rl_attach), 20750703Swpaul DEVMETHOD(device_detach, rl_detach), 20850703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 20950703Swpaul 21050703Swpaul /* bus interface */ 21150703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 21250703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 21350703Swpaul 21450703Swpaul /* MII interface */ 21550703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 21650703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 21750703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 21850703Swpaul 21950703Swpaul { 0, 0 } 22050703Swpaul}; 22150703Swpaul 22250703Swpaulstatic driver_t rl_driver = { 22351455Swpaul "rl", 22450703Swpaul rl_methods, 22550703Swpaul sizeof(struct rl_softc) 22650703Swpaul}; 22750703Swpaul 22850703Swpaulstatic devclass_t rl_devclass; 22950703Swpaul 23051533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 23167931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 23251473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 23350703Swpaul 23440516Swpaul#define EE_SET(x) \ 23540516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 23640516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 23740516Swpaul 23840516Swpaul#define EE_CLR(x) \ 23940516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24040516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 24140516Swpaul 24240516Swpaul/* 24340516Swpaul * Send a read command and address to the EEPROM, check for ACK. 24440516Swpaul */ 24540516Swpaulstatic void rl_eeprom_putbyte(sc, addr) 24640516Swpaul struct rl_softc *sc; 24741656Swpaul int addr; 24840516Swpaul{ 24940516Swpaul register int d, i; 25040516Swpaul 25167931Swpaul d = addr | sc->rl_eecmd_read; 25240516Swpaul 25340516Swpaul /* 25455170Sbillf * Feed in each bit and strobe the clock. 25540516Swpaul */ 25640516Swpaul for (i = 0x400; i; i >>= 1) { 25740516Swpaul if (d & i) { 25840516Swpaul EE_SET(RL_EE_DATAIN); 25940516Swpaul } else { 26040516Swpaul EE_CLR(RL_EE_DATAIN); 26140516Swpaul } 26240516Swpaul DELAY(100); 26340516Swpaul EE_SET(RL_EE_CLK); 26440516Swpaul DELAY(150); 26540516Swpaul EE_CLR(RL_EE_CLK); 26640516Swpaul DELAY(100); 26740516Swpaul } 26840516Swpaul 26940516Swpaul return; 27040516Swpaul} 27140516Swpaul 27240516Swpaul/* 27340516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27440516Swpaul */ 27540516Swpaulstatic void rl_eeprom_getword(sc, addr, dest) 27640516Swpaul struct rl_softc *sc; 27741656Swpaul int addr; 27840516Swpaul u_int16_t *dest; 27940516Swpaul{ 28040516Swpaul register int i; 28140516Swpaul u_int16_t word = 0; 28240516Swpaul 28340516Swpaul /* Enter EEPROM access mode. */ 28440516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 28540516Swpaul 28640516Swpaul /* 28740516Swpaul * Send address of word we want to read. 28840516Swpaul */ 28940516Swpaul rl_eeprom_putbyte(sc, addr); 29040516Swpaul 29140516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 29240516Swpaul 29340516Swpaul /* 29440516Swpaul * Start reading bits from EEPROM. 29540516Swpaul */ 29640516Swpaul for (i = 0x8000; i; i >>= 1) { 29740516Swpaul EE_SET(RL_EE_CLK); 29840516Swpaul DELAY(100); 29940516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 30040516Swpaul word |= i; 30140516Swpaul EE_CLR(RL_EE_CLK); 30240516Swpaul DELAY(100); 30340516Swpaul } 30440516Swpaul 30540516Swpaul /* Turn off EEPROM access mode. */ 30640516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 30740516Swpaul 30840516Swpaul *dest = word; 30940516Swpaul 31040516Swpaul return; 31140516Swpaul} 31240516Swpaul 31340516Swpaul/* 31440516Swpaul * Read a sequence of words from the EEPROM. 31540516Swpaul */ 31640516Swpaulstatic void rl_read_eeprom(sc, dest, off, cnt, swap) 31740516Swpaul struct rl_softc *sc; 31840516Swpaul caddr_t dest; 31940516Swpaul int off; 32040516Swpaul int cnt; 32140516Swpaul int swap; 32240516Swpaul{ 32340516Swpaul int i; 32440516Swpaul u_int16_t word = 0, *ptr; 32540516Swpaul 32640516Swpaul for (i = 0; i < cnt; i++) { 32740516Swpaul rl_eeprom_getword(sc, off + i, &word); 32840516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 32940516Swpaul if (swap) 33040516Swpaul *ptr = ntohs(word); 33140516Swpaul else 33240516Swpaul *ptr = word; 33340516Swpaul } 33440516Swpaul 33540516Swpaul return; 33640516Swpaul} 33740516Swpaul 33840516Swpaul 33940516Swpaul/* 34040516Swpaul * MII access routines are provided for the 8129, which 34140516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 34240516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 34340516Swpaul * direct access PHY registers. 34440516Swpaul */ 34540516Swpaul#define MII_SET(x) \ 34640516Swpaul CSR_WRITE_1(sc, RL_MII, \ 34740516Swpaul CSR_READ_1(sc, RL_MII) | x) 34840516Swpaul 34940516Swpaul#define MII_CLR(x) \ 35040516Swpaul CSR_WRITE_1(sc, RL_MII, \ 35140516Swpaul CSR_READ_1(sc, RL_MII) & ~x) 35240516Swpaul 35340516Swpaul/* 35440516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 35540516Swpaul */ 35640516Swpaulstatic void rl_mii_sync(sc) 35740516Swpaul struct rl_softc *sc; 35840516Swpaul{ 35940516Swpaul register int i; 36040516Swpaul 36140516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 36240516Swpaul 36340516Swpaul for (i = 0; i < 32; i++) { 36440516Swpaul MII_SET(RL_MII_CLK); 36540516Swpaul DELAY(1); 36640516Swpaul MII_CLR(RL_MII_CLK); 36740516Swpaul DELAY(1); 36840516Swpaul } 36940516Swpaul 37040516Swpaul return; 37140516Swpaul} 37240516Swpaul 37340516Swpaul/* 37440516Swpaul * Clock a series of bits through the MII. 37540516Swpaul */ 37640516Swpaulstatic void rl_mii_send(sc, bits, cnt) 37740516Swpaul struct rl_softc *sc; 37840516Swpaul u_int32_t bits; 37940516Swpaul int cnt; 38040516Swpaul{ 38140516Swpaul int i; 38240516Swpaul 38340516Swpaul MII_CLR(RL_MII_CLK); 38440516Swpaul 38540516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 38640516Swpaul if (bits & i) { 38740516Swpaul MII_SET(RL_MII_DATAOUT); 38840516Swpaul } else { 38940516Swpaul MII_CLR(RL_MII_DATAOUT); 39040516Swpaul } 39140516Swpaul DELAY(1); 39240516Swpaul MII_CLR(RL_MII_CLK); 39340516Swpaul DELAY(1); 39440516Swpaul MII_SET(RL_MII_CLK); 39540516Swpaul } 39640516Swpaul} 39740516Swpaul 39840516Swpaul/* 39940516Swpaul * Read an PHY register through the MII. 40040516Swpaul */ 40140516Swpaulstatic int rl_mii_readreg(sc, frame) 40240516Swpaul struct rl_softc *sc; 40340516Swpaul struct rl_mii_frame *frame; 40440516Swpaul 40540516Swpaul{ 40667087Swpaul int i, ack; 40740516Swpaul 40867087Swpaul RL_LOCK(sc); 40940516Swpaul 41040516Swpaul /* 41140516Swpaul * Set up frame for RX. 41240516Swpaul */ 41340516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 41440516Swpaul frame->mii_opcode = RL_MII_READOP; 41540516Swpaul frame->mii_turnaround = 0; 41640516Swpaul frame->mii_data = 0; 41740516Swpaul 41840516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 41940516Swpaul 42040516Swpaul /* 42140516Swpaul * Turn on data xmit. 42240516Swpaul */ 42340516Swpaul MII_SET(RL_MII_DIR); 42440516Swpaul 42540516Swpaul rl_mii_sync(sc); 42640516Swpaul 42740516Swpaul /* 42840516Swpaul * Send command/address info. 42940516Swpaul */ 43040516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 43140516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 43240516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 43340516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 43440516Swpaul 43540516Swpaul /* Idle bit */ 43640516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 43740516Swpaul DELAY(1); 43840516Swpaul MII_SET(RL_MII_CLK); 43940516Swpaul DELAY(1); 44040516Swpaul 44140516Swpaul /* Turn off xmit. */ 44240516Swpaul MII_CLR(RL_MII_DIR); 44340516Swpaul 44440516Swpaul /* Check for ack */ 44540516Swpaul MII_CLR(RL_MII_CLK); 44640516Swpaul DELAY(1); 44740516Swpaul MII_SET(RL_MII_CLK); 44840516Swpaul DELAY(1); 44940516Swpaul ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 45040516Swpaul 45140516Swpaul /* 45240516Swpaul * Now try reading data bits. If the ack failed, we still 45340516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 45440516Swpaul */ 45540516Swpaul if (ack) { 45640516Swpaul for(i = 0; i < 16; i++) { 45740516Swpaul MII_CLR(RL_MII_CLK); 45840516Swpaul DELAY(1); 45940516Swpaul MII_SET(RL_MII_CLK); 46040516Swpaul DELAY(1); 46140516Swpaul } 46240516Swpaul goto fail; 46340516Swpaul } 46440516Swpaul 46540516Swpaul for (i = 0x8000; i; i >>= 1) { 46640516Swpaul MII_CLR(RL_MII_CLK); 46740516Swpaul DELAY(1); 46840516Swpaul if (!ack) { 46940516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 47040516Swpaul frame->mii_data |= i; 47140516Swpaul DELAY(1); 47240516Swpaul } 47340516Swpaul MII_SET(RL_MII_CLK); 47440516Swpaul DELAY(1); 47540516Swpaul } 47640516Swpaul 47740516Swpaulfail: 47840516Swpaul 47940516Swpaul MII_CLR(RL_MII_CLK); 48040516Swpaul DELAY(1); 48140516Swpaul MII_SET(RL_MII_CLK); 48240516Swpaul DELAY(1); 48340516Swpaul 48467087Swpaul RL_UNLOCK(sc); 48540516Swpaul 48640516Swpaul if (ack) 48740516Swpaul return(1); 48840516Swpaul return(0); 48940516Swpaul} 49040516Swpaul 49140516Swpaul/* 49240516Swpaul * Write to a PHY register through the MII. 49340516Swpaul */ 49440516Swpaulstatic int rl_mii_writereg(sc, frame) 49540516Swpaul struct rl_softc *sc; 49640516Swpaul struct rl_mii_frame *frame; 49740516Swpaul 49840516Swpaul{ 49967087Swpaul RL_LOCK(sc); 50040516Swpaul 50140516Swpaul /* 50240516Swpaul * Set up frame for TX. 50340516Swpaul */ 50440516Swpaul 50540516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 50640516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 50740516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 50840516Swpaul 50940516Swpaul /* 51040516Swpaul * Turn on data output. 51140516Swpaul */ 51240516Swpaul MII_SET(RL_MII_DIR); 51340516Swpaul 51440516Swpaul rl_mii_sync(sc); 51540516Swpaul 51640516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 51740516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 51840516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 51940516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 52040516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 52140516Swpaul rl_mii_send(sc, frame->mii_data, 16); 52240516Swpaul 52340516Swpaul /* Idle bit. */ 52440516Swpaul MII_SET(RL_MII_CLK); 52540516Swpaul DELAY(1); 52640516Swpaul MII_CLR(RL_MII_CLK); 52740516Swpaul DELAY(1); 52840516Swpaul 52940516Swpaul /* 53040516Swpaul * Turn off xmit. 53140516Swpaul */ 53240516Swpaul MII_CLR(RL_MII_DIR); 53340516Swpaul 53467087Swpaul RL_UNLOCK(sc); 53540516Swpaul 53640516Swpaul return(0); 53740516Swpaul} 53840516Swpaul 53950703Swpaulstatic int rl_miibus_readreg(dev, phy, reg) 54050703Swpaul device_t dev; 54150703Swpaul int phy, reg; 54250703Swpaul{ 54340516Swpaul struct rl_softc *sc; 54440516Swpaul struct rl_mii_frame frame; 54540516Swpaul u_int16_t rval = 0; 54640516Swpaul u_int16_t rl8139_reg = 0; 54740516Swpaul 54850703Swpaul sc = device_get_softc(dev); 54967087Swpaul RL_LOCK(sc); 55050703Swpaul 55140516Swpaul if (sc->rl_type == RL_8139) { 55250703Swpaul /* Pretend the internal PHY is only at address 0 */ 55367087Swpaul if (phy) { 55467087Swpaul RL_UNLOCK(sc); 55550703Swpaul return(0); 55667087Swpaul } 55740516Swpaul switch(reg) { 55850703Swpaul case MII_BMCR: 55940516Swpaul rl8139_reg = RL_BMCR; 56040516Swpaul break; 56150703Swpaul case MII_BMSR: 56240516Swpaul rl8139_reg = RL_BMSR; 56340516Swpaul break; 56450703Swpaul case MII_ANAR: 56540516Swpaul rl8139_reg = RL_ANAR; 56640516Swpaul break; 56750703Swpaul case MII_ANER: 56850703Swpaul rl8139_reg = RL_ANER; 56950703Swpaul break; 57050703Swpaul case MII_ANLPAR: 57140516Swpaul rl8139_reg = RL_LPAR; 57240516Swpaul break; 57350703Swpaul case MII_PHYIDR1: 57450703Swpaul case MII_PHYIDR2: 57567087Swpaul RL_UNLOCK(sc); 57650703Swpaul return(0); 57750703Swpaul break; 57840516Swpaul default: 57940516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 58067087Swpaul RL_UNLOCK(sc); 58140516Swpaul return(0); 58240516Swpaul } 58340516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 58467087Swpaul RL_UNLOCK(sc); 58540516Swpaul return(rval); 58640516Swpaul } 58740516Swpaul 58840516Swpaul bzero((char *)&frame, sizeof(frame)); 58940516Swpaul 59050703Swpaul frame.mii_phyaddr = phy; 59140516Swpaul frame.mii_regaddr = reg; 59240516Swpaul rl_mii_readreg(sc, &frame); 59367087Swpaul RL_UNLOCK(sc); 59440516Swpaul 59540516Swpaul return(frame.mii_data); 59640516Swpaul} 59740516Swpaul 59850703Swpaulstatic int rl_miibus_writereg(dev, phy, reg, data) 59950703Swpaul device_t dev; 60050703Swpaul int phy, reg, data; 60150703Swpaul{ 60240516Swpaul struct rl_softc *sc; 60340516Swpaul struct rl_mii_frame frame; 60440516Swpaul u_int16_t rl8139_reg = 0; 60540516Swpaul 60650703Swpaul sc = device_get_softc(dev); 60767087Swpaul RL_LOCK(sc); 60850703Swpaul 60940516Swpaul if (sc->rl_type == RL_8139) { 61050703Swpaul /* Pretend the internal PHY is only at address 0 */ 61167087Swpaul if (phy) { 61267087Swpaul RL_UNLOCK(sc); 61350703Swpaul return(0); 61467087Swpaul } 61540516Swpaul switch(reg) { 61650703Swpaul case MII_BMCR: 61740516Swpaul rl8139_reg = RL_BMCR; 61840516Swpaul break; 61950703Swpaul case MII_BMSR: 62040516Swpaul rl8139_reg = RL_BMSR; 62140516Swpaul break; 62250703Swpaul case MII_ANAR: 62340516Swpaul rl8139_reg = RL_ANAR; 62440516Swpaul break; 62550703Swpaul case MII_ANER: 62650703Swpaul rl8139_reg = RL_ANER; 62750703Swpaul break; 62850703Swpaul case MII_ANLPAR: 62940516Swpaul rl8139_reg = RL_LPAR; 63040516Swpaul break; 63150703Swpaul case MII_PHYIDR1: 63250703Swpaul case MII_PHYIDR2: 63367087Swpaul RL_UNLOCK(sc); 63450703Swpaul return(0); 63550703Swpaul break; 63640516Swpaul default: 63740516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 63867087Swpaul RL_UNLOCK(sc); 63950703Swpaul return(0); 64040516Swpaul } 64140516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 64267087Swpaul RL_UNLOCK(sc); 64350703Swpaul return(0); 64440516Swpaul } 64540516Swpaul 64640516Swpaul bzero((char *)&frame, sizeof(frame)); 64740516Swpaul 64850703Swpaul frame.mii_phyaddr = phy; 64940516Swpaul frame.mii_regaddr = reg; 65040516Swpaul frame.mii_data = data; 65140516Swpaul 65240516Swpaul rl_mii_writereg(sc, &frame); 65340516Swpaul 65467087Swpaul RL_UNLOCK(sc); 65550703Swpaul return(0); 65650703Swpaul} 65750703Swpaul 65850703Swpaulstatic void rl_miibus_statchg(dev) 65950703Swpaul device_t dev; 66050703Swpaul{ 66140516Swpaul return; 66240516Swpaul} 66340516Swpaul 66440516Swpaul/* 66543062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 66640516Swpaul */ 66740516Swpaulstatic u_int8_t rl_calchash(addr) 66841656Swpaul caddr_t addr; 66940516Swpaul{ 67040516Swpaul u_int32_t crc, carry; 67140516Swpaul int i, j; 67240516Swpaul u_int8_t c; 67340516Swpaul 67440516Swpaul /* Compute CRC for the address value. */ 67540516Swpaul crc = 0xFFFFFFFF; /* initial value */ 67640516Swpaul 67740516Swpaul for (i = 0; i < 6; i++) { 67840516Swpaul c = *(addr + i); 67940516Swpaul for (j = 0; j < 8; j++) { 68040516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 68140516Swpaul crc <<= 1; 68240516Swpaul c >>= 1; 68340516Swpaul if (carry) 68440516Swpaul crc = (crc ^ 0x04c11db6) | carry; 68540516Swpaul } 68640516Swpaul } 68740516Swpaul 68840516Swpaul /* return the filter bit position */ 68943062Swpaul return(crc >> 26); 69040516Swpaul} 69140516Swpaul 69240516Swpaul/* 69340516Swpaul * Program the 64-bit multicast hash filter. 69440516Swpaul */ 69540516Swpaulstatic void rl_setmulti(sc) 69640516Swpaul struct rl_softc *sc; 69740516Swpaul{ 69840516Swpaul struct ifnet *ifp; 69940516Swpaul int h = 0; 70040516Swpaul u_int32_t hashes[2] = { 0, 0 }; 70140516Swpaul struct ifmultiaddr *ifma; 70240516Swpaul u_int32_t rxfilt; 70340516Swpaul int mcnt = 0; 70440516Swpaul 70540516Swpaul ifp = &sc->arpcom.ac_if; 70640516Swpaul 70740516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 70840516Swpaul 70943062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 71040516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 71140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 71240516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 71340516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 71440516Swpaul return; 71540516Swpaul } 71640516Swpaul 71740516Swpaul /* first, zot all the existing hash bits */ 71840516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 71940516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 72040516Swpaul 72140516Swpaul /* now program new ones */ 72240516Swpaul for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 72340516Swpaul ifma = ifma->ifma_link.le_next) { 72440516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 72540516Swpaul continue; 72640516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 72740516Swpaul if (h < 32) 72840516Swpaul hashes[0] |= (1 << h); 72940516Swpaul else 73040516Swpaul hashes[1] |= (1 << (h - 32)); 73140516Swpaul mcnt++; 73240516Swpaul } 73340516Swpaul 73440516Swpaul if (mcnt) 73540516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 73640516Swpaul else 73740516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 73840516Swpaul 73940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 74040516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 74140516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 74240516Swpaul 74340516Swpaul return; 74440516Swpaul} 74540516Swpaul 74640516Swpaulstatic void rl_reset(sc) 74740516Swpaul struct rl_softc *sc; 74840516Swpaul{ 74940516Swpaul register int i; 75040516Swpaul 75140516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 75240516Swpaul 75340516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 75440516Swpaul DELAY(10); 75540516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 75640516Swpaul break; 75740516Swpaul } 75840516Swpaul if (i == RL_TIMEOUT) 75940516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 76040516Swpaul 76140516Swpaul return; 76240516Swpaul} 76340516Swpaul 76440516Swpaul/* 76540516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 76640516Swpaul * IDs against our list and return a device name if we find a match. 76740516Swpaul */ 76850703Swpaulstatic int rl_probe(dev) 76950703Swpaul device_t dev; 77040516Swpaul{ 77140516Swpaul struct rl_type *t; 77240516Swpaul 77340516Swpaul t = rl_devs; 77440516Swpaul 77540516Swpaul while(t->rl_name != NULL) { 77650703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 77750703Swpaul (pci_get_device(dev) == t->rl_did)) { 77850703Swpaul device_set_desc(dev, t->rl_name); 77950703Swpaul return(0); 78040516Swpaul } 78140516Swpaul t++; 78240516Swpaul } 78340516Swpaul 78450703Swpaul return(ENXIO); 78540516Swpaul} 78640516Swpaul 78740516Swpaul/* 78840516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 78940516Swpaul * setup and ethernet/BPF attach. 79040516Swpaul */ 79150703Swpaulstatic int rl_attach(dev) 79250703Swpaul device_t dev; 79340516Swpaul{ 79440516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 79540516Swpaul u_int32_t command; 79640516Swpaul struct rl_softc *sc; 79740516Swpaul struct ifnet *ifp; 79840516Swpaul u_int16_t rl_did = 0; 79950703Swpaul int unit, error = 0, rid; 80040516Swpaul 80150703Swpaul sc = device_get_softc(dev); 80250703Swpaul unit = device_get_unit(dev); 80340516Swpaul bzero(sc, sizeof(struct rl_softc)); 80440516Swpaul 80569583Swpaul mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_DEF); 80669583Swpaul RL_LOCK(sc); 80769583Swpaul 80840516Swpaul /* 80940516Swpaul * Handle power management nonsense. 81040516Swpaul */ 81140516Swpaul 81270167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 81370167Swpaul u_int32_t iobase, membase, irq; 81440516Swpaul 81570167Swpaul /* Save important PCI config data. */ 81670167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 81770167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 81870167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 81940516Swpaul 82070167Swpaul /* Reset the power state. */ 82170167Swpaul printf("rl%d: chip is is in D%d power mode " 82270167Swpaul "-- setting to D0\n", unit, 82370167Swpaul pci_get_powerstate(dev)); 82440516Swpaul 82570167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 82640516Swpaul 82770167Swpaul /* Restore PCI config data. */ 82870167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 82970167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 83070167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 83140516Swpaul } 83240516Swpaul 83340516Swpaul /* 83440516Swpaul * Map control/status registers. 83540516Swpaul */ 83661041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 83740516Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 83861041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 83961041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 84040516Swpaul 84140516Swpaul#ifdef RL_USEIOSPACE 84240516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 84340516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 84450703Swpaul error = ENXIO; 84540516Swpaul goto fail; 84640516Swpaul } 84740516Swpaul#else 84840516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 84940516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 85050703Swpaul error = ENXIO; 85140516Swpaul goto fail; 85240516Swpaul } 85350703Swpaul#endif 85440516Swpaul 85550703Swpaul rid = RL_RID; 85650703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 85750703Swpaul 0, ~0, 1, RF_ACTIVE); 85850703Swpaul 85950703Swpaul if (sc->rl_res == NULL) { 86050703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 86150703Swpaul error = ENXIO; 86240516Swpaul goto fail; 86340516Swpaul } 86440516Swpaul 86569127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 86669127Sroger * unstable when left to autoselect the media 86769127Sroger * The best workaround is to set the device to the required 86869127Sroger * media type or to set it to the 10 Meg speed. 86969127Sroger */ 87069127Sroger 87169127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 87269127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 87369127Sroger } 87469127Sroger 87550703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 87650703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 87750703Swpaul 87850703Swpaul rid = 0; 87950703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 88050703Swpaul RF_SHAREABLE | RF_ACTIVE); 88150703Swpaul 88250703Swpaul if (sc->rl_irq == NULL) { 88340516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 88450703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 88550703Swpaul error = ENXIO; 88640516Swpaul goto fail; 88740516Swpaul } 88840516Swpaul 88950703Swpaul error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 89050703Swpaul rl_intr, sc, &sc->rl_intrhand); 89150703Swpaul 89250703Swpaul if (error) { 89368215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 89450703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 89550703Swpaul printf("rl%d: couldn't set up irq\n", unit); 89650703Swpaul goto fail; 89750703Swpaul } 89850703Swpaul 89950703Swpaul callout_handle_init(&sc->rl_stat_ch); 90050703Swpaul 90140516Swpaul /* Reset the adapter. */ 90240516Swpaul rl_reset(sc); 90367931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 90467931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 90568215Swpaul if (rl_did != 0x8129) 90667931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 90740516Swpaul 90840516Swpaul /* 90940516Swpaul * Get station address from the EEPROM. 91040516Swpaul */ 91140516Swpaul rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 91240516Swpaul 91340516Swpaul /* 91440516Swpaul * A RealTek chip was detected. Inform the world. 91540516Swpaul */ 91640516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 91740516Swpaul 91840516Swpaul sc->rl_unit = unit; 91940516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 92040516Swpaul 92140516Swpaul /* 92240516Swpaul * Now read the exact device type from the EEPROM to find 92340516Swpaul * out if it's an 8129 or 8139. 92440516Swpaul */ 92540516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 92640516Swpaul 92744238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 92867771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 92967771Swpaul rl_did == RT_DEVICEID_8138) 93040516Swpaul sc->rl_type = RL_8139; 93140516Swpaul else if (rl_did == RT_DEVICEID_8129) 93240516Swpaul sc->rl_type = RL_8129; 93340516Swpaul else { 93440516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 93550703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 93668215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 93750703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 93850703Swpaul error = ENXIO; 93940516Swpaul goto fail; 94040516Swpaul } 94140516Swpaul 94260043Swpaul sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF, 94351657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 94440516Swpaul 94540516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 94640516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 94750703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 94868215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 94950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 95050703Swpaul error = ENXIO; 95140516Swpaul goto fail; 95240516Swpaul } 95340516Swpaul 95448028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 95548028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 95648028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 95748028Swpaul 95850703Swpaul /* Do MII setup */ 95950703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 96050703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 96150703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 96250703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 96368215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 96450703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 96550703Swpaul free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 96650703Swpaul error = ENXIO; 96750703Swpaul goto fail; 96850703Swpaul } 96950703Swpaul 97040516Swpaul ifp = &sc->arpcom.ac_if; 97140516Swpaul ifp->if_softc = sc; 97240516Swpaul ifp->if_unit = unit; 97340516Swpaul ifp->if_name = "rl"; 97440516Swpaul ifp->if_mtu = ETHERMTU; 97540516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 97640516Swpaul ifp->if_ioctl = rl_ioctl; 97740516Swpaul ifp->if_output = ether_output; 97840516Swpaul ifp->if_start = rl_start; 97940516Swpaul ifp->if_watchdog = rl_watchdog; 98040516Swpaul ifp->if_init = rl_init; 98140516Swpaul ifp->if_baudrate = 10000000; 98245633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 98340516Swpaul 98440516Swpaul /* 98563090Sarchie * Call MI attach routine. 98640516Swpaul */ 98763090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 98867087Swpaul RL_UNLOCK(sc); 98967087Swpaul return(0); 99040516Swpaul 99140516Swpaulfail: 99267087Swpaul RL_UNLOCK(sc); 99367087Swpaul mtx_destroy(&sc->rl_mtx); 99450703Swpaul return(error); 99540516Swpaul} 99640516Swpaul 99750703Swpaulstatic int rl_detach(dev) 99850703Swpaul device_t dev; 99950703Swpaul{ 100050703Swpaul struct rl_softc *sc; 100150703Swpaul struct ifnet *ifp; 100250703Swpaul 100350703Swpaul sc = device_get_softc(dev); 100467087Swpaul RL_LOCK(sc); 100550703Swpaul ifp = &sc->arpcom.ac_if; 100650703Swpaul 100763090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 100850703Swpaul rl_stop(sc); 100950703Swpaul 101050703Swpaul bus_generic_detach(dev); 101150703Swpaul device_delete_child(dev, sc->rl_miibus); 101250703Swpaul 101350703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 101468215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 101550703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 101650703Swpaul 101752426Swpaul contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF); 101850703Swpaul 101967087Swpaul RL_UNLOCK(sc); 102067087Swpaul mtx_destroy(&sc->rl_mtx); 102150703Swpaul 102250703Swpaul return(0); 102350703Swpaul} 102450703Swpaul 102540516Swpaul/* 102640516Swpaul * Initialize the transmit descriptors. 102740516Swpaul */ 102840516Swpaulstatic int rl_list_tx_init(sc) 102940516Swpaul struct rl_softc *sc; 103040516Swpaul{ 103140516Swpaul struct rl_chain_data *cd; 103240516Swpaul int i; 103340516Swpaul 103440516Swpaul cd = &sc->rl_cdata; 103540516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 103645633Swpaul cd->rl_tx_chain[i] = NULL; 103748028Swpaul CSR_WRITE_4(sc, 103848028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 103940516Swpaul } 104040516Swpaul 104145633Swpaul sc->rl_cdata.cur_tx = 0; 104245633Swpaul sc->rl_cdata.last_tx = 0; 104340516Swpaul 104440516Swpaul return(0); 104540516Swpaul} 104640516Swpaul 104740516Swpaul/* 104840516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 104940516Swpaul * the higher level protocols. 105040516Swpaul * 105140516Swpaul * You know there's something wrong with a PCI bus-master chip design 105240516Swpaul * when you have to use m_devget(). 105340516Swpaul * 105440516Swpaul * The receive operation is badly documented in the datasheet, so I'll 105540516Swpaul * attempt to document it here. The driver provides a buffer area and 105640516Swpaul * places its base address in the RX buffer start address register. 105740516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 105840516Swpaul * is preceeded by a 32-bit RX status word which specifies the length 105940516Swpaul * of the frame and certain other status bits. Each frame (starting with 106040516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 106140516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 106240516Swpaul * the 'rx status register' mentioned in the datasheet. 106348028Swpaul * 106448028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 106548028Swpaul * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 106648028Swpaul * the ring buffer starting at an address two bytes before the actual 106748028Swpaul * data location. We can then shave off the first two bytes using m_adj(). 106848028Swpaul * The reason we do this is because m_devget() doesn't let us specify an 106948028Swpaul * offset into the mbuf storage space, so we have to artificially create 107048028Swpaul * one. The ring is allocated in such a way that there are a few unused 107148028Swpaul * bytes of space preceecing it so that it will be safe for us to do the 107248028Swpaul * 2-byte backstep even if reading from the ring at offset 0. 107340516Swpaul */ 107440516Swpaulstatic void rl_rxeof(sc) 107540516Swpaul struct rl_softc *sc; 107640516Swpaul{ 107740516Swpaul struct ether_header *eh; 107840516Swpaul struct mbuf *m; 107940516Swpaul struct ifnet *ifp; 108040516Swpaul int total_len = 0; 108140516Swpaul u_int32_t rxstat; 108240516Swpaul caddr_t rxbufpos; 108340516Swpaul int wrap = 0; 108440516Swpaul u_int16_t cur_rx; 108540516Swpaul u_int16_t limit; 108640516Swpaul u_int16_t rx_bytes = 0, max_bytes; 108740516Swpaul 108840516Swpaul ifp = &sc->arpcom.ac_if; 108940516Swpaul 109040516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 109140516Swpaul 109240516Swpaul /* Do not try to read past this point. */ 109340516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 109440516Swpaul 109540516Swpaul if (limit < cur_rx) 109640516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 109740516Swpaul else 109840516Swpaul max_bytes = limit - cur_rx; 109940516Swpaul 110042738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 110140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 110240516Swpaul rxstat = *(u_int32_t *)rxbufpos; 110340516Swpaul 110440516Swpaul /* 110540516Swpaul * Here's a totally undocumented fact for you. When the 110640516Swpaul * RealTek chip is in the process of copying a packet into 110740516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 110840516Swpaul * packet header with this value, you need to stop. The 110940516Swpaul * datasheet makes absolutely no mention of this and 111040516Swpaul * RealTek should be shot for this. 111140516Swpaul */ 111240516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 111340516Swpaul break; 111440516Swpaul 111540516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 111640516Swpaul ifp->if_ierrors++; 111750703Swpaul rl_init(sc); 111850703Swpaul return; 111940516Swpaul } 112040516Swpaul 112140516Swpaul /* No errors; receive the packet. */ 112240516Swpaul total_len = rxstat >> 16; 112340516Swpaul rx_bytes += total_len + 4; 112440516Swpaul 112540516Swpaul /* 112642051Swpaul * XXX The RealTek chip includes the CRC with every 112742051Swpaul * received frame, and there's no way to turn this 112842051Swpaul * behavior off (at least, I can't find anything in 112942051Swpaul * the manual that explains how to do it) so we have 113042051Swpaul * to trim off the CRC manually. 113142051Swpaul */ 113242051Swpaul total_len -= ETHER_CRC_LEN; 113342051Swpaul 113442051Swpaul /* 113540516Swpaul * Avoid trying to read more bytes than we know 113640516Swpaul * the chip has prepared for us. 113740516Swpaul */ 113840516Swpaul if (rx_bytes > max_bytes) 113940516Swpaul break; 114040516Swpaul 114140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 114240516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 114340516Swpaul 114440516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 114540516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 114640516Swpaul 114740516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 114840516Swpaul 114940516Swpaul if (total_len > wrap) { 115060043Swpaul /* 115160043Swpaul * Fool m_devget() into thinking we want to copy 115260043Swpaul * the whole buffer so we don't end up fragmenting 115360043Swpaul * the data. 115460043Swpaul */ 115548028Swpaul m = m_devget(rxbufpos - RL_ETHER_ALIGN, 115660043Swpaul total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 115740516Swpaul if (m == NULL) { 115840516Swpaul ifp->if_ierrors++; 115940516Swpaul printf("rl%d: out of mbufs, tried to " 116052426Swpaul "copy %d bytes\n", sc->rl_unit, wrap); 116152426Swpaul } else { 116248028Swpaul m_adj(m, RL_ETHER_ALIGN); 116340516Swpaul m_copyback(m, wrap, total_len - wrap, 116440516Swpaul sc->rl_cdata.rl_rx_buf); 116548028Swpaul } 116642051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 116740516Swpaul } else { 116848028Swpaul m = m_devget(rxbufpos - RL_ETHER_ALIGN, 116948028Swpaul total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 117040516Swpaul if (m == NULL) { 117140516Swpaul ifp->if_ierrors++; 117240516Swpaul printf("rl%d: out of mbufs, tried to " 117352426Swpaul "copy %d bytes\n", sc->rl_unit, total_len); 117448028Swpaul } else 117548028Swpaul m_adj(m, RL_ETHER_ALIGN); 117642051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 117740516Swpaul } 117840516Swpaul 117940516Swpaul /* 118040516Swpaul * Round up to 32-bit boundary. 118140516Swpaul */ 118240516Swpaul cur_rx = (cur_rx + 3) & ~3; 118340516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 118440516Swpaul 118540516Swpaul if (m == NULL) 118640516Swpaul continue; 118740516Swpaul 118840516Swpaul eh = mtod(m, struct ether_header *); 118940516Swpaul ifp->if_ipackets++; 119040516Swpaul 119140516Swpaul /* Remove header from mbuf and pass it on. */ 119240516Swpaul m_adj(m, sizeof(struct ether_header)); 119340516Swpaul ether_input(ifp, eh, m); 119440516Swpaul } 119540516Swpaul 119640516Swpaul return; 119740516Swpaul} 119840516Swpaul 119940516Swpaul/* 120040516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 120140516Swpaul * the list buffers. 120240516Swpaul */ 120340516Swpaulstatic void rl_txeof(sc) 120440516Swpaul struct rl_softc *sc; 120540516Swpaul{ 120640516Swpaul struct ifnet *ifp; 120740516Swpaul u_int32_t txstat; 120840516Swpaul 120940516Swpaul ifp = &sc->arpcom.ac_if; 121040516Swpaul 121140516Swpaul /* Clear the timeout timer. */ 121240516Swpaul ifp->if_timer = 0; 121340516Swpaul 121440516Swpaul /* 121540516Swpaul * Go through our tx list and free mbufs for those 121640516Swpaul * frames that have been uploaded. 121740516Swpaul */ 121845633Swpaul do { 121945633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 122045633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 122145633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 122240516Swpaul break; 122340516Swpaul 122445633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 122540516Swpaul 122645633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 122745633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 122845633Swpaul RL_LAST_TXMBUF(sc) = NULL; 122945633Swpaul } 123045633Swpaul if (txstat & RL_TXSTAT_TX_OK) 123145633Swpaul ifp->if_opackets++; 123245633Swpaul else { 123352426Swpaul int oldthresh; 123445633Swpaul ifp->if_oerrors++; 123545633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 123645633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 123745633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 123852426Swpaul oldthresh = sc->rl_txthresh; 123952426Swpaul /* error recovery */ 124052426Swpaul rl_reset(sc); 124152426Swpaul rl_init(sc); 124252426Swpaul /* 124352426Swpaul * If there was a transmit underrun, 124452426Swpaul * bump the TX threshold. 124552426Swpaul */ 124652426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 124752426Swpaul sc->rl_txthresh = oldthresh + 32; 124852426Swpaul return; 124945633Swpaul } 125045633Swpaul RL_INC(sc->rl_cdata.last_tx); 125145633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 125245633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 125340516Swpaul 125450703Swpaul return; 125550703Swpaul} 125640516Swpaul 125750703Swpaulstatic void rl_tick(xsc) 125850703Swpaul void *xsc; 125950703Swpaul{ 126050703Swpaul struct rl_softc *sc; 126150703Swpaul struct mii_data *mii; 126250703Swpaul 126350703Swpaul sc = xsc; 126467087Swpaul RL_LOCK(sc); 126550703Swpaul mii = device_get_softc(sc->rl_miibus); 126650703Swpaul 126750703Swpaul mii_tick(mii); 126850703Swpaul 126950703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 127067087Swpaul RL_UNLOCK(sc); 127150703Swpaul 127240516Swpaul return; 127340516Swpaul} 127440516Swpaul 127540516Swpaulstatic void rl_intr(arg) 127640516Swpaul void *arg; 127740516Swpaul{ 127840516Swpaul struct rl_softc *sc; 127940516Swpaul struct ifnet *ifp; 128040516Swpaul u_int16_t status; 128140516Swpaul 128240516Swpaul sc = arg; 128367087Swpaul RL_LOCK(sc); 128440516Swpaul ifp = &sc->arpcom.ac_if; 128540516Swpaul 128640516Swpaul /* Disable interrupts. */ 128740516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 128840516Swpaul 128940516Swpaul for (;;) { 129040516Swpaul 129140516Swpaul status = CSR_READ_2(sc, RL_ISR); 129240516Swpaul if (status) 129340516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 129440516Swpaul 129540516Swpaul if ((status & RL_INTRS) == 0) 129640516Swpaul break; 129740516Swpaul 129840516Swpaul if (status & RL_ISR_RX_OK) 129940516Swpaul rl_rxeof(sc); 130040516Swpaul 130140516Swpaul if (status & RL_ISR_RX_ERR) 130240516Swpaul rl_rxeof(sc); 130340516Swpaul 130445633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 130540516Swpaul rl_txeof(sc); 130640516Swpaul 130740516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 130840516Swpaul rl_reset(sc); 130940516Swpaul rl_init(sc); 131040516Swpaul } 131140516Swpaul 131240516Swpaul } 131340516Swpaul 131440516Swpaul /* Re-enable interrupts. */ 131540516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 131640516Swpaul 131752426Swpaul if (ifp->if_snd.ifq_head != NULL) 131840516Swpaul rl_start(ifp); 131940516Swpaul 132067087Swpaul RL_UNLOCK(sc); 132167087Swpaul 132240516Swpaul return; 132340516Swpaul} 132440516Swpaul 132540516Swpaul/* 132640516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 132740516Swpaul * pointers to the fragment pointers. 132840516Swpaul */ 132945633Swpaulstatic int rl_encap(sc, m_head) 133040516Swpaul struct rl_softc *sc; 133140516Swpaul struct mbuf *m_head; 133240516Swpaul{ 133341243Swpaul struct mbuf *m_new = NULL; 133440516Swpaul 133540516Swpaul /* 133645633Swpaul * The RealTek is brain damaged and wants longword-aligned 133745633Swpaul * TX buffers, plus we can only have one fragment buffer 133845633Swpaul * per packet. We have to copy pretty much all the time. 133940516Swpaul */ 134040516Swpaul 134141243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 134241243Swpaul if (m_new == NULL) { 134341243Swpaul printf("rl%d: no memory for tx list", sc->rl_unit); 134441243Swpaul return(1); 134541243Swpaul } 134641243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 134741243Swpaul MCLGET(m_new, M_DONTWAIT); 134841243Swpaul if (!(m_new->m_flags & M_EXT)) { 134941243Swpaul m_freem(m_new); 135041243Swpaul printf("rl%d: no memory for tx list", 135141243Swpaul sc->rl_unit); 135240516Swpaul return(1); 135340516Swpaul } 135440516Swpaul } 135552426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 135641243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 135741243Swpaul m_freem(m_head); 135841243Swpaul m_head = m_new; 135940516Swpaul 136040516Swpaul /* Pad frames to at least 60 bytes. */ 136141243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 136255058Swpaul /* 136355058Swpaul * Make security concious people happy: zero out the 136455058Swpaul * bytes in the pad area, since we don't know what 136555058Swpaul * this mbuf cluster buffer's previous user might 136655058Swpaul * have left in it. 136755058Swpaul */ 136855058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 136955058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 137040516Swpaul m_head->m_pkthdr.len += 137152426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 137241243Swpaul m_head->m_len = m_head->m_pkthdr.len; 137341243Swpaul } 137440516Swpaul 137545633Swpaul RL_CUR_TXMBUF(sc) = m_head; 137640516Swpaul 137740516Swpaul return(0); 137840516Swpaul} 137940516Swpaul 138040516Swpaul/* 138140516Swpaul * Main transmit routine. 138240516Swpaul */ 138340516Swpaul 138440516Swpaulstatic void rl_start(ifp) 138540516Swpaul struct ifnet *ifp; 138640516Swpaul{ 138740516Swpaul struct rl_softc *sc; 138840516Swpaul struct mbuf *m_head = NULL; 138940516Swpaul 139040516Swpaul sc = ifp->if_softc; 139167087Swpaul RL_LOCK(sc); 139240516Swpaul 139345633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 139440516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 139540516Swpaul if (m_head == NULL) 139640516Swpaul break; 139740516Swpaul 139858801Swpaul if (rl_encap(sc, m_head)) { 139958801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 140058801Swpaul ifp->if_flags |= IFF_OACTIVE; 140158801Swpaul break; 140258801Swpaul } 140340516Swpaul 140440516Swpaul /* 140540516Swpaul * If there's a BPF listener, bounce a copy of this frame 140640516Swpaul * to him. 140740516Swpaul */ 140840516Swpaul if (ifp->if_bpf) 140945633Swpaul bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 141051583Swpaul 141140516Swpaul /* 141240516Swpaul * Transmit the frame. 141340516Swpaul */ 141445633Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 141545633Swpaul vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 141645633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 141752426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 141852426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 141945633Swpaul 142045633Swpaul RL_INC(sc->rl_cdata.cur_tx); 142140516Swpaul } 142240516Swpaul 142340516Swpaul /* 142445633Swpaul * We broke out of the loop because all our TX slots are 142545633Swpaul * full. Mark the NIC as busy until it drains some of the 142645633Swpaul * packets from the queue. 142745633Swpaul */ 142845633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 142945633Swpaul ifp->if_flags |= IFF_OACTIVE; 143045633Swpaul 143145633Swpaul /* 143240516Swpaul * Set a timeout in case the chip goes out to lunch. 143340516Swpaul */ 143440516Swpaul ifp->if_timer = 5; 143567087Swpaul RL_UNLOCK(sc); 143640516Swpaul 143740516Swpaul return; 143840516Swpaul} 143940516Swpaul 144040516Swpaulstatic void rl_init(xsc) 144140516Swpaul void *xsc; 144240516Swpaul{ 144340516Swpaul struct rl_softc *sc = xsc; 144440516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 144550703Swpaul struct mii_data *mii; 144667087Swpaul int i; 144740516Swpaul u_int32_t rxcfg = 0; 144840516Swpaul 144967087Swpaul RL_LOCK(sc); 145050703Swpaul mii = device_get_softc(sc->rl_miibus); 145140516Swpaul 145240516Swpaul /* 145340516Swpaul * Cancel pending I/O and free all RX/TX buffers. 145440516Swpaul */ 145540516Swpaul rl_stop(sc); 145640516Swpaul 145740516Swpaul /* Init our MAC address */ 145840516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 145940516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 146040516Swpaul } 146140516Swpaul 146240516Swpaul /* Init the RX buffer pointer register. */ 146340516Swpaul CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 146440516Swpaul 146540516Swpaul /* Init TX descriptors. */ 146640516Swpaul rl_list_tx_init(sc); 146740516Swpaul 146840516Swpaul /* 146940516Swpaul * Enable transmit and receive. 147040516Swpaul */ 147140516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 147240516Swpaul 147340516Swpaul /* 147445633Swpaul * Set the initial TX and RX configuration. 147540516Swpaul */ 147645633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 147740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 147840516Swpaul 147940516Swpaul /* Set the individual bit to receive frames for this host only. */ 148040516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 148140516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 148240516Swpaul 148340516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 148440516Swpaul if (ifp->if_flags & IFF_PROMISC) { 148540516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 148640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 148740516Swpaul } else { 148840516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 148940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 149040516Swpaul } 149140516Swpaul 149240516Swpaul /* 149340516Swpaul * Set capture broadcast bit to capture broadcast frames. 149440516Swpaul */ 149540516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 149640516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 149740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 149840516Swpaul } else { 149940516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 150040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 150140516Swpaul } 150240516Swpaul 150340516Swpaul /* 150440516Swpaul * Program the multicast filter, if necessary. 150540516Swpaul */ 150640516Swpaul rl_setmulti(sc); 150740516Swpaul 150840516Swpaul /* 150940516Swpaul * Enable interrupts. 151040516Swpaul */ 151140516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 151240516Swpaul 151352426Swpaul /* Set initial TX threshold */ 151452426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 151552426Swpaul 151640516Swpaul /* Start RX/TX process. */ 151740516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 151840516Swpaul 151940516Swpaul /* Enable receiver and transmitter. */ 152040516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 152140516Swpaul 152250703Swpaul mii_mediachg(mii); 152340516Swpaul 152440516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 152540516Swpaul 152640516Swpaul ifp->if_flags |= IFF_RUNNING; 152740516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 152840516Swpaul 152950703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 153067087Swpaul RL_UNLOCK(sc); 153150703Swpaul 153240516Swpaul return; 153340516Swpaul} 153440516Swpaul 153540516Swpaul/* 153640516Swpaul * Set media options. 153740516Swpaul */ 153840516Swpaulstatic int rl_ifmedia_upd(ifp) 153940516Swpaul struct ifnet *ifp; 154040516Swpaul{ 154140516Swpaul struct rl_softc *sc; 154250703Swpaul struct mii_data *mii; 154340516Swpaul 154440516Swpaul sc = ifp->if_softc; 154550703Swpaul mii = device_get_softc(sc->rl_miibus); 154650703Swpaul mii_mediachg(mii); 154740516Swpaul 154840516Swpaul return(0); 154940516Swpaul} 155040516Swpaul 155140516Swpaul/* 155240516Swpaul * Report current media status. 155340516Swpaul */ 155440516Swpaulstatic void rl_ifmedia_sts(ifp, ifmr) 155540516Swpaul struct ifnet *ifp; 155640516Swpaul struct ifmediareq *ifmr; 155740516Swpaul{ 155840516Swpaul struct rl_softc *sc; 155950703Swpaul struct mii_data *mii; 156040516Swpaul 156140516Swpaul sc = ifp->if_softc; 156250703Swpaul mii = device_get_softc(sc->rl_miibus); 156340516Swpaul 156450703Swpaul mii_pollstat(mii); 156550703Swpaul ifmr->ifm_active = mii->mii_media_active; 156650703Swpaul ifmr->ifm_status = mii->mii_media_status; 156740516Swpaul 156840516Swpaul return; 156940516Swpaul} 157040516Swpaul 157140516Swpaulstatic int rl_ioctl(ifp, command, data) 157240516Swpaul struct ifnet *ifp; 157340516Swpaul u_long command; 157440516Swpaul caddr_t data; 157540516Swpaul{ 157640516Swpaul struct rl_softc *sc = ifp->if_softc; 157740516Swpaul struct ifreq *ifr = (struct ifreq *) data; 157850703Swpaul struct mii_data *mii; 157967087Swpaul int error = 0; 158040516Swpaul 158167087Swpaul RL_LOCK(sc); 158240516Swpaul 158340516Swpaul switch(command) { 158440516Swpaul case SIOCSIFADDR: 158540516Swpaul case SIOCGIFADDR: 158640516Swpaul case SIOCSIFMTU: 158740516Swpaul error = ether_ioctl(ifp, command, data); 158840516Swpaul break; 158940516Swpaul case SIOCSIFFLAGS: 159040516Swpaul if (ifp->if_flags & IFF_UP) { 159140516Swpaul rl_init(sc); 159240516Swpaul } else { 159340516Swpaul if (ifp->if_flags & IFF_RUNNING) 159440516Swpaul rl_stop(sc); 159540516Swpaul } 159640516Swpaul error = 0; 159740516Swpaul break; 159840516Swpaul case SIOCADDMULTI: 159940516Swpaul case SIOCDELMULTI: 160040516Swpaul rl_setmulti(sc); 160140516Swpaul error = 0; 160240516Swpaul break; 160340516Swpaul case SIOCGIFMEDIA: 160440516Swpaul case SIOCSIFMEDIA: 160550703Swpaul mii = device_get_softc(sc->rl_miibus); 160650703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 160740516Swpaul break; 160840516Swpaul default: 160940516Swpaul error = EINVAL; 161040516Swpaul break; 161140516Swpaul } 161240516Swpaul 161367087Swpaul RL_UNLOCK(sc); 161440516Swpaul 161540516Swpaul return(error); 161640516Swpaul} 161740516Swpaul 161840516Swpaulstatic void rl_watchdog(ifp) 161940516Swpaul struct ifnet *ifp; 162040516Swpaul{ 162140516Swpaul struct rl_softc *sc; 162240516Swpaul 162340516Swpaul sc = ifp->if_softc; 162467087Swpaul RL_LOCK(sc); 162540516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 162640516Swpaul ifp->if_oerrors++; 162750703Swpaul 162840516Swpaul rl_txeof(sc); 162940516Swpaul rl_rxeof(sc); 163040516Swpaul rl_init(sc); 163167087Swpaul RL_UNLOCK(sc); 163240516Swpaul 163340516Swpaul return; 163440516Swpaul} 163540516Swpaul 163640516Swpaul/* 163740516Swpaul * Stop the adapter and free any mbufs allocated to the 163840516Swpaul * RX and TX lists. 163940516Swpaul */ 164040516Swpaulstatic void rl_stop(sc) 164140516Swpaul struct rl_softc *sc; 164240516Swpaul{ 164340516Swpaul register int i; 164440516Swpaul struct ifnet *ifp; 164540516Swpaul 164667087Swpaul RL_LOCK(sc); 164740516Swpaul ifp = &sc->arpcom.ac_if; 164840516Swpaul ifp->if_timer = 0; 164940516Swpaul 165050703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 165150703Swpaul 165240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 165340516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 165440516Swpaul 165540516Swpaul /* 165640516Swpaul * Free the TX list buffers. 165740516Swpaul */ 165840516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 165945633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 166045633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 166145633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 166245633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 166340516Swpaul } 166440516Swpaul } 166540516Swpaul 166640516Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 166767087Swpaul RL_UNLOCK(sc); 166840516Swpaul return; 166940516Swpaul} 167040516Swpaul 167140516Swpaul/* 167240516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 167340516Swpaul * get confused by errant DMAs when rebooting. 167440516Swpaul */ 167550703Swpaulstatic void rl_shutdown(dev) 167650703Swpaul device_t dev; 167740516Swpaul{ 167850703Swpaul struct rl_softc *sc; 167940516Swpaul 168050703Swpaul sc = device_get_softc(dev); 168150703Swpaul 168240516Swpaul rl_stop(sc); 168340516Swpaul 168440516Swpaul return; 168540516Swpaul} 1686