if_rl.c revision 69583
140516Swpaul/*
240516Swpaul * Copyright (c) 1997, 1998
340516Swpaul *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
440516Swpaul *
540516Swpaul * Redistribution and use in source and binary forms, with or without
640516Swpaul * modification, are permitted provided that the following conditions
740516Swpaul * are met:
840516Swpaul * 1. Redistributions of source code must retain the above copyright
940516Swpaul *    notice, this list of conditions and the following disclaimer.
1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright
1140516Swpaul *    notice, this list of conditions and the following disclaimer in the
1240516Swpaul *    documentation and/or other materials provided with the distribution.
1340516Swpaul * 3. All advertising materials mentioning features or use of this software
1440516Swpaul *    must display the following acknowledgement:
1540516Swpaul *	This product includes software developed by Bill Paul.
1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors
1740516Swpaul *    may be used to endorse or promote products derived from this software
1840516Swpaul *    without specific prior written permission.
1940516Swpaul *
2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2340516Swpaul * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE.
3140516Swpaul *
3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 69583 2000-12-04 22:46:50Z wpaul $
3340516Swpaul */
3440516Swpaul
3540516Swpaul/*
3640516Swpaul * RealTek 8129/8139 PCI NIC driver
3740516Swpaul *
3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on
3940516Swpaul * the RealTek chipset. Datasheets can be obtained from
4040516Swpaul * www.realtek.com.tw.
4140516Swpaul *
4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu>
4340516Swpaul * Electrical Engineering Department
4440516Swpaul * Columbia University, New York City
4540516Swpaul */
4640516Swpaul
4740516Swpaul/*
4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible
5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master
5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance
5240516Swpaul * gains that bus-master DMA usually offers.
5340516Swpaul *
5440516Swpaul * For transmission, the chip offers a series of four TX descriptor
5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned
5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to
5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely
5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet
5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only
6040516Swpaul * four descriptor registers means that we can never have more than four
6140516Swpaul * packets queued for transmission at any one time.
6240516Swpaul *
6340516Swpaul * Reception is not much better. The driver has to allocate a single large
6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received
6540516Swpaul * frames. Because we don't know where within this region received packets
6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer
6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol
6840516Swpaul * levels.
6940516Swpaul *
7040516Swpaul * It's impossible given this rotten design to really achieve decent
7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or
7240516Swpaul * some equally overmuscled CPU to drive it.
7340516Swpaul *
7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although
7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the
7640516Swpaul * PHY registers are directly accessible through the 8139's register
7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
7840516Swpaul * filter.
7940516Swpaul *
8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY
8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where
8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need
8340516Swpaul * to select which interface to use depending on the chip type.
8440516Swpaul */
8540516Swpaul
8640516Swpaul#include <sys/param.h>
8740516Swpaul#include <sys/systm.h>
8840516Swpaul#include <sys/sockio.h>
8940516Swpaul#include <sys/mbuf.h>
9040516Swpaul#include <sys/malloc.h>
9140516Swpaul#include <sys/kernel.h>
9240516Swpaul#include <sys/socket.h>
9340516Swpaul
9440516Swpaul#include <net/if.h>
9540516Swpaul#include <net/if_arp.h>
9640516Swpaul#include <net/ethernet.h>
9740516Swpaul#include <net/if_dl.h>
9840516Swpaul#include <net/if_media.h>
9940516Swpaul
10040516Swpaul#include <net/bpf.h>
10140516Swpaul
10240516Swpaul#include <vm/vm.h>              /* for vtophys */
10340516Swpaul#include <vm/pmap.h>            /* for vtophys */
10441569Swpaul#include <machine/bus_pio.h>
10541569Swpaul#include <machine/bus_memio.h>
10641569Swpaul#include <machine/bus.h>
10750703Swpaul#include <machine/resource.h>
10850703Swpaul#include <sys/bus.h>
10950703Swpaul#include <sys/rman.h>
11040516Swpaul
11150703Swpaul#include <dev/mii/mii.h>
11250703Swpaul#include <dev/mii/miivar.h>
11350703Swpaul
11440516Swpaul#include <pci/pcireg.h>
11540516Swpaul#include <pci/pcivar.h>
11640516Swpaul
11759758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1);
11859758Speter
11951089Speter/* "controller miibus0" required.  See GENERIC if you get errors here. */
12050703Swpaul#include "miibus_if.h"
12150703Swpaul
12240516Swpaul/*
12340516Swpaul * Default to using PIO access for this driver. On SMP systems,
12440516Swpaul * there appear to be problems with memory mapped mode: it looks like
12540516Swpaul * doing too many memory mapped access back to back in rapid succession
12640516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction
12740516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on
12840516Swpaul * uniprocessor systems though.
12940516Swpaul */
13040516Swpaul#define RL_USEIOSPACE
13140516Swpaul
13240516Swpaul#include <pci/if_rlreg.h>
13340516Swpaul
13440516Swpaul#ifndef lint
13541591Sarchiestatic const char rcsid[] =
13650477Speter  "$FreeBSD: head/sys/pci/if_rl.c 69583 2000-12-04 22:46:50Z wpaul $";
13740516Swpaul#endif
13840516Swpaul
13940516Swpaul/*
14040516Swpaul * Various supported device vendors/types and their names.
14140516Swpaul */
14240516Swpaulstatic struct rl_type rl_devs[] = {
14340516Swpaul	{ RT_VENDORID, RT_DEVICEID_8129,
14440516Swpaul		"RealTek 8129 10/100BaseTX" },
14540516Swpaul	{ RT_VENDORID, RT_DEVICEID_8139,
14640516Swpaul		"RealTek 8139 10/100BaseTX" },
14767771Swpaul	{ RT_VENDORID, RT_DEVICEID_8138,
14867771Swpaul		"RealTek 8139 10/100BaseTX CardBus" },
14941243Swpaul	{ ACCTON_VENDORID, ACCTON_DEVICEID_5030,
15041243Swpaul		"Accton MPX 5030/5038 10/100BaseTX" },
15144238Swpaul	{ DELTA_VENDORID, DELTA_DEVICEID_8139,
15244238Swpaul		"Delta Electronics 8139 10/100BaseTX" },
15344238Swpaul	{ ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
15444238Swpaul		"Addtron Technolgy 8139 10/100BaseTX" },
15540516Swpaul	{ 0, 0, NULL }
15640516Swpaul};
15740516Swpaul
15850703Swpaulstatic int rl_probe		__P((device_t));
15950703Swpaulstatic int rl_attach		__P((device_t));
16050703Swpaulstatic int rl_detach		__P((device_t));
16140516Swpaul
16245633Swpaulstatic int rl_encap		__P((struct rl_softc *, struct mbuf * ));
16340516Swpaul
16440516Swpaulstatic void rl_rxeof		__P((struct rl_softc *));
16540516Swpaulstatic void rl_txeof		__P((struct rl_softc *));
16640516Swpaulstatic void rl_intr		__P((void *));
16750703Swpaulstatic void rl_tick		__P((void *));
16840516Swpaulstatic void rl_start		__P((struct ifnet *));
16940516Swpaulstatic int rl_ioctl		__P((struct ifnet *, u_long, caddr_t));
17040516Swpaulstatic void rl_init		__P((void *));
17140516Swpaulstatic void rl_stop		__P((struct rl_softc *));
17240516Swpaulstatic void rl_watchdog		__P((struct ifnet *));
17350703Swpaulstatic void rl_shutdown		__P((device_t));
17440516Swpaulstatic int rl_ifmedia_upd	__P((struct ifnet *));
17540516Swpaulstatic void rl_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));
17640516Swpaul
17741656Swpaulstatic void rl_eeprom_putbyte	__P((struct rl_softc *, int));
17841656Swpaulstatic void rl_eeprom_getword	__P((struct rl_softc *, int, u_int16_t *));
17940516Swpaulstatic void rl_read_eeprom	__P((struct rl_softc *, caddr_t,
18040516Swpaul					int, int, int));
18140516Swpaulstatic void rl_mii_sync		__P((struct rl_softc *));
18240516Swpaulstatic void rl_mii_send		__P((struct rl_softc *, u_int32_t, int));
18340516Swpaulstatic int rl_mii_readreg	__P((struct rl_softc *, struct rl_mii_frame *));
18440516Swpaulstatic int rl_mii_writereg	__P((struct rl_softc *, struct rl_mii_frame *));
18540516Swpaul
18650703Swpaulstatic int rl_miibus_readreg	__P((device_t, int, int));
18750703Swpaulstatic int rl_miibus_writereg	__P((device_t, int, int, int));
18850703Swpaulstatic void rl_miibus_statchg	__P((device_t));
18940516Swpaul
19041656Swpaulstatic u_int8_t rl_calchash	__P((caddr_t));
19140516Swpaulstatic void rl_setmulti		__P((struct rl_softc *));
19240516Swpaulstatic void rl_reset		__P((struct rl_softc *));
19340516Swpaulstatic int rl_list_tx_init	__P((struct rl_softc *));
19440516Swpaul
19550703Swpaul#ifdef RL_USEIOSPACE
19650703Swpaul#define RL_RES			SYS_RES_IOPORT
19750703Swpaul#define RL_RID			RL_PCI_LOIO
19850703Swpaul#else
19950703Swpaul#define RL_RES			SYS_RES_MEMORY
20050703Swpaul#define RL_RID			RL_PCI_LOMEM
20150703Swpaul#endif
20250703Swpaul
20350703Swpaulstatic device_method_t rl_methods[] = {
20450703Swpaul	/* Device interface */
20550703Swpaul	DEVMETHOD(device_probe,		rl_probe),
20650703Swpaul	DEVMETHOD(device_attach,	rl_attach),
20750703Swpaul	DEVMETHOD(device_detach,	rl_detach),
20850703Swpaul	DEVMETHOD(device_shutdown,	rl_shutdown),
20950703Swpaul
21050703Swpaul	/* bus interface */
21150703Swpaul	DEVMETHOD(bus_print_child,	bus_generic_print_child),
21250703Swpaul	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
21350703Swpaul
21450703Swpaul	/* MII interface */
21550703Swpaul	DEVMETHOD(miibus_readreg,	rl_miibus_readreg),
21650703Swpaul	DEVMETHOD(miibus_writereg,	rl_miibus_writereg),
21750703Swpaul	DEVMETHOD(miibus_statchg,	rl_miibus_statchg),
21850703Swpaul
21950703Swpaul	{ 0, 0 }
22050703Swpaul};
22150703Swpaul
22250703Swpaulstatic driver_t rl_driver = {
22351455Swpaul	"rl",
22450703Swpaul	rl_methods,
22550703Swpaul	sizeof(struct rl_softc)
22650703Swpaul};
22750703Swpaul
22850703Swpaulstatic devclass_t rl_devclass;
22950703Swpaul
23051533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
23167931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
23251473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
23350703Swpaul
23440516Swpaul#define EE_SET(x)					\
23540516Swpaul	CSR_WRITE_1(sc, RL_EECMD,			\
23640516Swpaul		CSR_READ_1(sc, RL_EECMD) | x)
23740516Swpaul
23840516Swpaul#define EE_CLR(x)					\
23940516Swpaul	CSR_WRITE_1(sc, RL_EECMD,			\
24040516Swpaul		CSR_READ_1(sc, RL_EECMD) & ~x)
24140516Swpaul
24240516Swpaul/*
24340516Swpaul * Send a read command and address to the EEPROM, check for ACK.
24440516Swpaul */
24540516Swpaulstatic void rl_eeprom_putbyte(sc, addr)
24640516Swpaul	struct rl_softc		*sc;
24741656Swpaul	int			addr;
24840516Swpaul{
24940516Swpaul	register int		d, i;
25040516Swpaul
25167931Swpaul	d = addr | sc->rl_eecmd_read;
25240516Swpaul
25340516Swpaul	/*
25455170Sbillf	 * Feed in each bit and strobe the clock.
25540516Swpaul	 */
25640516Swpaul	for (i = 0x400; i; i >>= 1) {
25740516Swpaul		if (d & i) {
25840516Swpaul			EE_SET(RL_EE_DATAIN);
25940516Swpaul		} else {
26040516Swpaul			EE_CLR(RL_EE_DATAIN);
26140516Swpaul		}
26240516Swpaul		DELAY(100);
26340516Swpaul		EE_SET(RL_EE_CLK);
26440516Swpaul		DELAY(150);
26540516Swpaul		EE_CLR(RL_EE_CLK);
26640516Swpaul		DELAY(100);
26740516Swpaul	}
26840516Swpaul
26940516Swpaul	return;
27040516Swpaul}
27140516Swpaul
27240516Swpaul/*
27340516Swpaul * Read a word of data stored in the EEPROM at address 'addr.'
27440516Swpaul */
27540516Swpaulstatic void rl_eeprom_getword(sc, addr, dest)
27640516Swpaul	struct rl_softc		*sc;
27741656Swpaul	int			addr;
27840516Swpaul	u_int16_t		*dest;
27940516Swpaul{
28040516Swpaul	register int		i;
28140516Swpaul	u_int16_t		word = 0;
28240516Swpaul
28340516Swpaul	/* Enter EEPROM access mode. */
28440516Swpaul	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
28540516Swpaul
28640516Swpaul	/*
28740516Swpaul	 * Send address of word we want to read.
28840516Swpaul	 */
28940516Swpaul	rl_eeprom_putbyte(sc, addr);
29040516Swpaul
29140516Swpaul	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
29240516Swpaul
29340516Swpaul	/*
29440516Swpaul	 * Start reading bits from EEPROM.
29540516Swpaul	 */
29640516Swpaul	for (i = 0x8000; i; i >>= 1) {
29740516Swpaul		EE_SET(RL_EE_CLK);
29840516Swpaul		DELAY(100);
29940516Swpaul		if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
30040516Swpaul			word |= i;
30140516Swpaul		EE_CLR(RL_EE_CLK);
30240516Swpaul		DELAY(100);
30340516Swpaul	}
30440516Swpaul
30540516Swpaul	/* Turn off EEPROM access mode. */
30640516Swpaul	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
30740516Swpaul
30840516Swpaul	*dest = word;
30940516Swpaul
31040516Swpaul	return;
31140516Swpaul}
31240516Swpaul
31340516Swpaul/*
31440516Swpaul * Read a sequence of words from the EEPROM.
31540516Swpaul */
31640516Swpaulstatic void rl_read_eeprom(sc, dest, off, cnt, swap)
31740516Swpaul	struct rl_softc		*sc;
31840516Swpaul	caddr_t			dest;
31940516Swpaul	int			off;
32040516Swpaul	int			cnt;
32140516Swpaul	int			swap;
32240516Swpaul{
32340516Swpaul	int			i;
32440516Swpaul	u_int16_t		word = 0, *ptr;
32540516Swpaul
32640516Swpaul	for (i = 0; i < cnt; i++) {
32740516Swpaul		rl_eeprom_getword(sc, off + i, &word);
32840516Swpaul		ptr = (u_int16_t *)(dest + (i * 2));
32940516Swpaul		if (swap)
33040516Swpaul			*ptr = ntohs(word);
33140516Swpaul		else
33240516Swpaul			*ptr = word;
33340516Swpaul	}
33440516Swpaul
33540516Swpaul	return;
33640516Swpaul}
33740516Swpaul
33840516Swpaul
33940516Swpaul/*
34040516Swpaul * MII access routines are provided for the 8129, which
34140516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things
34240516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
34340516Swpaul * direct access PHY registers.
34440516Swpaul */
34540516Swpaul#define MII_SET(x)					\
34640516Swpaul	CSR_WRITE_1(sc, RL_MII,				\
34740516Swpaul		CSR_READ_1(sc, RL_MII) | x)
34840516Swpaul
34940516Swpaul#define MII_CLR(x)					\
35040516Swpaul	CSR_WRITE_1(sc, RL_MII,				\
35140516Swpaul		CSR_READ_1(sc, RL_MII) & ~x)
35240516Swpaul
35340516Swpaul/*
35440516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times.
35540516Swpaul */
35640516Swpaulstatic void rl_mii_sync(sc)
35740516Swpaul	struct rl_softc		*sc;
35840516Swpaul{
35940516Swpaul	register int		i;
36040516Swpaul
36140516Swpaul	MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
36240516Swpaul
36340516Swpaul	for (i = 0; i < 32; i++) {
36440516Swpaul		MII_SET(RL_MII_CLK);
36540516Swpaul		DELAY(1);
36640516Swpaul		MII_CLR(RL_MII_CLK);
36740516Swpaul		DELAY(1);
36840516Swpaul	}
36940516Swpaul
37040516Swpaul	return;
37140516Swpaul}
37240516Swpaul
37340516Swpaul/*
37440516Swpaul * Clock a series of bits through the MII.
37540516Swpaul */
37640516Swpaulstatic void rl_mii_send(sc, bits, cnt)
37740516Swpaul	struct rl_softc		*sc;
37840516Swpaul	u_int32_t		bits;
37940516Swpaul	int			cnt;
38040516Swpaul{
38140516Swpaul	int			i;
38240516Swpaul
38340516Swpaul	MII_CLR(RL_MII_CLK);
38440516Swpaul
38540516Swpaul	for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
38640516Swpaul                if (bits & i) {
38740516Swpaul			MII_SET(RL_MII_DATAOUT);
38840516Swpaul                } else {
38940516Swpaul			MII_CLR(RL_MII_DATAOUT);
39040516Swpaul                }
39140516Swpaul		DELAY(1);
39240516Swpaul		MII_CLR(RL_MII_CLK);
39340516Swpaul		DELAY(1);
39440516Swpaul		MII_SET(RL_MII_CLK);
39540516Swpaul	}
39640516Swpaul}
39740516Swpaul
39840516Swpaul/*
39940516Swpaul * Read an PHY register through the MII.
40040516Swpaul */
40140516Swpaulstatic int rl_mii_readreg(sc, frame)
40240516Swpaul	struct rl_softc		*sc;
40340516Swpaul	struct rl_mii_frame	*frame;
40440516Swpaul
40540516Swpaul{
40667087Swpaul	int			i, ack;
40740516Swpaul
40867087Swpaul	RL_LOCK(sc);
40940516Swpaul
41040516Swpaul	/*
41140516Swpaul	 * Set up frame for RX.
41240516Swpaul	 */
41340516Swpaul	frame->mii_stdelim = RL_MII_STARTDELIM;
41440516Swpaul	frame->mii_opcode = RL_MII_READOP;
41540516Swpaul	frame->mii_turnaround = 0;
41640516Swpaul	frame->mii_data = 0;
41740516Swpaul
41840516Swpaul	CSR_WRITE_2(sc, RL_MII, 0);
41940516Swpaul
42040516Swpaul	/*
42140516Swpaul 	 * Turn on data xmit.
42240516Swpaul	 */
42340516Swpaul	MII_SET(RL_MII_DIR);
42440516Swpaul
42540516Swpaul	rl_mii_sync(sc);
42640516Swpaul
42740516Swpaul	/*
42840516Swpaul	 * Send command/address info.
42940516Swpaul	 */
43040516Swpaul	rl_mii_send(sc, frame->mii_stdelim, 2);
43140516Swpaul	rl_mii_send(sc, frame->mii_opcode, 2);
43240516Swpaul	rl_mii_send(sc, frame->mii_phyaddr, 5);
43340516Swpaul	rl_mii_send(sc, frame->mii_regaddr, 5);
43440516Swpaul
43540516Swpaul	/* Idle bit */
43640516Swpaul	MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
43740516Swpaul	DELAY(1);
43840516Swpaul	MII_SET(RL_MII_CLK);
43940516Swpaul	DELAY(1);
44040516Swpaul
44140516Swpaul	/* Turn off xmit. */
44240516Swpaul	MII_CLR(RL_MII_DIR);
44340516Swpaul
44440516Swpaul	/* Check for ack */
44540516Swpaul	MII_CLR(RL_MII_CLK);
44640516Swpaul	DELAY(1);
44740516Swpaul	MII_SET(RL_MII_CLK);
44840516Swpaul	DELAY(1);
44940516Swpaul	ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
45040516Swpaul
45140516Swpaul	/*
45240516Swpaul	 * Now try reading data bits. If the ack failed, we still
45340516Swpaul	 * need to clock through 16 cycles to keep the PHY(s) in sync.
45440516Swpaul	 */
45540516Swpaul	if (ack) {
45640516Swpaul		for(i = 0; i < 16; i++) {
45740516Swpaul			MII_CLR(RL_MII_CLK);
45840516Swpaul			DELAY(1);
45940516Swpaul			MII_SET(RL_MII_CLK);
46040516Swpaul			DELAY(1);
46140516Swpaul		}
46240516Swpaul		goto fail;
46340516Swpaul	}
46440516Swpaul
46540516Swpaul	for (i = 0x8000; i; i >>= 1) {
46640516Swpaul		MII_CLR(RL_MII_CLK);
46740516Swpaul		DELAY(1);
46840516Swpaul		if (!ack) {
46940516Swpaul			if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
47040516Swpaul				frame->mii_data |= i;
47140516Swpaul			DELAY(1);
47240516Swpaul		}
47340516Swpaul		MII_SET(RL_MII_CLK);
47440516Swpaul		DELAY(1);
47540516Swpaul	}
47640516Swpaul
47740516Swpaulfail:
47840516Swpaul
47940516Swpaul	MII_CLR(RL_MII_CLK);
48040516Swpaul	DELAY(1);
48140516Swpaul	MII_SET(RL_MII_CLK);
48240516Swpaul	DELAY(1);
48340516Swpaul
48467087Swpaul	RL_UNLOCK(sc);
48540516Swpaul
48640516Swpaul	if (ack)
48740516Swpaul		return(1);
48840516Swpaul	return(0);
48940516Swpaul}
49040516Swpaul
49140516Swpaul/*
49240516Swpaul * Write to a PHY register through the MII.
49340516Swpaul */
49440516Swpaulstatic int rl_mii_writereg(sc, frame)
49540516Swpaul	struct rl_softc		*sc;
49640516Swpaul	struct rl_mii_frame	*frame;
49740516Swpaul
49840516Swpaul{
49967087Swpaul	RL_LOCK(sc);
50040516Swpaul
50140516Swpaul	/*
50240516Swpaul	 * Set up frame for TX.
50340516Swpaul	 */
50440516Swpaul
50540516Swpaul	frame->mii_stdelim = RL_MII_STARTDELIM;
50640516Swpaul	frame->mii_opcode = RL_MII_WRITEOP;
50740516Swpaul	frame->mii_turnaround = RL_MII_TURNAROUND;
50840516Swpaul
50940516Swpaul	/*
51040516Swpaul 	 * Turn on data output.
51140516Swpaul	 */
51240516Swpaul	MII_SET(RL_MII_DIR);
51340516Swpaul
51440516Swpaul	rl_mii_sync(sc);
51540516Swpaul
51640516Swpaul	rl_mii_send(sc, frame->mii_stdelim, 2);
51740516Swpaul	rl_mii_send(sc, frame->mii_opcode, 2);
51840516Swpaul	rl_mii_send(sc, frame->mii_phyaddr, 5);
51940516Swpaul	rl_mii_send(sc, frame->mii_regaddr, 5);
52040516Swpaul	rl_mii_send(sc, frame->mii_turnaround, 2);
52140516Swpaul	rl_mii_send(sc, frame->mii_data, 16);
52240516Swpaul
52340516Swpaul	/* Idle bit. */
52440516Swpaul	MII_SET(RL_MII_CLK);
52540516Swpaul	DELAY(1);
52640516Swpaul	MII_CLR(RL_MII_CLK);
52740516Swpaul	DELAY(1);
52840516Swpaul
52940516Swpaul	/*
53040516Swpaul	 * Turn off xmit.
53140516Swpaul	 */
53240516Swpaul	MII_CLR(RL_MII_DIR);
53340516Swpaul
53467087Swpaul	RL_UNLOCK(sc);
53540516Swpaul
53640516Swpaul	return(0);
53740516Swpaul}
53840516Swpaul
53950703Swpaulstatic int rl_miibus_readreg(dev, phy, reg)
54050703Swpaul	device_t		dev;
54150703Swpaul	int			phy, reg;
54250703Swpaul{
54340516Swpaul	struct rl_softc		*sc;
54440516Swpaul	struct rl_mii_frame	frame;
54540516Swpaul	u_int16_t		rval = 0;
54640516Swpaul	u_int16_t		rl8139_reg = 0;
54740516Swpaul
54850703Swpaul	sc = device_get_softc(dev);
54967087Swpaul	RL_LOCK(sc);
55050703Swpaul
55140516Swpaul	if (sc->rl_type == RL_8139) {
55250703Swpaul		/* Pretend the internal PHY is only at address 0 */
55367087Swpaul		if (phy) {
55467087Swpaul			RL_UNLOCK(sc);
55550703Swpaul			return(0);
55667087Swpaul		}
55740516Swpaul		switch(reg) {
55850703Swpaul		case MII_BMCR:
55940516Swpaul			rl8139_reg = RL_BMCR;
56040516Swpaul			break;
56150703Swpaul		case MII_BMSR:
56240516Swpaul			rl8139_reg = RL_BMSR;
56340516Swpaul			break;
56450703Swpaul		case MII_ANAR:
56540516Swpaul			rl8139_reg = RL_ANAR;
56640516Swpaul			break;
56750703Swpaul		case MII_ANER:
56850703Swpaul			rl8139_reg = RL_ANER;
56950703Swpaul			break;
57050703Swpaul		case MII_ANLPAR:
57140516Swpaul			rl8139_reg = RL_LPAR;
57240516Swpaul			break;
57350703Swpaul		case MII_PHYIDR1:
57450703Swpaul		case MII_PHYIDR2:
57567087Swpaul			RL_UNLOCK(sc);
57650703Swpaul			return(0);
57750703Swpaul			break;
57840516Swpaul		default:
57940516Swpaul			printf("rl%d: bad phy register\n", sc->rl_unit);
58067087Swpaul			RL_UNLOCK(sc);
58140516Swpaul			return(0);
58240516Swpaul		}
58340516Swpaul		rval = CSR_READ_2(sc, rl8139_reg);
58467087Swpaul		RL_UNLOCK(sc);
58540516Swpaul		return(rval);
58640516Swpaul	}
58740516Swpaul
58840516Swpaul	bzero((char *)&frame, sizeof(frame));
58940516Swpaul
59050703Swpaul	frame.mii_phyaddr = phy;
59140516Swpaul	frame.mii_regaddr = reg;
59240516Swpaul	rl_mii_readreg(sc, &frame);
59367087Swpaul	RL_UNLOCK(sc);
59440516Swpaul
59540516Swpaul	return(frame.mii_data);
59640516Swpaul}
59740516Swpaul
59850703Swpaulstatic int rl_miibus_writereg(dev, phy, reg, data)
59950703Swpaul	device_t		dev;
60050703Swpaul	int			phy, reg, data;
60150703Swpaul{
60240516Swpaul	struct rl_softc		*sc;
60340516Swpaul	struct rl_mii_frame	frame;
60440516Swpaul	u_int16_t		rl8139_reg = 0;
60540516Swpaul
60650703Swpaul	sc = device_get_softc(dev);
60767087Swpaul	RL_LOCK(sc);
60850703Swpaul
60940516Swpaul	if (sc->rl_type == RL_8139) {
61050703Swpaul		/* Pretend the internal PHY is only at address 0 */
61167087Swpaul		if (phy) {
61267087Swpaul			RL_UNLOCK(sc);
61350703Swpaul			return(0);
61467087Swpaul		}
61540516Swpaul		switch(reg) {
61650703Swpaul		case MII_BMCR:
61740516Swpaul			rl8139_reg = RL_BMCR;
61840516Swpaul			break;
61950703Swpaul		case MII_BMSR:
62040516Swpaul			rl8139_reg = RL_BMSR;
62140516Swpaul			break;
62250703Swpaul		case MII_ANAR:
62340516Swpaul			rl8139_reg = RL_ANAR;
62440516Swpaul			break;
62550703Swpaul		case MII_ANER:
62650703Swpaul			rl8139_reg = RL_ANER;
62750703Swpaul			break;
62850703Swpaul		case MII_ANLPAR:
62940516Swpaul			rl8139_reg = RL_LPAR;
63040516Swpaul			break;
63150703Swpaul		case MII_PHYIDR1:
63250703Swpaul		case MII_PHYIDR2:
63367087Swpaul			RL_UNLOCK(sc);
63450703Swpaul			return(0);
63550703Swpaul			break;
63640516Swpaul		default:
63740516Swpaul			printf("rl%d: bad phy register\n", sc->rl_unit);
63867087Swpaul			RL_UNLOCK(sc);
63950703Swpaul			return(0);
64040516Swpaul		}
64140516Swpaul		CSR_WRITE_2(sc, rl8139_reg, data);
64267087Swpaul		RL_UNLOCK(sc);
64350703Swpaul		return(0);
64440516Swpaul	}
64540516Swpaul
64640516Swpaul	bzero((char *)&frame, sizeof(frame));
64740516Swpaul
64850703Swpaul	frame.mii_phyaddr = phy;
64940516Swpaul	frame.mii_regaddr = reg;
65040516Swpaul	frame.mii_data = data;
65140516Swpaul
65240516Swpaul	rl_mii_writereg(sc, &frame);
65340516Swpaul
65467087Swpaul	RL_UNLOCK(sc);
65550703Swpaul	return(0);
65650703Swpaul}
65750703Swpaul
65850703Swpaulstatic void rl_miibus_statchg(dev)
65950703Swpaul	device_t		dev;
66050703Swpaul{
66140516Swpaul	return;
66240516Swpaul}
66340516Swpaul
66440516Swpaul/*
66543062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits.
66640516Swpaul */
66740516Swpaulstatic u_int8_t rl_calchash(addr)
66841656Swpaul	caddr_t			addr;
66940516Swpaul{
67040516Swpaul	u_int32_t		crc, carry;
67140516Swpaul	int			i, j;
67240516Swpaul	u_int8_t		c;
67340516Swpaul
67440516Swpaul	/* Compute CRC for the address value. */
67540516Swpaul	crc = 0xFFFFFFFF; /* initial value */
67640516Swpaul
67740516Swpaul	for (i = 0; i < 6; i++) {
67840516Swpaul		c = *(addr + i);
67940516Swpaul		for (j = 0; j < 8; j++) {
68040516Swpaul			carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
68140516Swpaul			crc <<= 1;
68240516Swpaul			c >>= 1;
68340516Swpaul			if (carry)
68440516Swpaul				crc = (crc ^ 0x04c11db6) | carry;
68540516Swpaul		}
68640516Swpaul	}
68740516Swpaul
68840516Swpaul	/* return the filter bit position */
68943062Swpaul	return(crc >> 26);
69040516Swpaul}
69140516Swpaul
69240516Swpaul/*
69340516Swpaul * Program the 64-bit multicast hash filter.
69440516Swpaul */
69540516Swpaulstatic void rl_setmulti(sc)
69640516Swpaul	struct rl_softc		*sc;
69740516Swpaul{
69840516Swpaul	struct ifnet		*ifp;
69940516Swpaul	int			h = 0;
70040516Swpaul	u_int32_t		hashes[2] = { 0, 0 };
70140516Swpaul	struct ifmultiaddr	*ifma;
70240516Swpaul	u_int32_t		rxfilt;
70340516Swpaul	int			mcnt = 0;
70440516Swpaul
70540516Swpaul	ifp = &sc->arpcom.ac_if;
70640516Swpaul
70740516Swpaul	rxfilt = CSR_READ_4(sc, RL_RXCFG);
70840516Swpaul
70943062Swpaul	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
71040516Swpaul		rxfilt |= RL_RXCFG_RX_MULTI;
71140516Swpaul		CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
71240516Swpaul		CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
71340516Swpaul		CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
71440516Swpaul		return;
71540516Swpaul	}
71640516Swpaul
71740516Swpaul	/* first, zot all the existing hash bits */
71840516Swpaul	CSR_WRITE_4(sc, RL_MAR0, 0);
71940516Swpaul	CSR_WRITE_4(sc, RL_MAR4, 0);
72040516Swpaul
72140516Swpaul	/* now program new ones */
72240516Swpaul	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
72340516Swpaul				ifma = ifma->ifma_link.le_next) {
72440516Swpaul		if (ifma->ifma_addr->sa_family != AF_LINK)
72540516Swpaul			continue;
72640516Swpaul		h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
72740516Swpaul		if (h < 32)
72840516Swpaul			hashes[0] |= (1 << h);
72940516Swpaul		else
73040516Swpaul			hashes[1] |= (1 << (h - 32));
73140516Swpaul		mcnt++;
73240516Swpaul	}
73340516Swpaul
73440516Swpaul	if (mcnt)
73540516Swpaul		rxfilt |= RL_RXCFG_RX_MULTI;
73640516Swpaul	else
73740516Swpaul		rxfilt &= ~RL_RXCFG_RX_MULTI;
73840516Swpaul
73940516Swpaul	CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
74040516Swpaul	CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
74140516Swpaul	CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
74240516Swpaul
74340516Swpaul	return;
74440516Swpaul}
74540516Swpaul
74640516Swpaulstatic void rl_reset(sc)
74740516Swpaul	struct rl_softc		*sc;
74840516Swpaul{
74940516Swpaul	register int		i;
75040516Swpaul
75140516Swpaul	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
75240516Swpaul
75340516Swpaul	for (i = 0; i < RL_TIMEOUT; i++) {
75440516Swpaul		DELAY(10);
75540516Swpaul		if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
75640516Swpaul			break;
75740516Swpaul	}
75840516Swpaul	if (i == RL_TIMEOUT)
75940516Swpaul		printf("rl%d: reset never completed!\n", sc->rl_unit);
76040516Swpaul
76140516Swpaul        return;
76240516Swpaul}
76340516Swpaul
76440516Swpaul/*
76540516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
76640516Swpaul * IDs against our list and return a device name if we find a match.
76740516Swpaul */
76850703Swpaulstatic int rl_probe(dev)
76950703Swpaul	device_t		dev;
77040516Swpaul{
77140516Swpaul	struct rl_type		*t;
77240516Swpaul
77340516Swpaul	t = rl_devs;
77440516Swpaul
77540516Swpaul	while(t->rl_name != NULL) {
77650703Swpaul		if ((pci_get_vendor(dev) == t->rl_vid) &&
77750703Swpaul		    (pci_get_device(dev) == t->rl_did)) {
77850703Swpaul			device_set_desc(dev, t->rl_name);
77950703Swpaul			return(0);
78040516Swpaul		}
78140516Swpaul		t++;
78240516Swpaul	}
78340516Swpaul
78450703Swpaul	return(ENXIO);
78540516Swpaul}
78640516Swpaul
78740516Swpaul/*
78840516Swpaul * Attach the interface. Allocate softc structures, do ifmedia
78940516Swpaul * setup and ethernet/BPF attach.
79040516Swpaul */
79150703Swpaulstatic int rl_attach(dev)
79250703Swpaul	device_t		dev;
79340516Swpaul{
79440516Swpaul	u_char			eaddr[ETHER_ADDR_LEN];
79540516Swpaul	u_int32_t		command;
79640516Swpaul	struct rl_softc		*sc;
79740516Swpaul	struct ifnet		*ifp;
79840516Swpaul	u_int16_t		rl_did = 0;
79950703Swpaul	int			unit, error = 0, rid;
80040516Swpaul
80150703Swpaul	sc = device_get_softc(dev);
80250703Swpaul	unit = device_get_unit(dev);
80340516Swpaul	bzero(sc, sizeof(struct rl_softc));
80440516Swpaul
80569583Swpaul	mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_DEF);
80669583Swpaul	RL_LOCK(sc);
80769583Swpaul
80840516Swpaul	/*
80940516Swpaul	 * Handle power management nonsense.
81040516Swpaul	 */
81140516Swpaul
81250703Swpaul	command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF;
81340516Swpaul	if (command == 0x01) {
81440516Swpaul
81550703Swpaul		command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4);
81640516Swpaul		if (command & RL_PSTATE_MASK) {
81740516Swpaul			u_int32_t		iobase, membase, irq;
81840516Swpaul
81940516Swpaul			/* Save important PCI config data. */
82050703Swpaul			iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
82150703Swpaul			membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
82250703Swpaul			irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
82340516Swpaul
82440516Swpaul			/* Reset the power state. */
82540516Swpaul			printf("rl%d: chip is is in D%d power mode "
82640516Swpaul			"-- setting to D0\n", unit, command & RL_PSTATE_MASK);
82740516Swpaul			command &= 0xFFFFFFFC;
82850703Swpaul			pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4);
82940516Swpaul
83040516Swpaul			/* Restore PCI config data. */
83150703Swpaul			pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
83250703Swpaul			pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
83350703Swpaul			pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
83440516Swpaul		}
83540516Swpaul	}
83640516Swpaul
83740516Swpaul	/*
83840516Swpaul	 * Map control/status registers.
83940516Swpaul	 */
84061041Speter	command = pci_read_config(dev, PCIR_COMMAND, 4);
84140516Swpaul	command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
84261041Speter	pci_write_config(dev, PCIR_COMMAND, command, 4);
84361041Speter	command = pci_read_config(dev, PCIR_COMMAND, 4);
84440516Swpaul
84540516Swpaul#ifdef RL_USEIOSPACE
84640516Swpaul	if (!(command & PCIM_CMD_PORTEN)) {
84740516Swpaul		printf("rl%d: failed to enable I/O ports!\n", unit);
84850703Swpaul		error = ENXIO;
84940516Swpaul		goto fail;
85040516Swpaul	}
85140516Swpaul#else
85240516Swpaul	if (!(command & PCIM_CMD_MEMEN)) {
85340516Swpaul		printf("rl%d: failed to enable memory mapping!\n", unit);
85450703Swpaul		error = ENXIO;
85540516Swpaul		goto fail;
85640516Swpaul	}
85750703Swpaul#endif
85840516Swpaul
85950703Swpaul	rid = RL_RID;
86050703Swpaul	sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
86150703Swpaul	    0, ~0, 1, RF_ACTIVE);
86250703Swpaul
86350703Swpaul	if (sc->rl_res == NULL) {
86450703Swpaul		printf ("rl%d: couldn't map ports/memory\n", unit);
86550703Swpaul		error = ENXIO;
86640516Swpaul		goto fail;
86740516Swpaul	}
86840516Swpaul
86969127Sroger	/* Detect the Realtek 8139B. For some reason, this chip is very
87069127Sroger	 * unstable when left to autoselect the media
87169127Sroger	 * The best workaround is to set the device to the required
87269127Sroger	 * media type or to set it to the 10 Meg speed.
87369127Sroger	 */
87469127Sroger
87569127Sroger	if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
87669127Sroger		printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit);
87769127Sroger	}
87869127Sroger
87950703Swpaul	sc->rl_btag = rman_get_bustag(sc->rl_res);
88050703Swpaul	sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
88150703Swpaul
88250703Swpaul	rid = 0;
88350703Swpaul	sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
88450703Swpaul	    RF_SHAREABLE | RF_ACTIVE);
88550703Swpaul
88650703Swpaul	if (sc->rl_irq == NULL) {
88740516Swpaul		printf("rl%d: couldn't map interrupt\n", unit);
88850703Swpaul		bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
88950703Swpaul		error = ENXIO;
89040516Swpaul		goto fail;
89140516Swpaul	}
89240516Swpaul
89350703Swpaul	error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
89450703Swpaul	    rl_intr, sc, &sc->rl_intrhand);
89550703Swpaul
89650703Swpaul	if (error) {
89768215Swpaul		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
89850703Swpaul		bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
89950703Swpaul		printf("rl%d: couldn't set up irq\n", unit);
90050703Swpaul		goto fail;
90150703Swpaul	}
90250703Swpaul
90350703Swpaul	callout_handle_init(&sc->rl_stat_ch);
90450703Swpaul
90540516Swpaul	/* Reset the adapter. */
90640516Swpaul	rl_reset(sc);
90767931Swpaul	sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
90867931Swpaul	rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
90968215Swpaul	if (rl_did != 0x8129)
91067931Swpaul		sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
91140516Swpaul
91240516Swpaul	/*
91340516Swpaul	 * Get station address from the EEPROM.
91440516Swpaul	 */
91540516Swpaul	rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
91640516Swpaul
91740516Swpaul	/*
91840516Swpaul	 * A RealTek chip was detected. Inform the world.
91940516Swpaul	 */
92040516Swpaul	printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
92140516Swpaul
92240516Swpaul	sc->rl_unit = unit;
92340516Swpaul	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
92440516Swpaul
92540516Swpaul	/*
92640516Swpaul	 * Now read the exact device type from the EEPROM to find
92740516Swpaul	 * out if it's an 8129 or 8139.
92840516Swpaul	 */
92940516Swpaul	rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
93040516Swpaul
93144238Swpaul	if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
93267771Swpaul	    rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
93367771Swpaul	    rl_did == RT_DEVICEID_8138)
93440516Swpaul		sc->rl_type = RL_8139;
93540516Swpaul	else if (rl_did == RT_DEVICEID_8129)
93640516Swpaul		sc->rl_type = RL_8129;
93740516Swpaul	else {
93840516Swpaul		printf("rl%d: unknown device ID: %x\n", unit, rl_did);
93950703Swpaul		bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
94068215Swpaul		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
94150703Swpaul		bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
94250703Swpaul		error = ENXIO;
94340516Swpaul		goto fail;
94440516Swpaul	}
94540516Swpaul
94660043Swpaul	sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF,
94751657Swpaul		M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
94840516Swpaul
94940516Swpaul	if (sc->rl_cdata.rl_rx_buf == NULL) {
95040516Swpaul		printf("rl%d: no memory for list buffers!\n", unit);
95150703Swpaul		bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
95268215Swpaul		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
95350703Swpaul		bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
95450703Swpaul		error = ENXIO;
95540516Swpaul		goto fail;
95640516Swpaul	}
95740516Swpaul
95848028Swpaul	/* Leave a few bytes before the start of the RX ring buffer. */
95948028Swpaul	sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
96048028Swpaul	sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
96148028Swpaul
96250703Swpaul	/* Do MII setup */
96350703Swpaul	if (mii_phy_probe(dev, &sc->rl_miibus,
96450703Swpaul	    rl_ifmedia_upd, rl_ifmedia_sts)) {
96550703Swpaul		printf("rl%d: MII without any phy!\n", sc->rl_unit);
96650703Swpaul		bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
96768215Swpaul		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
96850703Swpaul		bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
96950703Swpaul		free(sc->rl_cdata.rl_rx_buf, M_DEVBUF);
97050703Swpaul		error = ENXIO;
97150703Swpaul		goto fail;
97250703Swpaul	}
97350703Swpaul
97440516Swpaul	ifp = &sc->arpcom.ac_if;
97540516Swpaul	ifp->if_softc = sc;
97640516Swpaul	ifp->if_unit = unit;
97740516Swpaul	ifp->if_name = "rl";
97840516Swpaul	ifp->if_mtu = ETHERMTU;
97940516Swpaul	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
98040516Swpaul	ifp->if_ioctl = rl_ioctl;
98140516Swpaul	ifp->if_output = ether_output;
98240516Swpaul	ifp->if_start = rl_start;
98340516Swpaul	ifp->if_watchdog = rl_watchdog;
98440516Swpaul	ifp->if_init = rl_init;
98540516Swpaul	ifp->if_baudrate = 10000000;
98645633Swpaul	ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
98740516Swpaul
98840516Swpaul	/*
98963090Sarchie	 * Call MI attach routine.
99040516Swpaul	 */
99163090Sarchie	ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
99267087Swpaul	RL_UNLOCK(sc);
99367087Swpaul	return(0);
99440516Swpaul
99540516Swpaulfail:
99667087Swpaul	RL_UNLOCK(sc);
99767087Swpaul	mtx_destroy(&sc->rl_mtx);
99850703Swpaul	return(error);
99940516Swpaul}
100040516Swpaul
100150703Swpaulstatic int rl_detach(dev)
100250703Swpaul	device_t		dev;
100350703Swpaul{
100450703Swpaul	struct rl_softc		*sc;
100550703Swpaul	struct ifnet		*ifp;
100650703Swpaul
100750703Swpaul	sc = device_get_softc(dev);
100867087Swpaul	RL_LOCK(sc);
100950703Swpaul	ifp = &sc->arpcom.ac_if;
101050703Swpaul
101163090Sarchie	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
101250703Swpaul	rl_stop(sc);
101350703Swpaul
101450703Swpaul	bus_generic_detach(dev);
101550703Swpaul	device_delete_child(dev, sc->rl_miibus);
101650703Swpaul
101750703Swpaul	bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
101868215Swpaul	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
101950703Swpaul	bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
102050703Swpaul
102152426Swpaul	contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF);
102250703Swpaul
102367087Swpaul	RL_UNLOCK(sc);
102467087Swpaul	mtx_destroy(&sc->rl_mtx);
102550703Swpaul
102650703Swpaul	return(0);
102750703Swpaul}
102850703Swpaul
102940516Swpaul/*
103040516Swpaul * Initialize the transmit descriptors.
103140516Swpaul */
103240516Swpaulstatic int rl_list_tx_init(sc)
103340516Swpaul	struct rl_softc		*sc;
103440516Swpaul{
103540516Swpaul	struct rl_chain_data	*cd;
103640516Swpaul	int			i;
103740516Swpaul
103840516Swpaul	cd = &sc->rl_cdata;
103940516Swpaul	for (i = 0; i < RL_TX_LIST_CNT; i++) {
104045633Swpaul		cd->rl_tx_chain[i] = NULL;
104148028Swpaul		CSR_WRITE_4(sc,
104248028Swpaul		    RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
104340516Swpaul	}
104440516Swpaul
104545633Swpaul	sc->rl_cdata.cur_tx = 0;
104645633Swpaul	sc->rl_cdata.last_tx = 0;
104740516Swpaul
104840516Swpaul	return(0);
104940516Swpaul}
105040516Swpaul
105140516Swpaul/*
105240516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to
105340516Swpaul * the higher level protocols.
105440516Swpaul *
105540516Swpaul * You know there's something wrong with a PCI bus-master chip design
105640516Swpaul * when you have to use m_devget().
105740516Swpaul *
105840516Swpaul * The receive operation is badly documented in the datasheet, so I'll
105940516Swpaul * attempt to document it here. The driver provides a buffer area and
106040516Swpaul * places its base address in the RX buffer start address register.
106140516Swpaul * The chip then begins copying frames into the RX buffer. Each frame
106240516Swpaul * is preceeded by a 32-bit RX status word which specifies the length
106340516Swpaul * of the frame and certain other status bits. Each frame (starting with
106440516Swpaul * the status word) is also 32-bit aligned. The frame length is in the
106540516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with
106640516Swpaul * the 'rx status register' mentioned in the datasheet.
106748028Swpaul *
106848028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned
106948028Swpaul * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
107048028Swpaul * the ring buffer starting at an address two bytes before the actual
107148028Swpaul * data location. We can then shave off the first two bytes using m_adj().
107248028Swpaul * The reason we do this is because m_devget() doesn't let us specify an
107348028Swpaul * offset into the mbuf storage space, so we have to artificially create
107448028Swpaul * one. The ring is allocated in such a way that there are a few unused
107548028Swpaul * bytes of space preceecing it so that it will be safe for us to do the
107648028Swpaul * 2-byte backstep even if reading from the ring at offset 0.
107740516Swpaul */
107840516Swpaulstatic void rl_rxeof(sc)
107940516Swpaul	struct rl_softc		*sc;
108040516Swpaul{
108140516Swpaul        struct ether_header	*eh;
108240516Swpaul        struct mbuf		*m;
108340516Swpaul        struct ifnet		*ifp;
108440516Swpaul	int			total_len = 0;
108540516Swpaul	u_int32_t		rxstat;
108640516Swpaul	caddr_t			rxbufpos;
108740516Swpaul	int			wrap = 0;
108840516Swpaul	u_int16_t		cur_rx;
108940516Swpaul	u_int16_t		limit;
109040516Swpaul	u_int16_t		rx_bytes = 0, max_bytes;
109140516Swpaul
109240516Swpaul	ifp = &sc->arpcom.ac_if;
109340516Swpaul
109440516Swpaul	cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
109540516Swpaul
109640516Swpaul	/* Do not try to read past this point. */
109740516Swpaul	limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
109840516Swpaul
109940516Swpaul	if (limit < cur_rx)
110040516Swpaul		max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
110140516Swpaul	else
110240516Swpaul		max_bytes = limit - cur_rx;
110340516Swpaul
110442738Swpaul	while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
110540516Swpaul		rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
110640516Swpaul		rxstat = *(u_int32_t *)rxbufpos;
110740516Swpaul
110840516Swpaul		/*
110940516Swpaul		 * Here's a totally undocumented fact for you. When the
111040516Swpaul		 * RealTek chip is in the process of copying a packet into
111140516Swpaul		 * RAM for you, the length will be 0xfff0. If you spot a
111240516Swpaul		 * packet header with this value, you need to stop. The
111340516Swpaul		 * datasheet makes absolutely no mention of this and
111440516Swpaul		 * RealTek should be shot for this.
111540516Swpaul		 */
111640516Swpaul		if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
111740516Swpaul			break;
111840516Swpaul
111940516Swpaul		if (!(rxstat & RL_RXSTAT_RXOK)) {
112040516Swpaul			ifp->if_ierrors++;
112150703Swpaul			rl_init(sc);
112250703Swpaul			return;
112340516Swpaul		}
112440516Swpaul
112540516Swpaul		/* No errors; receive the packet. */
112640516Swpaul		total_len = rxstat >> 16;
112740516Swpaul		rx_bytes += total_len + 4;
112840516Swpaul
112940516Swpaul		/*
113042051Swpaul		 * XXX The RealTek chip includes the CRC with every
113142051Swpaul		 * received frame, and there's no way to turn this
113242051Swpaul		 * behavior off (at least, I can't find anything in
113342051Swpaul	 	 * the manual that explains how to do it) so we have
113442051Swpaul		 * to trim off the CRC manually.
113542051Swpaul		 */
113642051Swpaul		total_len -= ETHER_CRC_LEN;
113742051Swpaul
113842051Swpaul		/*
113940516Swpaul		 * Avoid trying to read more bytes than we know
114040516Swpaul		 * the chip has prepared for us.
114140516Swpaul		 */
114240516Swpaul		if (rx_bytes > max_bytes)
114340516Swpaul			break;
114440516Swpaul
114540516Swpaul		rxbufpos = sc->rl_cdata.rl_rx_buf +
114640516Swpaul			((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
114740516Swpaul
114840516Swpaul		if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
114940516Swpaul			rxbufpos = sc->rl_cdata.rl_rx_buf;
115040516Swpaul
115140516Swpaul		wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
115240516Swpaul
115340516Swpaul		if (total_len > wrap) {
115460043Swpaul			/*
115560043Swpaul			 * Fool m_devget() into thinking we want to copy
115660043Swpaul			 * the whole buffer so we don't end up fragmenting
115760043Swpaul			 * the data.
115860043Swpaul			 */
115948028Swpaul			m = m_devget(rxbufpos - RL_ETHER_ALIGN,
116060043Swpaul			    total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
116140516Swpaul			if (m == NULL) {
116240516Swpaul				ifp->if_ierrors++;
116340516Swpaul				printf("rl%d: out of mbufs, tried to "
116452426Swpaul				    "copy %d bytes\n", sc->rl_unit, wrap);
116552426Swpaul			} else {
116648028Swpaul				m_adj(m, RL_ETHER_ALIGN);
116740516Swpaul				m_copyback(m, wrap, total_len - wrap,
116840516Swpaul					sc->rl_cdata.rl_rx_buf);
116948028Swpaul			}
117042051Swpaul			cur_rx = (total_len - wrap + ETHER_CRC_LEN);
117140516Swpaul		} else {
117248028Swpaul			m = m_devget(rxbufpos - RL_ETHER_ALIGN,
117348028Swpaul			    total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
117440516Swpaul			if (m == NULL) {
117540516Swpaul				ifp->if_ierrors++;
117640516Swpaul				printf("rl%d: out of mbufs, tried to "
117752426Swpaul				    "copy %d bytes\n", sc->rl_unit, total_len);
117848028Swpaul			} else
117948028Swpaul				m_adj(m, RL_ETHER_ALIGN);
118042051Swpaul			cur_rx += total_len + 4 + ETHER_CRC_LEN;
118140516Swpaul		}
118240516Swpaul
118340516Swpaul		/*
118440516Swpaul		 * Round up to 32-bit boundary.
118540516Swpaul		 */
118640516Swpaul		cur_rx = (cur_rx + 3) & ~3;
118740516Swpaul		CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
118840516Swpaul
118940516Swpaul		if (m == NULL)
119040516Swpaul			continue;
119140516Swpaul
119240516Swpaul		eh = mtod(m, struct ether_header *);
119340516Swpaul		ifp->if_ipackets++;
119440516Swpaul
119540516Swpaul		/* Remove header from mbuf and pass it on. */
119640516Swpaul		m_adj(m, sizeof(struct ether_header));
119740516Swpaul		ether_input(ifp, eh, m);
119840516Swpaul	}
119940516Swpaul
120040516Swpaul	return;
120140516Swpaul}
120240516Swpaul
120340516Swpaul/*
120440516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up
120540516Swpaul * the list buffers.
120640516Swpaul */
120740516Swpaulstatic void rl_txeof(sc)
120840516Swpaul	struct rl_softc		*sc;
120940516Swpaul{
121040516Swpaul	struct ifnet		*ifp;
121140516Swpaul	u_int32_t		txstat;
121240516Swpaul
121340516Swpaul	ifp = &sc->arpcom.ac_if;
121440516Swpaul
121540516Swpaul	/* Clear the timeout timer. */
121640516Swpaul	ifp->if_timer = 0;
121740516Swpaul
121840516Swpaul	/*
121940516Swpaul	 * Go through our tx list and free mbufs for those
122040516Swpaul	 * frames that have been uploaded.
122140516Swpaul	 */
122245633Swpaul	do {
122345633Swpaul		txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
122445633Swpaul		if (!(txstat & (RL_TXSTAT_TX_OK|
122545633Swpaul		    RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
122640516Swpaul			break;
122740516Swpaul
122845633Swpaul		ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
122940516Swpaul
123045633Swpaul		if (RL_LAST_TXMBUF(sc) != NULL) {
123145633Swpaul			m_freem(RL_LAST_TXMBUF(sc));
123245633Swpaul			RL_LAST_TXMBUF(sc) = NULL;
123345633Swpaul		}
123445633Swpaul		if (txstat & RL_TXSTAT_TX_OK)
123545633Swpaul			ifp->if_opackets++;
123645633Swpaul		else {
123752426Swpaul			int			oldthresh;
123845633Swpaul			ifp->if_oerrors++;
123945633Swpaul			if ((txstat & RL_TXSTAT_TXABRT) ||
124045633Swpaul			    (txstat & RL_TXSTAT_OUTOFWIN))
124145633Swpaul				CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
124252426Swpaul			oldthresh = sc->rl_txthresh;
124352426Swpaul			/* error recovery */
124452426Swpaul			rl_reset(sc);
124552426Swpaul			rl_init(sc);
124652426Swpaul			/*
124752426Swpaul			 * If there was a transmit underrun,
124852426Swpaul			 * bump the TX threshold.
124952426Swpaul			 */
125052426Swpaul			if (txstat & RL_TXSTAT_TX_UNDERRUN)
125152426Swpaul				sc->rl_txthresh = oldthresh + 32;
125252426Swpaul			return;
125345633Swpaul		}
125445633Swpaul		RL_INC(sc->rl_cdata.last_tx);
125545633Swpaul		ifp->if_flags &= ~IFF_OACTIVE;
125645633Swpaul	} while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
125740516Swpaul
125850703Swpaul	return;
125950703Swpaul}
126040516Swpaul
126150703Swpaulstatic void rl_tick(xsc)
126250703Swpaul	void			*xsc;
126350703Swpaul{
126450703Swpaul	struct rl_softc		*sc;
126550703Swpaul	struct mii_data		*mii;
126650703Swpaul
126750703Swpaul	sc = xsc;
126867087Swpaul	RL_LOCK(sc);
126950703Swpaul	mii = device_get_softc(sc->rl_miibus);
127050703Swpaul
127150703Swpaul	mii_tick(mii);
127250703Swpaul
127350703Swpaul	sc->rl_stat_ch = timeout(rl_tick, sc, hz);
127467087Swpaul	RL_UNLOCK(sc);
127550703Swpaul
127640516Swpaul	return;
127740516Swpaul}
127840516Swpaul
127940516Swpaulstatic void rl_intr(arg)
128040516Swpaul	void			*arg;
128140516Swpaul{
128240516Swpaul	struct rl_softc		*sc;
128340516Swpaul	struct ifnet		*ifp;
128440516Swpaul	u_int16_t		status;
128540516Swpaul
128640516Swpaul	sc = arg;
128767087Swpaul	RL_LOCK(sc);
128840516Swpaul	ifp = &sc->arpcom.ac_if;
128940516Swpaul
129040516Swpaul	/* Disable interrupts. */
129140516Swpaul	CSR_WRITE_2(sc, RL_IMR, 0x0000);
129240516Swpaul
129340516Swpaul	for (;;) {
129440516Swpaul
129540516Swpaul		status = CSR_READ_2(sc, RL_ISR);
129640516Swpaul		if (status)
129740516Swpaul			CSR_WRITE_2(sc, RL_ISR, status);
129840516Swpaul
129940516Swpaul		if ((status & RL_INTRS) == 0)
130040516Swpaul			break;
130140516Swpaul
130240516Swpaul		if (status & RL_ISR_RX_OK)
130340516Swpaul			rl_rxeof(sc);
130440516Swpaul
130540516Swpaul		if (status & RL_ISR_RX_ERR)
130640516Swpaul			rl_rxeof(sc);
130740516Swpaul
130845633Swpaul		if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
130940516Swpaul			rl_txeof(sc);
131040516Swpaul
131140516Swpaul		if (status & RL_ISR_SYSTEM_ERR) {
131240516Swpaul			rl_reset(sc);
131340516Swpaul			rl_init(sc);
131440516Swpaul		}
131540516Swpaul
131640516Swpaul	}
131740516Swpaul
131840516Swpaul	/* Re-enable interrupts. */
131940516Swpaul	CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
132040516Swpaul
132152426Swpaul	if (ifp->if_snd.ifq_head != NULL)
132240516Swpaul		rl_start(ifp);
132340516Swpaul
132467087Swpaul	RL_UNLOCK(sc);
132567087Swpaul
132640516Swpaul	return;
132740516Swpaul}
132840516Swpaul
132940516Swpaul/*
133040516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
133140516Swpaul * pointers to the fragment pointers.
133240516Swpaul */
133345633Swpaulstatic int rl_encap(sc, m_head)
133440516Swpaul	struct rl_softc		*sc;
133540516Swpaul	struct mbuf		*m_head;
133640516Swpaul{
133741243Swpaul	struct mbuf		*m_new = NULL;
133840516Swpaul
133940516Swpaul	/*
134045633Swpaul	 * The RealTek is brain damaged and wants longword-aligned
134145633Swpaul	 * TX buffers, plus we can only have one fragment buffer
134245633Swpaul	 * per packet. We have to copy pretty much all the time.
134340516Swpaul	 */
134440516Swpaul
134541243Swpaul	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
134641243Swpaul	if (m_new == NULL) {
134741243Swpaul		printf("rl%d: no memory for tx list", sc->rl_unit);
134841243Swpaul		return(1);
134941243Swpaul	}
135041243Swpaul	if (m_head->m_pkthdr.len > MHLEN) {
135141243Swpaul		MCLGET(m_new, M_DONTWAIT);
135241243Swpaul		if (!(m_new->m_flags & M_EXT)) {
135341243Swpaul			m_freem(m_new);
135441243Swpaul			printf("rl%d: no memory for tx list",
135541243Swpaul					sc->rl_unit);
135640516Swpaul			return(1);
135740516Swpaul		}
135840516Swpaul	}
135952426Swpaul	m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
136041243Swpaul	m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
136141243Swpaul	m_freem(m_head);
136241243Swpaul	m_head = m_new;
136340516Swpaul
136440516Swpaul	/* Pad frames to at least 60 bytes. */
136541243Swpaul	if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
136655058Swpaul		/*
136755058Swpaul		 * Make security concious people happy: zero out the
136855058Swpaul		 * bytes in the pad area, since we don't know what
136955058Swpaul		 * this mbuf cluster buffer's previous user might
137055058Swpaul		 * have left in it.
137155058Swpaul	 	 */
137255058Swpaul		bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
137355058Swpaul		     RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
137440516Swpaul		m_head->m_pkthdr.len +=
137552426Swpaul		    (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
137641243Swpaul		m_head->m_len = m_head->m_pkthdr.len;
137741243Swpaul	}
137840516Swpaul
137945633Swpaul	RL_CUR_TXMBUF(sc) = m_head;
138040516Swpaul
138140516Swpaul	return(0);
138240516Swpaul}
138340516Swpaul
138440516Swpaul/*
138540516Swpaul * Main transmit routine.
138640516Swpaul */
138740516Swpaul
138840516Swpaulstatic void rl_start(ifp)
138940516Swpaul	struct ifnet		*ifp;
139040516Swpaul{
139140516Swpaul	struct rl_softc		*sc;
139240516Swpaul	struct mbuf		*m_head = NULL;
139340516Swpaul
139440516Swpaul	sc = ifp->if_softc;
139567087Swpaul	RL_LOCK(sc);
139640516Swpaul
139745633Swpaul	while(RL_CUR_TXMBUF(sc) == NULL) {
139840516Swpaul		IF_DEQUEUE(&ifp->if_snd, m_head);
139940516Swpaul		if (m_head == NULL)
140040516Swpaul			break;
140140516Swpaul
140258801Swpaul		if (rl_encap(sc, m_head)) {
140358801Swpaul			IF_PREPEND(&ifp->if_snd, m_head);
140458801Swpaul			ifp->if_flags |= IFF_OACTIVE;
140558801Swpaul			break;
140658801Swpaul		}
140740516Swpaul
140840516Swpaul		/*
140940516Swpaul		 * If there's a BPF listener, bounce a copy of this frame
141040516Swpaul		 * to him.
141140516Swpaul		 */
141240516Swpaul		if (ifp->if_bpf)
141345633Swpaul			bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
141451583Swpaul
141540516Swpaul		/*
141640516Swpaul		 * Transmit the frame.
141740516Swpaul	 	 */
141845633Swpaul		CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
141945633Swpaul		    vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
142045633Swpaul		CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
142152426Swpaul		    RL_TXTHRESH(sc->rl_txthresh) |
142252426Swpaul		    RL_CUR_TXMBUF(sc)->m_pkthdr.len);
142345633Swpaul
142445633Swpaul		RL_INC(sc->rl_cdata.cur_tx);
142540516Swpaul	}
142640516Swpaul
142740516Swpaul	/*
142845633Swpaul	 * We broke out of the loop because all our TX slots are
142945633Swpaul	 * full. Mark the NIC as busy until it drains some of the
143045633Swpaul	 * packets from the queue.
143145633Swpaul	 */
143245633Swpaul	if (RL_CUR_TXMBUF(sc) != NULL)
143345633Swpaul		ifp->if_flags |= IFF_OACTIVE;
143445633Swpaul
143545633Swpaul	/*
143640516Swpaul	 * Set a timeout in case the chip goes out to lunch.
143740516Swpaul	 */
143840516Swpaul	ifp->if_timer = 5;
143967087Swpaul	RL_UNLOCK(sc);
144040516Swpaul
144140516Swpaul	return;
144240516Swpaul}
144340516Swpaul
144440516Swpaulstatic void rl_init(xsc)
144540516Swpaul	void			*xsc;
144640516Swpaul{
144740516Swpaul	struct rl_softc		*sc = xsc;
144840516Swpaul	struct ifnet		*ifp = &sc->arpcom.ac_if;
144950703Swpaul	struct mii_data		*mii;
145067087Swpaul	int			i;
145140516Swpaul	u_int32_t		rxcfg = 0;
145240516Swpaul
145367087Swpaul	RL_LOCK(sc);
145450703Swpaul	mii = device_get_softc(sc->rl_miibus);
145540516Swpaul
145640516Swpaul	/*
145740516Swpaul	 * Cancel pending I/O and free all RX/TX buffers.
145840516Swpaul	 */
145940516Swpaul	rl_stop(sc);
146040516Swpaul
146140516Swpaul	/* Init our MAC address */
146240516Swpaul	for (i = 0; i < ETHER_ADDR_LEN; i++) {
146340516Swpaul		CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
146440516Swpaul	}
146540516Swpaul
146640516Swpaul	/* Init the RX buffer pointer register. */
146740516Swpaul	CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
146840516Swpaul
146940516Swpaul	/* Init TX descriptors. */
147040516Swpaul	rl_list_tx_init(sc);
147140516Swpaul
147240516Swpaul	/*
147340516Swpaul	 * Enable transmit and receive.
147440516Swpaul	 */
147540516Swpaul	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
147640516Swpaul
147740516Swpaul	/*
147845633Swpaul	 * Set the initial TX and RX configuration.
147940516Swpaul	 */
148045633Swpaul	CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
148140516Swpaul	CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
148240516Swpaul
148340516Swpaul	/* Set the individual bit to receive frames for this host only. */
148440516Swpaul	rxcfg = CSR_READ_4(sc, RL_RXCFG);
148540516Swpaul	rxcfg |= RL_RXCFG_RX_INDIV;
148640516Swpaul
148740516Swpaul	/* If we want promiscuous mode, set the allframes bit. */
148840516Swpaul	if (ifp->if_flags & IFF_PROMISC) {
148940516Swpaul		rxcfg |= RL_RXCFG_RX_ALLPHYS;
149040516Swpaul		CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
149140516Swpaul	} else {
149240516Swpaul		rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
149340516Swpaul		CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
149440516Swpaul	}
149540516Swpaul
149640516Swpaul	/*
149740516Swpaul	 * Set capture broadcast bit to capture broadcast frames.
149840516Swpaul	 */
149940516Swpaul	if (ifp->if_flags & IFF_BROADCAST) {
150040516Swpaul		rxcfg |= RL_RXCFG_RX_BROAD;
150140516Swpaul		CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
150240516Swpaul	} else {
150340516Swpaul		rxcfg &= ~RL_RXCFG_RX_BROAD;
150440516Swpaul		CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
150540516Swpaul	}
150640516Swpaul
150740516Swpaul	/*
150840516Swpaul	 * Program the multicast filter, if necessary.
150940516Swpaul	 */
151040516Swpaul	rl_setmulti(sc);
151140516Swpaul
151240516Swpaul	/*
151340516Swpaul	 * Enable interrupts.
151440516Swpaul	 */
151540516Swpaul	CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
151640516Swpaul
151752426Swpaul	/* Set initial TX threshold */
151852426Swpaul	sc->rl_txthresh = RL_TX_THRESH_INIT;
151952426Swpaul
152040516Swpaul	/* Start RX/TX process. */
152140516Swpaul	CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
152240516Swpaul
152340516Swpaul	/* Enable receiver and transmitter. */
152440516Swpaul	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
152540516Swpaul
152650703Swpaul	mii_mediachg(mii);
152740516Swpaul
152840516Swpaul	CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
152940516Swpaul
153040516Swpaul	ifp->if_flags |= IFF_RUNNING;
153140516Swpaul	ifp->if_flags &= ~IFF_OACTIVE;
153240516Swpaul
153350703Swpaul	sc->rl_stat_ch = timeout(rl_tick, sc, hz);
153467087Swpaul	RL_UNLOCK(sc);
153550703Swpaul
153640516Swpaul	return;
153740516Swpaul}
153840516Swpaul
153940516Swpaul/*
154040516Swpaul * Set media options.
154140516Swpaul */
154240516Swpaulstatic int rl_ifmedia_upd(ifp)
154340516Swpaul	struct ifnet		*ifp;
154440516Swpaul{
154540516Swpaul	struct rl_softc		*sc;
154650703Swpaul	struct mii_data		*mii;
154740516Swpaul
154840516Swpaul	sc = ifp->if_softc;
154950703Swpaul	mii = device_get_softc(sc->rl_miibus);
155050703Swpaul	mii_mediachg(mii);
155140516Swpaul
155240516Swpaul	return(0);
155340516Swpaul}
155440516Swpaul
155540516Swpaul/*
155640516Swpaul * Report current media status.
155740516Swpaul */
155840516Swpaulstatic void rl_ifmedia_sts(ifp, ifmr)
155940516Swpaul	struct ifnet		*ifp;
156040516Swpaul	struct ifmediareq	*ifmr;
156140516Swpaul{
156240516Swpaul	struct rl_softc		*sc;
156350703Swpaul	struct mii_data		*mii;
156440516Swpaul
156540516Swpaul	sc = ifp->if_softc;
156650703Swpaul	mii = device_get_softc(sc->rl_miibus);
156740516Swpaul
156850703Swpaul	mii_pollstat(mii);
156950703Swpaul	ifmr->ifm_active = mii->mii_media_active;
157050703Swpaul	ifmr->ifm_status = mii->mii_media_status;
157140516Swpaul
157240516Swpaul	return;
157340516Swpaul}
157440516Swpaul
157540516Swpaulstatic int rl_ioctl(ifp, command, data)
157640516Swpaul	struct ifnet		*ifp;
157740516Swpaul	u_long			command;
157840516Swpaul	caddr_t			data;
157940516Swpaul{
158040516Swpaul	struct rl_softc		*sc = ifp->if_softc;
158140516Swpaul	struct ifreq		*ifr = (struct ifreq *) data;
158250703Swpaul	struct mii_data		*mii;
158367087Swpaul	int			error = 0;
158440516Swpaul
158567087Swpaul	RL_LOCK(sc);
158640516Swpaul
158740516Swpaul	switch(command) {
158840516Swpaul	case SIOCSIFADDR:
158940516Swpaul	case SIOCGIFADDR:
159040516Swpaul	case SIOCSIFMTU:
159140516Swpaul		error = ether_ioctl(ifp, command, data);
159240516Swpaul		break;
159340516Swpaul	case SIOCSIFFLAGS:
159440516Swpaul		if (ifp->if_flags & IFF_UP) {
159540516Swpaul			rl_init(sc);
159640516Swpaul		} else {
159740516Swpaul			if (ifp->if_flags & IFF_RUNNING)
159840516Swpaul				rl_stop(sc);
159940516Swpaul		}
160040516Swpaul		error = 0;
160140516Swpaul		break;
160240516Swpaul	case SIOCADDMULTI:
160340516Swpaul	case SIOCDELMULTI:
160440516Swpaul		rl_setmulti(sc);
160540516Swpaul		error = 0;
160640516Swpaul		break;
160740516Swpaul	case SIOCGIFMEDIA:
160840516Swpaul	case SIOCSIFMEDIA:
160950703Swpaul		mii = device_get_softc(sc->rl_miibus);
161050703Swpaul		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
161140516Swpaul		break;
161240516Swpaul	default:
161340516Swpaul		error = EINVAL;
161440516Swpaul		break;
161540516Swpaul	}
161640516Swpaul
161767087Swpaul	RL_UNLOCK(sc);
161840516Swpaul
161940516Swpaul	return(error);
162040516Swpaul}
162140516Swpaul
162240516Swpaulstatic void rl_watchdog(ifp)
162340516Swpaul	struct ifnet		*ifp;
162440516Swpaul{
162540516Swpaul	struct rl_softc		*sc;
162640516Swpaul
162740516Swpaul	sc = ifp->if_softc;
162867087Swpaul	RL_LOCK(sc);
162940516Swpaul	printf("rl%d: watchdog timeout\n", sc->rl_unit);
163040516Swpaul	ifp->if_oerrors++;
163150703Swpaul
163240516Swpaul	rl_txeof(sc);
163340516Swpaul	rl_rxeof(sc);
163440516Swpaul	rl_init(sc);
163567087Swpaul	RL_UNLOCK(sc);
163640516Swpaul
163740516Swpaul	return;
163840516Swpaul}
163940516Swpaul
164040516Swpaul/*
164140516Swpaul * Stop the adapter and free any mbufs allocated to the
164240516Swpaul * RX and TX lists.
164340516Swpaul */
164440516Swpaulstatic void rl_stop(sc)
164540516Swpaul	struct rl_softc		*sc;
164640516Swpaul{
164740516Swpaul	register int		i;
164840516Swpaul	struct ifnet		*ifp;
164940516Swpaul
165067087Swpaul	RL_LOCK(sc);
165140516Swpaul	ifp = &sc->arpcom.ac_if;
165240516Swpaul	ifp->if_timer = 0;
165340516Swpaul
165450703Swpaul	untimeout(rl_tick, sc, sc->rl_stat_ch);
165550703Swpaul
165640516Swpaul	CSR_WRITE_1(sc, RL_COMMAND, 0x00);
165740516Swpaul	CSR_WRITE_2(sc, RL_IMR, 0x0000);
165840516Swpaul
165940516Swpaul	/*
166040516Swpaul	 * Free the TX list buffers.
166140516Swpaul	 */
166240516Swpaul	for (i = 0; i < RL_TX_LIST_CNT; i++) {
166345633Swpaul		if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
166445633Swpaul			m_freem(sc->rl_cdata.rl_tx_chain[i]);
166545633Swpaul			sc->rl_cdata.rl_tx_chain[i] = NULL;
166645633Swpaul			CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
166740516Swpaul		}
166840516Swpaul	}
166940516Swpaul
167040516Swpaul	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
167167087Swpaul	RL_UNLOCK(sc);
167240516Swpaul	return;
167340516Swpaul}
167440516Swpaul
167540516Swpaul/*
167640516Swpaul * Stop all chip I/O so that the kernel's probe routines don't
167740516Swpaul * get confused by errant DMAs when rebooting.
167840516Swpaul */
167950703Swpaulstatic void rl_shutdown(dev)
168050703Swpaul	device_t		dev;
168140516Swpaul{
168250703Swpaul	struct rl_softc		*sc;
168340516Swpaul
168450703Swpaul	sc = device_get_softc(dev);
168550703Swpaul
168640516Swpaul	rl_stop(sc);
168740516Swpaul
168840516Swpaul	return;
168940516Swpaul}
1690