if_rl.c revision 41656
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_rl.c,v 1.18 1998/12/10 17:52:36 wpaul Exp $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include "bpfilter.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#if NBPFILTER > 0 103#include <net/bpf.h> 104#endif 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/clock.h> /* for DELAY */ 109#include <machine/bus_pio.h> 110#include <machine/bus_memio.h> 111#include <machine/bus.h> 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116/* 117 * Default to using PIO access for this driver. On SMP systems, 118 * there appear to be problems with memory mapped mode: it looks like 119 * doing too many memory mapped access back to back in rapid succession 120 * can hang the bus. I'm inclined to blame this on crummy design/construction 121 * on the part of RealTek. Memory mapped mode does appear to work on 122 * uniprocessor systems though. 123 */ 124#define RL_USEIOSPACE 125 126#include <pci/if_rlreg.h> 127 128#ifndef lint 129static const char rcsid[] = 130 "$Id: if_rl.c,v 1.18 1998/12/10 17:52:36 wpaul Exp $"; 131#endif 132 133/* 134 * Various supported device vendors/types and their names. 135 */ 136static struct rl_type rl_devs[] = { 137 { RT_VENDORID, RT_DEVICEID_8129, 138 "RealTek 8129 10/100BaseTX" }, 139 { RT_VENDORID, RT_DEVICEID_8139, 140 "RealTek 8139 10/100BaseTX" }, 141 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 142 "Accton MPX 5030/5038 10/100BaseTX" }, 143 { 0, 0, NULL } 144}; 145 146/* 147 * Various supported PHY vendors/types and their names. Note that 148 * this driver will work with pretty much any MII-compliant PHY, 149 * so failure to positively identify the chip is not a fatal error. 150 */ 151 152static struct rl_type rl_phys[] = { 153 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 154 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 155 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 156 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 157 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 158 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 159 { 0, 0, "<MII-compliant physical interface>" } 160}; 161 162static unsigned long rl_count = 0; 163static char *rl_probe __P((pcici_t, pcidi_t)); 164static void rl_attach __P((pcici_t, int)); 165 166static int rl_encap __P((struct rl_softc *, struct rl_chain *, 167 struct mbuf * )); 168 169static void rl_rxeof __P((struct rl_softc *)); 170static void rl_txeof __P((struct rl_softc *)); 171static void rl_txeoc __P((struct rl_softc *)); 172static void rl_intr __P((void *)); 173static void rl_start __P((struct ifnet *)); 174static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 175static void rl_init __P((void *)); 176static void rl_stop __P((struct rl_softc *)); 177static void rl_watchdog __P((struct ifnet *)); 178static void rl_shutdown __P((int, void *)); 179static int rl_ifmedia_upd __P((struct ifnet *)); 180static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 181 182static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 183static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 184static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 185 int, int, int)); 186static void rl_mii_sync __P((struct rl_softc *)); 187static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 188static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 189static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 190 191static u_int16_t rl_phy_readreg __P((struct rl_softc *, int)); 192static void rl_phy_writereg __P((struct rl_softc *, int, int)); 193 194static void rl_autoneg_xmit __P((struct rl_softc *)); 195static void rl_autoneg_mii __P((struct rl_softc *, int, int)); 196static void rl_setmode_mii __P((struct rl_softc *, int)); 197static void rl_getmode_mii __P((struct rl_softc *)); 198static u_int8_t rl_calchash __P((caddr_t)); 199static void rl_setmulti __P((struct rl_softc *)); 200static void rl_reset __P((struct rl_softc *)); 201static int rl_list_tx_init __P((struct rl_softc *)); 202 203#define EE_SET(x) \ 204 CSR_WRITE_1(sc, RL_EECMD, \ 205 CSR_READ_1(sc, RL_EECMD) | x) 206 207#define EE_CLR(x) \ 208 CSR_WRITE_1(sc, RL_EECMD, \ 209 CSR_READ_1(sc, RL_EECMD) & ~x) 210 211/* 212 * Send a read command and address to the EEPROM, check for ACK. 213 */ 214static void rl_eeprom_putbyte(sc, addr) 215 struct rl_softc *sc; 216 int addr; 217{ 218 register int d, i; 219 220 d = addr | RL_EECMD_READ; 221 222 /* 223 * Feed in each bit and stobe the clock. 224 */ 225 for (i = 0x400; i; i >>= 1) { 226 if (d & i) { 227 EE_SET(RL_EE_DATAIN); 228 } else { 229 EE_CLR(RL_EE_DATAIN); 230 } 231 DELAY(100); 232 EE_SET(RL_EE_CLK); 233 DELAY(150); 234 EE_CLR(RL_EE_CLK); 235 DELAY(100); 236 } 237 238 return; 239} 240 241/* 242 * Read a word of data stored in the EEPROM at address 'addr.' 243 */ 244static void rl_eeprom_getword(sc, addr, dest) 245 struct rl_softc *sc; 246 int addr; 247 u_int16_t *dest; 248{ 249 register int i; 250 u_int16_t word = 0; 251 252 /* Enter EEPROM access mode. */ 253 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 254 255 /* 256 * Send address of word we want to read. 257 */ 258 rl_eeprom_putbyte(sc, addr); 259 260 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 261 262 /* 263 * Start reading bits from EEPROM. 264 */ 265 for (i = 0x8000; i; i >>= 1) { 266 EE_SET(RL_EE_CLK); 267 DELAY(100); 268 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 269 word |= i; 270 EE_CLR(RL_EE_CLK); 271 DELAY(100); 272 } 273 274 /* Turn off EEPROM access mode. */ 275 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 276 277 *dest = word; 278 279 return; 280} 281 282/* 283 * Read a sequence of words from the EEPROM. 284 */ 285static void rl_read_eeprom(sc, dest, off, cnt, swap) 286 struct rl_softc *sc; 287 caddr_t dest; 288 int off; 289 int cnt; 290 int swap; 291{ 292 int i; 293 u_int16_t word = 0, *ptr; 294 295 for (i = 0; i < cnt; i++) { 296 rl_eeprom_getword(sc, off + i, &word); 297 ptr = (u_int16_t *)(dest + (i * 2)); 298 if (swap) 299 *ptr = ntohs(word); 300 else 301 *ptr = word; 302 } 303 304 return; 305} 306 307 308/* 309 * MII access routines are provided for the 8129, which 310 * doesn't have a built-in PHY. For the 8139, we fake things 311 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 312 * direct access PHY registers. 313 */ 314#define MII_SET(x) \ 315 CSR_WRITE_1(sc, RL_MII, \ 316 CSR_READ_1(sc, RL_MII) | x) 317 318#define MII_CLR(x) \ 319 CSR_WRITE_1(sc, RL_MII, \ 320 CSR_READ_1(sc, RL_MII) & ~x) 321 322/* 323 * Sync the PHYs by setting data bit and strobing the clock 32 times. 324 */ 325static void rl_mii_sync(sc) 326 struct rl_softc *sc; 327{ 328 register int i; 329 330 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 331 332 for (i = 0; i < 32; i++) { 333 MII_SET(RL_MII_CLK); 334 DELAY(1); 335 MII_CLR(RL_MII_CLK); 336 DELAY(1); 337 } 338 339 return; 340} 341 342/* 343 * Clock a series of bits through the MII. 344 */ 345static void rl_mii_send(sc, bits, cnt) 346 struct rl_softc *sc; 347 u_int32_t bits; 348 int cnt; 349{ 350 int i; 351 352 MII_CLR(RL_MII_CLK); 353 354 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 355 if (bits & i) { 356 MII_SET(RL_MII_DATAOUT); 357 } else { 358 MII_CLR(RL_MII_DATAOUT); 359 } 360 DELAY(1); 361 MII_CLR(RL_MII_CLK); 362 DELAY(1); 363 MII_SET(RL_MII_CLK); 364 } 365} 366 367/* 368 * Read an PHY register through the MII. 369 */ 370static int rl_mii_readreg(sc, frame) 371 struct rl_softc *sc; 372 struct rl_mii_frame *frame; 373 374{ 375 int i, ack, s; 376 377 s = splimp(); 378 379 /* 380 * Set up frame for RX. 381 */ 382 frame->mii_stdelim = RL_MII_STARTDELIM; 383 frame->mii_opcode = RL_MII_READOP; 384 frame->mii_turnaround = 0; 385 frame->mii_data = 0; 386 387 CSR_WRITE_2(sc, RL_MII, 0); 388 389 /* 390 * Turn on data xmit. 391 */ 392 MII_SET(RL_MII_DIR); 393 394 rl_mii_sync(sc); 395 396 /* 397 * Send command/address info. 398 */ 399 rl_mii_send(sc, frame->mii_stdelim, 2); 400 rl_mii_send(sc, frame->mii_opcode, 2); 401 rl_mii_send(sc, frame->mii_phyaddr, 5); 402 rl_mii_send(sc, frame->mii_regaddr, 5); 403 404 /* Idle bit */ 405 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 406 DELAY(1); 407 MII_SET(RL_MII_CLK); 408 DELAY(1); 409 410 /* Turn off xmit. */ 411 MII_CLR(RL_MII_DIR); 412 413 /* Check for ack */ 414 MII_CLR(RL_MII_CLK); 415 DELAY(1); 416 MII_SET(RL_MII_CLK); 417 DELAY(1); 418 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 419 420 /* 421 * Now try reading data bits. If the ack failed, we still 422 * need to clock through 16 cycles to keep the PHY(s) in sync. 423 */ 424 if (ack) { 425 for(i = 0; i < 16; i++) { 426 MII_CLR(RL_MII_CLK); 427 DELAY(1); 428 MII_SET(RL_MII_CLK); 429 DELAY(1); 430 } 431 goto fail; 432 } 433 434 for (i = 0x8000; i; i >>= 1) { 435 MII_CLR(RL_MII_CLK); 436 DELAY(1); 437 if (!ack) { 438 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 439 frame->mii_data |= i; 440 DELAY(1); 441 } 442 MII_SET(RL_MII_CLK); 443 DELAY(1); 444 } 445 446fail: 447 448 MII_CLR(RL_MII_CLK); 449 DELAY(1); 450 MII_SET(RL_MII_CLK); 451 DELAY(1); 452 453 splx(s); 454 455 if (ack) 456 return(1); 457 return(0); 458} 459 460/* 461 * Write to a PHY register through the MII. 462 */ 463static int rl_mii_writereg(sc, frame) 464 struct rl_softc *sc; 465 struct rl_mii_frame *frame; 466 467{ 468 int s; 469 470 s = splimp(); 471 /* 472 * Set up frame for TX. 473 */ 474 475 frame->mii_stdelim = RL_MII_STARTDELIM; 476 frame->mii_opcode = RL_MII_WRITEOP; 477 frame->mii_turnaround = RL_MII_TURNAROUND; 478 479 /* 480 * Turn on data output. 481 */ 482 MII_SET(RL_MII_DIR); 483 484 rl_mii_sync(sc); 485 486 rl_mii_send(sc, frame->mii_stdelim, 2); 487 rl_mii_send(sc, frame->mii_opcode, 2); 488 rl_mii_send(sc, frame->mii_phyaddr, 5); 489 rl_mii_send(sc, frame->mii_regaddr, 5); 490 rl_mii_send(sc, frame->mii_turnaround, 2); 491 rl_mii_send(sc, frame->mii_data, 16); 492 493 /* Idle bit. */ 494 MII_SET(RL_MII_CLK); 495 DELAY(1); 496 MII_CLR(RL_MII_CLK); 497 DELAY(1); 498 499 /* 500 * Turn off xmit. 501 */ 502 MII_CLR(RL_MII_DIR); 503 504 splx(s); 505 506 return(0); 507} 508 509static u_int16_t rl_phy_readreg(sc, reg) 510 struct rl_softc *sc; 511 int reg; 512{ 513 struct rl_mii_frame frame; 514 u_int16_t rval = 0; 515 u_int16_t rl8139_reg = 0; 516 517 if (sc->rl_type == RL_8139) { 518 switch(reg) { 519 case PHY_BMCR: 520 rl8139_reg = RL_BMCR; 521 break; 522 case PHY_BMSR: 523 rl8139_reg = RL_BMSR; 524 break; 525 case PHY_ANAR: 526 rl8139_reg = RL_ANAR; 527 break; 528 case PHY_LPAR: 529 rl8139_reg = RL_LPAR; 530 break; 531 default: 532 printf("rl%d: bad phy register\n", sc->rl_unit); 533 return(0); 534 } 535 rval = CSR_READ_2(sc, rl8139_reg); 536 return(rval); 537 } 538 539 bzero((char *)&frame, sizeof(frame)); 540 541 frame.mii_phyaddr = sc->rl_phy_addr; 542 frame.mii_regaddr = reg; 543 rl_mii_readreg(sc, &frame); 544 545 return(frame.mii_data); 546} 547 548static void rl_phy_writereg(sc, reg, data) 549 struct rl_softc *sc; 550 int reg; 551 int data; 552{ 553 struct rl_mii_frame frame; 554 u_int16_t rl8139_reg = 0; 555 556 if (sc->rl_type == RL_8139) { 557 switch(reg) { 558 case PHY_BMCR: 559 rl8139_reg = RL_BMCR; 560 break; 561 case PHY_BMSR: 562 rl8139_reg = RL_BMSR; 563 break; 564 case PHY_ANAR: 565 rl8139_reg = RL_ANAR; 566 break; 567 case PHY_LPAR: 568 rl8139_reg = RL_LPAR; 569 break; 570 default: 571 printf("rl%d: bad phy register\n", sc->rl_unit); 572 return; 573 } 574 CSR_WRITE_2(sc, rl8139_reg, data); 575 return; 576 } 577 578 bzero((char *)&frame, sizeof(frame)); 579 580 frame.mii_phyaddr = sc->rl_phy_addr; 581 frame.mii_regaddr = reg; 582 frame.mii_data = data; 583 584 rl_mii_writereg(sc, &frame); 585 586 return; 587} 588 589/* 590 * Calculate CRC of a multicast group address, return the lower 6 bits. 591 */ 592static u_int8_t rl_calchash(addr) 593 caddr_t addr; 594{ 595 u_int32_t crc, carry; 596 int i, j; 597 u_int8_t c; 598 599 /* Compute CRC for the address value. */ 600 crc = 0xFFFFFFFF; /* initial value */ 601 602 for (i = 0; i < 6; i++) { 603 c = *(addr + i); 604 for (j = 0; j < 8; j++) { 605 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 606 crc <<= 1; 607 c >>= 1; 608 if (carry) 609 crc = (crc ^ 0x04c11db6) | carry; 610 } 611 } 612 613 /* return the filter bit position */ 614 return(crc & 0x0000003F); 615} 616 617/* 618 * Program the 64-bit multicast hash filter. 619 */ 620static void rl_setmulti(sc) 621 struct rl_softc *sc; 622{ 623 struct ifnet *ifp; 624 int h = 0; 625 u_int32_t hashes[2] = { 0, 0 }; 626 struct ifmultiaddr *ifma; 627 u_int32_t rxfilt; 628 int mcnt = 0; 629 630 ifp = &sc->arpcom.ac_if; 631 632 rxfilt = CSR_READ_4(sc, RL_RXCFG); 633 634 if (ifp->if_flags & IFF_ALLMULTI) { 635 rxfilt |= RL_RXCFG_RX_MULTI; 636 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 637 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 638 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 639 return; 640 } 641 642 /* first, zot all the existing hash bits */ 643 CSR_WRITE_4(sc, RL_MAR0, 0); 644 CSR_WRITE_4(sc, RL_MAR4, 0); 645 646 /* now program new ones */ 647 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 648 ifma = ifma->ifma_link.le_next) { 649 if (ifma->ifma_addr->sa_family != AF_LINK) 650 continue; 651 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 652 if (h < 32) 653 hashes[0] |= (1 << h); 654 else 655 hashes[1] |= (1 << (h - 32)); 656 mcnt++; 657 } 658 659 if (mcnt) 660 rxfilt |= RL_RXCFG_RX_MULTI; 661 else 662 rxfilt &= ~RL_RXCFG_RX_MULTI; 663 664 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 665 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 666 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 667 668 return; 669} 670 671/* 672 * Initiate an autonegotiation session. 673 */ 674static void rl_autoneg_xmit(sc) 675 struct rl_softc *sc; 676{ 677 u_int16_t phy_sts; 678 679 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 680 DELAY(500); 681 while(rl_phy_readreg(sc, PHY_BMCR) 682 & PHY_BMCR_RESET); 683 684 phy_sts = rl_phy_readreg(sc, PHY_BMCR); 685 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 686 rl_phy_writereg(sc, PHY_BMCR, phy_sts); 687 688 return; 689} 690 691/* 692 * Invoke autonegotiation on a PHY. Also used with the 8139 internal 693 * transceiver. 694 */ 695static void rl_autoneg_mii(sc, flag, verbose) 696 struct rl_softc *sc; 697 int flag; 698 int verbose; 699{ 700 u_int16_t phy_sts = 0, media, advert, ability; 701 struct ifnet *ifp; 702 struct ifmedia *ifm; 703 704 ifm = &sc->ifmedia; 705 ifp = &sc->arpcom.ac_if; 706 707 /* 708 * The 100baseT4 PHY sometimes has the 'autoneg supported' 709 * bit cleared in the status register, but has the 'autoneg enabled' 710 * bit set in the control register. This is a contradiction, and 711 * I'm not sure how to handle it. If you want to force an attempt 712 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 713 * and see what happens. 714 */ 715#ifndef FORCE_AUTONEG_TFOUR 716 /* 717 * First, see if autoneg is supported. If not, there's 718 * no point in continuing. 719 */ 720 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 721 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 722 if (verbose) 723 printf("rl%d: autonegotiation not supported\n", 724 sc->rl_unit); 725 return; 726 } 727#endif 728 729 switch (flag) { 730 case RL_FLAG_FORCEDELAY: 731 /* 732 * XXX Never use this option anywhere but in the probe 733 * routine: making the kernel stop dead in its tracks 734 * for three whole seconds after we've gone multi-user 735 * is really bad manners. 736 */ 737 rl_autoneg_xmit(sc); 738 DELAY(5000000); 739 break; 740 case RL_FLAG_SCHEDDELAY: 741 /* 742 * Wait for the transmitter to go idle before starting 743 * an autoneg session, otherwise rl_start() may clobber 744 * our timeout, and we don't want to allow transmission 745 * during an autoneg session since that can screw it up. 746 */ 747 if (sc->rl_cdata.rl_tx_cnt) { 748 sc->rl_want_auto = 1; 749 return; 750 } 751 rl_autoneg_xmit(sc); 752 ifp->if_timer = 5; 753 sc->rl_autoneg = 1; 754 sc->rl_want_auto = 0; 755 return; 756 break; 757 case RL_FLAG_DELAYTIMEO: 758 ifp->if_timer = 0; 759 sc->rl_autoneg = 0; 760 break; 761 default: 762 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag); 763 return; 764 } 765 766 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 767 if (verbose) 768 printf("rl%d: autoneg complete, ", sc->rl_unit); 769 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 770 } else { 771 if (verbose) 772 printf("rl%d: autoneg not complete, ", sc->rl_unit); 773 } 774 775 media = rl_phy_readreg(sc, PHY_BMCR); 776 777 /* Link is good. Report modes and set duplex mode. */ 778 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 779 if (verbose) 780 printf("link status good "); 781 advert = rl_phy_readreg(sc, PHY_ANAR); 782 ability = rl_phy_readreg(sc, PHY_LPAR); 783 784 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 785 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 786 media |= PHY_BMCR_SPEEDSEL; 787 media &= ~PHY_BMCR_DUPLEX; 788 printf("(100baseT4)\n"); 789 } else if (advert & PHY_ANAR_100BTXFULL && 790 ability & PHY_ANAR_100BTXFULL) { 791 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 792 media |= PHY_BMCR_SPEEDSEL; 793 media |= PHY_BMCR_DUPLEX; 794 printf("(full-duplex, 100Mbps)\n"); 795 } else if (advert & PHY_ANAR_100BTXHALF && 796 ability & PHY_ANAR_100BTXHALF) { 797 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 798 media |= PHY_BMCR_SPEEDSEL; 799 media &= ~PHY_BMCR_DUPLEX; 800 printf("(half-duplex, 100Mbps)\n"); 801 } else if (advert & PHY_ANAR_10BTFULL && 802 ability & PHY_ANAR_10BTFULL) { 803 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 804 media &= ~PHY_BMCR_SPEEDSEL; 805 media |= PHY_BMCR_DUPLEX; 806 printf("(full-duplex, 10Mbps)\n"); 807 } else { 808 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 809 media &= ~PHY_BMCR_SPEEDSEL; 810 media &= ~PHY_BMCR_DUPLEX; 811 printf("(half-duplex, 10Mbps)\n"); 812 } 813 814 /* Set ASIC's duplex mode to match the PHY. */ 815 rl_phy_writereg(sc, PHY_BMCR, media); 816 } else { 817 if (verbose) 818 printf("no carrier\n"); 819 } 820 821 rl_init(sc); 822 823 if (sc->rl_tx_pend) { 824 sc->rl_autoneg = 0; 825 sc->rl_tx_pend = 0; 826 rl_start(ifp); 827 } 828 829 return; 830} 831 832static void rl_getmode_mii(sc) 833 struct rl_softc *sc; 834{ 835 u_int16_t bmsr; 836 struct ifnet *ifp; 837 838 ifp = &sc->arpcom.ac_if; 839 840 bmsr = rl_phy_readreg(sc, PHY_BMSR); 841 if (bootverbose) 842 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr); 843 844 /* fallback */ 845 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 846 847 if (bmsr & PHY_BMSR_10BTHALF) { 848 if (bootverbose) 849 printf("rl%d: 10Mbps half-duplex mode supported\n", 850 sc->rl_unit); 851 ifmedia_add(&sc->ifmedia, 852 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 853 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 854 } 855 856 if (bmsr & PHY_BMSR_10BTFULL) { 857 if (bootverbose) 858 printf("rl%d: 10Mbps full-duplex mode supported\n", 859 sc->rl_unit); 860 ifmedia_add(&sc->ifmedia, 861 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 862 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 863 } 864 865 if (bmsr & PHY_BMSR_100BTXHALF) { 866 if (bootverbose) 867 printf("rl%d: 100Mbps half-duplex mode supported\n", 868 sc->rl_unit); 869 ifp->if_baudrate = 100000000; 870 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 871 ifmedia_add(&sc->ifmedia, 872 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 873 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 874 } 875 876 if (bmsr & PHY_BMSR_100BTXFULL) { 877 if (bootverbose) 878 printf("rl%d: 100Mbps full-duplex mode supported\n", 879 sc->rl_unit); 880 ifp->if_baudrate = 100000000; 881 ifmedia_add(&sc->ifmedia, 882 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 883 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 884 } 885 886 /* Some also support 100BaseT4. */ 887 if (bmsr & PHY_BMSR_100BT4) { 888 if (bootverbose) 889 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit); 890 ifp->if_baudrate = 100000000; 891 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 892 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 893#ifdef FORCE_AUTONEG_TFOUR 894 if (bootverbose) 895 printf("rl%d: forcing on autoneg support for BT4\n", 896 sc->rl_unit); 897 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 898 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 899#endif 900 } 901 902 if (bmsr & PHY_BMSR_CANAUTONEG) { 903 if (bootverbose) 904 printf("rl%d: autoneg supported\n", sc->rl_unit); 905 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 906 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 907 } 908 909 return; 910} 911 912/* 913 * Set speed and duplex mode. 914 */ 915static void rl_setmode_mii(sc, media) 916 struct rl_softc *sc; 917 int media; 918{ 919 u_int16_t bmcr; 920 921 printf("rl%d: selecting MII, ", sc->rl_unit); 922 923 bmcr = rl_phy_readreg(sc, PHY_BMCR); 924 925 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 926 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 927 928 if (IFM_SUBTYPE(media) == IFM_100_T4) { 929 printf("100Mbps/T4, half-duplex\n"); 930 bmcr |= PHY_BMCR_SPEEDSEL; 931 bmcr &= ~PHY_BMCR_DUPLEX; 932 } 933 934 if (IFM_SUBTYPE(media) == IFM_100_TX) { 935 printf("100Mbps, "); 936 bmcr |= PHY_BMCR_SPEEDSEL; 937 } 938 939 if (IFM_SUBTYPE(media) == IFM_10_T) { 940 printf("10Mbps, "); 941 bmcr &= ~PHY_BMCR_SPEEDSEL; 942 } 943 944 if ((media & IFM_GMASK) == IFM_FDX) { 945 printf("full duplex\n"); 946 bmcr |= PHY_BMCR_DUPLEX; 947 } else { 948 printf("half duplex\n"); 949 bmcr &= ~PHY_BMCR_DUPLEX; 950 } 951 952 rl_phy_writereg(sc, PHY_BMCR, bmcr); 953 954 return; 955} 956 957static void rl_reset(sc) 958 struct rl_softc *sc; 959{ 960 register int i; 961 962 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 963 964 for (i = 0; i < RL_TIMEOUT; i++) { 965 DELAY(10); 966 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 967 break; 968 } 969 if (i == RL_TIMEOUT) 970 printf("rl%d: reset never completed!\n", sc->rl_unit); 971 972 return; 973} 974 975/* 976 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 977 * IDs against our list and return a device name if we find a match. 978 */ 979static char * 980rl_probe(config_id, device_id) 981 pcici_t config_id; 982 pcidi_t device_id; 983{ 984 struct rl_type *t; 985 986 t = rl_devs; 987 988 while(t->rl_name != NULL) { 989 if ((device_id & 0xFFFF) == t->rl_vid && 990 ((device_id >> 16) & 0xFFFF) == t->rl_did) { 991 return(t->rl_name); 992 } 993 t++; 994 } 995 996 return(NULL); 997} 998 999/* 1000 * Attach the interface. Allocate softc structures, do ifmedia 1001 * setup and ethernet/BPF attach. 1002 */ 1003static void 1004rl_attach(config_id, unit) 1005 pcici_t config_id; 1006 int unit; 1007{ 1008 int s, i; 1009#ifndef RL_USEIOSPACE 1010 vm_offset_t pbase, vbase; 1011#endif 1012 u_char eaddr[ETHER_ADDR_LEN]; 1013 u_int32_t command; 1014 struct rl_softc *sc; 1015 struct ifnet *ifp; 1016 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1017 struct rl_type *p; 1018 u_int16_t phy_vid, phy_did, phy_sts; 1019 u_int16_t rl_did = 0; 1020 1021 s = splimp(); 1022 1023 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT); 1024 if (sc == NULL) { 1025 printf("rl%d: no memory for softc struct!\n", unit); 1026 return; 1027 } 1028 bzero(sc, sizeof(struct rl_softc)); 1029 1030 /* 1031 * Handle power management nonsense. 1032 */ 1033 1034 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF; 1035 if (command == 0x01) { 1036 1037 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL); 1038 if (command & RL_PSTATE_MASK) { 1039 u_int32_t iobase, membase, irq; 1040 1041 /* Save important PCI config data. */ 1042 iobase = pci_conf_read(config_id, RL_PCI_LOIO); 1043 membase = pci_conf_read(config_id, RL_PCI_LOMEM); 1044 irq = pci_conf_read(config_id, RL_PCI_INTLINE); 1045 1046 /* Reset the power state. */ 1047 printf("rl%d: chip is is in D%d power mode " 1048 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 1049 command &= 0xFFFFFFFC; 1050 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command); 1051 1052 /* Restore PCI config data. */ 1053 pci_conf_write(config_id, RL_PCI_LOIO, iobase); 1054 pci_conf_write(config_id, RL_PCI_LOMEM, membase); 1055 pci_conf_write(config_id, RL_PCI_INTLINE, irq); 1056 } 1057 } 1058 1059 /* 1060 * Map control/status registers. 1061 */ 1062 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1063 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1064 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1065 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1066 1067#ifdef RL_USEIOSPACE 1068 if (!(command & PCIM_CMD_PORTEN)) { 1069 printf("rl%d: failed to enable I/O ports!\n", unit); 1070 free(sc, M_DEVBUF); 1071 goto fail; 1072 } 1073 1074 if (!pci_map_port(config_id, RL_PCI_LOIO, 1075 (u_int16_t *)&(sc->rl_bhandle))) { 1076 printf ("rl%d: couldn't map ports\n", unit); 1077 goto fail; 1078 } 1079 sc->rl_btag = I386_BUS_SPACE_IO; 1080#else 1081 if (!(command & PCIM_CMD_MEMEN)) { 1082 printf("rl%d: failed to enable memory mapping!\n", unit); 1083 goto fail; 1084 } 1085 1086 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) { 1087 printf ("rl%d: couldn't map memory\n", unit); 1088 goto fail; 1089 } 1090 sc->rl_btag = I386_BUS_SPACE_MEM; 1091 sc->rl_bhandle = vbase; 1092#endif 1093 1094 /* Allocate interrupt */ 1095 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) { 1096 printf("rl%d: couldn't map interrupt\n", unit); 1097 goto fail; 1098 } 1099 1100 /* Reset the adapter. */ 1101 rl_reset(sc); 1102 1103 /* 1104 * Get station address from the EEPROM. 1105 */ 1106 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 1107 1108 /* 1109 * A RealTek chip was detected. Inform the world. 1110 */ 1111 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1112 1113 sc->rl_unit = unit; 1114 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1115 1116 /* 1117 * Now read the exact device type from the EEPROM to find 1118 * out if it's an 8129 or 8139. 1119 */ 1120 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1121 1122 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030) 1123 sc->rl_type = RL_8139; 1124 else if (rl_did == RT_DEVICEID_8129) 1125 sc->rl_type = RL_8129; 1126 else { 1127 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1128 free(sc, M_DEVBUF); 1129 goto fail; 1130 } 1131 1132 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF, 1133 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1134 1135 if (sc->rl_cdata.rl_rx_buf == NULL) { 1136 free(sc, M_DEVBUF); 1137 printf("rl%d: no memory for list buffers!\n", unit); 1138 goto fail; 1139 } 1140 1141 ifp = &sc->arpcom.ac_if; 1142 ifp->if_softc = sc; 1143 ifp->if_unit = unit; 1144 ifp->if_name = "rl"; 1145 ifp->if_mtu = ETHERMTU; 1146 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1147 ifp->if_ioctl = rl_ioctl; 1148 ifp->if_output = ether_output; 1149 ifp->if_start = rl_start; 1150 ifp->if_watchdog = rl_watchdog; 1151 ifp->if_init = rl_init; 1152 ifp->if_baudrate = 10000000; 1153 1154 if (sc->rl_type == RL_8129) { 1155 if (bootverbose) 1156 printf("rl%d: probing for a PHY\n", sc->rl_unit); 1157 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) { 1158 if (bootverbose) 1159 printf("rl%d: checking address: %d\n", 1160 sc->rl_unit, i); 1161 sc->rl_phy_addr = i; 1162 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1163 DELAY(500); 1164 while(rl_phy_readreg(sc, PHY_BMCR) 1165 & PHY_BMCR_RESET); 1166 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR))) 1167 break; 1168 } 1169 if (phy_sts) { 1170 phy_vid = rl_phy_readreg(sc, PHY_VENID); 1171 phy_did = rl_phy_readreg(sc, PHY_DEVID); 1172 if (bootverbose) 1173 printf("rl%d: found PHY at address %d, ", 1174 sc->rl_unit, sc->rl_phy_addr); 1175 if (bootverbose) 1176 printf("vendor id: %x device id: %x\n", 1177 phy_vid, phy_did); 1178 p = rl_phys; 1179 while(p->rl_vid) { 1180 if (phy_vid == p->rl_vid && 1181 (phy_did | 0x000F) == p->rl_did) { 1182 sc->rl_pinfo = p; 1183 break; 1184 } 1185 p++; 1186 } 1187 if (sc->rl_pinfo == NULL) 1188 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN]; 1189 if (bootverbose) 1190 printf("rl%d: PHY type: %s\n", 1191 sc->rl_unit, sc->rl_pinfo->rl_name); 1192 } else { 1193 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1194 } 1195 } 1196 1197 /* 1198 * Do ifmedia setup. 1199 */ 1200 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts); 1201 1202 rl_getmode_mii(sc); 1203 1204 /* Choose a default media. */ 1205 media = IFM_ETHER|IFM_AUTO; 1206 ifmedia_set(&sc->ifmedia, media); 1207 1208 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1); 1209 1210 /* 1211 * Call MI attach routines. 1212 */ 1213 if_attach(ifp); 1214 ether_ifattach(ifp); 1215 1216#if NBPFILTER > 0 1217 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1218#endif 1219 at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC); 1220 1221fail: 1222 splx(s); 1223 return; 1224} 1225 1226/* 1227 * Initialize the transmit descriptors. 1228 */ 1229static int rl_list_tx_init(sc) 1230 struct rl_softc *sc; 1231{ 1232 struct rl_chain_data *cd; 1233 int i; 1234 1235 cd = &sc->rl_cdata; 1236 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1237 cd->rl_tx_chain[i].rl_desc = i * 4; 1238 CSR_WRITE_4(sc, RL_TXADDR0 + cd->rl_tx_chain[i].rl_desc, 0); 1239 CSR_WRITE_4(sc, RL_TXSTAT0 + cd->rl_tx_chain[i].rl_desc, 0); 1240 if (i == (RL_TX_LIST_CNT - 1)) 1241 cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[0]; 1242 else 1243 cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[i + 1]; 1244 } 1245 1246 sc->rl_cdata.rl_tx_cnt = 0; 1247 cd->rl_tx_cur = cd->rl_tx_free = &cd->rl_tx_chain[0]; 1248 1249 return(0); 1250} 1251 1252/* 1253 * A frame has been uploaded: pass the resulting mbuf chain up to 1254 * the higher level protocols. 1255 * 1256 * You know there's something wrong with a PCI bus-master chip design 1257 * when you have to use m_devget(). 1258 * 1259 * The receive operation is badly documented in the datasheet, so I'll 1260 * attempt to document it here. The driver provides a buffer area and 1261 * places its base address in the RX buffer start address register. 1262 * The chip then begins copying frames into the RX buffer. Each frame 1263 * is preceeded by a 32-bit RX status word which specifies the length 1264 * of the frame and certain other status bits. Each frame (starting with 1265 * the status word) is also 32-bit aligned. The frame length is in the 1266 * first 16 bits of the status word; the lower 15 bits correspond with 1267 * the 'rx status register' mentioned in the datasheet. 1268 */ 1269static void rl_rxeof(sc) 1270 struct rl_softc *sc; 1271{ 1272 struct ether_header *eh; 1273 struct mbuf *m; 1274 struct ifnet *ifp; 1275 int total_len = 0; 1276 u_int32_t rxstat; 1277 caddr_t rxbufpos; 1278 int wrap = 0; 1279 u_int16_t cur_rx; 1280 u_int16_t limit; 1281 u_int16_t rx_bytes = 0, max_bytes; 1282 1283 ifp = &sc->arpcom.ac_if; 1284 1285 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1286 1287 /* Do not try to read past this point. */ 1288 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1289 1290 if (limit < cur_rx) 1291 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1292 else 1293 max_bytes = limit - cur_rx; 1294 1295 while((CSR_READ_1(sc, RL_COMMAND) & 1) == 0) { 1296 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1297 rxstat = *(u_int32_t *)rxbufpos; 1298 1299 /* 1300 * Here's a totally undocumented fact for you. When the 1301 * RealTek chip is in the process of copying a packet into 1302 * RAM for you, the length will be 0xfff0. If you spot a 1303 * packet header with this value, you need to stop. The 1304 * datasheet makes absolutely no mention of this and 1305 * RealTek should be shot for this. 1306 */ 1307 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1308 break; 1309 1310 if (!(rxstat & RL_RXSTAT_RXOK)) { 1311 ifp->if_ierrors++; 1312 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 1313 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 1314 RL_RXSTAT_ALIGNERR)) { 1315 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 1316 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 1317 RL_CMD_RX_ENB); 1318 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1319 CSR_WRITE_4(sc, RL_RXADDR, 1320 vtophys(sc->rl_cdata.rl_rx_buf)); 1321 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1322 cur_rx = 0; 1323 } 1324 break; 1325 } 1326 1327 /* No errors; receive the packet. */ 1328 total_len = rxstat >> 16; 1329 rx_bytes += total_len + 4; 1330 1331 /* 1332 * Avoid trying to read more bytes than we know 1333 * the chip has prepared for us. 1334 */ 1335 if (rx_bytes > max_bytes) 1336 break; 1337 1338 rxbufpos = sc->rl_cdata.rl_rx_buf + 1339 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1340 1341 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1342 rxbufpos = sc->rl_cdata.rl_rx_buf; 1343 1344 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1345 1346 if (total_len > wrap) { 1347 m = m_devget(rxbufpos, wrap, 0, ifp, NULL); 1348 if (m == NULL) { 1349 ifp->if_ierrors++; 1350 printf("rl%d: out of mbufs, tried to " 1351 "copy %d bytes\n", sc->rl_unit, wrap); 1352 } 1353 else 1354 m_copyback(m, wrap, total_len - wrap, 1355 sc->rl_cdata.rl_rx_buf); 1356 cur_rx = (total_len - wrap); 1357 } else { 1358 m = m_devget(rxbufpos, total_len, 0, ifp, NULL); 1359 if (m == NULL) { 1360 ifp->if_ierrors++; 1361 printf("rl%d: out of mbufs, tried to " 1362 "copy %d bytes\n", sc->rl_unit, total_len); 1363 } 1364 cur_rx += total_len + 4; 1365 } 1366 1367 /* 1368 * Round up to 32-bit boundary. 1369 */ 1370 cur_rx = (cur_rx + 3) & ~3; 1371 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1372 1373 if (m == NULL) 1374 continue; 1375 1376 eh = mtod(m, struct ether_header *); 1377 ifp->if_ipackets++; 1378 1379#if NBPFILTER > 0 1380 /* 1381 * Handle BPF listeners. Let the BPF user see the packet, but 1382 * don't pass it up to the ether_input() layer unless it's 1383 * a broadcast packet, multicast packet, matches our ethernet 1384 * address or the interface is in promiscuous mode. 1385 */ 1386 if (ifp->if_bpf) { 1387 bpf_mtap(ifp, m); 1388 if (ifp->if_flags & IFF_PROMISC && 1389 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1390 ETHER_ADDR_LEN) && 1391 (eh->ether_dhost[0] & 1) == 0)) { 1392 m_freem(m); 1393 continue; 1394 } 1395 } 1396#endif 1397 /* Remove header from mbuf and pass it on. */ 1398 m_adj(m, sizeof(struct ether_header)); 1399 ether_input(ifp, eh, m); 1400 } 1401 1402 return; 1403} 1404 1405/* 1406 * A frame was downloaded to the chip. It's safe for us to clean up 1407 * the list buffers. 1408 */ 1409static void rl_txeof(sc) 1410 struct rl_softc *sc; 1411{ 1412 struct rl_chain *cur_tx; 1413 struct ifnet *ifp; 1414 u_int32_t txstat; 1415 1416 ifp = &sc->arpcom.ac_if; 1417 1418 /* Clear the timeout timer. */ 1419 ifp->if_timer = 0; 1420 1421 /* 1422 * Go through our tx list and free mbufs for those 1423 * frames that have been uploaded. 1424 */ 1425 if (sc->rl_cdata.rl_tx_free == NULL) 1426 return; 1427 1428 while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) { 1429 cur_tx = sc->rl_cdata.rl_tx_free; 1430 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc); 1431 1432 if (!(txstat & RL_TXSTAT_TX_OK)) 1433 break; 1434 1435 if (txstat & RL_TXSTAT_COLLCNT) 1436 ifp->if_collisions += 1437 (txstat & RL_TXSTAT_COLLCNT) >> 24; 1438 1439 sc->rl_cdata.rl_tx_free = cur_tx->rl_next; 1440 1441 sc->rl_cdata.rl_tx_cnt--; 1442 m_freem(cur_tx->rl_mbuf); 1443 cur_tx->rl_mbuf = NULL; 1444 ifp->if_opackets++; 1445 } 1446 1447 if (!sc->rl_cdata.rl_tx_cnt) { 1448 ifp->if_flags &= ~IFF_OACTIVE; 1449 if (sc->rl_want_auto) 1450 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1451 } else { 1452 if (ifp->if_snd.ifq_head != NULL) 1453 rl_start(ifp); 1454 } 1455 1456 return; 1457} 1458 1459/* 1460 * TX error handler. 1461 */ 1462static void rl_txeoc(sc) 1463 struct rl_softc *sc; 1464{ 1465 u_int32_t txstat; 1466 struct rl_chain *cur_tx; 1467 struct ifnet *ifp; 1468 1469 ifp = &sc->arpcom.ac_if; 1470 1471 if (sc->rl_cdata.rl_tx_free == NULL) 1472 return; 1473 1474 while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) { 1475 cur_tx = sc->rl_cdata.rl_tx_free; 1476 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc); 1477 1478 if (!(txstat & RL_TXSTAT_OWN)) 1479 break; 1480 1481 if (!(txstat & RL_TXSTAT_TX_OK)) { 1482 ifp->if_oerrors++; 1483 if (txstat & RL_TXSTAT_COLLCNT) 1484 ifp->if_collisions += 1485 (txstat & RL_TXSTAT_COLLCNT) >> 24; 1486 CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc, 1487 vtophys(mtod(cur_tx->rl_mbuf, caddr_t))); 1488 CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc, 1489 RL_TX_EARLYTHRESH | 1490 cur_tx->rl_mbuf->m_pkthdr.len); 1491 break; 1492 } else { 1493 if (txstat & RL_TXSTAT_COLLCNT) 1494 ifp->if_collisions += 1495 (txstat & RL_TXSTAT_COLLCNT) >> 24; 1496 sc->rl_cdata.rl_tx_free = cur_tx->rl_next; 1497 1498 sc->rl_cdata.rl_tx_cnt--; 1499 m_freem(cur_tx->rl_mbuf); 1500 cur_tx->rl_mbuf = NULL; 1501 ifp->if_opackets++; 1502 } 1503 } 1504 1505 return; 1506} 1507 1508static void rl_intr(arg) 1509 void *arg; 1510{ 1511 struct rl_softc *sc; 1512 struct ifnet *ifp; 1513 u_int16_t status; 1514 1515 sc = arg; 1516 ifp = &sc->arpcom.ac_if; 1517 1518 /* Disable interrupts. */ 1519 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1520 1521 for (;;) { 1522 1523 status = CSR_READ_2(sc, RL_ISR); 1524 if (status) 1525 CSR_WRITE_2(sc, RL_ISR, status); 1526 1527 if ((status & RL_INTRS) == 0) 1528 break; 1529 1530 if (status & RL_ISR_RX_OK) 1531 rl_rxeof(sc); 1532 1533 if (status & RL_ISR_RX_ERR) 1534 rl_rxeof(sc); 1535 1536 if (status & RL_ISR_TX_OK) 1537 rl_txeof(sc); 1538 1539 if (status & RL_ISR_TX_ERR) 1540 rl_txeoc(sc); 1541 1542 if (status & RL_ISR_SYSTEM_ERR) { 1543 rl_reset(sc); 1544 rl_init(sc); 1545 } 1546 1547 } 1548 1549 /* Re-enable interrupts. */ 1550 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1551 1552 if (ifp->if_snd.ifq_head != NULL) { 1553 rl_start(ifp); 1554 } 1555 1556 return; 1557} 1558 1559/* 1560 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1561 * pointers to the fragment pointers. 1562 */ 1563static int rl_encap(sc, c, m_head) 1564 struct rl_softc *sc; 1565 struct rl_chain *c; 1566 struct mbuf *m_head; 1567{ 1568 struct mbuf *m; 1569 struct mbuf *m_new = NULL; 1570 1571 /* 1572 * There are two possible encapsulation mechanisms 1573 * that we can use: an efficient one, and a very lossy 1574 * one. The efficient one only happens very rarely, 1575 * whereas the lossy one can and most likely will happen 1576 * all the time. 1577 * The efficient case happens if: 1578 * - the packet fits in a single mbuf 1579 * - the packet is 32-bit aligned within the mbuf data area 1580 * In this case, we can DMA from the mbuf directly. 1581 * The lossy case covers everything else. Bah. 1582 */ 1583 1584 m = m_head; 1585 1586 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1587 if (m_new == NULL) { 1588 printf("rl%d: no memory for tx list", sc->rl_unit); 1589 return(1); 1590 } 1591 if (m_head->m_pkthdr.len > MHLEN) { 1592 MCLGET(m_new, M_DONTWAIT); 1593 if (!(m_new->m_flags & M_EXT)) { 1594 m_freem(m_new); 1595 printf("rl%d: no memory for tx list", 1596 sc->rl_unit); 1597 return(1); 1598 } 1599 } 1600 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1601 mtod(m_new, caddr_t)); 1602 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1603 m_freem(m_head); 1604 m_head = m_new; 1605 1606 /* Pad frames to at least 60 bytes. */ 1607 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1608 m_head->m_pkthdr.len += 1609 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1610 m_head->m_len = m_head->m_pkthdr.len; 1611 } 1612 1613 c->rl_mbuf = m_head; 1614 1615 return(0); 1616} 1617 1618/* 1619 * Main transmit routine. 1620 */ 1621 1622static void rl_start(ifp) 1623 struct ifnet *ifp; 1624{ 1625 struct rl_softc *sc; 1626 struct mbuf *m_head = NULL; 1627 struct rl_chain *cur_tx = NULL; 1628 1629 sc = ifp->if_softc; 1630 1631 if (sc->rl_autoneg) { 1632 sc->rl_tx_pend = 1; 1633 return; 1634 } 1635 1636 /* 1637 * Check for an available queue slot. If there are none, 1638 * punt. 1639 */ 1640 if (sc->rl_cdata.rl_tx_cur->rl_mbuf != NULL) { 1641 ifp->if_flags |= IFF_OACTIVE; 1642 return; 1643 } 1644 1645 while(sc->rl_cdata.rl_tx_cur->rl_mbuf == NULL) { 1646 IF_DEQUEUE(&ifp->if_snd, m_head); 1647 if (m_head == NULL) 1648 break; 1649 1650 1651 /* Pick a descriptor off the free list. */ 1652 cur_tx = sc->rl_cdata.rl_tx_cur; 1653 sc->rl_cdata.rl_tx_cur = cur_tx->rl_next; 1654 sc->rl_cdata.rl_tx_cnt++; 1655 1656 /* Pack the data into the descriptor. */ 1657 rl_encap(sc, cur_tx, m_head); 1658 1659#if NBPFILTER > 0 1660 /* 1661 * If there's a BPF listener, bounce a copy of this frame 1662 * to him. 1663 */ 1664 if (ifp->if_bpf) 1665 bpf_mtap(ifp, cur_tx->rl_mbuf); 1666#endif 1667 /* 1668 * Transmit the frame. 1669 */ 1670 CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc, 1671 vtophys(mtod(cur_tx->rl_mbuf, caddr_t))); 1672 CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc, 1673 RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len); 1674 } 1675 1676 /* 1677 * Set a timeout in case the chip goes out to lunch. 1678 */ 1679 ifp->if_timer = 5; 1680 1681 return; 1682} 1683 1684static void rl_init(xsc) 1685 void *xsc; 1686{ 1687 struct rl_softc *sc = xsc; 1688 struct ifnet *ifp = &sc->arpcom.ac_if; 1689 int s, i; 1690 u_int32_t rxcfg = 0; 1691 u_int16_t phy_bmcr = 0; 1692 1693 if (sc->rl_autoneg) 1694 return; 1695 1696 s = splimp(); 1697 1698 /* 1699 * XXX Hack for the 8139: the built-in autoneg logic's state 1700 * gets reset by rl_init() when we don't want it to. Try 1701 * to preserve it. (For 8129 cards with real external PHYs, 1702 * the BMCR register doesn't change, but this doesn't hurt.) 1703 */ 1704 if (sc->rl_type == RL_8139) 1705 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR); 1706 1707 /* 1708 * Cancel pending I/O and free all RX/TX buffers. 1709 */ 1710 rl_stop(sc); 1711 1712 /* Init our MAC address */ 1713 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1714 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1715 } 1716 1717 /* Init the RX buffer pointer register. */ 1718 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1719 1720 /* Init TX descriptors. */ 1721 rl_list_tx_init(sc); 1722 1723 /* 1724 * Enable transmit and receive. 1725 */ 1726 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1727 1728 /* 1729 * Set the buffer size values. 1730 */ 1731 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1732 1733 /* Set the individual bit to receive frames for this host only. */ 1734 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1735 rxcfg |= RL_RXCFG_RX_INDIV; 1736 1737 /* If we want promiscuous mode, set the allframes bit. */ 1738 if (ifp->if_flags & IFF_PROMISC) { 1739 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1740 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1741 } else { 1742 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1743 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1744 } 1745 1746 /* 1747 * Set capture broadcast bit to capture broadcast frames. 1748 */ 1749 if (ifp->if_flags & IFF_BROADCAST) { 1750 rxcfg |= RL_RXCFG_RX_BROAD; 1751 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1752 } else { 1753 rxcfg &= ~RL_RXCFG_RX_BROAD; 1754 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1755 } 1756 1757 /* 1758 * Program the multicast filter, if necessary. 1759 */ 1760 rl_setmulti(sc); 1761 1762 /* 1763 * Enable interrupts. 1764 */ 1765 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1766 1767 /* Start RX/TX process. */ 1768 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1769 1770 /* Enable receiver and transmitter. */ 1771 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1772 1773 /* Restore state of BMCR */ 1774 if (sc->rl_pinfo != NULL) 1775 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1776 1777 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1778 1779 ifp->if_flags |= IFF_RUNNING; 1780 ifp->if_flags &= ~IFF_OACTIVE; 1781 1782 (void)splx(s); 1783 1784 return; 1785} 1786 1787/* 1788 * Set media options. 1789 */ 1790static int rl_ifmedia_upd(ifp) 1791 struct ifnet *ifp; 1792{ 1793 struct rl_softc *sc; 1794 struct ifmedia *ifm; 1795 1796 sc = ifp->if_softc; 1797 ifm = &sc->ifmedia; 1798 1799 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1800 return(EINVAL); 1801 1802 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1803 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1804 else 1805 rl_setmode_mii(sc, ifm->ifm_media); 1806 1807 return(0); 1808} 1809 1810/* 1811 * Report current media status. 1812 */ 1813static void rl_ifmedia_sts(ifp, ifmr) 1814 struct ifnet *ifp; 1815 struct ifmediareq *ifmr; 1816{ 1817 struct rl_softc *sc; 1818 u_int16_t advert = 0, ability = 0; 1819 1820 sc = ifp->if_softc; 1821 1822 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1823 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1824 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 1825 else 1826 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 1827 1828 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1829 ifmr->ifm_active |= IFM_FDX; 1830 else 1831 ifmr->ifm_active |= IFM_HDX; 1832 return; 1833 } 1834 1835 ability = rl_phy_readreg(sc, PHY_LPAR); 1836 advert = rl_phy_readreg(sc, PHY_ANAR); 1837 if (advert & PHY_ANAR_100BT4 && 1838 ability & PHY_ANAR_100BT4) { 1839 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 1840 } else if (advert & PHY_ANAR_100BTXFULL && 1841 ability & PHY_ANAR_100BTXFULL) { 1842 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 1843 } else if (advert & PHY_ANAR_100BTXHALF && 1844 ability & PHY_ANAR_100BTXHALF) { 1845 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 1846 } else if (advert & PHY_ANAR_10BTFULL && 1847 ability & PHY_ANAR_10BTFULL) { 1848 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 1849 } else if (advert & PHY_ANAR_10BTHALF && 1850 ability & PHY_ANAR_10BTHALF) { 1851 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 1852 } 1853 1854 return; 1855} 1856 1857static int rl_ioctl(ifp, command, data) 1858 struct ifnet *ifp; 1859 u_long command; 1860 caddr_t data; 1861{ 1862 struct rl_softc *sc = ifp->if_softc; 1863 struct ifreq *ifr = (struct ifreq *) data; 1864 int s, error = 0; 1865 1866 s = splimp(); 1867 1868 switch(command) { 1869 case SIOCSIFADDR: 1870 case SIOCGIFADDR: 1871 case SIOCSIFMTU: 1872 error = ether_ioctl(ifp, command, data); 1873 break; 1874 case SIOCSIFFLAGS: 1875 if (ifp->if_flags & IFF_UP) { 1876 rl_init(sc); 1877 } else { 1878 if (ifp->if_flags & IFF_RUNNING) 1879 rl_stop(sc); 1880 } 1881 error = 0; 1882 break; 1883 case SIOCADDMULTI: 1884 case SIOCDELMULTI: 1885 rl_setmulti(sc); 1886 error = 0; 1887 break; 1888 case SIOCGIFMEDIA: 1889 case SIOCSIFMEDIA: 1890 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1891 break; 1892 default: 1893 error = EINVAL; 1894 break; 1895 } 1896 1897 (void)splx(s); 1898 1899 return(error); 1900} 1901 1902static void rl_watchdog(ifp) 1903 struct ifnet *ifp; 1904{ 1905 struct rl_softc *sc; 1906 1907 sc = ifp->if_softc; 1908 1909 if (sc->rl_autoneg) { 1910 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1); 1911 return; 1912 } 1913 1914 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1915 ifp->if_oerrors++; 1916 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1917 printf("rl%d: no carrier - transceiver cable problem?\n", 1918 sc->rl_unit); 1919 rl_txeoc(sc); 1920 rl_txeof(sc); 1921 rl_rxeof(sc); 1922 rl_init(sc); 1923 1924 return; 1925} 1926 1927/* 1928 * Stop the adapter and free any mbufs allocated to the 1929 * RX and TX lists. 1930 */ 1931static void rl_stop(sc) 1932 struct rl_softc *sc; 1933{ 1934 register int i; 1935 struct ifnet *ifp; 1936 1937 ifp = &sc->arpcom.ac_if; 1938 ifp->if_timer = 0; 1939 1940 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1941 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1942 1943 /* 1944 * Free the TX list buffers. 1945 */ 1946 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1947 if (sc->rl_cdata.rl_tx_chain[i].rl_mbuf != NULL) { 1948 m_freem(sc->rl_cdata.rl_tx_chain[i].rl_mbuf); 1949 sc->rl_cdata.rl_tx_chain[i].rl_mbuf = NULL; 1950 CSR_WRITE_4(sc, RL_TXADDR0 + 1951 sc->rl_cdata.rl_tx_chain[i].rl_desc, 0x00000000); 1952 } 1953 } 1954 1955 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1956 1957 return; 1958} 1959 1960/* 1961 * Stop all chip I/O so that the kernel's probe routines don't 1962 * get confused by errant DMAs when rebooting. 1963 */ 1964static void rl_shutdown(howto, arg) 1965 int howto; 1966 void *arg; 1967{ 1968 struct rl_softc *sc = (struct rl_softc *)arg; 1969 1970 rl_stop(sc); 1971 1972 return; 1973} 1974 1975 1976static struct pci_device rl_device = { 1977 "rl", 1978 rl_probe, 1979 rl_attach, 1980 &rl_count, 1981 NULL 1982}; 1983DATA_SET(pcidevice_set, rl_device); 1984