if_rl.c revision 41273
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3241273Swpaul * $Id: if_rl.c,v 1.2 1998/11/18 21:03:57 wpaul Exp $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5640516Swpaul * on a doubleword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul * 8540516Swpaul * Note: beware of trying to use the Linux RealTek driver as a reference 8640516Swpaul * for information about the RealTek chip. It contains several bogosities. 8740516Swpaul * It contains definitions for several undocumented registers which it 8840516Swpaul * claims are 'required for proper operation' yet it does not use these 8940516Swpaul * registers anywhere in the code. It also refers to some undocumented 9040516Swpaul * 'Twister tuning codes' which it doesn't use anywhere. It also contains 9140516Swpaul * bit definitions for several registers which are totally ignored: magic 9240516Swpaul * numbers are used instead, making the code hard to read. 9340516Swpaul */ 9440516Swpaul 9540516Swpaul#include "bpfilter.h" 9640516Swpaul 9740516Swpaul#include <sys/param.h> 9840516Swpaul#include <sys/systm.h> 9940516Swpaul#include <sys/sockio.h> 10040516Swpaul#include <sys/mbuf.h> 10140516Swpaul#include <sys/malloc.h> 10240516Swpaul#include <sys/kernel.h> 10340516Swpaul#include <sys/socket.h> 10440516Swpaul 10540516Swpaul#include <net/if.h> 10640516Swpaul#include <net/if_arp.h> 10740516Swpaul#include <net/ethernet.h> 10840516Swpaul#include <net/if_dl.h> 10940516Swpaul#include <net/if_media.h> 11040516Swpaul 11140516Swpaul#if NBPFILTER > 0 11240516Swpaul#include <net/bpf.h> 11340516Swpaul#endif 11440516Swpaul 11540516Swpaul#include <vm/vm.h> /* for vtophys */ 11640516Swpaul#include <vm/pmap.h> /* for vtophys */ 11740516Swpaul#include <machine/clock.h> /* for DELAY */ 11840516Swpaul 11940516Swpaul#include <pci/pcireg.h> 12040516Swpaul#include <pci/pcivar.h> 12140516Swpaul 12240516Swpaul/* 12340516Swpaul * Default to using PIO access for this driver. On SMP systems, 12440516Swpaul * there appear to be problems with memory mapped mode: it looks like 12540516Swpaul * doing too many memory mapped access back to back in rapid succession 12640516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12740516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12840516Swpaul * uniprocessor systems though. 12940516Swpaul */ 13040516Swpaul#define RL_USEIOSPACE 13140516Swpaul 13240516Swpaul#include <pci/if_rlreg.h> 13340516Swpaul 13440516Swpaul#ifndef lint 13540516Swpaulstatic char rcsid[] = 13641273Swpaul "$Id: if_rl.c,v 1.2 1998/11/18 21:03:57 wpaul Exp $"; 13740516Swpaul#endif 13840516Swpaul 13940516Swpaul/* 14040516Swpaul * Various supported device vendors/types and their names. 14140516Swpaul */ 14240516Swpaulstatic struct rl_type rl_devs[] = { 14340516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14440516Swpaul "RealTek 8129 10/100BaseTX" }, 14540516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14640516Swpaul "RealTek 8139 10/100BaseTX" }, 14741243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14841243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14940516Swpaul { 0, 0, NULL } 15040516Swpaul}; 15140516Swpaul 15240516Swpaul/* 15340516Swpaul * Various supported PHY vendors/types and their names. Note that 15440516Swpaul * this driver will work with pretty much any MII-compliant PHY, 15540516Swpaul * so failure to positively identify the chip is not a fatal error. 15640516Swpaul */ 15740516Swpaul 15840516Swpaulstatic struct rl_type rl_phys[] = { 15940516Swpaul { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 16040516Swpaul { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 16140516Swpaul { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 16240516Swpaul { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 16340516Swpaul { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 16440516Swpaul { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 16540516Swpaul { 0, 0, "<MII-compliant physical interface>" } 16640516Swpaul}; 16740516Swpaul 16840516Swpaulstatic unsigned long rl_count = 0; 16940516Swpaulstatic char *rl_probe __P((pcici_t, pcidi_t)); 17040516Swpaulstatic void rl_attach __P((pcici_t, int)); 17140516Swpaul 17240516Swpaulstatic int rl_encap __P((struct rl_softc *, struct rl_chain *, 17340516Swpaul struct mbuf * )); 17440516Swpaul 17540516Swpaulstatic void rl_rxeof __P((struct rl_softc *)); 17640516Swpaulstatic void rl_txeof __P((struct rl_softc *)); 17740516Swpaulstatic void rl_txeoc __P((struct rl_softc *)); 17840516Swpaulstatic void rl_intr __P((void *)); 17940516Swpaulstatic void rl_start __P((struct ifnet *)); 18040516Swpaulstatic int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 18140516Swpaulstatic void rl_init __P((void *)); 18240516Swpaulstatic void rl_stop __P((struct rl_softc *)); 18340516Swpaulstatic void rl_watchdog __P((struct ifnet *)); 18440516Swpaulstatic void rl_shutdown __P((int, void *)); 18540516Swpaulstatic int rl_ifmedia_upd __P((struct ifnet *)); 18640516Swpaulstatic void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 18740516Swpaul 18840516Swpaulstatic void rl_eeprom_putbyte __P((struct rl_softc *, u_int8_t)); 18940516Swpaulstatic void rl_eeprom_getword __P((struct rl_softc *, u_int8_t, u_int16_t *)); 19040516Swpaulstatic void rl_read_eeprom __P((struct rl_softc *, caddr_t, 19140516Swpaul int, int, int)); 19240516Swpaulstatic void rl_mii_sync __P((struct rl_softc *)); 19340516Swpaulstatic void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 19440516Swpaulstatic int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 19540516Swpaulstatic int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 19640516Swpaul 19740516Swpaulstatic u_int16_t rl_phy_readreg __P((struct rl_softc *, int)); 19840516Swpaulstatic void rl_phy_writereg __P((struct rl_softc *, u_int16_t, u_int16_t)); 19940516Swpaul 20040516Swpaulstatic void rl_autoneg_xmit __P((struct rl_softc *)); 20140516Swpaulstatic void rl_autoneg_mii __P((struct rl_softc *, int, int)); 20240516Swpaulstatic void rl_setmode_mii __P((struct rl_softc *, int)); 20340516Swpaulstatic void rl_getmode_mii __P((struct rl_softc *)); 20440516Swpaulstatic u_int8_t rl_calchash __P((u_int8_t *)); 20540516Swpaulstatic void rl_setmulti __P((struct rl_softc *)); 20640516Swpaulstatic void rl_reset __P((struct rl_softc *)); 20740516Swpaulstatic int rl_list_tx_init __P((struct rl_softc *)); 20840516Swpaul 20940516Swpaul#define EE_SET(x) \ 21040516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 21140516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 21240516Swpaul 21340516Swpaul#define EE_CLR(x) \ 21440516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 21540516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 21640516Swpaul 21740516Swpaul/* 21840516Swpaul * Send a read command and address to the EEPROM, check for ACK. 21940516Swpaul */ 22040516Swpaulstatic void rl_eeprom_putbyte(sc, addr) 22140516Swpaul struct rl_softc *sc; 22240516Swpaul u_int8_t addr; 22340516Swpaul{ 22440516Swpaul register int d, i; 22540516Swpaul 22640516Swpaul d = addr | RL_EECMD_READ; 22740516Swpaul 22840516Swpaul /* 22940516Swpaul * Feed in each bit and stobe the clock. 23040516Swpaul */ 23140516Swpaul for (i = 0x400; i; i >>= 1) { 23240516Swpaul if (d & i) { 23340516Swpaul EE_SET(RL_EE_DATAIN); 23440516Swpaul } else { 23540516Swpaul EE_CLR(RL_EE_DATAIN); 23640516Swpaul } 23740516Swpaul DELAY(100); 23840516Swpaul EE_SET(RL_EE_CLK); 23940516Swpaul DELAY(150); 24040516Swpaul EE_CLR(RL_EE_CLK); 24140516Swpaul DELAY(100); 24240516Swpaul } 24340516Swpaul 24440516Swpaul return; 24540516Swpaul} 24640516Swpaul 24740516Swpaul/* 24840516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 24940516Swpaul */ 25040516Swpaulstatic void rl_eeprom_getword(sc, addr, dest) 25140516Swpaul struct rl_softc *sc; 25240516Swpaul u_int8_t addr; 25340516Swpaul u_int16_t *dest; 25440516Swpaul{ 25540516Swpaul register int i; 25640516Swpaul u_int16_t word = 0; 25740516Swpaul 25840516Swpaul /* Enter EEPROM access mode. */ 25940516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 26040516Swpaul 26140516Swpaul /* 26240516Swpaul * Send address of word we want to read. 26340516Swpaul */ 26440516Swpaul rl_eeprom_putbyte(sc, addr); 26540516Swpaul 26640516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 26740516Swpaul 26840516Swpaul /* 26940516Swpaul * Start reading bits from EEPROM. 27040516Swpaul */ 27140516Swpaul for (i = 0x8000; i; i >>= 1) { 27240516Swpaul EE_SET(RL_EE_CLK); 27340516Swpaul DELAY(100); 27440516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 27540516Swpaul word |= i; 27640516Swpaul EE_CLR(RL_EE_CLK); 27740516Swpaul DELAY(100); 27840516Swpaul } 27940516Swpaul 28040516Swpaul /* Turn off EEPROM access mode. */ 28140516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 28240516Swpaul 28340516Swpaul *dest = word; 28440516Swpaul 28540516Swpaul return; 28640516Swpaul} 28740516Swpaul 28840516Swpaul/* 28940516Swpaul * Read a sequence of words from the EEPROM. 29040516Swpaul */ 29140516Swpaulstatic void rl_read_eeprom(sc, dest, off, cnt, swap) 29240516Swpaul struct rl_softc *sc; 29340516Swpaul caddr_t dest; 29440516Swpaul int off; 29540516Swpaul int cnt; 29640516Swpaul int swap; 29740516Swpaul{ 29840516Swpaul int i; 29940516Swpaul u_int16_t word = 0, *ptr; 30040516Swpaul 30140516Swpaul for (i = 0; i < cnt; i++) { 30240516Swpaul rl_eeprom_getword(sc, off + i, &word); 30340516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 30440516Swpaul if (swap) 30540516Swpaul *ptr = ntohs(word); 30640516Swpaul else 30740516Swpaul *ptr = word; 30840516Swpaul } 30940516Swpaul 31040516Swpaul return; 31140516Swpaul} 31240516Swpaul 31340516Swpaul 31440516Swpaul/* 31540516Swpaul * MII access routines are provided for the 8129, which 31640516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 31740516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 31840516Swpaul * direct access PHY registers. 31940516Swpaul */ 32040516Swpaul#define MII_SET(x) \ 32140516Swpaul CSR_WRITE_1(sc, RL_MII, \ 32240516Swpaul CSR_READ_1(sc, RL_MII) | x) 32340516Swpaul 32440516Swpaul#define MII_CLR(x) \ 32540516Swpaul CSR_WRITE_1(sc, RL_MII, \ 32640516Swpaul CSR_READ_1(sc, RL_MII) & ~x) 32740516Swpaul 32840516Swpaul/* 32940516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 33040516Swpaul */ 33140516Swpaulstatic void rl_mii_sync(sc) 33240516Swpaul struct rl_softc *sc; 33340516Swpaul{ 33440516Swpaul register int i; 33540516Swpaul 33640516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 33740516Swpaul 33840516Swpaul for (i = 0; i < 32; i++) { 33940516Swpaul MII_SET(RL_MII_CLK); 34040516Swpaul DELAY(1); 34140516Swpaul MII_CLR(RL_MII_CLK); 34240516Swpaul DELAY(1); 34340516Swpaul } 34440516Swpaul 34540516Swpaul return; 34640516Swpaul} 34740516Swpaul 34840516Swpaul/* 34940516Swpaul * Clock a series of bits through the MII. 35040516Swpaul */ 35140516Swpaulstatic void rl_mii_send(sc, bits, cnt) 35240516Swpaul struct rl_softc *sc; 35340516Swpaul u_int32_t bits; 35440516Swpaul int cnt; 35540516Swpaul{ 35640516Swpaul int i; 35740516Swpaul 35840516Swpaul MII_CLR(RL_MII_CLK); 35940516Swpaul 36040516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 36140516Swpaul if (bits & i) { 36240516Swpaul MII_SET(RL_MII_DATAOUT); 36340516Swpaul } else { 36440516Swpaul MII_CLR(RL_MII_DATAOUT); 36540516Swpaul } 36640516Swpaul DELAY(1); 36740516Swpaul MII_CLR(RL_MII_CLK); 36840516Swpaul DELAY(1); 36940516Swpaul MII_SET(RL_MII_CLK); 37040516Swpaul } 37140516Swpaul} 37240516Swpaul 37340516Swpaul/* 37440516Swpaul * Read an PHY register through the MII. 37540516Swpaul */ 37640516Swpaulstatic int rl_mii_readreg(sc, frame) 37740516Swpaul struct rl_softc *sc; 37840516Swpaul struct rl_mii_frame *frame; 37940516Swpaul 38040516Swpaul{ 38140516Swpaul int i, ack, s; 38240516Swpaul 38340516Swpaul s = splimp(); 38440516Swpaul 38540516Swpaul /* 38640516Swpaul * Set up frame for RX. 38740516Swpaul */ 38840516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 38940516Swpaul frame->mii_opcode = RL_MII_READOP; 39040516Swpaul frame->mii_turnaround = 0; 39140516Swpaul frame->mii_data = 0; 39240516Swpaul 39340516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 39440516Swpaul 39540516Swpaul /* 39640516Swpaul * Turn on data xmit. 39740516Swpaul */ 39840516Swpaul MII_SET(RL_MII_DIR); 39940516Swpaul 40040516Swpaul rl_mii_sync(sc); 40140516Swpaul 40240516Swpaul /* 40340516Swpaul * Send command/address info. 40440516Swpaul */ 40540516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 40640516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 40740516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 40840516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 40940516Swpaul 41040516Swpaul /* Idle bit */ 41140516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 41240516Swpaul DELAY(1); 41340516Swpaul MII_SET(RL_MII_CLK); 41440516Swpaul DELAY(1); 41540516Swpaul 41640516Swpaul /* Turn off xmit. */ 41740516Swpaul MII_CLR(RL_MII_DIR); 41840516Swpaul 41940516Swpaul /* Check for ack */ 42040516Swpaul MII_CLR(RL_MII_CLK); 42140516Swpaul DELAY(1); 42240516Swpaul MII_SET(RL_MII_CLK); 42340516Swpaul DELAY(1); 42440516Swpaul ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 42540516Swpaul 42640516Swpaul /* 42740516Swpaul * Now try reading data bits. If the ack failed, we still 42840516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 42940516Swpaul */ 43040516Swpaul if (ack) { 43140516Swpaul for(i = 0; i < 16; i++) { 43240516Swpaul MII_CLR(RL_MII_CLK); 43340516Swpaul DELAY(1); 43440516Swpaul MII_SET(RL_MII_CLK); 43540516Swpaul DELAY(1); 43640516Swpaul } 43740516Swpaul goto fail; 43840516Swpaul } 43940516Swpaul 44040516Swpaul for (i = 0x8000; i; i >>= 1) { 44140516Swpaul MII_CLR(RL_MII_CLK); 44240516Swpaul DELAY(1); 44340516Swpaul if (!ack) { 44440516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 44540516Swpaul frame->mii_data |= i; 44640516Swpaul DELAY(1); 44740516Swpaul } 44840516Swpaul MII_SET(RL_MII_CLK); 44940516Swpaul DELAY(1); 45040516Swpaul } 45140516Swpaul 45240516Swpaulfail: 45340516Swpaul 45440516Swpaul MII_CLR(RL_MII_CLK); 45540516Swpaul DELAY(1); 45640516Swpaul MII_SET(RL_MII_CLK); 45740516Swpaul DELAY(1); 45840516Swpaul 45940516Swpaul splx(s); 46040516Swpaul 46140516Swpaul if (ack) 46240516Swpaul return(1); 46340516Swpaul return(0); 46440516Swpaul} 46540516Swpaul 46640516Swpaul/* 46740516Swpaul * Write to a PHY register through the MII. 46840516Swpaul */ 46940516Swpaulstatic int rl_mii_writereg(sc, frame) 47040516Swpaul struct rl_softc *sc; 47140516Swpaul struct rl_mii_frame *frame; 47240516Swpaul 47340516Swpaul{ 47440516Swpaul int s; 47540516Swpaul 47640516Swpaul s = splimp(); 47740516Swpaul /* 47840516Swpaul * Set up frame for TX. 47940516Swpaul */ 48040516Swpaul 48140516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 48240516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 48340516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 48440516Swpaul 48540516Swpaul /* 48640516Swpaul * Turn on data output. 48740516Swpaul */ 48840516Swpaul MII_SET(RL_MII_DIR); 48940516Swpaul 49040516Swpaul rl_mii_sync(sc); 49140516Swpaul 49240516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 49340516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 49440516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 49540516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 49640516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 49740516Swpaul rl_mii_send(sc, frame->mii_data, 16); 49840516Swpaul 49940516Swpaul /* Idle bit. */ 50040516Swpaul MII_SET(RL_MII_CLK); 50140516Swpaul DELAY(1); 50240516Swpaul MII_CLR(RL_MII_CLK); 50340516Swpaul DELAY(1); 50440516Swpaul 50540516Swpaul /* 50640516Swpaul * Turn off xmit. 50740516Swpaul */ 50840516Swpaul MII_CLR(RL_MII_DIR); 50940516Swpaul 51040516Swpaul splx(s); 51140516Swpaul 51240516Swpaul return(0); 51340516Swpaul} 51440516Swpaul 51540516Swpaulstatic u_int16_t rl_phy_readreg(sc, reg) 51640516Swpaul struct rl_softc *sc; 51740516Swpaul int reg; 51840516Swpaul{ 51940516Swpaul struct rl_mii_frame frame; 52040516Swpaul u_int16_t rval = 0; 52140516Swpaul u_int16_t rl8139_reg = 0; 52240516Swpaul 52340516Swpaul if (sc->rl_type == RL_8139) { 52440516Swpaul switch(reg) { 52540516Swpaul case PHY_BMCR: 52640516Swpaul rl8139_reg = RL_BMCR; 52740516Swpaul break; 52840516Swpaul case PHY_BMSR: 52940516Swpaul rl8139_reg = RL_BMSR; 53040516Swpaul break; 53140516Swpaul case PHY_ANAR: 53240516Swpaul rl8139_reg = RL_ANAR; 53340516Swpaul break; 53440516Swpaul case PHY_LPAR: 53540516Swpaul rl8139_reg = RL_LPAR; 53640516Swpaul break; 53740516Swpaul default: 53840516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 53940516Swpaul return(0); 54040516Swpaul } 54140516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 54240516Swpaul return(rval); 54340516Swpaul } 54440516Swpaul 54540516Swpaul bzero((char *)&frame, sizeof(frame)); 54640516Swpaul 54740516Swpaul frame.mii_phyaddr = sc->rl_phy_addr; 54840516Swpaul frame.mii_regaddr = reg; 54940516Swpaul rl_mii_readreg(sc, &frame); 55040516Swpaul 55140516Swpaul return(frame.mii_data); 55240516Swpaul} 55340516Swpaul 55440516Swpaulstatic void rl_phy_writereg(sc, reg, data) 55540516Swpaul struct rl_softc *sc; 55640516Swpaul u_int16_t reg; 55740516Swpaul u_int16_t data; 55840516Swpaul{ 55940516Swpaul struct rl_mii_frame frame; 56040516Swpaul u_int16_t rl8139_reg = 0; 56140516Swpaul 56240516Swpaul if (sc->rl_type == RL_8139) { 56340516Swpaul switch(reg) { 56440516Swpaul case PHY_BMCR: 56540516Swpaul rl8139_reg = RL_BMCR; 56640516Swpaul break; 56740516Swpaul case PHY_BMSR: 56840516Swpaul rl8139_reg = RL_BMSR; 56940516Swpaul break; 57040516Swpaul case PHY_ANAR: 57140516Swpaul rl8139_reg = RL_ANAR; 57240516Swpaul break; 57340516Swpaul case PHY_LPAR: 57440516Swpaul rl8139_reg = RL_LPAR; 57540516Swpaul break; 57640516Swpaul default: 57740516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 57840516Swpaul return; 57940516Swpaul } 58040516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 58141273Swpaul return; 58240516Swpaul } 58340516Swpaul 58440516Swpaul bzero((char *)&frame, sizeof(frame)); 58540516Swpaul 58640516Swpaul frame.mii_phyaddr = sc->rl_phy_addr; 58740516Swpaul frame.mii_regaddr = reg; 58840516Swpaul frame.mii_data = data; 58940516Swpaul 59040516Swpaul rl_mii_writereg(sc, &frame); 59140516Swpaul 59240516Swpaul return; 59340516Swpaul} 59440516Swpaul 59540516Swpaul/* 59640516Swpaul * Calculate CRC of a multicast group address, return the lower 6 bits. 59740516Swpaul */ 59840516Swpaulstatic u_int8_t rl_calchash(addr) 59940516Swpaul u_int8_t *addr; 60040516Swpaul{ 60140516Swpaul u_int32_t crc, carry; 60240516Swpaul int i, j; 60340516Swpaul u_int8_t c; 60440516Swpaul 60540516Swpaul /* Compute CRC for the address value. */ 60640516Swpaul crc = 0xFFFFFFFF; /* initial value */ 60740516Swpaul 60840516Swpaul for (i = 0; i < 6; i++) { 60940516Swpaul c = *(addr + i); 61040516Swpaul for (j = 0; j < 8; j++) { 61140516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 61240516Swpaul crc <<= 1; 61340516Swpaul c >>= 1; 61440516Swpaul if (carry) 61540516Swpaul crc = (crc ^ 0x04c11db6) | carry; 61640516Swpaul } 61740516Swpaul } 61840516Swpaul 61940516Swpaul /* return the filter bit position */ 62040516Swpaul return(crc & 0x0000003F); 62140516Swpaul} 62240516Swpaul 62340516Swpaul/* 62440516Swpaul * Program the 64-bit multicast hash filter. 62540516Swpaul */ 62640516Swpaulstatic void rl_setmulti(sc) 62740516Swpaul struct rl_softc *sc; 62840516Swpaul{ 62940516Swpaul struct ifnet *ifp; 63040516Swpaul int h = 0; 63140516Swpaul u_int32_t hashes[2] = { 0, 0 }; 63240516Swpaul struct ifmultiaddr *ifma; 63340516Swpaul u_int32_t rxfilt; 63440516Swpaul int mcnt = 0; 63540516Swpaul 63640516Swpaul ifp = &sc->arpcom.ac_if; 63740516Swpaul 63840516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 63940516Swpaul 64040516Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 64140516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 64240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 64340516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 64440516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 64540516Swpaul return; 64640516Swpaul } 64740516Swpaul 64840516Swpaul /* first, zot all the existing hash bits */ 64940516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 65040516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 65140516Swpaul 65240516Swpaul /* now program new ones */ 65340516Swpaul for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 65440516Swpaul ifma = ifma->ifma_link.le_next) { 65540516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65640516Swpaul continue; 65740516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65840516Swpaul if (h < 32) 65940516Swpaul hashes[0] |= (1 << h); 66040516Swpaul else 66140516Swpaul hashes[1] |= (1 << (h - 32)); 66240516Swpaul mcnt++; 66340516Swpaul } 66440516Swpaul 66540516Swpaul if (mcnt) 66640516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 66740516Swpaul else 66840516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 66940516Swpaul 67040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 67140516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 67240516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 67340516Swpaul 67440516Swpaul return; 67540516Swpaul} 67640516Swpaul 67740516Swpaul/* 67840516Swpaul * Initiate an autonegotiation session. 67940516Swpaul */ 68040516Swpaulstatic void rl_autoneg_xmit(sc) 68140516Swpaul struct rl_softc *sc; 68240516Swpaul{ 68340516Swpaul u_int16_t phy_sts; 68440516Swpaul 68540516Swpaul rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 68640516Swpaul DELAY(500); 68740516Swpaul while(rl_phy_readreg(sc, PHY_BMCR) 68840516Swpaul & PHY_BMCR_RESET); 68940516Swpaul 69040516Swpaul phy_sts = rl_phy_readreg(sc, PHY_BMCR); 69140516Swpaul phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 69240516Swpaul rl_phy_writereg(sc, PHY_BMCR, phy_sts); 69340516Swpaul 69440516Swpaul return; 69540516Swpaul} 69640516Swpaul 69740516Swpaul/* 69840516Swpaul * Invoke autonegotiation on a PHY. Also used with the 8139 internal 69940516Swpaul * transceiver. 70040516Swpaul */ 70140516Swpaulstatic void rl_autoneg_mii(sc, flag, verbose) 70240516Swpaul struct rl_softc *sc; 70340516Swpaul int flag; 70440516Swpaul int verbose; 70540516Swpaul{ 70640516Swpaul u_int16_t phy_sts = 0, media, advert, ability; 70740516Swpaul struct ifnet *ifp; 70840516Swpaul struct ifmedia *ifm; 70940516Swpaul 71040516Swpaul ifm = &sc->ifmedia; 71140516Swpaul ifp = &sc->arpcom.ac_if; 71240516Swpaul 71340516Swpaul /* 71440516Swpaul * The 100baseT4 PHY sometimes has the 'autoneg supported' 71540516Swpaul * bit cleared in the status register, but has the 'autoneg enabled' 71640516Swpaul * bit set in the control register. This is a contradiction, and 71740516Swpaul * I'm not sure how to handle it. If you want to force an attempt 71840516Swpaul * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 71940516Swpaul * and see what happens. 72040516Swpaul */ 72140516Swpaul#ifndef FORCE_AUTONEG_TFOUR 72240516Swpaul /* 72340516Swpaul * First, see if autoneg is supported. If not, there's 72440516Swpaul * no point in continuing. 72540516Swpaul */ 72640516Swpaul phy_sts = rl_phy_readreg(sc, PHY_BMSR); 72740516Swpaul if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 72840516Swpaul if (verbose) 72940516Swpaul printf("rl%d: autonegotiation not supported\n", 73040516Swpaul sc->rl_unit); 73140516Swpaul return; 73240516Swpaul } 73340516Swpaul#endif 73440516Swpaul 73540516Swpaul switch (flag) { 73640516Swpaul case RL_FLAG_FORCEDELAY: 73740516Swpaul /* 73840516Swpaul * XXX Never use this option anywhere but in the probe 73940516Swpaul * routine: making the kernel stop dead in its tracks 74040516Swpaul * for three whole seconds after we've gone multi-user 74140516Swpaul * is really bad manners. 74240516Swpaul */ 74340516Swpaul rl_autoneg_xmit(sc); 74440516Swpaul DELAY(5000000); 74540516Swpaul break; 74640516Swpaul case RL_FLAG_SCHEDDELAY: 74740516Swpaul /* 74840516Swpaul * Wait for the transmitter to go idle before starting 74940516Swpaul * an autoneg session, otherwise rl_start() may clobber 75040516Swpaul * our timeout, and we don't want to allow transmission 75140516Swpaul * during an autoneg session since that can screw it up. 75240516Swpaul */ 75340516Swpaul if (sc->rl_cdata.rl_tx_cnt) { 75440516Swpaul sc->rl_want_auto = 1; 75540516Swpaul return; 75640516Swpaul } 75740516Swpaul rl_autoneg_xmit(sc); 75840516Swpaul ifp->if_timer = 5; 75940516Swpaul sc->rl_autoneg = 1; 76040516Swpaul sc->rl_want_auto = 0; 76140516Swpaul return; 76240516Swpaul break; 76340516Swpaul case RL_FLAG_DELAYTIMEO: 76440516Swpaul ifp->if_timer = 0; 76540516Swpaul sc->rl_autoneg = 0; 76640516Swpaul break; 76740516Swpaul default: 76840516Swpaul printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag); 76940516Swpaul return; 77040516Swpaul } 77140516Swpaul 77240516Swpaul if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 77340516Swpaul if (verbose) 77440516Swpaul printf("rl%d: autoneg complete, ", sc->rl_unit); 77540516Swpaul phy_sts = rl_phy_readreg(sc, PHY_BMSR); 77640516Swpaul } else { 77740516Swpaul if (verbose) 77840516Swpaul printf("rl%d: autoneg not complete, ", sc->rl_unit); 77940516Swpaul } 78040516Swpaul 78140516Swpaul media = rl_phy_readreg(sc, PHY_BMCR); 78240516Swpaul 78340516Swpaul /* Link is good. Report modes and set duplex mode. */ 78440516Swpaul if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 78540516Swpaul if (verbose) 78640516Swpaul printf("link status good "); 78740516Swpaul advert = rl_phy_readreg(sc, PHY_ANAR); 78840516Swpaul ability = rl_phy_readreg(sc, PHY_LPAR); 78940516Swpaul 79040516Swpaul if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 79140516Swpaul ifm->ifm_media = IFM_ETHER|IFM_100_T4; 79240516Swpaul media |= PHY_BMCR_SPEEDSEL; 79340516Swpaul media &= ~PHY_BMCR_DUPLEX; 79440516Swpaul printf("(100baseT4)\n"); 79540516Swpaul } else if (advert & PHY_ANAR_100BTXFULL && 79640516Swpaul ability & PHY_ANAR_100BTXFULL) { 79740516Swpaul ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 79840516Swpaul media |= PHY_BMCR_SPEEDSEL; 79940516Swpaul media |= PHY_BMCR_DUPLEX; 80040516Swpaul printf("(full-duplex, 100Mbps)\n"); 80140516Swpaul } else if (advert & PHY_ANAR_100BTXHALF && 80240516Swpaul ability & PHY_ANAR_100BTXHALF) { 80340516Swpaul ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 80440516Swpaul media |= PHY_BMCR_SPEEDSEL; 80540516Swpaul media &= ~PHY_BMCR_DUPLEX; 80640516Swpaul printf("(half-duplex, 100Mbps)\n"); 80740516Swpaul } else if (advert & PHY_ANAR_10BTFULL && 80840516Swpaul ability & PHY_ANAR_10BTFULL) { 80940516Swpaul ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 81040516Swpaul media &= ~PHY_BMCR_SPEEDSEL; 81140516Swpaul media |= PHY_BMCR_DUPLEX; 81240516Swpaul printf("(full-duplex, 10Mbps)\n"); 81340516Swpaul } else if (advert & PHY_ANAR_10BTHALF && 81440516Swpaul ability & PHY_ANAR_10BTHALF) { 81540516Swpaul ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 81640516Swpaul media &= ~PHY_BMCR_SPEEDSEL; 81740516Swpaul media &= ~PHY_BMCR_DUPLEX; 81840516Swpaul printf("(half-duplex, 10Mbps)\n"); 81940516Swpaul } else { 82040516Swpaul ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 82140516Swpaul media &= ~PHY_BMCR_SPEEDSEL; 82240516Swpaul media &= ~PHY_BMCR_DUPLEX; 82340516Swpaul printf("(unknown mode! forcing half-duplex, 10Mbps)\n"); 82440516Swpaul } 82540516Swpaul 82640516Swpaul /* Set ASIC's duplex mode to match the PHY. */ 82740516Swpaul rl_phy_writereg(sc, PHY_BMCR, media); 82840516Swpaul } else { 82940516Swpaul if (verbose) 83040516Swpaul printf("no carrier\n"); 83140516Swpaul } 83240516Swpaul 83340516Swpaul rl_init(sc); 83440516Swpaul 83540516Swpaul if (sc->rl_tx_pend) { 83640516Swpaul sc->rl_autoneg = 0; 83740516Swpaul sc->rl_tx_pend = 0; 83840516Swpaul rl_start(ifp); 83940516Swpaul } 84040516Swpaul 84140516Swpaul return; 84240516Swpaul} 84340516Swpaul 84440516Swpaulstatic void rl_getmode_mii(sc) 84540516Swpaul struct rl_softc *sc; 84640516Swpaul{ 84740516Swpaul u_int16_t bmsr; 84840516Swpaul struct ifnet *ifp; 84940516Swpaul 85040516Swpaul ifp = &sc->arpcom.ac_if; 85140516Swpaul 85240516Swpaul bmsr = rl_phy_readreg(sc, PHY_BMSR); 85340516Swpaul if (bootverbose) 85440516Swpaul printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr); 85540516Swpaul 85640516Swpaul /* fallback */ 85740516Swpaul sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 85840516Swpaul 85940516Swpaul if (bmsr & PHY_BMSR_10BTHALF) { 86040516Swpaul if (bootverbose) 86140516Swpaul printf("rl%d: 10Mbps half-duplex mode supported\n", 86240516Swpaul sc->rl_unit); 86340516Swpaul ifmedia_add(&sc->ifmedia, 86440516Swpaul IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 86540516Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 86640516Swpaul } 86740516Swpaul 86840516Swpaul if (bmsr & PHY_BMSR_10BTFULL) { 86940516Swpaul if (bootverbose) 87040516Swpaul printf("rl%d: 10Mbps full-duplex mode supported\n", 87140516Swpaul sc->rl_unit); 87240516Swpaul ifmedia_add(&sc->ifmedia, 87340516Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 87440516Swpaul sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 87540516Swpaul } 87640516Swpaul 87740516Swpaul if (bmsr & PHY_BMSR_100BTXHALF) { 87840516Swpaul if (bootverbose) 87940516Swpaul printf("rl%d: 100Mbps half-duplex mode supported\n", 88040516Swpaul sc->rl_unit); 88140516Swpaul ifp->if_baudrate = 100000000; 88240516Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 88340516Swpaul ifmedia_add(&sc->ifmedia, 88440516Swpaul IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 88540516Swpaul sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 88640516Swpaul } 88740516Swpaul 88840516Swpaul if (bmsr & PHY_BMSR_100BTXFULL) { 88940516Swpaul if (bootverbose) 89040516Swpaul printf("rl%d: 100Mbps full-duplex mode supported\n", 89140516Swpaul sc->rl_unit); 89240516Swpaul ifp->if_baudrate = 100000000; 89340516Swpaul ifmedia_add(&sc->ifmedia, 89440516Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 89540516Swpaul sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 89640516Swpaul } 89740516Swpaul 89840516Swpaul /* Some also support 100BaseT4. */ 89940516Swpaul if (bmsr & PHY_BMSR_100BT4) { 90040516Swpaul if (bootverbose) 90140516Swpaul printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit); 90240516Swpaul ifp->if_baudrate = 100000000; 90340516Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 90440516Swpaul sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 90540516Swpaul#ifdef FORCE_AUTONEG_TFOUR 90640516Swpaul if (bootverbose) 90740516Swpaul printf("rl%d: forcing on autoneg support for BT4\n", 90840516Swpaul sc->rl_unit); 90940516Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 91040516Swpaul sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 91140516Swpaul#endif 91240516Swpaul } 91340516Swpaul 91440516Swpaul if (bmsr & PHY_BMSR_CANAUTONEG) { 91540516Swpaul if (bootverbose) 91640516Swpaul printf("rl%d: autoneg supported\n", sc->rl_unit); 91740516Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 91840516Swpaul sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 91940516Swpaul } 92040516Swpaul 92140516Swpaul return; 92240516Swpaul} 92340516Swpaul 92440516Swpaul/* 92540516Swpaul * Set speed and duplex mode. 92640516Swpaul */ 92740516Swpaulstatic void rl_setmode_mii(sc, media) 92840516Swpaul struct rl_softc *sc; 92940516Swpaul int media; 93040516Swpaul{ 93140516Swpaul u_int16_t bmcr; 93240516Swpaul 93340516Swpaul printf("rl%d: selecting MII, ", sc->rl_unit); 93440516Swpaul 93540516Swpaul bmcr = rl_phy_readreg(sc, PHY_BMCR); 93640516Swpaul 93740516Swpaul bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 93840516Swpaul PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 93940516Swpaul 94040516Swpaul if (IFM_SUBTYPE(media) == IFM_100_T4) { 94140516Swpaul printf("100Mbps/T4, half-duplex\n"); 94240516Swpaul bmcr |= PHY_BMCR_SPEEDSEL; 94340516Swpaul bmcr &= ~PHY_BMCR_DUPLEX; 94440516Swpaul } 94540516Swpaul 94640516Swpaul if (IFM_SUBTYPE(media) == IFM_100_TX) { 94740516Swpaul printf("100Mbps, "); 94840516Swpaul bmcr |= PHY_BMCR_SPEEDSEL; 94940516Swpaul } 95040516Swpaul 95140516Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 95240516Swpaul printf("10Mbps, "); 95340516Swpaul bmcr &= ~PHY_BMCR_SPEEDSEL; 95440516Swpaul } 95540516Swpaul 95640516Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 95740516Swpaul printf("full duplex\n"); 95840516Swpaul bmcr |= PHY_BMCR_DUPLEX; 95940516Swpaul } else { 96040516Swpaul printf("half duplex\n"); 96140516Swpaul bmcr &= ~PHY_BMCR_DUPLEX; 96240516Swpaul } 96340516Swpaul 96440516Swpaul rl_phy_writereg(sc, PHY_BMCR, bmcr); 96540516Swpaul 96640516Swpaul return; 96740516Swpaul} 96840516Swpaul 96940516Swpaulstatic void rl_reset(sc) 97040516Swpaul struct rl_softc *sc; 97140516Swpaul{ 97240516Swpaul register int i; 97340516Swpaul 97440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 97540516Swpaul 97640516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 97740516Swpaul DELAY(10); 97840516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 97940516Swpaul break; 98040516Swpaul } 98140516Swpaul if (i == RL_TIMEOUT) 98240516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 98340516Swpaul 98440516Swpaul return; 98540516Swpaul} 98640516Swpaul 98740516Swpaul/* 98840516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 98940516Swpaul * IDs against our list and return a device name if we find a match. 99040516Swpaul */ 99140516Swpaulstatic char * 99240516Swpaulrl_probe(config_id, device_id) 99340516Swpaul pcici_t config_id; 99440516Swpaul pcidi_t device_id; 99540516Swpaul{ 99640516Swpaul struct rl_type *t; 99740516Swpaul 99840516Swpaul t = rl_devs; 99940516Swpaul 100040516Swpaul while(t->rl_name != NULL) { 100140516Swpaul if ((device_id & 0xFFFF) == t->rl_vid && 100240516Swpaul ((device_id >> 16) & 0xFFFF) == t->rl_did) { 100340516Swpaul return(t->rl_name); 100440516Swpaul } 100540516Swpaul t++; 100640516Swpaul } 100740516Swpaul 100840516Swpaul return(NULL); 100940516Swpaul} 101040516Swpaul 101140516Swpaul/* 101240516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 101340516Swpaul * setup and ethernet/BPF attach. 101440516Swpaul */ 101540516Swpaulstatic void 101640516Swpaulrl_attach(config_id, unit) 101740516Swpaul pcici_t config_id; 101840516Swpaul int unit; 101940516Swpaul{ 102040516Swpaul int s, i; 102140516Swpaul#ifndef RL_USEIOSPACE 102240516Swpaul vm_offset_t pbase, vbase; 102340516Swpaul#endif 102440516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 102540516Swpaul u_int32_t command; 102640516Swpaul struct rl_softc *sc; 102740516Swpaul struct ifnet *ifp; 102840516Swpaul int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 102940516Swpaul struct rl_type *p; 103040516Swpaul u_int16_t phy_vid, phy_did, phy_sts; 103140516Swpaul u_int16_t rl_did = 0; 103240516Swpaul 103340516Swpaul s = splimp(); 103440516Swpaul 103540516Swpaul sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT); 103640516Swpaul if (sc == NULL) { 103740516Swpaul printf("rl%d: no memory for softc struct!\n", unit); 103840516Swpaul return; 103940516Swpaul } 104040516Swpaul bzero(sc, sizeof(struct rl_softc)); 104140516Swpaul 104240516Swpaul /* 104340516Swpaul * Handle power management nonsense. 104440516Swpaul */ 104540516Swpaul 104640516Swpaul command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF; 104740516Swpaul if (command == 0x01) { 104840516Swpaul 104940516Swpaul command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL); 105040516Swpaul if (command & RL_PSTATE_MASK) { 105140516Swpaul u_int32_t iobase, membase, irq; 105240516Swpaul 105340516Swpaul /* Save important PCI config data. */ 105440516Swpaul iobase = pci_conf_read(config_id, RL_PCI_LOIO); 105540516Swpaul membase = pci_conf_read(config_id, RL_PCI_LOMEM); 105640516Swpaul irq = pci_conf_read(config_id, RL_PCI_INTLINE); 105740516Swpaul 105840516Swpaul /* Reset the power state. */ 105940516Swpaul printf("rl%d: chip is is in D%d power mode " 106040516Swpaul "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 106140516Swpaul command &= 0xFFFFFFFC; 106240516Swpaul pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command); 106340516Swpaul 106440516Swpaul /* Restore PCI config data. */ 106540516Swpaul pci_conf_write(config_id, RL_PCI_LOIO, iobase); 106640516Swpaul pci_conf_write(config_id, RL_PCI_LOMEM, membase); 106740516Swpaul pci_conf_write(config_id, RL_PCI_INTLINE, irq); 106840516Swpaul } 106940516Swpaul } 107040516Swpaul 107140516Swpaul /* 107240516Swpaul * Map control/status registers. 107340516Swpaul */ 107440516Swpaul command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 107540516Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 107640516Swpaul pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 107740516Swpaul command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 107840516Swpaul 107940516Swpaul#ifdef RL_USEIOSPACE 108040516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 108140516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 108240516Swpaul free(sc, M_DEVBUF); 108340516Swpaul goto fail; 108440516Swpaul } 108540516Swpaul 108640516Swpaul sc->iobase = pci_conf_read(config_id, RL_PCI_LOIO) & 0xFFFFFFFC; 108740516Swpaul#else 108840516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 108940516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 109040516Swpaul goto fail; 109140516Swpaul } 109240516Swpaul 109340516Swpaul if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) { 109440516Swpaul printf ("rl%d: couldn't map memory\n", unit); 109540516Swpaul goto fail; 109640516Swpaul } 109740516Swpaul sc->csr = (volatile caddr_t)vbase; 109840516Swpaul#endif 109940516Swpaul 110040516Swpaul /* Allocate interrupt */ 110140516Swpaul if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) { 110240516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 110340516Swpaul goto fail; 110440516Swpaul } 110540516Swpaul 110640516Swpaul /* Reset the adapter. */ 110740516Swpaul rl_reset(sc); 110840516Swpaul 110940516Swpaul /* 111040516Swpaul * Get station address from the EEPROM. 111140516Swpaul */ 111240516Swpaul rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 111340516Swpaul 111440516Swpaul /* 111540516Swpaul * A RealTek chip was detected. Inform the world. 111640516Swpaul */ 111740516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 111840516Swpaul 111940516Swpaul sc->rl_unit = unit; 112040516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 112140516Swpaul 112240516Swpaul /* 112340516Swpaul * Now read the exact device type from the EEPROM to find 112440516Swpaul * out if it's an 8129 or 8139. 112540516Swpaul */ 112640516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 112740516Swpaul 112840516Swpaul if (rl_did == RT_DEVICEID_8139) 112940516Swpaul sc->rl_type = RL_8139; 113040516Swpaul else if (rl_did == RT_DEVICEID_8129) 113140516Swpaul sc->rl_type = RL_8129; 113240516Swpaul else { 113340516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 113440516Swpaul free(sc, M_DEVBUF); 113540516Swpaul goto fail; 113640516Swpaul } 113740516Swpaul 113840516Swpaul sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF, 113940516Swpaul M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 114040516Swpaul 114140516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 114240516Swpaul free(sc, M_DEVBUF); 114340516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 114440516Swpaul goto fail; 114540516Swpaul } 114640516Swpaul 114740516Swpaul ifp = &sc->arpcom.ac_if; 114840516Swpaul ifp->if_softc = sc; 114940516Swpaul ifp->if_unit = unit; 115040516Swpaul ifp->if_name = "rl"; 115140516Swpaul ifp->if_mtu = ETHERMTU; 115240516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 115340516Swpaul ifp->if_ioctl = rl_ioctl; 115440516Swpaul ifp->if_output = ether_output; 115540516Swpaul ifp->if_start = rl_start; 115640516Swpaul ifp->if_watchdog = rl_watchdog; 115740516Swpaul ifp->if_init = rl_init; 115840516Swpaul ifp->if_baudrate = 10000000; 115940516Swpaul 116040516Swpaul if (sc->rl_type == RL_8129) { 116140516Swpaul if (bootverbose) 116240516Swpaul printf("rl%d: probing for a PHY\n", sc->rl_unit); 116340516Swpaul for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) { 116440516Swpaul if (bootverbose) 116540516Swpaul printf("rl%d: checking address: %d\n", 116640516Swpaul sc->rl_unit, i); 116740516Swpaul sc->rl_phy_addr = i; 116840516Swpaul rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 116940516Swpaul DELAY(500); 117040516Swpaul while(rl_phy_readreg(sc, PHY_BMCR) 117140516Swpaul & PHY_BMCR_RESET); 117240516Swpaul if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR))) 117340516Swpaul break; 117440516Swpaul } 117540516Swpaul if (phy_sts) { 117640516Swpaul phy_vid = rl_phy_readreg(sc, PHY_VENID); 117740516Swpaul phy_did = rl_phy_readreg(sc, PHY_DEVID); 117840516Swpaul if (bootverbose) 117940516Swpaul printf("rl%d: found PHY at address %d, ", 118040516Swpaul sc->rl_unit, sc->rl_phy_addr); 118140516Swpaul if (bootverbose) 118240516Swpaul printf("vendor id: %x device id: %x\n", 118340516Swpaul phy_vid, phy_did); 118440516Swpaul p = rl_phys; 118540516Swpaul while(p->rl_vid) { 118640516Swpaul if (phy_vid == p->rl_vid && 118740516Swpaul (phy_did | 0x000F) == p->rl_did) { 118840516Swpaul sc->rl_pinfo = p; 118940516Swpaul break; 119040516Swpaul } 119140516Swpaul p++; 119240516Swpaul } 119340516Swpaul if (sc->rl_pinfo == NULL) 119440516Swpaul sc->rl_pinfo = &rl_phys[PHY_UNKNOWN]; 119540516Swpaul if (bootverbose) 119640516Swpaul printf("rl%d: PHY type: %s\n", 119740516Swpaul sc->rl_unit, sc->rl_pinfo->rl_name); 119840516Swpaul } else { 119940516Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 120040516Swpaul } 120140516Swpaul } 120240516Swpaul 120340516Swpaul /* 120440516Swpaul * Do ifmedia setup. 120540516Swpaul */ 120640516Swpaul ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts); 120740516Swpaul 120840516Swpaul rl_getmode_mii(sc); 120940516Swpaul 121040516Swpaul /* Choose a default media. */ 121140516Swpaul media = IFM_ETHER|IFM_AUTO; 121240516Swpaul ifmedia_set(&sc->ifmedia, media); 121340516Swpaul 121440516Swpaul rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1); 121540516Swpaul 121640516Swpaul /* 121740516Swpaul * Call MI attach routines. 121840516Swpaul */ 121940516Swpaul if_attach(ifp); 122040516Swpaul ether_ifattach(ifp); 122140516Swpaul 122240516Swpaul#if NBPFILTER > 0 122340516Swpaul bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 122440516Swpaul#endif 122540516Swpaul at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC); 122640516Swpaul 122740516Swpaulfail: 122840516Swpaul splx(s); 122940516Swpaul return; 123040516Swpaul} 123140516Swpaul 123240516Swpaul/* 123340516Swpaul * Initialize the transmit descriptors. 123440516Swpaul */ 123540516Swpaulstatic int rl_list_tx_init(sc) 123640516Swpaul struct rl_softc *sc; 123740516Swpaul{ 123840516Swpaul struct rl_chain_data *cd; 123940516Swpaul int i; 124040516Swpaul 124140516Swpaul cd = &sc->rl_cdata; 124240516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 124340516Swpaul cd->rl_tx_chain[i].rl_desc = i * 4; 124440516Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + cd->rl_tx_chain[i].rl_desc, 0); 124540516Swpaul CSR_WRITE_4(sc, RL_TXSTAT0 + cd->rl_tx_chain[i].rl_desc, 0); 124640516Swpaul if (i == (RL_TX_LIST_CNT - 1)) 124740516Swpaul cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[0]; 124840516Swpaul else 124940516Swpaul cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[i + 1]; 125040516Swpaul } 125140516Swpaul 125240516Swpaul sc->rl_cdata.rl_tx_cnt = 0; 125340516Swpaul cd->rl_tx_cur = cd->rl_tx_free = &cd->rl_tx_chain[0]; 125440516Swpaul 125540516Swpaul return(0); 125640516Swpaul} 125740516Swpaul 125840516Swpaul/* 125940516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 126040516Swpaul * the higher level protocols. 126140516Swpaul * 126240516Swpaul * You know there's something wrong with a PCI bus-master chip design 126340516Swpaul * when you have to use m_devget(). 126440516Swpaul * 126540516Swpaul * The receive operation is badly documented in the datasheet, so I'll 126640516Swpaul * attempt to document it here. The driver provides a buffer area and 126740516Swpaul * places its base address in the RX buffer start address register. 126840516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 126940516Swpaul * is preceeded by a 32-bit RX status word which specifies the length 127040516Swpaul * of the frame and certain other status bits. Each frame (starting with 127140516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 127240516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 127340516Swpaul * the 'rx status register' mentioned in the datasheet. 127440516Swpaul */ 127540516Swpaulstatic void rl_rxeof(sc) 127640516Swpaul struct rl_softc *sc; 127740516Swpaul{ 127840516Swpaul struct ether_header *eh; 127940516Swpaul struct mbuf *m; 128040516Swpaul struct ifnet *ifp; 128140516Swpaul int total_len = 0; 128240516Swpaul u_int32_t rxstat; 128340516Swpaul caddr_t rxbufpos; 128440516Swpaul int wrap = 0; 128540516Swpaul u_int16_t cur_rx; 128640516Swpaul u_int16_t limit; 128740516Swpaul u_int16_t rx_bytes = 0, max_bytes; 128840516Swpaul 128940516Swpaul ifp = &sc->arpcom.ac_if; 129040516Swpaul 129140516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 129240516Swpaul 129340516Swpaul /* Do not try to read past this point. */ 129440516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 129540516Swpaul 129640516Swpaul if (limit < cur_rx) 129740516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 129840516Swpaul else 129940516Swpaul max_bytes = limit - cur_rx; 130040516Swpaul 130140516Swpaul while((CSR_READ_1(sc, RL_COMMAND) & 1) == 0) { 130240516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 130340516Swpaul rxstat = *(u_int32_t *)rxbufpos; 130440516Swpaul 130540516Swpaul /* 130640516Swpaul * Here's a totally undocumented fact for you. When the 130740516Swpaul * RealTek chip is in the process of copying a packet into 130840516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 130940516Swpaul * packet header with this value, you need to stop. The 131040516Swpaul * datasheet makes absolutely no mention of this and 131140516Swpaul * RealTek should be shot for this. 131240516Swpaul */ 131340516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 131440516Swpaul break; 131540516Swpaul 131640516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 131740516Swpaul ifp->if_ierrors++; 131840516Swpaul if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 131940516Swpaul RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 132040516Swpaul RL_RXSTAT_ALIGNERR)) { 132140516Swpaul CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 132240516Swpaul CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 132340516Swpaul RL_CMD_RX_ENB); 132440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 132540516Swpaul CSR_WRITE_4(sc, RL_RXADDR, 132640516Swpaul vtophys(sc->rl_cdata.rl_rx_buf)); 132740516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 132840516Swpaul cur_rx = 0; 132940516Swpaul } 133040516Swpaul break; 133140516Swpaul } 133240516Swpaul 133340516Swpaul /* No errors; receive the packet. */ 133440516Swpaul total_len = rxstat >> 16; 133540516Swpaul rx_bytes += total_len + 4; 133640516Swpaul 133740516Swpaul /* 133840516Swpaul * Avoid trying to read more bytes than we know 133940516Swpaul * the chip has prepared for us. 134040516Swpaul */ 134140516Swpaul if (rx_bytes > max_bytes) 134240516Swpaul break; 134340516Swpaul 134440516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 134540516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 134640516Swpaul 134740516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 134840516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 134940516Swpaul 135040516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 135140516Swpaul 135240516Swpaul if (total_len > wrap) { 135340516Swpaul m = m_devget(rxbufpos, wrap, 0, ifp, NULL); 135440516Swpaul if (m == NULL) { 135540516Swpaul ifp->if_ierrors++; 135640516Swpaul printf("rl%d: out of mbufs, tried to " 135740516Swpaul "copy %d bytes\n", sc->rl_unit, wrap); 135840516Swpaul } 135940516Swpaul else 136040516Swpaul m_copyback(m, wrap, total_len - wrap, 136140516Swpaul sc->rl_cdata.rl_rx_buf); 136240516Swpaul cur_rx = (total_len - wrap); 136340516Swpaul } else { 136440516Swpaul m = m_devget(rxbufpos, total_len, 0, ifp, NULL); 136540516Swpaul if (m == NULL) { 136640516Swpaul ifp->if_ierrors++; 136740516Swpaul printf("rl%d: out of mbufs, tried to " 136840516Swpaul "copy %d bytes\n", sc->rl_unit, total_len); 136940516Swpaul } 137040516Swpaul cur_rx += total_len + 4; 137140516Swpaul } 137240516Swpaul 137340516Swpaul /* 137440516Swpaul * Round up to 32-bit boundary. 137540516Swpaul */ 137640516Swpaul cur_rx = (cur_rx + 3) & ~3; 137740516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 137840516Swpaul 137940516Swpaul if (m == NULL) 138040516Swpaul continue; 138140516Swpaul 138240516Swpaul eh = mtod(m, struct ether_header *); 138340516Swpaul ifp->if_ipackets++; 138440516Swpaul 138540516Swpaul#if NBPFILTER > 0 138640516Swpaul /* 138740516Swpaul * Handle BPF listeners. Let the BPF user see the packet, but 138840516Swpaul * don't pass it up to the ether_input() layer unless it's 138940516Swpaul * a broadcast packet, multicast packet, matches our ethernet 139040516Swpaul * address or the interface is in promiscuous mode. 139140516Swpaul */ 139240516Swpaul if (ifp->if_bpf) { 139340516Swpaul bpf_mtap(ifp, m); 139440516Swpaul if (ifp->if_flags & IFF_PROMISC && 139540516Swpaul (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 139640516Swpaul ETHER_ADDR_LEN) && 139740516Swpaul (eh->ether_dhost[0] & 1) == 0)) { 139840516Swpaul m_freem(m); 139940516Swpaul continue; 140040516Swpaul } 140140516Swpaul } 140240516Swpaul#endif 140340516Swpaul /* Remove header from mbuf and pass it on. */ 140440516Swpaul m_adj(m, sizeof(struct ether_header)); 140540516Swpaul ether_input(ifp, eh, m); 140640516Swpaul } 140740516Swpaul 140840516Swpaul return; 140940516Swpaul} 141040516Swpaul 141140516Swpaul/* 141240516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 141340516Swpaul * the list buffers. 141440516Swpaul */ 141540516Swpaulstatic void rl_txeof(sc) 141640516Swpaul struct rl_softc *sc; 141740516Swpaul{ 141840516Swpaul struct rl_chain *cur_tx; 141940516Swpaul struct ifnet *ifp; 142040516Swpaul u_int32_t txstat; 142140516Swpaul 142240516Swpaul ifp = &sc->arpcom.ac_if; 142340516Swpaul 142440516Swpaul /* Clear the timeout timer. */ 142540516Swpaul ifp->if_timer = 0; 142640516Swpaul 142740516Swpaul /* 142840516Swpaul * Go through our tx list and free mbufs for those 142940516Swpaul * frames that have been uploaded. 143040516Swpaul */ 143140516Swpaul if (sc->rl_cdata.rl_tx_free == NULL) 143240516Swpaul return; 143340516Swpaul 143440516Swpaul while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) { 143540516Swpaul cur_tx = sc->rl_cdata.rl_tx_free; 143640516Swpaul txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc); 143740516Swpaul 143840516Swpaul if (!(txstat & RL_TXSTAT_TX_OK)) 143940516Swpaul break; 144040516Swpaul 144140516Swpaul if (txstat & RL_TXSTAT_COLLCNT) 144240516Swpaul ifp->if_collisions += 144340516Swpaul (txstat & RL_TXSTAT_COLLCNT) >> 24; 144440516Swpaul 144540516Swpaul sc->rl_cdata.rl_tx_free = cur_tx->rl_next; 144640516Swpaul 144740516Swpaul sc->rl_cdata.rl_tx_cnt--; 144840516Swpaul m_freem(cur_tx->rl_mbuf); 144940516Swpaul cur_tx->rl_mbuf = NULL; 145040516Swpaul ifp->if_opackets++; 145140516Swpaul } 145240516Swpaul 145340516Swpaul if (!sc->rl_cdata.rl_tx_cnt) { 145440516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 145540516Swpaul if (sc->rl_want_auto) 145640516Swpaul rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 145740516Swpaul } else { 145840516Swpaul if (ifp->if_snd.ifq_head != NULL) 145940516Swpaul rl_start(ifp); 146040516Swpaul } 146140516Swpaul 146240516Swpaul return; 146340516Swpaul} 146440516Swpaul 146540516Swpaul/* 146640516Swpaul * TX error handler. 146740516Swpaul */ 146840516Swpaulstatic void rl_txeoc(sc) 146940516Swpaul struct rl_softc *sc; 147040516Swpaul{ 147140516Swpaul u_int32_t txstat; 147240516Swpaul struct rl_chain *cur_tx; 147340516Swpaul struct ifnet *ifp; 147440516Swpaul 147540516Swpaul ifp = &sc->arpcom.ac_if; 147640516Swpaul 147740516Swpaul if (sc->rl_cdata.rl_tx_free == NULL) 147840516Swpaul return; 147940516Swpaul 148040516Swpaul while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) { 148140516Swpaul cur_tx = sc->rl_cdata.rl_tx_free; 148240516Swpaul txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc); 148340516Swpaul 148440516Swpaul if (!(txstat & RL_TXSTAT_OWN)) 148540516Swpaul break; 148640516Swpaul 148740516Swpaul if (!(txstat & RL_TXSTAT_TX_OK)) { 148840516Swpaul ifp->if_oerrors++; 148940516Swpaul if (txstat & RL_TXSTAT_COLLCNT) 149040516Swpaul ifp->if_collisions += 149140516Swpaul (txstat & RL_TXSTAT_COLLCNT) >> 24; 149240516Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc, 149340516Swpaul vtophys(mtod(cur_tx->rl_mbuf, caddr_t))); 149440516Swpaul CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc, 149540516Swpaul RL_TX_EARLYTHRESH | 149640516Swpaul cur_tx->rl_mbuf->m_pkthdr.len); 149740516Swpaul break; 149840516Swpaul } else { 149940516Swpaul if (txstat & RL_TXSTAT_COLLCNT) 150040516Swpaul ifp->if_collisions += 150140516Swpaul (txstat & RL_TXSTAT_COLLCNT) >> 24; 150240516Swpaul sc->rl_cdata.rl_tx_free = cur_tx->rl_next; 150340516Swpaul 150440516Swpaul sc->rl_cdata.rl_tx_cnt--; 150540516Swpaul m_freem(cur_tx->rl_mbuf); 150640516Swpaul cur_tx->rl_mbuf = NULL; 150740516Swpaul ifp->if_opackets++; 150840516Swpaul } 150940516Swpaul } 151040516Swpaul 151140516Swpaul return; 151240516Swpaul} 151340516Swpaul 151440516Swpaulstatic void rl_intr(arg) 151540516Swpaul void *arg; 151640516Swpaul{ 151740516Swpaul struct rl_softc *sc; 151840516Swpaul struct ifnet *ifp; 151940516Swpaul u_int16_t status; 152040516Swpaul 152140516Swpaul sc = arg; 152240516Swpaul ifp = &sc->arpcom.ac_if; 152340516Swpaul 152440516Swpaul /* Disable interrupts. */ 152540516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 152640516Swpaul 152740516Swpaul for (;;) { 152840516Swpaul 152940516Swpaul status = CSR_READ_2(sc, RL_ISR); 153040516Swpaul if (status) 153140516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 153240516Swpaul 153340516Swpaul if ((status & RL_INTRS) == 0) 153440516Swpaul break; 153540516Swpaul 153640516Swpaul if (status & RL_ISR_RX_OK) 153740516Swpaul rl_rxeof(sc); 153840516Swpaul 153940516Swpaul if (status & RL_ISR_RX_ERR) 154040516Swpaul rl_rxeof(sc); 154140516Swpaul 154240516Swpaul if (status & RL_ISR_TX_OK) 154340516Swpaul rl_txeof(sc); 154440516Swpaul 154540516Swpaul if (status & RL_ISR_TX_ERR) 154640516Swpaul rl_txeoc(sc); 154740516Swpaul 154840516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 154940516Swpaul rl_reset(sc); 155040516Swpaul rl_init(sc); 155140516Swpaul } 155240516Swpaul 155340516Swpaul } 155440516Swpaul 155540516Swpaul /* Re-enable interrupts. */ 155640516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 155740516Swpaul 155840516Swpaul if (ifp->if_snd.ifq_head != NULL) { 155940516Swpaul rl_start(ifp); 156040516Swpaul } 156140516Swpaul 156240516Swpaul return; 156340516Swpaul} 156440516Swpaul 156540516Swpaul/* 156640516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 156740516Swpaul * pointers to the fragment pointers. 156840516Swpaul */ 156940516Swpaulstatic int rl_encap(sc, c, m_head) 157040516Swpaul struct rl_softc *sc; 157140516Swpaul struct rl_chain *c; 157240516Swpaul struct mbuf *m_head; 157340516Swpaul{ 157440516Swpaul struct mbuf *m; 157541243Swpaul struct mbuf *m_new = NULL; 157640516Swpaul 157740516Swpaul /* 157840516Swpaul * There are two possible encapsulation mechanisms 157940516Swpaul * that we can use: an efficient one, and a very lossy 158040516Swpaul * one. The efficient one only happens very rarely, 158140516Swpaul * whereas the lossy one can and most likely will happen 158240516Swpaul * all the time. 158340516Swpaul * The efficient case happens if: 158440516Swpaul * - the packet fits in a single mbuf 158540516Swpaul * - the packet is 32-bit aligned within the mbuf data area 158640516Swpaul * In this case, we can DMA from the mbuf directly. 158740516Swpaul * The lossy case covers everything else. Bah. 158840516Swpaul */ 158940516Swpaul 159040516Swpaul m = m_head; 159140516Swpaul 159241243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 159341243Swpaul if (m_new == NULL) { 159441243Swpaul printf("rl%d: no memory for tx list", sc->rl_unit); 159541243Swpaul return(1); 159641243Swpaul } 159741243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 159841243Swpaul MCLGET(m_new, M_DONTWAIT); 159941243Swpaul if (!(m_new->m_flags & M_EXT)) { 160041243Swpaul m_freem(m_new); 160141243Swpaul printf("rl%d: no memory for tx list", 160241243Swpaul sc->rl_unit); 160340516Swpaul return(1); 160440516Swpaul } 160540516Swpaul } 160641243Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 160741243Swpaul mtod(m_new, caddr_t)); 160841243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 160941243Swpaul m_freem(m_head); 161041243Swpaul m_head = m_new; 161140516Swpaul 161240516Swpaul /* Pad frames to at least 60 bytes. */ 161341243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 161440516Swpaul m_head->m_pkthdr.len += 161540516Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 161641243Swpaul m_head->m_len = m_head->m_pkthdr.len; 161741243Swpaul } 161840516Swpaul 161940516Swpaul c->rl_mbuf = m_head; 162040516Swpaul 162140516Swpaul return(0); 162240516Swpaul} 162340516Swpaul 162440516Swpaul/* 162540516Swpaul * Main transmit routine. 162640516Swpaul */ 162740516Swpaul 162840516Swpaulstatic void rl_start(ifp) 162940516Swpaul struct ifnet *ifp; 163040516Swpaul{ 163140516Swpaul struct rl_softc *sc; 163240516Swpaul struct mbuf *m_head = NULL; 163340516Swpaul struct rl_chain *cur_tx = NULL; 163440516Swpaul 163540516Swpaul sc = ifp->if_softc; 163640516Swpaul 163740516Swpaul if (sc->rl_autoneg) { 163840516Swpaul sc->rl_tx_pend = 1; 163940516Swpaul return; 164040516Swpaul } 164140516Swpaul 164240516Swpaul /* 164340516Swpaul * Check for an available queue slot. If there are none, 164440516Swpaul * punt. 164540516Swpaul */ 164640516Swpaul if (sc->rl_cdata.rl_tx_cur->rl_mbuf != NULL) { 164740516Swpaul ifp->if_flags |= IFF_OACTIVE; 164840516Swpaul return; 164940516Swpaul } 165040516Swpaul 165140516Swpaul while(sc->rl_cdata.rl_tx_cur->rl_mbuf == NULL) { 165240516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 165340516Swpaul if (m_head == NULL) 165440516Swpaul break; 165540516Swpaul 165640516Swpaul 165740516Swpaul /* Pick a descriptor off the free list. */ 165840516Swpaul cur_tx = sc->rl_cdata.rl_tx_cur; 165940516Swpaul sc->rl_cdata.rl_tx_cur = cur_tx->rl_next; 166040516Swpaul sc->rl_cdata.rl_tx_cnt++; 166140516Swpaul 166240516Swpaul /* Pack the data into the descriptor. */ 166340516Swpaul rl_encap(sc, cur_tx, m_head); 166440516Swpaul 166540516Swpaul#if NBPFILTER > 0 166640516Swpaul /* 166740516Swpaul * If there's a BPF listener, bounce a copy of this frame 166840516Swpaul * to him. 166940516Swpaul */ 167040516Swpaul if (ifp->if_bpf) 167140516Swpaul bpf_mtap(ifp, cur_tx->rl_mbuf); 167240516Swpaul#endif 167340516Swpaul /* 167440516Swpaul * Transmit the frame. 167540516Swpaul */ 167640516Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc, 167740516Swpaul vtophys(mtod(cur_tx->rl_mbuf, caddr_t))); 167840516Swpaul CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc, 167940516Swpaul RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len); 168040516Swpaul } 168140516Swpaul 168240516Swpaul /* 168340516Swpaul * Set a timeout in case the chip goes out to lunch. 168440516Swpaul */ 168540516Swpaul ifp->if_timer = 5; 168640516Swpaul 168740516Swpaul return; 168840516Swpaul} 168940516Swpaul 169040516Swpaulstatic void rl_init(xsc) 169140516Swpaul void *xsc; 169240516Swpaul{ 169340516Swpaul struct rl_softc *sc = xsc; 169440516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 169540516Swpaul int s, i; 169640516Swpaul u_int32_t rxcfg = 0; 169740516Swpaul u_int16_t phy_bmcr = 0; 169840516Swpaul 169940516Swpaul if (sc->rl_autoneg) 170040516Swpaul return; 170140516Swpaul 170240516Swpaul s = splimp(); 170340516Swpaul 170440516Swpaul /* 170540516Swpaul * XXX Hack for the 8139: the built-in autoneg logic's state 170640516Swpaul * gets reset by rl_init() when we don't want it to. Try 170740516Swpaul * to preserve it. (For 8129 cards with real external PHYs, 170840516Swpaul * the BMCR register doesn't change, but this doesn't hurt.) 170940516Swpaul */ 171040516Swpaul if (sc->rl_type == RL_8139) 171140516Swpaul phy_bmcr = rl_phy_readreg(sc, PHY_BMCR); 171240516Swpaul 171340516Swpaul /* 171440516Swpaul * Cancel pending I/O and free all RX/TX buffers. 171540516Swpaul */ 171640516Swpaul rl_stop(sc); 171740516Swpaul 171840516Swpaul /* Init our MAC address */ 171940516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 172040516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 172140516Swpaul } 172240516Swpaul 172340516Swpaul /* Init the RX buffer pointer register. */ 172440516Swpaul CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 172540516Swpaul 172640516Swpaul /* Init TX descriptors. */ 172740516Swpaul rl_list_tx_init(sc); 172840516Swpaul 172940516Swpaul /* 173040516Swpaul * Enable transmit and receive. 173140516Swpaul */ 173240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 173340516Swpaul 173440516Swpaul /* 173540516Swpaul * Set the buffer size values. 173640516Swpaul */ 173740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 173840516Swpaul 173940516Swpaul /* Set the individual bit to receive frames for this host only. */ 174040516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 174140516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 174240516Swpaul 174340516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 174440516Swpaul if (ifp->if_flags & IFF_PROMISC) { 174540516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 174640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 174740516Swpaul } else { 174840516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 174940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 175040516Swpaul } 175140516Swpaul 175240516Swpaul /* 175340516Swpaul * Set capture broadcast bit to capture broadcast frames. 175440516Swpaul */ 175540516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 175640516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 175740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 175840516Swpaul } else { 175940516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 176040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 176140516Swpaul } 176240516Swpaul 176340516Swpaul /* 176440516Swpaul * Program the multicast filter, if necessary. 176540516Swpaul */ 176640516Swpaul rl_setmulti(sc); 176740516Swpaul 176840516Swpaul /* 176940516Swpaul * Enable interrupts. 177040516Swpaul */ 177140516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 177240516Swpaul 177340516Swpaul /* Start RX/TX process. */ 177440516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 177540516Swpaul 177640516Swpaul /* Enable receiver and transmitter. */ 177740516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 177840516Swpaul 177940516Swpaul /* Restore state of BMCR */ 178040516Swpaul if (sc->rl_pinfo != NULL) 178140516Swpaul rl_phy_writereg(sc, PHY_BMCR, phy_bmcr); 178240516Swpaul 178340516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 178440516Swpaul 178540516Swpaul ifp->if_flags |= IFF_RUNNING; 178640516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 178740516Swpaul 178840516Swpaul (void)splx(s); 178940516Swpaul 179040516Swpaul return; 179140516Swpaul} 179240516Swpaul 179340516Swpaul/* 179440516Swpaul * Set media options. 179540516Swpaul */ 179640516Swpaulstatic int rl_ifmedia_upd(ifp) 179740516Swpaul struct ifnet *ifp; 179840516Swpaul{ 179940516Swpaul struct rl_softc *sc; 180040516Swpaul struct ifmedia *ifm; 180140516Swpaul 180240516Swpaul sc = ifp->if_softc; 180340516Swpaul ifm = &sc->ifmedia; 180440516Swpaul 180540516Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 180640516Swpaul return(EINVAL); 180740516Swpaul 180840516Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 180940516Swpaul rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 181040516Swpaul else 181140516Swpaul rl_setmode_mii(sc, ifm->ifm_media); 181240516Swpaul 181340516Swpaul return(0); 181440516Swpaul} 181540516Swpaul 181640516Swpaul/* 181740516Swpaul * Report current media status. 181840516Swpaul */ 181940516Swpaulstatic void rl_ifmedia_sts(ifp, ifmr) 182040516Swpaul struct ifnet *ifp; 182140516Swpaul struct ifmediareq *ifmr; 182240516Swpaul{ 182340516Swpaul struct rl_softc *sc; 182440516Swpaul u_int16_t advert = 0, ability = 0; 182540516Swpaul 182640516Swpaul sc = ifp->if_softc; 182740516Swpaul 182840516Swpaul if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 182940516Swpaul if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 183040516Swpaul ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 183140516Swpaul else 183240516Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 183340516Swpaul 183440516Swpaul if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 183540516Swpaul ifmr->ifm_active |= IFM_FDX; 183640516Swpaul else 183740516Swpaul ifmr->ifm_active |= IFM_HDX; 183840516Swpaul return; 183940516Swpaul } 184040516Swpaul 184140516Swpaul ability = rl_phy_readreg(sc, PHY_LPAR); 184240516Swpaul advert = rl_phy_readreg(sc, PHY_ANAR); 184340516Swpaul if (advert & PHY_ANAR_100BT4 && 184440516Swpaul ability & PHY_ANAR_100BT4) { 184540516Swpaul ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 184640516Swpaul } else if (advert & PHY_ANAR_100BTXFULL && 184740516Swpaul ability & PHY_ANAR_100BTXFULL) { 184840516Swpaul ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 184940516Swpaul } else if (advert & PHY_ANAR_100BTXHALF && 185040516Swpaul ability & PHY_ANAR_100BTXHALF) { 185140516Swpaul ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 185240516Swpaul } else if (advert & PHY_ANAR_10BTFULL && 185340516Swpaul ability & PHY_ANAR_10BTFULL) { 185440516Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 185540516Swpaul } else if (advert & PHY_ANAR_10BTHALF && 185640516Swpaul ability & PHY_ANAR_10BTHALF) { 185740516Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 185840516Swpaul } 185940516Swpaul 186040516Swpaul return; 186140516Swpaul} 186240516Swpaul 186340516Swpaulstatic int rl_ioctl(ifp, command, data) 186440516Swpaul struct ifnet *ifp; 186540516Swpaul u_long command; 186640516Swpaul caddr_t data; 186740516Swpaul{ 186840516Swpaul struct rl_softc *sc = ifp->if_softc; 186940516Swpaul struct ifreq *ifr = (struct ifreq *) data; 187040516Swpaul int s, error = 0; 187140516Swpaul 187240516Swpaul s = splimp(); 187340516Swpaul 187440516Swpaul switch(command) { 187540516Swpaul case SIOCSIFADDR: 187640516Swpaul case SIOCGIFADDR: 187740516Swpaul case SIOCSIFMTU: 187840516Swpaul error = ether_ioctl(ifp, command, data); 187940516Swpaul break; 188040516Swpaul case SIOCSIFFLAGS: 188140516Swpaul if (ifp->if_flags & IFF_UP) { 188240516Swpaul rl_init(sc); 188340516Swpaul } else { 188440516Swpaul if (ifp->if_flags & IFF_RUNNING) 188540516Swpaul rl_stop(sc); 188640516Swpaul } 188740516Swpaul error = 0; 188840516Swpaul break; 188940516Swpaul case SIOCADDMULTI: 189040516Swpaul case SIOCDELMULTI: 189140516Swpaul rl_setmulti(sc); 189240516Swpaul error = 0; 189340516Swpaul break; 189440516Swpaul case SIOCGIFMEDIA: 189540516Swpaul case SIOCSIFMEDIA: 189640516Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 189740516Swpaul break; 189840516Swpaul default: 189940516Swpaul error = EINVAL; 190040516Swpaul break; 190140516Swpaul } 190240516Swpaul 190340516Swpaul (void)splx(s); 190440516Swpaul 190540516Swpaul return(error); 190640516Swpaul} 190740516Swpaul 190840516Swpaulstatic void rl_watchdog(ifp) 190940516Swpaul struct ifnet *ifp; 191040516Swpaul{ 191140516Swpaul struct rl_softc *sc; 191240516Swpaul 191340516Swpaul sc = ifp->if_softc; 191440516Swpaul 191540516Swpaul if (sc->rl_autoneg) { 191640516Swpaul rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1); 191740516Swpaul return; 191840516Swpaul } 191940516Swpaul 192040516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 192140516Swpaul ifp->if_oerrors++; 192240516Swpaul if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 192340516Swpaul printf("rl%d: no carrier - transceiver cable problem?\n", 192440516Swpaul sc->rl_unit); 192540516Swpaul rl_txeoc(sc); 192640516Swpaul rl_txeof(sc); 192740516Swpaul rl_rxeof(sc); 192840516Swpaul rl_init(sc); 192940516Swpaul 193040516Swpaul return; 193140516Swpaul} 193240516Swpaul 193340516Swpaul/* 193440516Swpaul * Stop the adapter and free any mbufs allocated to the 193540516Swpaul * RX and TX lists. 193640516Swpaul */ 193740516Swpaulstatic void rl_stop(sc) 193840516Swpaul struct rl_softc *sc; 193940516Swpaul{ 194040516Swpaul register int i; 194140516Swpaul struct ifnet *ifp; 194240516Swpaul 194340516Swpaul ifp = &sc->arpcom.ac_if; 194440516Swpaul ifp->if_timer = 0; 194540516Swpaul 194640516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 194740516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 194840516Swpaul 194940516Swpaul /* 195040516Swpaul * Free the TX list buffers. 195140516Swpaul */ 195240516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 195340516Swpaul if (sc->rl_cdata.rl_tx_chain[i].rl_mbuf != NULL) { 195440516Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i].rl_mbuf); 195540516Swpaul sc->rl_cdata.rl_tx_chain[i].rl_mbuf = NULL; 195640516Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + 195740516Swpaul sc->rl_cdata.rl_tx_chain[i].rl_desc, 0x00000000); 195840516Swpaul } 195940516Swpaul } 196040516Swpaul 196140516Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 196240516Swpaul 196340516Swpaul return; 196440516Swpaul} 196540516Swpaul 196640516Swpaul/* 196740516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 196840516Swpaul * get confused by errant DMAs when rebooting. 196940516Swpaul */ 197040516Swpaulstatic void rl_shutdown(howto, arg) 197140516Swpaul int howto; 197240516Swpaul void *arg; 197340516Swpaul{ 197440516Swpaul struct rl_softc *sc = (struct rl_softc *)arg; 197540516Swpaul 197640516Swpaul rl_stop(sc); 197740516Swpaul 197840516Swpaul return; 197940516Swpaul} 198040516Swpaul 198140516Swpaul 198240516Swpaulstatic struct pci_device rl_device = { 198340516Swpaul "rl", 198440516Swpaul rl_probe, 198540516Swpaul rl_attach, 198640516Swpaul &rl_count, 198740516Swpaul NULL 198840516Swpaul}; 198940516SwpaulDATA_SET(pcidevice_set, rl_device); 1990