if_rl.c revision 129633
140516Swpaul/* 2119868Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul */ 3240516Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 129633 2004-05-23 21:05:08Z yar $"); 35122678Sobrien 3640516Swpaul/* 37119868Swpaul * RealTek 8129/8139 PCI NIC driver 3840516Swpaul * 39119868Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 40119868Swpaul * the RealTek chipset. Datasheets can be obtained from 4140516Swpaul * www.realtek.com.tw. 4240516Swpaul * 43119868Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 44119868Swpaul * Electrical Engineering Department 45119868Swpaul * Columbia University, New York City 4640516Swpaul */ 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 87108729Sjake#include <sys/endian.h> 8840516Swpaul#include <sys/systm.h> 8940516Swpaul#include <sys/sockio.h> 9040516Swpaul#include <sys/mbuf.h> 9140516Swpaul#include <sys/malloc.h> 9240516Swpaul#include <sys/kernel.h> 9340516Swpaul#include <sys/socket.h> 9440516Swpaul 9540516Swpaul#include <net/if.h> 9640516Swpaul#include <net/if_arp.h> 9740516Swpaul#include <net/ethernet.h> 9840516Swpaul#include <net/if_dl.h> 9940516Swpaul#include <net/if_media.h> 10040516Swpaul 10140516Swpaul#include <net/bpf.h> 10240516Swpaul 10341569Swpaul#include <machine/bus_pio.h> 10441569Swpaul#include <machine/bus_memio.h> 10541569Swpaul#include <machine/bus.h> 10650703Swpaul#include <machine/resource.h> 10750703Swpaul#include <sys/bus.h> 10850703Swpaul#include <sys/rman.h> 10940516Swpaul 11050703Swpaul#include <dev/mii/mii.h> 11150703Swpaul#include <dev/mii/miivar.h> 11250703Swpaul 113119871Swpaul#include <dev/pci/pcireg.h> 114119871Swpaul#include <dev/pci/pcivar.h> 11540516Swpaul 116113506SmdoddMODULE_DEPEND(rl, pci, 1, 1, 1); 117113506SmdoddMODULE_DEPEND(rl, ether, 1, 1, 1); 11859758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11959758Speter 12051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12150703Swpaul#include "miibus_if.h" 12250703Swpaul 12340516Swpaul/* 12440516Swpaul * Default to using PIO access for this driver. On SMP systems, 12540516Swpaul * there appear to be problems with memory mapped mode: it looks like 12640516Swpaul * doing too many memory mapped access back to back in rapid succession 12740516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12840516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12940516Swpaul * uniprocessor systems though. 13040516Swpaul */ 13140516Swpaul#define RL_USEIOSPACE 13240516Swpaul 13340516Swpaul#include <pci/if_rlreg.h> 13440516Swpaul 13540516Swpaul/* 13640516Swpaul * Various supported device vendors/types and their names. 13740516Swpaul */ 13840516Swpaulstatic struct rl_type rl_devs[] = { 139117388Swpaul { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 14040516Swpaul "RealTek 8129 10/100BaseTX" }, 141117388Swpaul { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 14240516Swpaul "RealTek 8139 10/100BaseTX" }, 143117388Swpaul { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 14467771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 145118978Swpaul { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 146118978Swpaul "RealTek 8100 10/100BaseTX" }, 147117388Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 14841243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 149117388Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 15044238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 151117388Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 15244238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 153117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 15472813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 155117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 15696112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 157117388Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 15894400Swpaul "Nortel Networks 10/100BaseTX" }, 159117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 160103020Siwasaki "Corega FEther CB-TXD" }, 161117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 162109095Ssanpei "Corega FEtherII CB-TXD" }, 163117388Swpaul { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 164111381Sdan "Peppercon AG ROL-F" }, 165117388Swpaul { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 166112379Ssanpei "Planex FNW-3800-TX" }, 167117388Swpaul { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 168117388Swpaul "Compaq HNE-300" }, 169117388Swpaul { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 170117388Swpaul "LevelOne FPC-0106TX" }, 171117388Swpaul { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 172117388Swpaul "Edimax EP-4103DL CardBus" }, 173123740Speter { 0, 0, 0, NULL } 17440516Swpaul}; 17540516Swpaul 17692739Salfredstatic int rl_probe (device_t); 17792739Salfredstatic int rl_attach (device_t); 17892739Salfredstatic int rl_detach (device_t); 17940516Swpaul 180119868Swpaulstatic int rl_encap (struct rl_softc *, struct mbuf * ); 18140516Swpaul 18292739Salfredstatic void rl_rxeof (struct rl_softc *); 18392739Salfredstatic void rl_txeof (struct rl_softc *); 18492739Salfredstatic void rl_intr (void *); 18592739Salfredstatic void rl_tick (void *); 18692739Salfredstatic void rl_start (struct ifnet *); 18792739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 18892739Salfredstatic void rl_init (void *); 18992739Salfredstatic void rl_stop (struct rl_softc *); 19092739Salfredstatic void rl_watchdog (struct ifnet *); 19192739Salfredstatic int rl_suspend (device_t); 19292739Salfredstatic int rl_resume (device_t); 19392739Salfredstatic void rl_shutdown (device_t); 19492739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 19592739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 19640516Swpaul 19792739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 19892739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 19992739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 20092739Salfredstatic void rl_mii_sync (struct rl_softc *); 20192739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 20292739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 20392739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 20440516Swpaul 20592739Salfredstatic int rl_miibus_readreg (device_t, int, int); 20692739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 20792739Salfredstatic void rl_miibus_statchg (device_t); 20840516Swpaul 209123289Sobrienstatic uint32_t rl_mchash (const uint8_t *); 21092739Salfredstatic void rl_setmulti (struct rl_softc *); 21192739Salfredstatic void rl_reset (struct rl_softc *); 21292739Salfredstatic int rl_list_tx_init (struct rl_softc *); 21340516Swpaul 21492739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 21592739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 21681713Swpaul 21750703Swpaul#ifdef RL_USEIOSPACE 21850703Swpaul#define RL_RES SYS_RES_IOPORT 21950703Swpaul#define RL_RID RL_PCI_LOIO 22050703Swpaul#else 22150703Swpaul#define RL_RES SYS_RES_MEMORY 22250703Swpaul#define RL_RID RL_PCI_LOMEM 22350703Swpaul#endif 22450703Swpaul 22550703Swpaulstatic device_method_t rl_methods[] = { 22650703Swpaul /* Device interface */ 22750703Swpaul DEVMETHOD(device_probe, rl_probe), 22850703Swpaul DEVMETHOD(device_attach, rl_attach), 22950703Swpaul DEVMETHOD(device_detach, rl_detach), 23086822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 23186822Siwasaki DEVMETHOD(device_resume, rl_resume), 23250703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 23350703Swpaul 23450703Swpaul /* bus interface */ 23550703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 23650703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 23750703Swpaul 23850703Swpaul /* MII interface */ 23950703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 24050703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 24150703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 24250703Swpaul 24350703Swpaul { 0, 0 } 24450703Swpaul}; 24550703Swpaul 24650703Swpaulstatic driver_t rl_driver = { 24751455Swpaul "rl", 24850703Swpaul rl_methods, 24950703Swpaul sizeof(struct rl_softc) 25050703Swpaul}; 25150703Swpaul 25250703Swpaulstatic devclass_t rl_devclass; 25350703Swpaul 254113506SmdoddDRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 255123019SimpDRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 25651473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 25750703Swpaul 25840516Swpaul#define EE_SET(x) \ 25940516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 26040516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 26140516Swpaul 26240516Swpaul#define EE_CLR(x) \ 26340516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 26440516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 26540516Swpaul 26681713Swpaulstatic void 26781713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 26881713Swpaul void *arg; 26981713Swpaul bus_dma_segment_t *segs; 27081713Swpaul int nseg, error; 27181713Swpaul{ 27281713Swpaul struct rl_softc *sc; 27381713Swpaul 27481713Swpaul sc = arg; 27581713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 27681713Swpaul 27781713Swpaul return; 27881713Swpaul} 27981713Swpaul 28081713Swpaulstatic void 28181713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 28281713Swpaul void *arg; 28381713Swpaul bus_dma_segment_t *segs; 28481713Swpaul int nseg, error; 28581713Swpaul{ 28681713Swpaul struct rl_softc *sc; 28781713Swpaul 28881713Swpaul sc = arg; 28981713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 29081713Swpaul 29181713Swpaul return; 29281713Swpaul} 29381713Swpaul 29440516Swpaul/* 29540516Swpaul * Send a read command and address to the EEPROM, check for ACK. 29640516Swpaul */ 297102335Salfredstatic void 298102335Salfredrl_eeprom_putbyte(sc, addr) 29940516Swpaul struct rl_softc *sc; 30041656Swpaul int addr; 30140516Swpaul{ 30240516Swpaul register int d, i; 30340516Swpaul 30467931Swpaul d = addr | sc->rl_eecmd_read; 30540516Swpaul 30640516Swpaul /* 30755170Sbillf * Feed in each bit and strobe the clock. 30840516Swpaul */ 30940516Swpaul for (i = 0x400; i; i >>= 1) { 31040516Swpaul if (d & i) { 31140516Swpaul EE_SET(RL_EE_DATAIN); 31240516Swpaul } else { 31340516Swpaul EE_CLR(RL_EE_DATAIN); 31440516Swpaul } 31540516Swpaul DELAY(100); 31640516Swpaul EE_SET(RL_EE_CLK); 31740516Swpaul DELAY(150); 31840516Swpaul EE_CLR(RL_EE_CLK); 31940516Swpaul DELAY(100); 32040516Swpaul } 32140516Swpaul 32240516Swpaul return; 32340516Swpaul} 32440516Swpaul 32540516Swpaul/* 32640516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 32740516Swpaul */ 328102335Salfredstatic void 329102335Salfredrl_eeprom_getword(sc, addr, dest) 33040516Swpaul struct rl_softc *sc; 33141656Swpaul int addr; 33240516Swpaul u_int16_t *dest; 33340516Swpaul{ 33440516Swpaul register int i; 33540516Swpaul u_int16_t word = 0; 33640516Swpaul 33740516Swpaul /* Enter EEPROM access mode. */ 33840516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33940516Swpaul 34040516Swpaul /* 34140516Swpaul * Send address of word we want to read. 34240516Swpaul */ 34340516Swpaul rl_eeprom_putbyte(sc, addr); 34440516Swpaul 34540516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 34640516Swpaul 34740516Swpaul /* 34840516Swpaul * Start reading bits from EEPROM. 34940516Swpaul */ 35040516Swpaul for (i = 0x8000; i; i >>= 1) { 35140516Swpaul EE_SET(RL_EE_CLK); 35240516Swpaul DELAY(100); 35340516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 35440516Swpaul word |= i; 35540516Swpaul EE_CLR(RL_EE_CLK); 35640516Swpaul DELAY(100); 35740516Swpaul } 35840516Swpaul 35940516Swpaul /* Turn off EEPROM access mode. */ 36040516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 36140516Swpaul 36240516Swpaul *dest = word; 36340516Swpaul 36440516Swpaul return; 36540516Swpaul} 36640516Swpaul 36740516Swpaul/* 36840516Swpaul * Read a sequence of words from the EEPROM. 36940516Swpaul */ 370102335Salfredstatic void 371102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 37240516Swpaul struct rl_softc *sc; 37340516Swpaul caddr_t dest; 37440516Swpaul int off; 37540516Swpaul int cnt; 37640516Swpaul int swap; 37740516Swpaul{ 37840516Swpaul int i; 37940516Swpaul u_int16_t word = 0, *ptr; 38040516Swpaul 38140516Swpaul for (i = 0; i < cnt; i++) { 38240516Swpaul rl_eeprom_getword(sc, off + i, &word); 38340516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 38440516Swpaul if (swap) 38540516Swpaul *ptr = ntohs(word); 38640516Swpaul else 38740516Swpaul *ptr = word; 38840516Swpaul } 38940516Swpaul 39040516Swpaul return; 39140516Swpaul} 39240516Swpaul 39340516Swpaul 39440516Swpaul/* 39540516Swpaul * MII access routines are provided for the 8129, which 39640516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 39740516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 39840516Swpaul * direct access PHY registers. 39940516Swpaul */ 40040516Swpaul#define MII_SET(x) \ 40140516Swpaul CSR_WRITE_1(sc, RL_MII, \ 402105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 40340516Swpaul 40440516Swpaul#define MII_CLR(x) \ 40540516Swpaul CSR_WRITE_1(sc, RL_MII, \ 406105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 40740516Swpaul 40840516Swpaul/* 40940516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 41040516Swpaul */ 411102335Salfredstatic void 412102335Salfredrl_mii_sync(sc) 41340516Swpaul struct rl_softc *sc; 41440516Swpaul{ 41540516Swpaul register int i; 41640516Swpaul 41740516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 41840516Swpaul 41940516Swpaul for (i = 0; i < 32; i++) { 42040516Swpaul MII_SET(RL_MII_CLK); 42140516Swpaul DELAY(1); 42240516Swpaul MII_CLR(RL_MII_CLK); 42340516Swpaul DELAY(1); 42440516Swpaul } 42540516Swpaul 42640516Swpaul return; 42740516Swpaul} 42840516Swpaul 42940516Swpaul/* 43040516Swpaul * Clock a series of bits through the MII. 43140516Swpaul */ 432102335Salfredstatic void 433102335Salfredrl_mii_send(sc, bits, cnt) 43440516Swpaul struct rl_softc *sc; 43540516Swpaul u_int32_t bits; 43640516Swpaul int cnt; 43740516Swpaul{ 43840516Swpaul int i; 43940516Swpaul 44040516Swpaul MII_CLR(RL_MII_CLK); 44140516Swpaul 44240516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 443109109Sdes if (bits & i) { 44440516Swpaul MII_SET(RL_MII_DATAOUT); 445109109Sdes } else { 44640516Swpaul MII_CLR(RL_MII_DATAOUT); 447109109Sdes } 44840516Swpaul DELAY(1); 44940516Swpaul MII_CLR(RL_MII_CLK); 45040516Swpaul DELAY(1); 45140516Swpaul MII_SET(RL_MII_CLK); 45240516Swpaul } 45340516Swpaul} 45440516Swpaul 45540516Swpaul/* 45640516Swpaul * Read an PHY register through the MII. 45740516Swpaul */ 458102335Salfredstatic int 459102335Salfredrl_mii_readreg(sc, frame) 46040516Swpaul struct rl_softc *sc; 46140516Swpaul struct rl_mii_frame *frame; 462109109Sdes 46340516Swpaul{ 46467087Swpaul int i, ack; 46540516Swpaul 46667087Swpaul RL_LOCK(sc); 46740516Swpaul 46840516Swpaul /* 46940516Swpaul * Set up frame for RX. 47040516Swpaul */ 47140516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 47240516Swpaul frame->mii_opcode = RL_MII_READOP; 47340516Swpaul frame->mii_turnaround = 0; 47440516Swpaul frame->mii_data = 0; 475109109Sdes 47640516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 47740516Swpaul 47840516Swpaul /* 479109109Sdes * Turn on data xmit. 48040516Swpaul */ 48140516Swpaul MII_SET(RL_MII_DIR); 48240516Swpaul 48340516Swpaul rl_mii_sync(sc); 48440516Swpaul 48540516Swpaul /* 48640516Swpaul * Send command/address info. 48740516Swpaul */ 48840516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 48940516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 49040516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 49140516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 49240516Swpaul 49340516Swpaul /* Idle bit */ 49440516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 49540516Swpaul DELAY(1); 49640516Swpaul MII_SET(RL_MII_CLK); 49740516Swpaul DELAY(1); 49840516Swpaul 49940516Swpaul /* Turn off xmit. */ 50040516Swpaul MII_CLR(RL_MII_DIR); 50140516Swpaul 50240516Swpaul /* Check for ack */ 50340516Swpaul MII_CLR(RL_MII_CLK); 50440516Swpaul DELAY(1); 505109058Smbr ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 50640516Swpaul MII_SET(RL_MII_CLK); 50740516Swpaul DELAY(1); 50840516Swpaul 50940516Swpaul /* 51040516Swpaul * Now try reading data bits. If the ack failed, we still 51140516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 51240516Swpaul */ 51340516Swpaul if (ack) { 51440516Swpaul for(i = 0; i < 16; i++) { 51540516Swpaul MII_CLR(RL_MII_CLK); 51640516Swpaul DELAY(1); 51740516Swpaul MII_SET(RL_MII_CLK); 51840516Swpaul DELAY(1); 51940516Swpaul } 52040516Swpaul goto fail; 52140516Swpaul } 52240516Swpaul 52340516Swpaul for (i = 0x8000; i; i >>= 1) { 52440516Swpaul MII_CLR(RL_MII_CLK); 52540516Swpaul DELAY(1); 52640516Swpaul if (!ack) { 52740516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 52840516Swpaul frame->mii_data |= i; 52940516Swpaul DELAY(1); 53040516Swpaul } 53140516Swpaul MII_SET(RL_MII_CLK); 53240516Swpaul DELAY(1); 53340516Swpaul } 53440516Swpaul 53540516Swpaulfail: 53640516Swpaul 53740516Swpaul MII_CLR(RL_MII_CLK); 53840516Swpaul DELAY(1); 53940516Swpaul MII_SET(RL_MII_CLK); 54040516Swpaul DELAY(1); 54140516Swpaul 54267087Swpaul RL_UNLOCK(sc); 54340516Swpaul 54440516Swpaul if (ack) 54540516Swpaul return(1); 54640516Swpaul return(0); 54740516Swpaul} 54840516Swpaul 54940516Swpaul/* 55040516Swpaul * Write to a PHY register through the MII. 55140516Swpaul */ 552102335Salfredstatic int 553102335Salfredrl_mii_writereg(sc, frame) 55440516Swpaul struct rl_softc *sc; 55540516Swpaul struct rl_mii_frame *frame; 556109109Sdes 55740516Swpaul{ 55867087Swpaul RL_LOCK(sc); 55940516Swpaul 56040516Swpaul /* 56140516Swpaul * Set up frame for TX. 56240516Swpaul */ 56340516Swpaul 56440516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 56540516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 56640516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 567109109Sdes 56840516Swpaul /* 569109109Sdes * Turn on data output. 57040516Swpaul */ 57140516Swpaul MII_SET(RL_MII_DIR); 57240516Swpaul 57340516Swpaul rl_mii_sync(sc); 57440516Swpaul 57540516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 57640516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 57740516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 57840516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 57940516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 58040516Swpaul rl_mii_send(sc, frame->mii_data, 16); 58140516Swpaul 58240516Swpaul /* Idle bit. */ 58340516Swpaul MII_SET(RL_MII_CLK); 58440516Swpaul DELAY(1); 58540516Swpaul MII_CLR(RL_MII_CLK); 58640516Swpaul DELAY(1); 58740516Swpaul 58840516Swpaul /* 58940516Swpaul * Turn off xmit. 59040516Swpaul */ 59140516Swpaul MII_CLR(RL_MII_DIR); 59240516Swpaul 59367087Swpaul RL_UNLOCK(sc); 59440516Swpaul 59540516Swpaul return(0); 59640516Swpaul} 59740516Swpaul 598102335Salfredstatic int 599102335Salfredrl_miibus_readreg(dev, phy, reg) 60050703Swpaul device_t dev; 60150703Swpaul int phy, reg; 60250703Swpaul{ 60340516Swpaul struct rl_softc *sc; 60440516Swpaul struct rl_mii_frame frame; 60540516Swpaul u_int16_t rval = 0; 60640516Swpaul u_int16_t rl8139_reg = 0; 60740516Swpaul 60850703Swpaul sc = device_get_softc(dev); 60967087Swpaul RL_LOCK(sc); 61050703Swpaul 611119868Swpaul if (sc->rl_type == RL_8139) { 61250703Swpaul /* Pretend the internal PHY is only at address 0 */ 61367087Swpaul if (phy) { 61467087Swpaul RL_UNLOCK(sc); 61550703Swpaul return(0); 61667087Swpaul } 61740516Swpaul switch(reg) { 61850703Swpaul case MII_BMCR: 61940516Swpaul rl8139_reg = RL_BMCR; 62040516Swpaul break; 62150703Swpaul case MII_BMSR: 62240516Swpaul rl8139_reg = RL_BMSR; 62340516Swpaul break; 62450703Swpaul case MII_ANAR: 62540516Swpaul rl8139_reg = RL_ANAR; 62640516Swpaul break; 62750703Swpaul case MII_ANER: 62850703Swpaul rl8139_reg = RL_ANER; 62950703Swpaul break; 63050703Swpaul case MII_ANLPAR: 63140516Swpaul rl8139_reg = RL_LPAR; 63240516Swpaul break; 63350703Swpaul case MII_PHYIDR1: 63450703Swpaul case MII_PHYIDR2: 63567087Swpaul RL_UNLOCK(sc); 63650703Swpaul return(0); 63794149Swpaul /* 63894149Swpaul * Allow the rlphy driver to read the media status 63994149Swpaul * register. If we have a link partner which does not 64094149Swpaul * support NWAY, this is the register which will tell 64194149Swpaul * us the results of parallel detection. 64294149Swpaul */ 64394149Swpaul case RL_MEDIASTAT: 64494149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 64594149Swpaul RL_UNLOCK(sc); 64694149Swpaul return(rval); 64740516Swpaul default: 64840516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 64967087Swpaul RL_UNLOCK(sc); 65040516Swpaul return(0); 65140516Swpaul } 65240516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 65367087Swpaul RL_UNLOCK(sc); 65440516Swpaul return(rval); 65540516Swpaul } 65640516Swpaul 65740516Swpaul bzero((char *)&frame, sizeof(frame)); 65840516Swpaul 65950703Swpaul frame.mii_phyaddr = phy; 66040516Swpaul frame.mii_regaddr = reg; 66140516Swpaul rl_mii_readreg(sc, &frame); 66267087Swpaul RL_UNLOCK(sc); 66340516Swpaul 66440516Swpaul return(frame.mii_data); 66540516Swpaul} 66640516Swpaul 667102335Salfredstatic int 668102335Salfredrl_miibus_writereg(dev, phy, reg, data) 66950703Swpaul device_t dev; 67050703Swpaul int phy, reg, data; 67150703Swpaul{ 67240516Swpaul struct rl_softc *sc; 67340516Swpaul struct rl_mii_frame frame; 67440516Swpaul u_int16_t rl8139_reg = 0; 67540516Swpaul 67650703Swpaul sc = device_get_softc(dev); 67767087Swpaul RL_LOCK(sc); 67850703Swpaul 679119868Swpaul if (sc->rl_type == RL_8139) { 68050703Swpaul /* Pretend the internal PHY is only at address 0 */ 68167087Swpaul if (phy) { 68267087Swpaul RL_UNLOCK(sc); 68350703Swpaul return(0); 68467087Swpaul } 68540516Swpaul switch(reg) { 68650703Swpaul case MII_BMCR: 68740516Swpaul rl8139_reg = RL_BMCR; 68840516Swpaul break; 68950703Swpaul case MII_BMSR: 69040516Swpaul rl8139_reg = RL_BMSR; 69140516Swpaul break; 69250703Swpaul case MII_ANAR: 69340516Swpaul rl8139_reg = RL_ANAR; 69440516Swpaul break; 69550703Swpaul case MII_ANER: 69650703Swpaul rl8139_reg = RL_ANER; 69750703Swpaul break; 69850703Swpaul case MII_ANLPAR: 69940516Swpaul rl8139_reg = RL_LPAR; 70040516Swpaul break; 70150703Swpaul case MII_PHYIDR1: 70250703Swpaul case MII_PHYIDR2: 70367087Swpaul RL_UNLOCK(sc); 70450703Swpaul return(0); 70550703Swpaul break; 70640516Swpaul default: 70740516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 70867087Swpaul RL_UNLOCK(sc); 70950703Swpaul return(0); 71040516Swpaul } 71140516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 71267087Swpaul RL_UNLOCK(sc); 71350703Swpaul return(0); 71440516Swpaul } 71540516Swpaul 71640516Swpaul bzero((char *)&frame, sizeof(frame)); 71740516Swpaul 71850703Swpaul frame.mii_phyaddr = phy; 71940516Swpaul frame.mii_regaddr = reg; 72040516Swpaul frame.mii_data = data; 72140516Swpaul 72240516Swpaul rl_mii_writereg(sc, &frame); 72340516Swpaul 72467087Swpaul RL_UNLOCK(sc); 72550703Swpaul return(0); 72650703Swpaul} 72750703Swpaul 728102335Salfredstatic void 729102335Salfredrl_miibus_statchg(dev) 73050703Swpaul device_t dev; 73150703Swpaul{ 73240516Swpaul return; 73340516Swpaul} 73440516Swpaul 73540516Swpaul/* 73643062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 73740516Swpaul */ 738122625Sobrienstatic u_int32_t 739122625Sobrienrl_mchash(addr) 740123289Sobrien const uint8_t *addr; 74140516Swpaul{ 742123289Sobrien uint32_t crc, carry; 743123289Sobrien int idx, bit; 744123289Sobrien uint8_t data; 74540516Swpaul 74640516Swpaul /* Compute CRC for the address value. */ 74740516Swpaul crc = 0xFFFFFFFF; /* initial value */ 74840516Swpaul 749122625Sobrien for (idx = 0; idx < 6; idx++) { 750122625Sobrien for (data = *addr++, bit = 0; bit < 8; bit++, data >>=1 ) { 751122625Sobrien carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 75240516Swpaul crc <<= 1; 75340516Swpaul if (carry) 75440516Swpaul crc = (crc ^ 0x04c11db6) | carry; 75540516Swpaul } 75640516Swpaul } 75740516Swpaul 75840516Swpaul /* return the filter bit position */ 75943062Swpaul return(crc >> 26); 76040516Swpaul} 76140516Swpaul 76240516Swpaul/* 76340516Swpaul * Program the 64-bit multicast hash filter. 76440516Swpaul */ 765102335Salfredstatic void 766102335Salfredrl_setmulti(sc) 76740516Swpaul struct rl_softc *sc; 76840516Swpaul{ 76940516Swpaul struct ifnet *ifp; 77040516Swpaul int h = 0; 77140516Swpaul u_int32_t hashes[2] = { 0, 0 }; 77240516Swpaul struct ifmultiaddr *ifma; 77340516Swpaul u_int32_t rxfilt; 77440516Swpaul int mcnt = 0; 77540516Swpaul 77640516Swpaul ifp = &sc->arpcom.ac_if; 77740516Swpaul 77840516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 77940516Swpaul 78043062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 78140516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 78240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 78340516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 78440516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 78540516Swpaul return; 78640516Swpaul } 78740516Swpaul 78840516Swpaul /* first, zot all the existing hash bits */ 78940516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 79040516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 79140516Swpaul 79240516Swpaul /* now program new ones */ 79372084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 79440516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 79540516Swpaul continue; 796122625Sobrien h = rl_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 79740516Swpaul if (h < 32) 79840516Swpaul hashes[0] |= (1 << h); 79940516Swpaul else 80040516Swpaul hashes[1] |= (1 << (h - 32)); 80140516Swpaul mcnt++; 80240516Swpaul } 80340516Swpaul 80440516Swpaul if (mcnt) 80540516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 80640516Swpaul else 80740516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 80840516Swpaul 80940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 81040516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 81140516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 81240516Swpaul 81340516Swpaul return; 81440516Swpaul} 81540516Swpaul 816102335Salfredstatic void 817102335Salfredrl_reset(sc) 81840516Swpaul struct rl_softc *sc; 81940516Swpaul{ 82040516Swpaul register int i; 82140516Swpaul 82240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 82340516Swpaul 82440516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 82540516Swpaul DELAY(10); 82640516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 82740516Swpaul break; 82840516Swpaul } 82940516Swpaul if (i == RL_TIMEOUT) 83040516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 83140516Swpaul 832109109Sdes return; 83340516Swpaul} 83440516Swpaul 83540516Swpaul/* 83640516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 83740516Swpaul * IDs against our list and return a device name if we find a match. 83840516Swpaul */ 839102335Salfredstatic int 840102335Salfredrl_probe(dev) 84150703Swpaul device_t dev; 84240516Swpaul{ 84340516Swpaul struct rl_type *t; 844119868Swpaul struct rl_softc *sc; 845117388Swpaul int rid; 846117388Swpaul u_int32_t hwrev; 84740516Swpaul 84840516Swpaul t = rl_devs; 849117388Swpaul sc = device_get_softc(dev); 85040516Swpaul 85140516Swpaul while(t->rl_name != NULL) { 85250703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 85350703Swpaul (pci_get_device(dev) == t->rl_did)) { 854117388Swpaul 855117388Swpaul /* 856117388Swpaul * Temporarily map the I/O space 857117388Swpaul * so we can read the chip ID register. 858117388Swpaul */ 859117388Swpaul rid = RL_RID; 860127135Snjl sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 861127135Snjl RF_ACTIVE); 862117388Swpaul if (sc->rl_res == NULL) { 863117388Swpaul device_printf(dev, 864117388Swpaul "couldn't map ports/memory\n"); 865117388Swpaul return(ENXIO); 866117388Swpaul } 867117388Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 868117388Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 869117388Swpaul mtx_init(&sc->rl_mtx, 870117388Swpaul device_get_nameunit(dev), 871117388Swpaul MTX_NETWORK_LOCK, MTX_DEF); 872119868Swpaul RL_LOCK(sc); 873119868Swpaul hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 874119868Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 875117388Swpaul RL_UNLOCK(sc); 876117388Swpaul mtx_destroy(&sc->rl_mtx); 877119868Swpaul 878119868Swpaul /* Don't attach to 8139C+ or 8169/8110 chips. */ 879119868Swpaul if (hwrev == RL_HWREV_8139CPLUS || 880124076Swpaul (hwrev == RL_HWREV_8169 && 881124076Swpaul t->rl_did == RT_DEVICEID_8169) || 882119954Swpaul hwrev == RL_HWREV_8169S || 883119954Swpaul hwrev == RL_HWREV_8110S) { 884119868Swpaul t++; 885119868Swpaul continue; 886119868Swpaul } 887119868Swpaul 888119868Swpaul device_set_desc(dev, t->rl_name); 88950703Swpaul return(0); 89040516Swpaul } 89140516Swpaul t++; 89240516Swpaul } 89340516Swpaul 89450703Swpaul return(ENXIO); 89540516Swpaul} 89640516Swpaul 89740516Swpaul/* 89840516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 89940516Swpaul * setup and ethernet/BPF attach. 90040516Swpaul */ 901102335Salfredstatic int 902102335Salfredrl_attach(dev) 90350703Swpaul device_t dev; 90440516Swpaul{ 90540516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 906108729Sjake u_int16_t as[3]; 90740516Swpaul struct rl_softc *sc; 90840516Swpaul struct ifnet *ifp; 909119868Swpaul u_int16_t rl_did = 0; 910117388Swpaul struct rl_type *t; 911108729Sjake int unit, error = 0, rid, i; 91240516Swpaul 91350703Swpaul sc = device_get_softc(dev); 91450703Swpaul unit = device_get_unit(dev); 91540516Swpaul 91693818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 91793818Sjhb MTX_DEF | MTX_RECURSE); 918117208Simp#ifndef BURN_BRIDGES 91940516Swpaul /* 92040516Swpaul * Handle power management nonsense. 92140516Swpaul */ 92240516Swpaul 92370167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 92470167Swpaul u_int32_t iobase, membase, irq; 92540516Swpaul 92670167Swpaul /* Save important PCI config data. */ 92770167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 92870167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 92970167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 93040516Swpaul 93170167Swpaul /* Reset the power state. */ 93270167Swpaul printf("rl%d: chip is is in D%d power mode " 93370167Swpaul "-- setting to D0\n", unit, 93470167Swpaul pci_get_powerstate(dev)); 93540516Swpaul 93670167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 93740516Swpaul 93870167Swpaul /* Restore PCI config data. */ 93970167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 94070167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 94170167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 94240516Swpaul } 943117208Simp#endif 94440516Swpaul /* 94540516Swpaul * Map control/status registers. 94640516Swpaul */ 94772813Swpaul pci_enable_busmaster(dev); 94840516Swpaul 949109109Sdes rid = RL_RID; 950127135Snjl sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 95150703Swpaul 95250703Swpaul if (sc->rl_res == NULL) { 95350703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 95450703Swpaul error = ENXIO; 95540516Swpaul goto fail; 95640516Swpaul } 95740516Swpaul 958117388Swpaul#ifdef notdef 95969127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 96069127Sroger * unstable when left to autoselect the media 96169127Sroger * The best workaround is to set the device to the required 96269127Sroger * media type or to set it to the 10 Meg speed. 96369127Sroger */ 96469127Sroger 96569127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 966119868Swpaul printf("rl%d: Realtek 8139B detected. Warning, " 967119868Swpaul "this may be unstable in autoselect mode\n", unit); 96869127Sroger } 969117388Swpaul#endif 97069127Sroger 97150703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 97250703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 97350703Swpaul 974112872Snjl /* Allocate interrupt */ 97550703Swpaul rid = 0; 976127135Snjl sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 97750703Swpaul RF_SHAREABLE | RF_ACTIVE); 97850703Swpaul 97950703Swpaul if (sc->rl_irq == NULL) { 98040516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 98150703Swpaul error = ENXIO; 98240516Swpaul goto fail; 98340516Swpaul } 98440516Swpaul 98540516Swpaul /* Reset the adapter. */ 98640516Swpaul rl_reset(sc); 98767931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 98867931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 98968215Swpaul if (rl_did != 0x8129) 99067931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 99140516Swpaul 99240516Swpaul /* 99340516Swpaul * Get station address from the EEPROM. 99440516Swpaul */ 995108729Sjake rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 996108729Sjake for (i = 0; i < 3; i++) { 997108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 998108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 999108729Sjake } 100040516Swpaul 100140516Swpaul sc->rl_unit = unit; 100240516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 100340516Swpaul 100440516Swpaul /* 100540516Swpaul * Now read the exact device type from the EEPROM to find 100640516Swpaul * out if it's an 8129 or 8139. 100740516Swpaul */ 100840516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 100940516Swpaul 1010117388Swpaul t = rl_devs; 1011119868Swpaul sc->rl_type = 0; 1012117388Swpaul while(t->rl_name != NULL) { 1013117388Swpaul if (rl_did == t->rl_did) { 1014117388Swpaul sc->rl_type = t->rl_basetype; 1015117388Swpaul break; 1016117388Swpaul } 1017117388Swpaul t++; 1018117388Swpaul } 1019119868Swpaul 1020119868Swpaul if (sc->rl_type == 0) { 102140516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 102250703Swpaul error = ENXIO; 102340516Swpaul goto fail; 102440516Swpaul } 102540516Swpaul 102681713Swpaul /* 102781713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 102881713Swpaul */ 102981713Swpaul#define RL_NSEG_NEW 32 1030109109Sdes error = bus_dma_tag_create(NULL, /* parent */ 103181713Swpaul 1, 0, /* alignment, boundary */ 103281713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 103381713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 103481713Swpaul NULL, NULL, /* filter, filterarg */ 103581713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1036109109Sdes BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 103781713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1038117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 103981713Swpaul &sc->rl_parent_tag); 1040112872Snjl if (error) 1041112872Snjl goto fail; 104240516Swpaul 104381713Swpaul /* 1044119868Swpaul * Now allocate a tag for the DMA descriptor lists. 1045119868Swpaul * All of our lists are allocated as a contiguous block 1046119868Swpaul * of memory. 104781713Swpaul */ 1048119868Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1049119868Swpaul 1, 0, /* alignment, boundary */ 1050119868Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 1051119868Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 1052119868Swpaul NULL, NULL, /* filter, filterarg */ 1053119868Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1054119868Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1055119868Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1056119868Swpaul NULL, NULL, /* lockfunc, lockarg */ 1057119868Swpaul &sc->rl_tag); 1058112872Snjl if (error) 1059112872Snjl goto fail; 106081713Swpaul 1061119868Swpaul /* 1062119868Swpaul * Now allocate a chunk of DMA-able memory based on the 1063119868Swpaul * tag we just created. 1064119868Swpaul */ 1065119868Swpaul error = bus_dmamem_alloc(sc->rl_tag, 1066119868Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1067119868Swpaul &sc->rl_cdata.rl_rx_dmamap); 1068119868Swpaul 1069119868Swpaul if (error) { 1070119868Swpaul printf("rl%d: no memory for list buffers!\n", unit); 1071119868Swpaul bus_dma_tag_destroy(sc->rl_tag); 1072119868Swpaul sc->rl_tag = NULL; 1073119868Swpaul goto fail; 1074119868Swpaul } 1075119868Swpaul 1076119868Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 1077119868Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1078119868Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1079119868Swpaul 108050703Swpaul /* Do MII setup */ 108150703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 108250703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 108350703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 108450703Swpaul error = ENXIO; 108550703Swpaul goto fail; 108650703Swpaul } 108750703Swpaul 108840516Swpaul ifp = &sc->arpcom.ac_if; 108940516Swpaul ifp->if_softc = sc; 1090121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 109140516Swpaul ifp->if_mtu = ETHERMTU; 109240516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 109340516Swpaul ifp->if_ioctl = rl_ioctl; 1094119868Swpaul ifp->if_start = rl_start; 109540516Swpaul ifp->if_watchdog = rl_watchdog; 109640516Swpaul ifp->if_init = rl_init; 109740516Swpaul ifp->if_baudrate = 10000000; 1098119976Swpaul ifp->if_capabilities = IFCAP_VLAN_MTU; 1099128121Sru#ifdef DEVICE_POLLING 1100128121Sru ifp->if_capabilities |= IFCAP_POLLING; 1101128121Sru#endif 1102119977Swpaul ifp->if_capenable = ifp->if_capabilities; 1103119868Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1104119976Swpaul 1105112872Snjl callout_handle_init(&sc->rl_stat_ch); 1106112872Snjl 110740516Swpaul /* 110863090Sarchie * Call MI attach routine. 110940516Swpaul */ 1110106936Ssam ether_ifattach(ifp, eaddr); 1111106157Simp 1112113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1113106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1114119868Swpaul rl_intr, sc, &sc->rl_intrhand); 1115106157Simp 1116106157Simp if (error) { 1117106157Simp printf("rl%d: couldn't set up irq\n", unit); 1118113609Snjl ether_ifdetach(ifp); 1119106157Simp goto fail; 1120106157Simp } 1121106157Simp 112240516Swpaulfail: 1123112872Snjl if (error) 1124112872Snjl rl_detach(dev); 1125112872Snjl 1126110601Snjl return (error); 112740516Swpaul} 112840516Swpaul 1129113609Snjl/* 1130113609Snjl * Shutdown hardware and free up resources. This can be called any 1131113609Snjl * time after the mutex has been initialized. It is called in both 1132113609Snjl * the error case in attach and the normal detach case so it needs 1133113609Snjl * to be careful about only freeing resources that have actually been 1134113609Snjl * allocated. 1135113609Snjl */ 1136102335Salfredstatic int 1137102335Salfredrl_detach(dev) 113850703Swpaul device_t dev; 113950703Swpaul{ 114050703Swpaul struct rl_softc *sc; 114150703Swpaul struct ifnet *ifp; 114250703Swpaul 114350703Swpaul sc = device_get_softc(dev); 1144112880Sjhb KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 114567087Swpaul RL_LOCK(sc); 114650703Swpaul ifp = &sc->arpcom.ac_if; 114750703Swpaul 1148113609Snjl /* These should only be active if attach succeeded */ 1149113812Simp if (device_is_attached(dev)) { 1150113609Snjl rl_stop(sc); 1151112872Snjl ether_ifdetach(ifp); 1152113609Snjl } 1153113609Snjl if (sc->rl_miibus) 1154112872Snjl device_delete_child(dev, sc->rl_miibus); 1155113609Snjl bus_generic_detach(dev); 115650703Swpaul 1157112872Snjl if (sc->rl_intrhand) 1158112872Snjl bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1159112872Snjl if (sc->rl_irq) 1160112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1161112872Snjl if (sc->rl_res) 1162112872Snjl bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 116350703Swpaul 1164119868Swpaul if (sc->rl_tag) { 1165119868Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1166119868Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1167119868Swpaul sc->rl_cdata.rl_rx_dmamap); 1168119868Swpaul bus_dma_tag_destroy(sc->rl_tag); 1169112872Snjl } 1170112872Snjl if (sc->rl_parent_tag) 1171112872Snjl bus_dma_tag_destroy(sc->rl_parent_tag); 117250703Swpaul 117367087Swpaul RL_UNLOCK(sc); 117467087Swpaul mtx_destroy(&sc->rl_mtx); 117550703Swpaul 117650703Swpaul return(0); 117750703Swpaul} 117850703Swpaul 117940516Swpaul/* 118040516Swpaul * Initialize the transmit descriptors. 118140516Swpaul */ 1182102335Salfredstatic int 1183102335Salfredrl_list_tx_init(sc) 118440516Swpaul struct rl_softc *sc; 118540516Swpaul{ 118640516Swpaul struct rl_chain_data *cd; 118740516Swpaul int i; 118840516Swpaul 118940516Swpaul cd = &sc->rl_cdata; 119040516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 119145633Swpaul cd->rl_tx_chain[i] = NULL; 119248028Swpaul CSR_WRITE_4(sc, 119348028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 119440516Swpaul } 119540516Swpaul 119645633Swpaul sc->rl_cdata.cur_tx = 0; 119745633Swpaul sc->rl_cdata.last_tx = 0; 119840516Swpaul 119940516Swpaul return(0); 120040516Swpaul} 120140516Swpaul 120240516Swpaul/* 120340516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 120440516Swpaul * the higher level protocols. 120540516Swpaul * 120640516Swpaul * You know there's something wrong with a PCI bus-master chip design 120740516Swpaul * when you have to use m_devget(). 120840516Swpaul * 120940516Swpaul * The receive operation is badly documented in the datasheet, so I'll 121040516Swpaul * attempt to document it here. The driver provides a buffer area and 121140516Swpaul * places its base address in the RX buffer start address register. 121240516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 121372645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 121440516Swpaul * of the frame and certain other status bits. Each frame (starting with 121540516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 121640516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 121740516Swpaul * the 'rx status register' mentioned in the datasheet. 121848028Swpaul * 121948028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 122078508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1221109109Sdes * as the offset argument to m_devget(). 122240516Swpaul */ 1223102335Salfredstatic void 1224102335Salfredrl_rxeof(sc) 122540516Swpaul struct rl_softc *sc; 122640516Swpaul{ 1227109109Sdes struct mbuf *m; 1228109109Sdes struct ifnet *ifp; 122940516Swpaul int total_len = 0; 123040516Swpaul u_int32_t rxstat; 123140516Swpaul caddr_t rxbufpos; 123240516Swpaul int wrap = 0; 123340516Swpaul u_int16_t cur_rx; 123440516Swpaul u_int16_t limit; 123540516Swpaul u_int16_t rx_bytes = 0, max_bytes; 123640516Swpaul 1237122689Ssam RL_LOCK_ASSERT(sc); 1238122689Ssam 123940516Swpaul ifp = &sc->arpcom.ac_if; 124040516Swpaul 124181713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1242108729Sjake BUS_DMASYNC_POSTREAD); 124381713Swpaul 124440516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 124540516Swpaul 124640516Swpaul /* Do not try to read past this point. */ 124740516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 124840516Swpaul 124940516Swpaul if (limit < cur_rx) 125040516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 125140516Swpaul else 125240516Swpaul max_bytes = limit - cur_rx; 125340516Swpaul 125442738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 125594883Sluigi#ifdef DEVICE_POLLING 1256102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 125794883Sluigi if (sc->rxcycles <= 0) 125894883Sluigi break; 125994883Sluigi sc->rxcycles--; 126094883Sluigi } 126194883Sluigi#endif /* DEVICE_POLLING */ 126240516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1263108729Sjake rxstat = le32toh(*(u_int32_t *)rxbufpos); 126440516Swpaul 126540516Swpaul /* 126640516Swpaul * Here's a totally undocumented fact for you. When the 126740516Swpaul * RealTek chip is in the process of copying a packet into 126840516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 126940516Swpaul * packet header with this value, you need to stop. The 127040516Swpaul * datasheet makes absolutely no mention of this and 127140516Swpaul * RealTek should be shot for this. 127240516Swpaul */ 127340516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 127440516Swpaul break; 1275109109Sdes 127640516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 127740516Swpaul ifp->if_ierrors++; 127850703Swpaul rl_init(sc); 127950703Swpaul return; 128040516Swpaul } 128140516Swpaul 1282109109Sdes /* No errors; receive the packet. */ 128340516Swpaul total_len = rxstat >> 16; 128440516Swpaul rx_bytes += total_len + 4; 128540516Swpaul 128640516Swpaul /* 128742051Swpaul * XXX The RealTek chip includes the CRC with every 128842051Swpaul * received frame, and there's no way to turn this 128942051Swpaul * behavior off (at least, I can't find anything in 1290109109Sdes * the manual that explains how to do it) so we have 129142051Swpaul * to trim off the CRC manually. 129242051Swpaul */ 129342051Swpaul total_len -= ETHER_CRC_LEN; 129442051Swpaul 129542051Swpaul /* 129640516Swpaul * Avoid trying to read more bytes than we know 129740516Swpaul * the chip has prepared for us. 129840516Swpaul */ 129940516Swpaul if (rx_bytes > max_bytes) 130040516Swpaul break; 130140516Swpaul 130240516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 130340516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 130440516Swpaul 130540516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 130640516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 130740516Swpaul 130840516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 130940516Swpaul 131040516Swpaul if (total_len > wrap) { 131178508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 131278508Sbmilekic NULL); 131340516Swpaul if (m == NULL) { 131440516Swpaul ifp->if_ierrors++; 131552426Swpaul } else { 131640516Swpaul m_copyback(m, wrap, total_len - wrap, 131740516Swpaul sc->rl_cdata.rl_rx_buf); 131848028Swpaul } 131942051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 132040516Swpaul } else { 132178508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 132278508Sbmilekic NULL); 132340516Swpaul if (m == NULL) { 132440516Swpaul ifp->if_ierrors++; 132578508Sbmilekic } 132642051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 132740516Swpaul } 132840516Swpaul 132940516Swpaul /* 133040516Swpaul * Round up to 32-bit boundary. 133140516Swpaul */ 133240516Swpaul cur_rx = (cur_rx + 3) & ~3; 133340516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 133440516Swpaul 133540516Swpaul if (m == NULL) 133640516Swpaul continue; 133740516Swpaul 133840516Swpaul ifp->if_ipackets++; 1339122689Ssam RL_UNLOCK(sc); 1340106936Ssam (*ifp->if_input)(ifp, m); 1341122689Ssam RL_LOCK(sc); 134240516Swpaul } 134340516Swpaul 134440516Swpaul return; 134540516Swpaul} 134640516Swpaul 134740516Swpaul/* 134840516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 134940516Swpaul * the list buffers. 135040516Swpaul */ 1351102335Salfredstatic void 1352102335Salfredrl_txeof(sc) 135340516Swpaul struct rl_softc *sc; 135440516Swpaul{ 135540516Swpaul struct ifnet *ifp; 135640516Swpaul u_int32_t txstat; 135740516Swpaul 135840516Swpaul ifp = &sc->arpcom.ac_if; 135940516Swpaul 136040516Swpaul /* 136140516Swpaul * Go through our tx list and free mbufs for those 136240516Swpaul * frames that have been uploaded. 136340516Swpaul */ 136445633Swpaul do { 1365127783Sru if (RL_LAST_TXMBUF(sc) == NULL) 1366127783Sru break; 136745633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 136845633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 136945633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 137040516Swpaul break; 137140516Swpaul 137245633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 137340516Swpaul 1374127783Sru bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1375127783Sru bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1376127783Sru m_freem(RL_LAST_TXMBUF(sc)); 1377127783Sru RL_LAST_TXMBUF(sc) = NULL; 137845633Swpaul if (txstat & RL_TXSTAT_TX_OK) 137945633Swpaul ifp->if_opackets++; 138045633Swpaul else { 138152426Swpaul int oldthresh; 138245633Swpaul ifp->if_oerrors++; 138345633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 138445633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 138545633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 138652426Swpaul oldthresh = sc->rl_txthresh; 138752426Swpaul /* error recovery */ 138852426Swpaul rl_reset(sc); 138952426Swpaul rl_init(sc); 139052426Swpaul /* 139152426Swpaul * If there was a transmit underrun, 139252426Swpaul * bump the TX threshold. 139352426Swpaul */ 139452426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 139552426Swpaul sc->rl_txthresh = oldthresh + 32; 139652426Swpaul return; 139745633Swpaul } 139845633Swpaul RL_INC(sc->rl_cdata.last_tx); 139945633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 140045633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 140140516Swpaul 1402127783Sru if (RL_LAST_TXMBUF(sc) == NULL) 1403127783Sru ifp->if_timer = 0; 1404127783Sru else if (ifp->if_timer == 0) 1405127783Sru ifp->if_timer = 5; 140699165Sluigi 140750703Swpaul return; 140850703Swpaul} 140940516Swpaul 1410102335Salfredstatic void 1411102335Salfredrl_tick(xsc) 141250703Swpaul void *xsc; 141350703Swpaul{ 141450703Swpaul struct rl_softc *sc; 141550703Swpaul struct mii_data *mii; 141650703Swpaul 141750703Swpaul sc = xsc; 141867087Swpaul RL_LOCK(sc); 141950703Swpaul mii = device_get_softc(sc->rl_miibus); 142050703Swpaul 142150703Swpaul mii_tick(mii); 142250703Swpaul 142350703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 142467087Swpaul RL_UNLOCK(sc); 142550703Swpaul 142640516Swpaul return; 142740516Swpaul} 142840516Swpaul 142994883Sluigi#ifdef DEVICE_POLLING 143094883Sluigistatic void 143194883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 143294883Sluigi{ 143394883Sluigi struct rl_softc *sc = ifp->if_softc; 143494883Sluigi 143594883Sluigi RL_LOCK(sc); 1436128121Sru if (!(ifp->if_capenable & IFCAP_POLLING)) { 1437128121Sru ether_poll_deregister(ifp); 1438128121Sru cmd = POLL_DEREGISTER; 1439128121Sru } 144094883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1441119868Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 144294883Sluigi goto done; 144394883Sluigi } 144494883Sluigi 144594883Sluigi sc->rxcycles = count; 1446119868Swpaul rl_rxeof(sc); 1447119868Swpaul rl_txeof(sc); 144894883Sluigi if (ifp->if_snd.ifq_head != NULL) 1449119868Swpaul rl_start(ifp); 145094883Sluigi 145194883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 145294883Sluigi u_int16_t status; 145394883Sluigi 145494883Sluigi status = CSR_READ_2(sc, RL_ISR); 1455100957Sjhb if (status == 0xffff) 1456100957Sjhb goto done; 145794883Sluigi if (status) 145894883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 145994883Sluigi 146094883Sluigi /* 146194883Sluigi * XXX check behaviour on receiver stalls. 146294883Sluigi */ 146394883Sluigi 146494883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 146594883Sluigi rl_reset(sc); 146694883Sluigi rl_init(sc); 146794883Sluigi } 146894883Sluigi } 146994883Sluigidone: 147094883Sluigi RL_UNLOCK(sc); 147194883Sluigi} 147294883Sluigi#endif /* DEVICE_POLLING */ 147394883Sluigi 1474102335Salfredstatic void 1475102335Salfredrl_intr(arg) 147640516Swpaul void *arg; 147740516Swpaul{ 147840516Swpaul struct rl_softc *sc; 147940516Swpaul struct ifnet *ifp; 148040516Swpaul u_int16_t status; 148140516Swpaul 148240516Swpaul sc = arg; 148386822Siwasaki 148486822Siwasaki if (sc->suspended) { 148586822Siwasaki return; 148686822Siwasaki } 148786822Siwasaki 148867087Swpaul RL_LOCK(sc); 148940516Swpaul ifp = &sc->arpcom.ac_if; 149040516Swpaul 149194883Sluigi#ifdef DEVICE_POLLING 1492102052Ssobomax if (ifp->if_flags & IFF_POLLING) 149394883Sluigi goto done; 1494128121Sru if ((ifp->if_capenable & IFCAP_POLLING) && 1495128121Sru ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 149694883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 149794883Sluigi rl_poll(ifp, 0, 1); 149894883Sluigi goto done; 149994883Sluigi } 150094883Sluigi#endif /* DEVICE_POLLING */ 150140516Swpaul 150240516Swpaul for (;;) { 150340516Swpaul 150440516Swpaul status = CSR_READ_2(sc, RL_ISR); 1505100957Sjhb /* If the card has gone away the read returns 0xffff. */ 1506100957Sjhb if (status == 0xffff) 1507100957Sjhb break; 150840516Swpaul if (status) 150940516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 151040516Swpaul 151140516Swpaul if ((status & RL_INTRS) == 0) 151240516Swpaul break; 151340516Swpaul 151440516Swpaul if (status & RL_ISR_RX_OK) 151540516Swpaul rl_rxeof(sc); 151640516Swpaul 151740516Swpaul if (status & RL_ISR_RX_ERR) 151840516Swpaul rl_rxeof(sc); 151940516Swpaul 152045633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 152140516Swpaul rl_txeof(sc); 152240516Swpaul 152340516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 152440516Swpaul rl_reset(sc); 152540516Swpaul rl_init(sc); 152640516Swpaul } 152740516Swpaul 152840516Swpaul } 152940516Swpaul 153052426Swpaul if (ifp->if_snd.ifq_head != NULL) 1531119868Swpaul rl_start(ifp); 153240516Swpaul 153394883Sluigi#ifdef DEVICE_POLLING 153494883Sluigidone: 153594883Sluigi#endif 153667087Swpaul RL_UNLOCK(sc); 153767087Swpaul 153840516Swpaul return; 153940516Swpaul} 154040516Swpaul 154140516Swpaul/* 154240516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 154340516Swpaul * pointers to the fragment pointers. 154440516Swpaul */ 1545102335Salfredstatic int 1546102335Salfredrl_encap(sc, m_head) 154740516Swpaul struct rl_softc *sc; 154840516Swpaul struct mbuf *m_head; 154940516Swpaul{ 155041243Swpaul struct mbuf *m_new = NULL; 155140516Swpaul 155240516Swpaul /* 155345633Swpaul * The RealTek is brain damaged and wants longword-aligned 155445633Swpaul * TX buffers, plus we can only have one fragment buffer 155545633Swpaul * per packet. We have to copy pretty much all the time. 155640516Swpaul */ 1557112839Ssilby m_new = m_defrag(m_head, M_DONTWAIT); 155840516Swpaul 1559113496Ssilby if (m_new == NULL) { 1560113496Ssilby m_freem(m_head); 156141243Swpaul return(1); 1562113496Ssilby } 156341243Swpaul m_head = m_new; 156440516Swpaul 156540516Swpaul /* Pad frames to at least 60 bytes. */ 156641243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 156755058Swpaul /* 156855058Swpaul * Make security concious people happy: zero out the 156955058Swpaul * bytes in the pad area, since we don't know what 157055058Swpaul * this mbuf cluster buffer's previous user might 157155058Swpaul * have left in it. 1572109109Sdes */ 157355058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 157455058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 157540516Swpaul m_head->m_pkthdr.len += 157652426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 157741243Swpaul m_head->m_len = m_head->m_pkthdr.len; 157841243Swpaul } 157940516Swpaul 158045633Swpaul RL_CUR_TXMBUF(sc) = m_head; 158140516Swpaul 158240516Swpaul return(0); 158340516Swpaul} 158440516Swpaul 158540516Swpaul/* 158640516Swpaul * Main transmit routine. 158740516Swpaul */ 158840516Swpaul 1589102335Salfredstatic void 1590102335Salfredrl_start(ifp) 159140516Swpaul struct ifnet *ifp; 159240516Swpaul{ 159340516Swpaul struct rl_softc *sc; 159440516Swpaul struct mbuf *m_head = NULL; 159540516Swpaul 159640516Swpaul sc = ifp->if_softc; 159767087Swpaul RL_LOCK(sc); 159840516Swpaul 159945633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 160040516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 160140516Swpaul if (m_head == NULL) 160240516Swpaul break; 160340516Swpaul 160458801Swpaul if (rl_encap(sc, m_head)) { 160558801Swpaul break; 160658801Swpaul } 160740516Swpaul 160840516Swpaul /* 160940516Swpaul * If there's a BPF listener, bounce a copy of this frame 161040516Swpaul * to him. 161140516Swpaul */ 1612106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 161351583Swpaul 161440516Swpaul /* 161540516Swpaul * Transmit the frame. 1616109109Sdes */ 161781713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 161881713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 161981713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 1620119868Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 162181713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 162281713Swpaul BUS_DMASYNC_PREREAD); 162345633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 162452426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 162552426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 162645633Swpaul 162745633Swpaul RL_INC(sc->rl_cdata.cur_tx); 1628113237Ssilby 1629113237Ssilby /* 1630113237Ssilby * Set a timeout in case the chip goes out to lunch. 1631113237Ssilby */ 1632113237Ssilby ifp->if_timer = 5; 163340516Swpaul } 163440516Swpaul 163540516Swpaul /* 163645633Swpaul * We broke out of the loop because all our TX slots are 163745633Swpaul * full. Mark the NIC as busy until it drains some of the 163845633Swpaul * packets from the queue. 163945633Swpaul */ 164045633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 164145633Swpaul ifp->if_flags |= IFF_OACTIVE; 164245633Swpaul 164367087Swpaul RL_UNLOCK(sc); 164440516Swpaul 164540516Swpaul return; 164640516Swpaul} 164740516Swpaul 1648102335Salfredstatic void 1649102335Salfredrl_init(xsc) 165040516Swpaul void *xsc; 165140516Swpaul{ 165240516Swpaul struct rl_softc *sc = xsc; 165340516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 165450703Swpaul struct mii_data *mii; 165540516Swpaul u_int32_t rxcfg = 0; 165640516Swpaul 165767087Swpaul RL_LOCK(sc); 165850703Swpaul mii = device_get_softc(sc->rl_miibus); 165940516Swpaul 166040516Swpaul /* 166140516Swpaul * Cancel pending I/O and free all RX/TX buffers. 166240516Swpaul */ 166340516Swpaul rl_stop(sc); 166440516Swpaul 1665117029Swpaul /* 1666117029Swpaul * Init our MAC address. Even though the chipset 1667117029Swpaul * documentation doesn't mention it, we need to enter "Config 1668117029Swpaul * register write enable" mode to modify the ID registers. 1669117029Swpaul */ 1670117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1671119738Stmm CSR_WRITE_STREAM_4(sc, RL_IDR0, 1672119738Stmm *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1673119738Stmm CSR_WRITE_STREAM_4(sc, RL_IDR4, 1674119738Stmm *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1675117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 167640516Swpaul 1677119868Swpaul /* Init the RX buffer pointer register. */ 1678119868Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1679119868Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1680119868Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1681119868Swpaul BUS_DMASYNC_PREWRITE); 168240516Swpaul 1683119868Swpaul /* Init TX descriptors. */ 1684119868Swpaul rl_list_tx_init(sc); 168540516Swpaul 168640516Swpaul /* 168740516Swpaul * Enable transmit and receive. 168840516Swpaul */ 168940516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 169040516Swpaul 169140516Swpaul /* 169245633Swpaul * Set the initial TX and RX configuration. 169340516Swpaul */ 169445633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 169540516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 169640516Swpaul 169740516Swpaul /* Set the individual bit to receive frames for this host only. */ 169840516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 169940516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 170040516Swpaul 170140516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 170240516Swpaul if (ifp->if_flags & IFF_PROMISC) { 170340516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 170440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 170540516Swpaul } else { 170640516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 170740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 170840516Swpaul } 170940516Swpaul 171040516Swpaul /* 171140516Swpaul * Set capture broadcast bit to capture broadcast frames. 171240516Swpaul */ 171340516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 171440516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 171540516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 171640516Swpaul } else { 171740516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 171840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 171940516Swpaul } 172040516Swpaul 172140516Swpaul /* 172240516Swpaul * Program the multicast filter, if necessary. 172340516Swpaul */ 172440516Swpaul rl_setmulti(sc); 172540516Swpaul 172694883Sluigi#ifdef DEVICE_POLLING 172740516Swpaul /* 172894883Sluigi * Disable interrupts if we are polling. 172994883Sluigi */ 1730102052Ssobomax if (ifp->if_flags & IFF_POLLING) 173194883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 173294883Sluigi else /* otherwise ... */ 173394883Sluigi#endif /* DEVICE_POLLING */ 173494883Sluigi /* 173540516Swpaul * Enable interrupts. 173640516Swpaul */ 1737119868Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 173840516Swpaul 173952426Swpaul /* Set initial TX threshold */ 174052426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 174152426Swpaul 174240516Swpaul /* Start RX/TX process. */ 174340516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1744119868Swpaul 174540516Swpaul /* Enable receiver and transmitter. */ 174640516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 174740516Swpaul 174850703Swpaul mii_mediachg(mii); 174940516Swpaul 175040516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 175140516Swpaul 175240516Swpaul ifp->if_flags |= IFF_RUNNING; 175340516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 175440516Swpaul 175550703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 175667087Swpaul RL_UNLOCK(sc); 175750703Swpaul 175840516Swpaul return; 175940516Swpaul} 176040516Swpaul 176140516Swpaul/* 176240516Swpaul * Set media options. 176340516Swpaul */ 1764102335Salfredstatic int 1765102335Salfredrl_ifmedia_upd(ifp) 176640516Swpaul struct ifnet *ifp; 176740516Swpaul{ 176840516Swpaul struct rl_softc *sc; 176950703Swpaul struct mii_data *mii; 177040516Swpaul 177140516Swpaul sc = ifp->if_softc; 177250703Swpaul mii = device_get_softc(sc->rl_miibus); 177350703Swpaul mii_mediachg(mii); 177440516Swpaul 177540516Swpaul return(0); 177640516Swpaul} 177740516Swpaul 177840516Swpaul/* 177940516Swpaul * Report current media status. 178040516Swpaul */ 1781102335Salfredstatic void 1782102335Salfredrl_ifmedia_sts(ifp, ifmr) 178340516Swpaul struct ifnet *ifp; 178440516Swpaul struct ifmediareq *ifmr; 178540516Swpaul{ 178640516Swpaul struct rl_softc *sc; 178750703Swpaul struct mii_data *mii; 178840516Swpaul 178940516Swpaul sc = ifp->if_softc; 179050703Swpaul mii = device_get_softc(sc->rl_miibus); 179140516Swpaul 179250703Swpaul mii_pollstat(mii); 179350703Swpaul ifmr->ifm_active = mii->mii_media_active; 179450703Swpaul ifmr->ifm_status = mii->mii_media_status; 179540516Swpaul 179640516Swpaul return; 179740516Swpaul} 179840516Swpaul 1799102335Salfredstatic int 1800102335Salfredrl_ioctl(ifp, command, data) 180140516Swpaul struct ifnet *ifp; 180240516Swpaul u_long command; 180340516Swpaul caddr_t data; 180440516Swpaul{ 180540516Swpaul struct rl_softc *sc = ifp->if_softc; 180640516Swpaul struct ifreq *ifr = (struct ifreq *) data; 180750703Swpaul struct mii_data *mii; 180867087Swpaul int error = 0; 180940516Swpaul 181067087Swpaul RL_LOCK(sc); 181140516Swpaul 181240516Swpaul switch(command) { 181340516Swpaul case SIOCSIFFLAGS: 181440516Swpaul if (ifp->if_flags & IFF_UP) { 181540516Swpaul rl_init(sc); 181640516Swpaul } else { 181740516Swpaul if (ifp->if_flags & IFF_RUNNING) 181840516Swpaul rl_stop(sc); 181940516Swpaul } 182040516Swpaul error = 0; 182140516Swpaul break; 182240516Swpaul case SIOCADDMULTI: 182340516Swpaul case SIOCDELMULTI: 182440516Swpaul rl_setmulti(sc); 182540516Swpaul error = 0; 182640516Swpaul break; 182740516Swpaul case SIOCGIFMEDIA: 182840516Swpaul case SIOCSIFMEDIA: 182950703Swpaul mii = device_get_softc(sc->rl_miibus); 183050703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 183140516Swpaul break; 1832128121Sru case SIOCSIFCAP: 1833129633Syar ifp->if_capenable &= ~IFCAP_POLLING; 1834129633Syar ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1835128121Sru break; 183640516Swpaul default: 1837106936Ssam error = ether_ioctl(ifp, command, data); 183840516Swpaul break; 183940516Swpaul } 184040516Swpaul 184167087Swpaul RL_UNLOCK(sc); 184240516Swpaul 184340516Swpaul return(error); 184440516Swpaul} 184540516Swpaul 1846102335Salfredstatic void 1847102335Salfredrl_watchdog(ifp) 184840516Swpaul struct ifnet *ifp; 184940516Swpaul{ 185040516Swpaul struct rl_softc *sc; 185140516Swpaul 185240516Swpaul sc = ifp->if_softc; 185367087Swpaul RL_LOCK(sc); 185440516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 185540516Swpaul ifp->if_oerrors++; 185650703Swpaul 1857119868Swpaul rl_txeof(sc); 1858119868Swpaul rl_rxeof(sc); 185940516Swpaul rl_init(sc); 186067087Swpaul RL_UNLOCK(sc); 186140516Swpaul 186240516Swpaul return; 186340516Swpaul} 186440516Swpaul 186540516Swpaul/* 186640516Swpaul * Stop the adapter and free any mbufs allocated to the 186740516Swpaul * RX and TX lists. 186840516Swpaul */ 1869102335Salfredstatic void 1870102335Salfredrl_stop(sc) 187140516Swpaul struct rl_softc *sc; 187240516Swpaul{ 187340516Swpaul register int i; 187440516Swpaul struct ifnet *ifp; 187540516Swpaul 187667087Swpaul RL_LOCK(sc); 187740516Swpaul ifp = &sc->arpcom.ac_if; 187840516Swpaul ifp->if_timer = 0; 187940516Swpaul 188050703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 188194883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 188294883Sluigi#ifdef DEVICE_POLLING 188394883Sluigi ether_poll_deregister(ifp); 188494883Sluigi#endif /* DEVICE_POLLING */ 188550703Swpaul 188640516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 188740516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 1888119868Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 188940516Swpaul 1890119868Swpaul /* 1891119868Swpaul * Free the TX list buffers. 1892119868Swpaul */ 1893119868Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 1894119868Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1895119868Swpaul bus_dmamap_unload(sc->rl_tag, 1896119868Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 1897119868Swpaul bus_dmamap_destroy(sc->rl_tag, 1898119868Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 1899119868Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 1900119868Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 1901124816Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)), 1902124816Swpaul 0x0000000); 190340516Swpaul } 190440516Swpaul } 190540516Swpaul 190667087Swpaul RL_UNLOCK(sc); 190740516Swpaul return; 190840516Swpaul} 190940516Swpaul 191040516Swpaul/* 191186822Siwasaki * Device suspend routine. Stop the interface and save some PCI 191286822Siwasaki * settings in case the BIOS doesn't restore them properly on 191386822Siwasaki * resume. 191486822Siwasaki */ 1915102335Salfredstatic int 1916102335Salfredrl_suspend(dev) 191786822Siwasaki device_t dev; 191886822Siwasaki{ 191986822Siwasaki register int i; 192086822Siwasaki struct rl_softc *sc; 192186822Siwasaki 192286822Siwasaki sc = device_get_softc(dev); 192386822Siwasaki 192486822Siwasaki rl_stop(sc); 192586822Siwasaki 192686822Siwasaki for (i = 0; i < 5; i++) 1927119868Swpaul sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 192886822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 192986822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 193086822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 193186822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 193286822Siwasaki 193386822Siwasaki sc->suspended = 1; 193486822Siwasaki 193586822Siwasaki return (0); 193686822Siwasaki} 193786822Siwasaki 193886822Siwasaki/* 193986822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 194086822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 194186822Siwasaki * appropriate. 194286822Siwasaki */ 1943102335Salfredstatic int 1944102335Salfredrl_resume(dev) 194586822Siwasaki device_t dev; 194686822Siwasaki{ 194786822Siwasaki register int i; 194886822Siwasaki struct rl_softc *sc; 194986822Siwasaki struct ifnet *ifp; 195086822Siwasaki 195186822Siwasaki sc = device_get_softc(dev); 195286822Siwasaki ifp = &sc->arpcom.ac_if; 195386822Siwasaki 195486822Siwasaki /* better way to do this? */ 195586822Siwasaki for (i = 0; i < 5; i++) 1956119868Swpaul pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 195786822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 195886822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 195986822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 196086822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 196186822Siwasaki 196286822Siwasaki /* reenable busmastering */ 196386822Siwasaki pci_enable_busmaster(dev); 196486822Siwasaki pci_enable_io(dev, RL_RES); 196586822Siwasaki 1966109109Sdes /* reinitialize interface if necessary */ 1967109109Sdes if (ifp->if_flags & IFF_UP) 1968109109Sdes rl_init(sc); 196986822Siwasaki 197086822Siwasaki sc->suspended = 0; 197186822Siwasaki 197286822Siwasaki return (0); 197386822Siwasaki} 197486822Siwasaki 197586822Siwasaki/* 197640516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 197740516Swpaul * get confused by errant DMAs when rebooting. 197840516Swpaul */ 1979102335Salfredstatic void 1980102335Salfredrl_shutdown(dev) 198150703Swpaul device_t dev; 198240516Swpaul{ 198350703Swpaul struct rl_softc *sc; 198440516Swpaul 198550703Swpaul sc = device_get_softc(dev); 198650703Swpaul 198740516Swpaul rl_stop(sc); 198840516Swpaul 198940516Swpaul return; 199040516Swpaul} 1991