if_rl.c revision 127135
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 127135 2004-03-17 17:50:55Z njl $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/endian.h> 88#include <sys/systm.h> 89#include <sys/sockio.h> 90#include <sys/mbuf.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94 95#include <net/if.h> 96#include <net/if_arp.h> 97#include <net/ethernet.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100 101#include <net/bpf.h> 102 103#include <machine/bus_pio.h> 104#include <machine/bus_memio.h> 105#include <machine/bus.h> 106#include <machine/resource.h> 107#include <sys/bus.h> 108#include <sys/rman.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116MODULE_DEPEND(rl, pci, 1, 1, 1); 117MODULE_DEPEND(rl, ether, 1, 1, 1); 118MODULE_DEPEND(rl, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123/* 124 * Default to using PIO access for this driver. On SMP systems, 125 * there appear to be problems with memory mapped mode: it looks like 126 * doing too many memory mapped access back to back in rapid succession 127 * can hang the bus. I'm inclined to blame this on crummy design/construction 128 * on the part of RealTek. Memory mapped mode does appear to work on 129 * uniprocessor systems though. 130 */ 131#define RL_USEIOSPACE 132 133#include <pci/if_rlreg.h> 134 135/* 136 * Various supported device vendors/types and their names. 137 */ 138static struct rl_type rl_devs[] = { 139 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 140 "RealTek 8129 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 142 "RealTek 8139 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 144 "RealTek 8139 10/100BaseTX CardBus" }, 145 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 146 "RealTek 8100 10/100BaseTX" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 154 "D-Link DFE-530TX+ 10/100BaseTX" }, 155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 156 "D-Link DFE-690TXD 10/100BaseTX" }, 157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 158 "Nortel Networks 10/100BaseTX" }, 159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 160 "Corega FEther CB-TXD" }, 161 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 162 "Corega FEtherII CB-TXD" }, 163 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 164 "Peppercon AG ROL-F" }, 165 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 166 "Planex FNW-3800-TX" }, 167 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 168 "Compaq HNE-300" }, 169 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 170 "LevelOne FPC-0106TX" }, 171 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 172 "Edimax EP-4103DL CardBus" }, 173 { 0, 0, 0, NULL } 174}; 175 176static int rl_probe (device_t); 177static int rl_attach (device_t); 178static int rl_detach (device_t); 179 180static int rl_encap (struct rl_softc *, struct mbuf * ); 181 182static void rl_rxeof (struct rl_softc *); 183static void rl_txeof (struct rl_softc *); 184static void rl_intr (void *); 185static void rl_tick (void *); 186static void rl_start (struct ifnet *); 187static int rl_ioctl (struct ifnet *, u_long, caddr_t); 188static void rl_init (void *); 189static void rl_stop (struct rl_softc *); 190static void rl_watchdog (struct ifnet *); 191static int rl_suspend (device_t); 192static int rl_resume (device_t); 193static void rl_shutdown (device_t); 194static int rl_ifmedia_upd (struct ifnet *); 195static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 196 197static void rl_eeprom_putbyte (struct rl_softc *, int); 198static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 199static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 200static void rl_mii_sync (struct rl_softc *); 201static void rl_mii_send (struct rl_softc *, u_int32_t, int); 202static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 203static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 204 205static int rl_miibus_readreg (device_t, int, int); 206static int rl_miibus_writereg (device_t, int, int, int); 207static void rl_miibus_statchg (device_t); 208 209static uint32_t rl_mchash (const uint8_t *); 210static void rl_setmulti (struct rl_softc *); 211static void rl_reset (struct rl_softc *); 212static int rl_list_tx_init (struct rl_softc *); 213 214static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 215static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 216 217#ifdef RL_USEIOSPACE 218#define RL_RES SYS_RES_IOPORT 219#define RL_RID RL_PCI_LOIO 220#else 221#define RL_RES SYS_RES_MEMORY 222#define RL_RID RL_PCI_LOMEM 223#endif 224 225static device_method_t rl_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_probe, rl_probe), 228 DEVMETHOD(device_attach, rl_attach), 229 DEVMETHOD(device_detach, rl_detach), 230 DEVMETHOD(device_suspend, rl_suspend), 231 DEVMETHOD(device_resume, rl_resume), 232 DEVMETHOD(device_shutdown, rl_shutdown), 233 234 /* bus interface */ 235 DEVMETHOD(bus_print_child, bus_generic_print_child), 236 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 237 238 /* MII interface */ 239 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 240 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 241 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 242 243 { 0, 0 } 244}; 245 246static driver_t rl_driver = { 247 "rl", 248 rl_methods, 249 sizeof(struct rl_softc) 250}; 251 252static devclass_t rl_devclass; 253 254DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 255DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 256DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 257 258#define EE_SET(x) \ 259 CSR_WRITE_1(sc, RL_EECMD, \ 260 CSR_READ_1(sc, RL_EECMD) | x) 261 262#define EE_CLR(x) \ 263 CSR_WRITE_1(sc, RL_EECMD, \ 264 CSR_READ_1(sc, RL_EECMD) & ~x) 265 266static void 267rl_dma_map_rxbuf(arg, segs, nseg, error) 268 void *arg; 269 bus_dma_segment_t *segs; 270 int nseg, error; 271{ 272 struct rl_softc *sc; 273 274 sc = arg; 275 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 276 277 return; 278} 279 280static void 281rl_dma_map_txbuf(arg, segs, nseg, error) 282 void *arg; 283 bus_dma_segment_t *segs; 284 int nseg, error; 285{ 286 struct rl_softc *sc; 287 288 sc = arg; 289 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 290 291 return; 292} 293 294/* 295 * Send a read command and address to the EEPROM, check for ACK. 296 */ 297static void 298rl_eeprom_putbyte(sc, addr) 299 struct rl_softc *sc; 300 int addr; 301{ 302 register int d, i; 303 304 d = addr | sc->rl_eecmd_read; 305 306 /* 307 * Feed in each bit and strobe the clock. 308 */ 309 for (i = 0x400; i; i >>= 1) { 310 if (d & i) { 311 EE_SET(RL_EE_DATAIN); 312 } else { 313 EE_CLR(RL_EE_DATAIN); 314 } 315 DELAY(100); 316 EE_SET(RL_EE_CLK); 317 DELAY(150); 318 EE_CLR(RL_EE_CLK); 319 DELAY(100); 320 } 321 322 return; 323} 324 325/* 326 * Read a word of data stored in the EEPROM at address 'addr.' 327 */ 328static void 329rl_eeprom_getword(sc, addr, dest) 330 struct rl_softc *sc; 331 int addr; 332 u_int16_t *dest; 333{ 334 register int i; 335 u_int16_t word = 0; 336 337 /* Enter EEPROM access mode. */ 338 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 339 340 /* 341 * Send address of word we want to read. 342 */ 343 rl_eeprom_putbyte(sc, addr); 344 345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 346 347 /* 348 * Start reading bits from EEPROM. 349 */ 350 for (i = 0x8000; i; i >>= 1) { 351 EE_SET(RL_EE_CLK); 352 DELAY(100); 353 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 354 word |= i; 355 EE_CLR(RL_EE_CLK); 356 DELAY(100); 357 } 358 359 /* Turn off EEPROM access mode. */ 360 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 361 362 *dest = word; 363 364 return; 365} 366 367/* 368 * Read a sequence of words from the EEPROM. 369 */ 370static void 371rl_read_eeprom(sc, dest, off, cnt, swap) 372 struct rl_softc *sc; 373 caddr_t dest; 374 int off; 375 int cnt; 376 int swap; 377{ 378 int i; 379 u_int16_t word = 0, *ptr; 380 381 for (i = 0; i < cnt; i++) { 382 rl_eeprom_getword(sc, off + i, &word); 383 ptr = (u_int16_t *)(dest + (i * 2)); 384 if (swap) 385 *ptr = ntohs(word); 386 else 387 *ptr = word; 388 } 389 390 return; 391} 392 393 394/* 395 * MII access routines are provided for the 8129, which 396 * doesn't have a built-in PHY. For the 8139, we fake things 397 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 398 * direct access PHY registers. 399 */ 400#define MII_SET(x) \ 401 CSR_WRITE_1(sc, RL_MII, \ 402 CSR_READ_1(sc, RL_MII) | (x)) 403 404#define MII_CLR(x) \ 405 CSR_WRITE_1(sc, RL_MII, \ 406 CSR_READ_1(sc, RL_MII) & ~(x)) 407 408/* 409 * Sync the PHYs by setting data bit and strobing the clock 32 times. 410 */ 411static void 412rl_mii_sync(sc) 413 struct rl_softc *sc; 414{ 415 register int i; 416 417 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 418 419 for (i = 0; i < 32; i++) { 420 MII_SET(RL_MII_CLK); 421 DELAY(1); 422 MII_CLR(RL_MII_CLK); 423 DELAY(1); 424 } 425 426 return; 427} 428 429/* 430 * Clock a series of bits through the MII. 431 */ 432static void 433rl_mii_send(sc, bits, cnt) 434 struct rl_softc *sc; 435 u_int32_t bits; 436 int cnt; 437{ 438 int i; 439 440 MII_CLR(RL_MII_CLK); 441 442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 443 if (bits & i) { 444 MII_SET(RL_MII_DATAOUT); 445 } else { 446 MII_CLR(RL_MII_DATAOUT); 447 } 448 DELAY(1); 449 MII_CLR(RL_MII_CLK); 450 DELAY(1); 451 MII_SET(RL_MII_CLK); 452 } 453} 454 455/* 456 * Read an PHY register through the MII. 457 */ 458static int 459rl_mii_readreg(sc, frame) 460 struct rl_softc *sc; 461 struct rl_mii_frame *frame; 462 463{ 464 int i, ack; 465 466 RL_LOCK(sc); 467 468 /* 469 * Set up frame for RX. 470 */ 471 frame->mii_stdelim = RL_MII_STARTDELIM; 472 frame->mii_opcode = RL_MII_READOP; 473 frame->mii_turnaround = 0; 474 frame->mii_data = 0; 475 476 CSR_WRITE_2(sc, RL_MII, 0); 477 478 /* 479 * Turn on data xmit. 480 */ 481 MII_SET(RL_MII_DIR); 482 483 rl_mii_sync(sc); 484 485 /* 486 * Send command/address info. 487 */ 488 rl_mii_send(sc, frame->mii_stdelim, 2); 489 rl_mii_send(sc, frame->mii_opcode, 2); 490 rl_mii_send(sc, frame->mii_phyaddr, 5); 491 rl_mii_send(sc, frame->mii_regaddr, 5); 492 493 /* Idle bit */ 494 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 495 DELAY(1); 496 MII_SET(RL_MII_CLK); 497 DELAY(1); 498 499 /* Turn off xmit. */ 500 MII_CLR(RL_MII_DIR); 501 502 /* Check for ack */ 503 MII_CLR(RL_MII_CLK); 504 DELAY(1); 505 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 506 MII_SET(RL_MII_CLK); 507 DELAY(1); 508 509 /* 510 * Now try reading data bits. If the ack failed, we still 511 * need to clock through 16 cycles to keep the PHY(s) in sync. 512 */ 513 if (ack) { 514 for(i = 0; i < 16; i++) { 515 MII_CLR(RL_MII_CLK); 516 DELAY(1); 517 MII_SET(RL_MII_CLK); 518 DELAY(1); 519 } 520 goto fail; 521 } 522 523 for (i = 0x8000; i; i >>= 1) { 524 MII_CLR(RL_MII_CLK); 525 DELAY(1); 526 if (!ack) { 527 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 528 frame->mii_data |= i; 529 DELAY(1); 530 } 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 } 534 535fail: 536 537 MII_CLR(RL_MII_CLK); 538 DELAY(1); 539 MII_SET(RL_MII_CLK); 540 DELAY(1); 541 542 RL_UNLOCK(sc); 543 544 if (ack) 545 return(1); 546 return(0); 547} 548 549/* 550 * Write to a PHY register through the MII. 551 */ 552static int 553rl_mii_writereg(sc, frame) 554 struct rl_softc *sc; 555 struct rl_mii_frame *frame; 556 557{ 558 RL_LOCK(sc); 559 560 /* 561 * Set up frame for TX. 562 */ 563 564 frame->mii_stdelim = RL_MII_STARTDELIM; 565 frame->mii_opcode = RL_MII_WRITEOP; 566 frame->mii_turnaround = RL_MII_TURNAROUND; 567 568 /* 569 * Turn on data output. 570 */ 571 MII_SET(RL_MII_DIR); 572 573 rl_mii_sync(sc); 574 575 rl_mii_send(sc, frame->mii_stdelim, 2); 576 rl_mii_send(sc, frame->mii_opcode, 2); 577 rl_mii_send(sc, frame->mii_phyaddr, 5); 578 rl_mii_send(sc, frame->mii_regaddr, 5); 579 rl_mii_send(sc, frame->mii_turnaround, 2); 580 rl_mii_send(sc, frame->mii_data, 16); 581 582 /* Idle bit. */ 583 MII_SET(RL_MII_CLK); 584 DELAY(1); 585 MII_CLR(RL_MII_CLK); 586 DELAY(1); 587 588 /* 589 * Turn off xmit. 590 */ 591 MII_CLR(RL_MII_DIR); 592 593 RL_UNLOCK(sc); 594 595 return(0); 596} 597 598static int 599rl_miibus_readreg(dev, phy, reg) 600 device_t dev; 601 int phy, reg; 602{ 603 struct rl_softc *sc; 604 struct rl_mii_frame frame; 605 u_int16_t rval = 0; 606 u_int16_t rl8139_reg = 0; 607 608 sc = device_get_softc(dev); 609 RL_LOCK(sc); 610 611 if (sc->rl_type == RL_8139) { 612 /* Pretend the internal PHY is only at address 0 */ 613 if (phy) { 614 RL_UNLOCK(sc); 615 return(0); 616 } 617 switch(reg) { 618 case MII_BMCR: 619 rl8139_reg = RL_BMCR; 620 break; 621 case MII_BMSR: 622 rl8139_reg = RL_BMSR; 623 break; 624 case MII_ANAR: 625 rl8139_reg = RL_ANAR; 626 break; 627 case MII_ANER: 628 rl8139_reg = RL_ANER; 629 break; 630 case MII_ANLPAR: 631 rl8139_reg = RL_LPAR; 632 break; 633 case MII_PHYIDR1: 634 case MII_PHYIDR2: 635 RL_UNLOCK(sc); 636 return(0); 637 /* 638 * Allow the rlphy driver to read the media status 639 * register. If we have a link partner which does not 640 * support NWAY, this is the register which will tell 641 * us the results of parallel detection. 642 */ 643 case RL_MEDIASTAT: 644 rval = CSR_READ_1(sc, RL_MEDIASTAT); 645 RL_UNLOCK(sc); 646 return(rval); 647 default: 648 printf("rl%d: bad phy register\n", sc->rl_unit); 649 RL_UNLOCK(sc); 650 return(0); 651 } 652 rval = CSR_READ_2(sc, rl8139_reg); 653 RL_UNLOCK(sc); 654 return(rval); 655 } 656 657 bzero((char *)&frame, sizeof(frame)); 658 659 frame.mii_phyaddr = phy; 660 frame.mii_regaddr = reg; 661 rl_mii_readreg(sc, &frame); 662 RL_UNLOCK(sc); 663 664 return(frame.mii_data); 665} 666 667static int 668rl_miibus_writereg(dev, phy, reg, data) 669 device_t dev; 670 int phy, reg, data; 671{ 672 struct rl_softc *sc; 673 struct rl_mii_frame frame; 674 u_int16_t rl8139_reg = 0; 675 676 sc = device_get_softc(dev); 677 RL_LOCK(sc); 678 679 if (sc->rl_type == RL_8139) { 680 /* Pretend the internal PHY is only at address 0 */ 681 if (phy) { 682 RL_UNLOCK(sc); 683 return(0); 684 } 685 switch(reg) { 686 case MII_BMCR: 687 rl8139_reg = RL_BMCR; 688 break; 689 case MII_BMSR: 690 rl8139_reg = RL_BMSR; 691 break; 692 case MII_ANAR: 693 rl8139_reg = RL_ANAR; 694 break; 695 case MII_ANER: 696 rl8139_reg = RL_ANER; 697 break; 698 case MII_ANLPAR: 699 rl8139_reg = RL_LPAR; 700 break; 701 case MII_PHYIDR1: 702 case MII_PHYIDR2: 703 RL_UNLOCK(sc); 704 return(0); 705 break; 706 default: 707 printf("rl%d: bad phy register\n", sc->rl_unit); 708 RL_UNLOCK(sc); 709 return(0); 710 } 711 CSR_WRITE_2(sc, rl8139_reg, data); 712 RL_UNLOCK(sc); 713 return(0); 714 } 715 716 bzero((char *)&frame, sizeof(frame)); 717 718 frame.mii_phyaddr = phy; 719 frame.mii_regaddr = reg; 720 frame.mii_data = data; 721 722 rl_mii_writereg(sc, &frame); 723 724 RL_UNLOCK(sc); 725 return(0); 726} 727 728static void 729rl_miibus_statchg(dev) 730 device_t dev; 731{ 732 return; 733} 734 735/* 736 * Calculate CRC of a multicast group address, return the upper 6 bits. 737 */ 738static u_int32_t 739rl_mchash(addr) 740 const uint8_t *addr; 741{ 742 uint32_t crc, carry; 743 int idx, bit; 744 uint8_t data; 745 746 /* Compute CRC for the address value. */ 747 crc = 0xFFFFFFFF; /* initial value */ 748 749 for (idx = 0; idx < 6; idx++) { 750 for (data = *addr++, bit = 0; bit < 8; bit++, data >>=1 ) { 751 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 752 crc <<= 1; 753 if (carry) 754 crc = (crc ^ 0x04c11db6) | carry; 755 } 756 } 757 758 /* return the filter bit position */ 759 return(crc >> 26); 760} 761 762/* 763 * Program the 64-bit multicast hash filter. 764 */ 765static void 766rl_setmulti(sc) 767 struct rl_softc *sc; 768{ 769 struct ifnet *ifp; 770 int h = 0; 771 u_int32_t hashes[2] = { 0, 0 }; 772 struct ifmultiaddr *ifma; 773 u_int32_t rxfilt; 774 int mcnt = 0; 775 776 ifp = &sc->arpcom.ac_if; 777 778 rxfilt = CSR_READ_4(sc, RL_RXCFG); 779 780 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 781 rxfilt |= RL_RXCFG_RX_MULTI; 782 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 783 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 784 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 785 return; 786 } 787 788 /* first, zot all the existing hash bits */ 789 CSR_WRITE_4(sc, RL_MAR0, 0); 790 CSR_WRITE_4(sc, RL_MAR4, 0); 791 792 /* now program new ones */ 793 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 794 if (ifma->ifma_addr->sa_family != AF_LINK) 795 continue; 796 h = rl_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 797 if (h < 32) 798 hashes[0] |= (1 << h); 799 else 800 hashes[1] |= (1 << (h - 32)); 801 mcnt++; 802 } 803 804 if (mcnt) 805 rxfilt |= RL_RXCFG_RX_MULTI; 806 else 807 rxfilt &= ~RL_RXCFG_RX_MULTI; 808 809 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 810 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 811 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 812 813 return; 814} 815 816static void 817rl_reset(sc) 818 struct rl_softc *sc; 819{ 820 register int i; 821 822 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 823 824 for (i = 0; i < RL_TIMEOUT; i++) { 825 DELAY(10); 826 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 827 break; 828 } 829 if (i == RL_TIMEOUT) 830 printf("rl%d: reset never completed!\n", sc->rl_unit); 831 832 return; 833} 834 835/* 836 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 837 * IDs against our list and return a device name if we find a match. 838 */ 839static int 840rl_probe(dev) 841 device_t dev; 842{ 843 struct rl_type *t; 844 struct rl_softc *sc; 845 int rid; 846 u_int32_t hwrev; 847 848 t = rl_devs; 849 sc = device_get_softc(dev); 850 851 while(t->rl_name != NULL) { 852 if ((pci_get_vendor(dev) == t->rl_vid) && 853 (pci_get_device(dev) == t->rl_did)) { 854 855 /* 856 * Temporarily map the I/O space 857 * so we can read the chip ID register. 858 */ 859 rid = RL_RID; 860 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 861 RF_ACTIVE); 862 if (sc->rl_res == NULL) { 863 device_printf(dev, 864 "couldn't map ports/memory\n"); 865 return(ENXIO); 866 } 867 sc->rl_btag = rman_get_bustag(sc->rl_res); 868 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 869 mtx_init(&sc->rl_mtx, 870 device_get_nameunit(dev), 871 MTX_NETWORK_LOCK, MTX_DEF); 872 RL_LOCK(sc); 873 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 874 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 875 RL_UNLOCK(sc); 876 mtx_destroy(&sc->rl_mtx); 877 878 /* Don't attach to 8139C+ or 8169/8110 chips. */ 879 if (hwrev == RL_HWREV_8139CPLUS || 880 (hwrev == RL_HWREV_8169 && 881 t->rl_did == RT_DEVICEID_8169) || 882 hwrev == RL_HWREV_8169S || 883 hwrev == RL_HWREV_8110S) { 884 t++; 885 continue; 886 } 887 888 device_set_desc(dev, t->rl_name); 889 return(0); 890 } 891 t++; 892 } 893 894 return(ENXIO); 895} 896 897/* 898 * Attach the interface. Allocate softc structures, do ifmedia 899 * setup and ethernet/BPF attach. 900 */ 901static int 902rl_attach(dev) 903 device_t dev; 904{ 905 u_char eaddr[ETHER_ADDR_LEN]; 906 u_int16_t as[3]; 907 struct rl_softc *sc; 908 struct ifnet *ifp; 909 u_int16_t rl_did = 0; 910 struct rl_type *t; 911 int unit, error = 0, rid, i; 912 913 sc = device_get_softc(dev); 914 unit = device_get_unit(dev); 915 916 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 917 MTX_DEF | MTX_RECURSE); 918#ifndef BURN_BRIDGES 919 /* 920 * Handle power management nonsense. 921 */ 922 923 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 924 u_int32_t iobase, membase, irq; 925 926 /* Save important PCI config data. */ 927 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 928 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 929 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 930 931 /* Reset the power state. */ 932 printf("rl%d: chip is is in D%d power mode " 933 "-- setting to D0\n", unit, 934 pci_get_powerstate(dev)); 935 936 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 937 938 /* Restore PCI config data. */ 939 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 940 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 941 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 942 } 943#endif 944 /* 945 * Map control/status registers. 946 */ 947 pci_enable_busmaster(dev); 948 949 rid = RL_RID; 950 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 951 952 if (sc->rl_res == NULL) { 953 printf ("rl%d: couldn't map ports/memory\n", unit); 954 error = ENXIO; 955 goto fail; 956 } 957 958#ifdef notdef 959 /* Detect the Realtek 8139B. For some reason, this chip is very 960 * unstable when left to autoselect the media 961 * The best workaround is to set the device to the required 962 * media type or to set it to the 10 Meg speed. 963 */ 964 965 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 966 printf("rl%d: Realtek 8139B detected. Warning, " 967 "this may be unstable in autoselect mode\n", unit); 968 } 969#endif 970 971 sc->rl_btag = rman_get_bustag(sc->rl_res); 972 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 973 974 /* Allocate interrupt */ 975 rid = 0; 976 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 977 RF_SHAREABLE | RF_ACTIVE); 978 979 if (sc->rl_irq == NULL) { 980 printf("rl%d: couldn't map interrupt\n", unit); 981 error = ENXIO; 982 goto fail; 983 } 984 985 /* Reset the adapter. */ 986 rl_reset(sc); 987 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 988 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 989 if (rl_did != 0x8129) 990 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 991 992 /* 993 * Get station address from the EEPROM. 994 */ 995 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 996 for (i = 0; i < 3; i++) { 997 eaddr[(i * 2) + 0] = as[i] & 0xff; 998 eaddr[(i * 2) + 1] = as[i] >> 8; 999 } 1000 1001 sc->rl_unit = unit; 1002 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1003 1004 /* 1005 * Now read the exact device type from the EEPROM to find 1006 * out if it's an 8129 or 8139. 1007 */ 1008 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1009 1010 t = rl_devs; 1011 sc->rl_type = 0; 1012 while(t->rl_name != NULL) { 1013 if (rl_did == t->rl_did) { 1014 sc->rl_type = t->rl_basetype; 1015 break; 1016 } 1017 t++; 1018 } 1019 1020 if (sc->rl_type == 0) { 1021 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1022 error = ENXIO; 1023 goto fail; 1024 } 1025 1026 /* 1027 * Allocate the parent bus DMA tag appropriate for PCI. 1028 */ 1029#define RL_NSEG_NEW 32 1030 error = bus_dma_tag_create(NULL, /* parent */ 1031 1, 0, /* alignment, boundary */ 1032 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1033 BUS_SPACE_MAXADDR, /* highaddr */ 1034 NULL, NULL, /* filter, filterarg */ 1035 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1036 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1037 BUS_DMA_ALLOCNOW, /* flags */ 1038 NULL, NULL, /* lockfunc, lockarg */ 1039 &sc->rl_parent_tag); 1040 if (error) 1041 goto fail; 1042 1043 /* 1044 * Now allocate a tag for the DMA descriptor lists. 1045 * All of our lists are allocated as a contiguous block 1046 * of memory. 1047 */ 1048 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1049 1, 0, /* alignment, boundary */ 1050 BUS_SPACE_MAXADDR, /* lowaddr */ 1051 BUS_SPACE_MAXADDR, /* highaddr */ 1052 NULL, NULL, /* filter, filterarg */ 1053 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1054 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1055 BUS_DMA_ALLOCNOW, /* flags */ 1056 NULL, NULL, /* lockfunc, lockarg */ 1057 &sc->rl_tag); 1058 if (error) 1059 goto fail; 1060 1061 /* 1062 * Now allocate a chunk of DMA-able memory based on the 1063 * tag we just created. 1064 */ 1065 error = bus_dmamem_alloc(sc->rl_tag, 1066 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1067 &sc->rl_cdata.rl_rx_dmamap); 1068 1069 if (error) { 1070 printf("rl%d: no memory for list buffers!\n", unit); 1071 bus_dma_tag_destroy(sc->rl_tag); 1072 sc->rl_tag = NULL; 1073 goto fail; 1074 } 1075 1076 /* Leave a few bytes before the start of the RX ring buffer. */ 1077 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1078 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1079 1080 /* Do MII setup */ 1081 if (mii_phy_probe(dev, &sc->rl_miibus, 1082 rl_ifmedia_upd, rl_ifmedia_sts)) { 1083 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1084 error = ENXIO; 1085 goto fail; 1086 } 1087 1088 ifp = &sc->arpcom.ac_if; 1089 ifp->if_softc = sc; 1090 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1091 ifp->if_mtu = ETHERMTU; 1092 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1093 ifp->if_ioctl = rl_ioctl; 1094 ifp->if_start = rl_start; 1095 ifp->if_watchdog = rl_watchdog; 1096 ifp->if_init = rl_init; 1097 ifp->if_baudrate = 10000000; 1098 ifp->if_capabilities = IFCAP_VLAN_MTU; 1099 ifp->if_capenable = ifp->if_capabilities; 1100 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1101 1102 callout_handle_init(&sc->rl_stat_ch); 1103 1104 /* 1105 * Call MI attach routine. 1106 */ 1107 ether_ifattach(ifp, eaddr); 1108 1109 /* Hook interrupt last to avoid having to lock softc */ 1110 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1111 rl_intr, sc, &sc->rl_intrhand); 1112 1113 if (error) { 1114 printf("rl%d: couldn't set up irq\n", unit); 1115 ether_ifdetach(ifp); 1116 goto fail; 1117 } 1118 1119fail: 1120 if (error) 1121 rl_detach(dev); 1122 1123 return (error); 1124} 1125 1126/* 1127 * Shutdown hardware and free up resources. This can be called any 1128 * time after the mutex has been initialized. It is called in both 1129 * the error case in attach and the normal detach case so it needs 1130 * to be careful about only freeing resources that have actually been 1131 * allocated. 1132 */ 1133static int 1134rl_detach(dev) 1135 device_t dev; 1136{ 1137 struct rl_softc *sc; 1138 struct ifnet *ifp; 1139 1140 sc = device_get_softc(dev); 1141 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1142 RL_LOCK(sc); 1143 ifp = &sc->arpcom.ac_if; 1144 1145 /* These should only be active if attach succeeded */ 1146 if (device_is_attached(dev)) { 1147 rl_stop(sc); 1148 ether_ifdetach(ifp); 1149 } 1150 if (sc->rl_miibus) 1151 device_delete_child(dev, sc->rl_miibus); 1152 bus_generic_detach(dev); 1153 1154 if (sc->rl_intrhand) 1155 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1156 if (sc->rl_irq) 1157 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1158 if (sc->rl_res) 1159 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1160 1161 if (sc->rl_tag) { 1162 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1163 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1164 sc->rl_cdata.rl_rx_dmamap); 1165 bus_dma_tag_destroy(sc->rl_tag); 1166 } 1167 if (sc->rl_parent_tag) 1168 bus_dma_tag_destroy(sc->rl_parent_tag); 1169 1170 RL_UNLOCK(sc); 1171 mtx_destroy(&sc->rl_mtx); 1172 1173 return(0); 1174} 1175 1176/* 1177 * Initialize the transmit descriptors. 1178 */ 1179static int 1180rl_list_tx_init(sc) 1181 struct rl_softc *sc; 1182{ 1183 struct rl_chain_data *cd; 1184 int i; 1185 1186 cd = &sc->rl_cdata; 1187 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1188 cd->rl_tx_chain[i] = NULL; 1189 CSR_WRITE_4(sc, 1190 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1191 } 1192 1193 sc->rl_cdata.cur_tx = 0; 1194 sc->rl_cdata.last_tx = 0; 1195 1196 return(0); 1197} 1198 1199/* 1200 * A frame has been uploaded: pass the resulting mbuf chain up to 1201 * the higher level protocols. 1202 * 1203 * You know there's something wrong with a PCI bus-master chip design 1204 * when you have to use m_devget(). 1205 * 1206 * The receive operation is badly documented in the datasheet, so I'll 1207 * attempt to document it here. The driver provides a buffer area and 1208 * places its base address in the RX buffer start address register. 1209 * The chip then begins copying frames into the RX buffer. Each frame 1210 * is preceded by a 32-bit RX status word which specifies the length 1211 * of the frame and certain other status bits. Each frame (starting with 1212 * the status word) is also 32-bit aligned. The frame length is in the 1213 * first 16 bits of the status word; the lower 15 bits correspond with 1214 * the 'rx status register' mentioned in the datasheet. 1215 * 1216 * Note: to make the Alpha happy, the frame payload needs to be aligned 1217 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1218 * as the offset argument to m_devget(). 1219 */ 1220static void 1221rl_rxeof(sc) 1222 struct rl_softc *sc; 1223{ 1224 struct mbuf *m; 1225 struct ifnet *ifp; 1226 int total_len = 0; 1227 u_int32_t rxstat; 1228 caddr_t rxbufpos; 1229 int wrap = 0; 1230 u_int16_t cur_rx; 1231 u_int16_t limit; 1232 u_int16_t rx_bytes = 0, max_bytes; 1233 1234 RL_LOCK_ASSERT(sc); 1235 1236 ifp = &sc->arpcom.ac_if; 1237 1238 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1239 BUS_DMASYNC_POSTREAD); 1240 1241 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1242 1243 /* Do not try to read past this point. */ 1244 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1245 1246 if (limit < cur_rx) 1247 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1248 else 1249 max_bytes = limit - cur_rx; 1250 1251 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1252#ifdef DEVICE_POLLING 1253 if (ifp->if_flags & IFF_POLLING) { 1254 if (sc->rxcycles <= 0) 1255 break; 1256 sc->rxcycles--; 1257 } 1258#endif /* DEVICE_POLLING */ 1259 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1260 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1261 1262 /* 1263 * Here's a totally undocumented fact for you. When the 1264 * RealTek chip is in the process of copying a packet into 1265 * RAM for you, the length will be 0xfff0. If you spot a 1266 * packet header with this value, you need to stop. The 1267 * datasheet makes absolutely no mention of this and 1268 * RealTek should be shot for this. 1269 */ 1270 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1271 break; 1272 1273 if (!(rxstat & RL_RXSTAT_RXOK)) { 1274 ifp->if_ierrors++; 1275 rl_init(sc); 1276 return; 1277 } 1278 1279 /* No errors; receive the packet. */ 1280 total_len = rxstat >> 16; 1281 rx_bytes += total_len + 4; 1282 1283 /* 1284 * XXX The RealTek chip includes the CRC with every 1285 * received frame, and there's no way to turn this 1286 * behavior off (at least, I can't find anything in 1287 * the manual that explains how to do it) so we have 1288 * to trim off the CRC manually. 1289 */ 1290 total_len -= ETHER_CRC_LEN; 1291 1292 /* 1293 * Avoid trying to read more bytes than we know 1294 * the chip has prepared for us. 1295 */ 1296 if (rx_bytes > max_bytes) 1297 break; 1298 1299 rxbufpos = sc->rl_cdata.rl_rx_buf + 1300 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1301 1302 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1303 rxbufpos = sc->rl_cdata.rl_rx_buf; 1304 1305 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1306 1307 if (total_len > wrap) { 1308 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1309 NULL); 1310 if (m == NULL) { 1311 ifp->if_ierrors++; 1312 } else { 1313 m_copyback(m, wrap, total_len - wrap, 1314 sc->rl_cdata.rl_rx_buf); 1315 } 1316 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1317 } else { 1318 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1319 NULL); 1320 if (m == NULL) { 1321 ifp->if_ierrors++; 1322 } 1323 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1324 } 1325 1326 /* 1327 * Round up to 32-bit boundary. 1328 */ 1329 cur_rx = (cur_rx + 3) & ~3; 1330 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1331 1332 if (m == NULL) 1333 continue; 1334 1335 ifp->if_ipackets++; 1336 RL_UNLOCK(sc); 1337 (*ifp->if_input)(ifp, m); 1338 RL_LOCK(sc); 1339 } 1340 1341 return; 1342} 1343 1344/* 1345 * A frame was downloaded to the chip. It's safe for us to clean up 1346 * the list buffers. 1347 */ 1348static void 1349rl_txeof(sc) 1350 struct rl_softc *sc; 1351{ 1352 struct ifnet *ifp; 1353 u_int32_t txstat; 1354 1355 ifp = &sc->arpcom.ac_if; 1356 1357 /* 1358 * Go through our tx list and free mbufs for those 1359 * frames that have been uploaded. 1360 */ 1361 do { 1362 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1363 if (!(txstat & (RL_TXSTAT_TX_OK| 1364 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1365 break; 1366 1367 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1368 1369 if (RL_LAST_TXMBUF(sc) != NULL) { 1370 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1371 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1372 m_freem(RL_LAST_TXMBUF(sc)); 1373 RL_LAST_TXMBUF(sc) = NULL; 1374 } 1375 if (txstat & RL_TXSTAT_TX_OK) 1376 ifp->if_opackets++; 1377 else { 1378 int oldthresh; 1379 ifp->if_oerrors++; 1380 if ((txstat & RL_TXSTAT_TXABRT) || 1381 (txstat & RL_TXSTAT_OUTOFWIN)) 1382 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1383 oldthresh = sc->rl_txthresh; 1384 /* error recovery */ 1385 rl_reset(sc); 1386 rl_init(sc); 1387 /* 1388 * If there was a transmit underrun, 1389 * bump the TX threshold. 1390 */ 1391 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1392 sc->rl_txthresh = oldthresh + 32; 1393 return; 1394 } 1395 RL_INC(sc->rl_cdata.last_tx); 1396 ifp->if_flags &= ~IFF_OACTIVE; 1397 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1398 1399 ifp->if_timer = 1400 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1401 1402 return; 1403} 1404 1405static void 1406rl_tick(xsc) 1407 void *xsc; 1408{ 1409 struct rl_softc *sc; 1410 struct mii_data *mii; 1411 1412 sc = xsc; 1413 RL_LOCK(sc); 1414 mii = device_get_softc(sc->rl_miibus); 1415 1416 mii_tick(mii); 1417 1418 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1419 RL_UNLOCK(sc); 1420 1421 return; 1422} 1423 1424#ifdef DEVICE_POLLING 1425static void 1426rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1427{ 1428 struct rl_softc *sc = ifp->if_softc; 1429 1430 RL_LOCK(sc); 1431 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1432 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1433 goto done; 1434 } 1435 1436 sc->rxcycles = count; 1437 rl_rxeof(sc); 1438 rl_txeof(sc); 1439 if (ifp->if_snd.ifq_head != NULL) 1440 rl_start(ifp); 1441 1442 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1443 u_int16_t status; 1444 1445 status = CSR_READ_2(sc, RL_ISR); 1446 if (status == 0xffff) 1447 goto done; 1448 if (status) 1449 CSR_WRITE_2(sc, RL_ISR, status); 1450 1451 /* 1452 * XXX check behaviour on receiver stalls. 1453 */ 1454 1455 if (status & RL_ISR_SYSTEM_ERR) { 1456 rl_reset(sc); 1457 rl_init(sc); 1458 } 1459 } 1460done: 1461 RL_UNLOCK(sc); 1462} 1463#endif /* DEVICE_POLLING */ 1464 1465static void 1466rl_intr(arg) 1467 void *arg; 1468{ 1469 struct rl_softc *sc; 1470 struct ifnet *ifp; 1471 u_int16_t status; 1472 1473 sc = arg; 1474 1475 if (sc->suspended) { 1476 return; 1477 } 1478 1479 RL_LOCK(sc); 1480 ifp = &sc->arpcom.ac_if; 1481 1482#ifdef DEVICE_POLLING 1483 if (ifp->if_flags & IFF_POLLING) 1484 goto done; 1485 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1486 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1487 rl_poll(ifp, 0, 1); 1488 goto done; 1489 } 1490#endif /* DEVICE_POLLING */ 1491 1492 for (;;) { 1493 1494 status = CSR_READ_2(sc, RL_ISR); 1495 /* If the card has gone away the read returns 0xffff. */ 1496 if (status == 0xffff) 1497 break; 1498 if (status) 1499 CSR_WRITE_2(sc, RL_ISR, status); 1500 1501 if ((status & RL_INTRS) == 0) 1502 break; 1503 1504 if (status & RL_ISR_RX_OK) 1505 rl_rxeof(sc); 1506 1507 if (status & RL_ISR_RX_ERR) 1508 rl_rxeof(sc); 1509 1510 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1511 rl_txeof(sc); 1512 1513 if (status & RL_ISR_SYSTEM_ERR) { 1514 rl_reset(sc); 1515 rl_init(sc); 1516 } 1517 1518 } 1519 1520 if (ifp->if_snd.ifq_head != NULL) 1521 rl_start(ifp); 1522 1523#ifdef DEVICE_POLLING 1524done: 1525#endif 1526 RL_UNLOCK(sc); 1527 1528 return; 1529} 1530 1531/* 1532 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1533 * pointers to the fragment pointers. 1534 */ 1535static int 1536rl_encap(sc, m_head) 1537 struct rl_softc *sc; 1538 struct mbuf *m_head; 1539{ 1540 struct mbuf *m_new = NULL; 1541 1542 /* 1543 * The RealTek is brain damaged and wants longword-aligned 1544 * TX buffers, plus we can only have one fragment buffer 1545 * per packet. We have to copy pretty much all the time. 1546 */ 1547 m_new = m_defrag(m_head, M_DONTWAIT); 1548 1549 if (m_new == NULL) { 1550 m_freem(m_head); 1551 return(1); 1552 } 1553 m_head = m_new; 1554 1555 /* Pad frames to at least 60 bytes. */ 1556 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1557 /* 1558 * Make security concious people happy: zero out the 1559 * bytes in the pad area, since we don't know what 1560 * this mbuf cluster buffer's previous user might 1561 * have left in it. 1562 */ 1563 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1564 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1565 m_head->m_pkthdr.len += 1566 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1567 m_head->m_len = m_head->m_pkthdr.len; 1568 } 1569 1570 RL_CUR_TXMBUF(sc) = m_head; 1571 1572 return(0); 1573} 1574 1575/* 1576 * Main transmit routine. 1577 */ 1578 1579static void 1580rl_start(ifp) 1581 struct ifnet *ifp; 1582{ 1583 struct rl_softc *sc; 1584 struct mbuf *m_head = NULL; 1585 1586 sc = ifp->if_softc; 1587 RL_LOCK(sc); 1588 1589 while(RL_CUR_TXMBUF(sc) == NULL) { 1590 IF_DEQUEUE(&ifp->if_snd, m_head); 1591 if (m_head == NULL) 1592 break; 1593 1594 if (rl_encap(sc, m_head)) { 1595 break; 1596 } 1597 1598 /* 1599 * If there's a BPF listener, bounce a copy of this frame 1600 * to him. 1601 */ 1602 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1603 1604 /* 1605 * Transmit the frame. 1606 */ 1607 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1608 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1609 mtod(RL_CUR_TXMBUF(sc), void *), 1610 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1611 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1612 BUS_DMASYNC_PREREAD); 1613 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1614 RL_TXTHRESH(sc->rl_txthresh) | 1615 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1616 1617 RL_INC(sc->rl_cdata.cur_tx); 1618 1619 /* 1620 * Set a timeout in case the chip goes out to lunch. 1621 */ 1622 ifp->if_timer = 5; 1623 } 1624 1625 /* 1626 * We broke out of the loop because all our TX slots are 1627 * full. Mark the NIC as busy until it drains some of the 1628 * packets from the queue. 1629 */ 1630 if (RL_CUR_TXMBUF(sc) != NULL) 1631 ifp->if_flags |= IFF_OACTIVE; 1632 1633 RL_UNLOCK(sc); 1634 1635 return; 1636} 1637 1638static void 1639rl_init(xsc) 1640 void *xsc; 1641{ 1642 struct rl_softc *sc = xsc; 1643 struct ifnet *ifp = &sc->arpcom.ac_if; 1644 struct mii_data *mii; 1645 u_int32_t rxcfg = 0; 1646 1647 RL_LOCK(sc); 1648 mii = device_get_softc(sc->rl_miibus); 1649 1650 /* 1651 * Cancel pending I/O and free all RX/TX buffers. 1652 */ 1653 rl_stop(sc); 1654 1655 /* 1656 * Init our MAC address. Even though the chipset 1657 * documentation doesn't mention it, we need to enter "Config 1658 * register write enable" mode to modify the ID registers. 1659 */ 1660 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1661 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1662 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1663 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1664 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1665 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1666 1667 /* Init the RX buffer pointer register. */ 1668 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1669 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1670 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1671 BUS_DMASYNC_PREWRITE); 1672 1673 /* Init TX descriptors. */ 1674 rl_list_tx_init(sc); 1675 1676 /* 1677 * Enable transmit and receive. 1678 */ 1679 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1680 1681 /* 1682 * Set the initial TX and RX configuration. 1683 */ 1684 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1685 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1686 1687 /* Set the individual bit to receive frames for this host only. */ 1688 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1689 rxcfg |= RL_RXCFG_RX_INDIV; 1690 1691 /* If we want promiscuous mode, set the allframes bit. */ 1692 if (ifp->if_flags & IFF_PROMISC) { 1693 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1694 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1695 } else { 1696 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1697 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1698 } 1699 1700 /* 1701 * Set capture broadcast bit to capture broadcast frames. 1702 */ 1703 if (ifp->if_flags & IFF_BROADCAST) { 1704 rxcfg |= RL_RXCFG_RX_BROAD; 1705 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1706 } else { 1707 rxcfg &= ~RL_RXCFG_RX_BROAD; 1708 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1709 } 1710 1711 /* 1712 * Program the multicast filter, if necessary. 1713 */ 1714 rl_setmulti(sc); 1715 1716#ifdef DEVICE_POLLING 1717 /* 1718 * Disable interrupts if we are polling. 1719 */ 1720 if (ifp->if_flags & IFF_POLLING) 1721 CSR_WRITE_2(sc, RL_IMR, 0); 1722 else /* otherwise ... */ 1723#endif /* DEVICE_POLLING */ 1724 /* 1725 * Enable interrupts. 1726 */ 1727 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1728 1729 /* Set initial TX threshold */ 1730 sc->rl_txthresh = RL_TX_THRESH_INIT; 1731 1732 /* Start RX/TX process. */ 1733 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1734 1735 /* Enable receiver and transmitter. */ 1736 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1737 1738 mii_mediachg(mii); 1739 1740 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1741 1742 ifp->if_flags |= IFF_RUNNING; 1743 ifp->if_flags &= ~IFF_OACTIVE; 1744 1745 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1746 RL_UNLOCK(sc); 1747 1748 return; 1749} 1750 1751/* 1752 * Set media options. 1753 */ 1754static int 1755rl_ifmedia_upd(ifp) 1756 struct ifnet *ifp; 1757{ 1758 struct rl_softc *sc; 1759 struct mii_data *mii; 1760 1761 sc = ifp->if_softc; 1762 mii = device_get_softc(sc->rl_miibus); 1763 mii_mediachg(mii); 1764 1765 return(0); 1766} 1767 1768/* 1769 * Report current media status. 1770 */ 1771static void 1772rl_ifmedia_sts(ifp, ifmr) 1773 struct ifnet *ifp; 1774 struct ifmediareq *ifmr; 1775{ 1776 struct rl_softc *sc; 1777 struct mii_data *mii; 1778 1779 sc = ifp->if_softc; 1780 mii = device_get_softc(sc->rl_miibus); 1781 1782 mii_pollstat(mii); 1783 ifmr->ifm_active = mii->mii_media_active; 1784 ifmr->ifm_status = mii->mii_media_status; 1785 1786 return; 1787} 1788 1789static int 1790rl_ioctl(ifp, command, data) 1791 struct ifnet *ifp; 1792 u_long command; 1793 caddr_t data; 1794{ 1795 struct rl_softc *sc = ifp->if_softc; 1796 struct ifreq *ifr = (struct ifreq *) data; 1797 struct mii_data *mii; 1798 int error = 0; 1799 1800 RL_LOCK(sc); 1801 1802 switch(command) { 1803 case SIOCSIFFLAGS: 1804 if (ifp->if_flags & IFF_UP) { 1805 rl_init(sc); 1806 } else { 1807 if (ifp->if_flags & IFF_RUNNING) 1808 rl_stop(sc); 1809 } 1810 error = 0; 1811 break; 1812 case SIOCADDMULTI: 1813 case SIOCDELMULTI: 1814 rl_setmulti(sc); 1815 error = 0; 1816 break; 1817 case SIOCGIFMEDIA: 1818 case SIOCSIFMEDIA: 1819 mii = device_get_softc(sc->rl_miibus); 1820 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1821 break; 1822 default: 1823 error = ether_ioctl(ifp, command, data); 1824 break; 1825 } 1826 1827 RL_UNLOCK(sc); 1828 1829 return(error); 1830} 1831 1832static void 1833rl_watchdog(ifp) 1834 struct ifnet *ifp; 1835{ 1836 struct rl_softc *sc; 1837 1838 sc = ifp->if_softc; 1839 RL_LOCK(sc); 1840 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1841 ifp->if_oerrors++; 1842 1843 rl_txeof(sc); 1844 rl_rxeof(sc); 1845 rl_init(sc); 1846 RL_UNLOCK(sc); 1847 1848 return; 1849} 1850 1851/* 1852 * Stop the adapter and free any mbufs allocated to the 1853 * RX and TX lists. 1854 */ 1855static void 1856rl_stop(sc) 1857 struct rl_softc *sc; 1858{ 1859 register int i; 1860 struct ifnet *ifp; 1861 1862 RL_LOCK(sc); 1863 ifp = &sc->arpcom.ac_if; 1864 ifp->if_timer = 0; 1865 1866 untimeout(rl_tick, sc, sc->rl_stat_ch); 1867 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1868#ifdef DEVICE_POLLING 1869 ether_poll_deregister(ifp); 1870#endif /* DEVICE_POLLING */ 1871 1872 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1873 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1874 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1875 1876 /* 1877 * Free the TX list buffers. 1878 */ 1879 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1880 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1881 bus_dmamap_unload(sc->rl_tag, 1882 sc->rl_cdata.rl_tx_dmamap[i]); 1883 bus_dmamap_destroy(sc->rl_tag, 1884 sc->rl_cdata.rl_tx_dmamap[i]); 1885 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1886 sc->rl_cdata.rl_tx_chain[i] = NULL; 1887 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)), 1888 0x0000000); 1889 } 1890 } 1891 1892 RL_UNLOCK(sc); 1893 return; 1894} 1895 1896/* 1897 * Device suspend routine. Stop the interface and save some PCI 1898 * settings in case the BIOS doesn't restore them properly on 1899 * resume. 1900 */ 1901static int 1902rl_suspend(dev) 1903 device_t dev; 1904{ 1905 register int i; 1906 struct rl_softc *sc; 1907 1908 sc = device_get_softc(dev); 1909 1910 rl_stop(sc); 1911 1912 for (i = 0; i < 5; i++) 1913 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1914 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1915 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1916 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1917 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1918 1919 sc->suspended = 1; 1920 1921 return (0); 1922} 1923 1924/* 1925 * Device resume routine. Restore some PCI settings in case the BIOS 1926 * doesn't, re-enable busmastering, and restart the interface if 1927 * appropriate. 1928 */ 1929static int 1930rl_resume(dev) 1931 device_t dev; 1932{ 1933 register int i; 1934 struct rl_softc *sc; 1935 struct ifnet *ifp; 1936 1937 sc = device_get_softc(dev); 1938 ifp = &sc->arpcom.ac_if; 1939 1940 /* better way to do this? */ 1941 for (i = 0; i < 5; i++) 1942 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1943 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1944 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1945 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1946 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1947 1948 /* reenable busmastering */ 1949 pci_enable_busmaster(dev); 1950 pci_enable_io(dev, RL_RES); 1951 1952 /* reinitialize interface if necessary */ 1953 if (ifp->if_flags & IFF_UP) 1954 rl_init(sc); 1955 1956 sc->suspended = 0; 1957 1958 return (0); 1959} 1960 1961/* 1962 * Stop all chip I/O so that the kernel's probe routines don't 1963 * get confused by errant DMAs when rebooting. 1964 */ 1965static void 1966rl_shutdown(dev) 1967 device_t dev; 1968{ 1969 struct rl_softc *sc; 1970 1971 sc = device_get_softc(dev); 1972 1973 rl_stop(sc); 1974 1975 return; 1976} 1977