if_rl.c revision 124816
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 124816 2004-01-21 22:29:51Z wpaul $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/endian.h> 88#include <sys/systm.h> 89#include <sys/sockio.h> 90#include <sys/mbuf.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94 95#include <net/if.h> 96#include <net/if_arp.h> 97#include <net/ethernet.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100 101#include <net/bpf.h> 102 103#include <machine/bus_pio.h> 104#include <machine/bus_memio.h> 105#include <machine/bus.h> 106#include <machine/resource.h> 107#include <sys/bus.h> 108#include <sys/rman.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116MODULE_DEPEND(rl, pci, 1, 1, 1); 117MODULE_DEPEND(rl, ether, 1, 1, 1); 118MODULE_DEPEND(rl, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123/* 124 * Default to using PIO access for this driver. On SMP systems, 125 * there appear to be problems with memory mapped mode: it looks like 126 * doing too many memory mapped access back to back in rapid succession 127 * can hang the bus. I'm inclined to blame this on crummy design/construction 128 * on the part of RealTek. Memory mapped mode does appear to work on 129 * uniprocessor systems though. 130 */ 131#define RL_USEIOSPACE 132 133#include <pci/if_rlreg.h> 134 135/* 136 * Various supported device vendors/types and their names. 137 */ 138static struct rl_type rl_devs[] = { 139 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 140 "RealTek 8129 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 142 "RealTek 8139 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 144 "RealTek 8139 10/100BaseTX CardBus" }, 145 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 146 "RealTek 8100 10/100BaseTX" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 154 "D-Link DFE-530TX+ 10/100BaseTX" }, 155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 156 "D-Link DFE-690TXD 10/100BaseTX" }, 157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 158 "Nortel Networks 10/100BaseTX" }, 159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 160 "Corega FEther CB-TXD" }, 161 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 162 "Corega FEtherII CB-TXD" }, 163 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 164 "Peppercon AG ROL-F" }, 165 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 166 "Planex FNW-3800-TX" }, 167 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 168 "Compaq HNE-300" }, 169 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 170 "LevelOne FPC-0106TX" }, 171 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 172 "Edimax EP-4103DL CardBus" }, 173 { 0, 0, 0, NULL } 174}; 175 176static int rl_probe (device_t); 177static int rl_attach (device_t); 178static int rl_detach (device_t); 179 180static int rl_encap (struct rl_softc *, struct mbuf * ); 181 182static void rl_rxeof (struct rl_softc *); 183static void rl_txeof (struct rl_softc *); 184static void rl_intr (void *); 185static void rl_tick (void *); 186static void rl_start (struct ifnet *); 187static int rl_ioctl (struct ifnet *, u_long, caddr_t); 188static void rl_init (void *); 189static void rl_stop (struct rl_softc *); 190static void rl_watchdog (struct ifnet *); 191static int rl_suspend (device_t); 192static int rl_resume (device_t); 193static void rl_shutdown (device_t); 194static int rl_ifmedia_upd (struct ifnet *); 195static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 196 197static void rl_eeprom_putbyte (struct rl_softc *, int); 198static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 199static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 200static void rl_mii_sync (struct rl_softc *); 201static void rl_mii_send (struct rl_softc *, u_int32_t, int); 202static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 203static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 204 205static int rl_miibus_readreg (device_t, int, int); 206static int rl_miibus_writereg (device_t, int, int, int); 207static void rl_miibus_statchg (device_t); 208 209static uint32_t rl_mchash (const uint8_t *); 210static void rl_setmulti (struct rl_softc *); 211static void rl_reset (struct rl_softc *); 212static int rl_list_tx_init (struct rl_softc *); 213 214static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 215static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 216 217#ifdef RL_USEIOSPACE 218#define RL_RES SYS_RES_IOPORT 219#define RL_RID RL_PCI_LOIO 220#else 221#define RL_RES SYS_RES_MEMORY 222#define RL_RID RL_PCI_LOMEM 223#endif 224 225static device_method_t rl_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_probe, rl_probe), 228 DEVMETHOD(device_attach, rl_attach), 229 DEVMETHOD(device_detach, rl_detach), 230 DEVMETHOD(device_suspend, rl_suspend), 231 DEVMETHOD(device_resume, rl_resume), 232 DEVMETHOD(device_shutdown, rl_shutdown), 233 234 /* bus interface */ 235 DEVMETHOD(bus_print_child, bus_generic_print_child), 236 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 237 238 /* MII interface */ 239 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 240 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 241 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 242 243 { 0, 0 } 244}; 245 246static driver_t rl_driver = { 247 "rl", 248 rl_methods, 249 sizeof(struct rl_softc) 250}; 251 252static devclass_t rl_devclass; 253 254DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 255DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 256DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 257 258#define EE_SET(x) \ 259 CSR_WRITE_1(sc, RL_EECMD, \ 260 CSR_READ_1(sc, RL_EECMD) | x) 261 262#define EE_CLR(x) \ 263 CSR_WRITE_1(sc, RL_EECMD, \ 264 CSR_READ_1(sc, RL_EECMD) & ~x) 265 266static void 267rl_dma_map_rxbuf(arg, segs, nseg, error) 268 void *arg; 269 bus_dma_segment_t *segs; 270 int nseg, error; 271{ 272 struct rl_softc *sc; 273 274 sc = arg; 275 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 276 277 return; 278} 279 280static void 281rl_dma_map_txbuf(arg, segs, nseg, error) 282 void *arg; 283 bus_dma_segment_t *segs; 284 int nseg, error; 285{ 286 struct rl_softc *sc; 287 288 sc = arg; 289 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 290 291 return; 292} 293 294/* 295 * Send a read command and address to the EEPROM, check for ACK. 296 */ 297static void 298rl_eeprom_putbyte(sc, addr) 299 struct rl_softc *sc; 300 int addr; 301{ 302 register int d, i; 303 304 d = addr | sc->rl_eecmd_read; 305 306 /* 307 * Feed in each bit and strobe the clock. 308 */ 309 for (i = 0x400; i; i >>= 1) { 310 if (d & i) { 311 EE_SET(RL_EE_DATAIN); 312 } else { 313 EE_CLR(RL_EE_DATAIN); 314 } 315 DELAY(100); 316 EE_SET(RL_EE_CLK); 317 DELAY(150); 318 EE_CLR(RL_EE_CLK); 319 DELAY(100); 320 } 321 322 return; 323} 324 325/* 326 * Read a word of data stored in the EEPROM at address 'addr.' 327 */ 328static void 329rl_eeprom_getword(sc, addr, dest) 330 struct rl_softc *sc; 331 int addr; 332 u_int16_t *dest; 333{ 334 register int i; 335 u_int16_t word = 0; 336 337 /* Enter EEPROM access mode. */ 338 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 339 340 /* 341 * Send address of word we want to read. 342 */ 343 rl_eeprom_putbyte(sc, addr); 344 345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 346 347 /* 348 * Start reading bits from EEPROM. 349 */ 350 for (i = 0x8000; i; i >>= 1) { 351 EE_SET(RL_EE_CLK); 352 DELAY(100); 353 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 354 word |= i; 355 EE_CLR(RL_EE_CLK); 356 DELAY(100); 357 } 358 359 /* Turn off EEPROM access mode. */ 360 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 361 362 *dest = word; 363 364 return; 365} 366 367/* 368 * Read a sequence of words from the EEPROM. 369 */ 370static void 371rl_read_eeprom(sc, dest, off, cnt, swap) 372 struct rl_softc *sc; 373 caddr_t dest; 374 int off; 375 int cnt; 376 int swap; 377{ 378 int i; 379 u_int16_t word = 0, *ptr; 380 381 for (i = 0; i < cnt; i++) { 382 rl_eeprom_getword(sc, off + i, &word); 383 ptr = (u_int16_t *)(dest + (i * 2)); 384 if (swap) 385 *ptr = ntohs(word); 386 else 387 *ptr = word; 388 } 389 390 return; 391} 392 393 394/* 395 * MII access routines are provided for the 8129, which 396 * doesn't have a built-in PHY. For the 8139, we fake things 397 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 398 * direct access PHY registers. 399 */ 400#define MII_SET(x) \ 401 CSR_WRITE_1(sc, RL_MII, \ 402 CSR_READ_1(sc, RL_MII) | (x)) 403 404#define MII_CLR(x) \ 405 CSR_WRITE_1(sc, RL_MII, \ 406 CSR_READ_1(sc, RL_MII) & ~(x)) 407 408/* 409 * Sync the PHYs by setting data bit and strobing the clock 32 times. 410 */ 411static void 412rl_mii_sync(sc) 413 struct rl_softc *sc; 414{ 415 register int i; 416 417 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 418 419 for (i = 0; i < 32; i++) { 420 MII_SET(RL_MII_CLK); 421 DELAY(1); 422 MII_CLR(RL_MII_CLK); 423 DELAY(1); 424 } 425 426 return; 427} 428 429/* 430 * Clock a series of bits through the MII. 431 */ 432static void 433rl_mii_send(sc, bits, cnt) 434 struct rl_softc *sc; 435 u_int32_t bits; 436 int cnt; 437{ 438 int i; 439 440 MII_CLR(RL_MII_CLK); 441 442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 443 if (bits & i) { 444 MII_SET(RL_MII_DATAOUT); 445 } else { 446 MII_CLR(RL_MII_DATAOUT); 447 } 448 DELAY(1); 449 MII_CLR(RL_MII_CLK); 450 DELAY(1); 451 MII_SET(RL_MII_CLK); 452 } 453} 454 455/* 456 * Read an PHY register through the MII. 457 */ 458static int 459rl_mii_readreg(sc, frame) 460 struct rl_softc *sc; 461 struct rl_mii_frame *frame; 462 463{ 464 int i, ack; 465 466 RL_LOCK(sc); 467 468 /* 469 * Set up frame for RX. 470 */ 471 frame->mii_stdelim = RL_MII_STARTDELIM; 472 frame->mii_opcode = RL_MII_READOP; 473 frame->mii_turnaround = 0; 474 frame->mii_data = 0; 475 476 CSR_WRITE_2(sc, RL_MII, 0); 477 478 /* 479 * Turn on data xmit. 480 */ 481 MII_SET(RL_MII_DIR); 482 483 rl_mii_sync(sc); 484 485 /* 486 * Send command/address info. 487 */ 488 rl_mii_send(sc, frame->mii_stdelim, 2); 489 rl_mii_send(sc, frame->mii_opcode, 2); 490 rl_mii_send(sc, frame->mii_phyaddr, 5); 491 rl_mii_send(sc, frame->mii_regaddr, 5); 492 493 /* Idle bit */ 494 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 495 DELAY(1); 496 MII_SET(RL_MII_CLK); 497 DELAY(1); 498 499 /* Turn off xmit. */ 500 MII_CLR(RL_MII_DIR); 501 502 /* Check for ack */ 503 MII_CLR(RL_MII_CLK); 504 DELAY(1); 505 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 506 MII_SET(RL_MII_CLK); 507 DELAY(1); 508 509 /* 510 * Now try reading data bits. If the ack failed, we still 511 * need to clock through 16 cycles to keep the PHY(s) in sync. 512 */ 513 if (ack) { 514 for(i = 0; i < 16; i++) { 515 MII_CLR(RL_MII_CLK); 516 DELAY(1); 517 MII_SET(RL_MII_CLK); 518 DELAY(1); 519 } 520 goto fail; 521 } 522 523 for (i = 0x8000; i; i >>= 1) { 524 MII_CLR(RL_MII_CLK); 525 DELAY(1); 526 if (!ack) { 527 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 528 frame->mii_data |= i; 529 DELAY(1); 530 } 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 } 534 535fail: 536 537 MII_CLR(RL_MII_CLK); 538 DELAY(1); 539 MII_SET(RL_MII_CLK); 540 DELAY(1); 541 542 RL_UNLOCK(sc); 543 544 if (ack) 545 return(1); 546 return(0); 547} 548 549/* 550 * Write to a PHY register through the MII. 551 */ 552static int 553rl_mii_writereg(sc, frame) 554 struct rl_softc *sc; 555 struct rl_mii_frame *frame; 556 557{ 558 RL_LOCK(sc); 559 560 /* 561 * Set up frame for TX. 562 */ 563 564 frame->mii_stdelim = RL_MII_STARTDELIM; 565 frame->mii_opcode = RL_MII_WRITEOP; 566 frame->mii_turnaround = RL_MII_TURNAROUND; 567 568 /* 569 * Turn on data output. 570 */ 571 MII_SET(RL_MII_DIR); 572 573 rl_mii_sync(sc); 574 575 rl_mii_send(sc, frame->mii_stdelim, 2); 576 rl_mii_send(sc, frame->mii_opcode, 2); 577 rl_mii_send(sc, frame->mii_phyaddr, 5); 578 rl_mii_send(sc, frame->mii_regaddr, 5); 579 rl_mii_send(sc, frame->mii_turnaround, 2); 580 rl_mii_send(sc, frame->mii_data, 16); 581 582 /* Idle bit. */ 583 MII_SET(RL_MII_CLK); 584 DELAY(1); 585 MII_CLR(RL_MII_CLK); 586 DELAY(1); 587 588 /* 589 * Turn off xmit. 590 */ 591 MII_CLR(RL_MII_DIR); 592 593 RL_UNLOCK(sc); 594 595 return(0); 596} 597 598static int 599rl_miibus_readreg(dev, phy, reg) 600 device_t dev; 601 int phy, reg; 602{ 603 struct rl_softc *sc; 604 struct rl_mii_frame frame; 605 u_int16_t rval = 0; 606 u_int16_t rl8139_reg = 0; 607 608 sc = device_get_softc(dev); 609 RL_LOCK(sc); 610 611 if (sc->rl_type == RL_8139) { 612 /* Pretend the internal PHY is only at address 0 */ 613 if (phy) { 614 RL_UNLOCK(sc); 615 return(0); 616 } 617 switch(reg) { 618 case MII_BMCR: 619 rl8139_reg = RL_BMCR; 620 break; 621 case MII_BMSR: 622 rl8139_reg = RL_BMSR; 623 break; 624 case MII_ANAR: 625 rl8139_reg = RL_ANAR; 626 break; 627 case MII_ANER: 628 rl8139_reg = RL_ANER; 629 break; 630 case MII_ANLPAR: 631 rl8139_reg = RL_LPAR; 632 break; 633 case MII_PHYIDR1: 634 case MII_PHYIDR2: 635 RL_UNLOCK(sc); 636 return(0); 637 /* 638 * Allow the rlphy driver to read the media status 639 * register. If we have a link partner which does not 640 * support NWAY, this is the register which will tell 641 * us the results of parallel detection. 642 */ 643 case RL_MEDIASTAT: 644 rval = CSR_READ_1(sc, RL_MEDIASTAT); 645 RL_UNLOCK(sc); 646 return(rval); 647 default: 648 printf("rl%d: bad phy register\n", sc->rl_unit); 649 RL_UNLOCK(sc); 650 return(0); 651 } 652 rval = CSR_READ_2(sc, rl8139_reg); 653 RL_UNLOCK(sc); 654 return(rval); 655 } 656 657 bzero((char *)&frame, sizeof(frame)); 658 659 frame.mii_phyaddr = phy; 660 frame.mii_regaddr = reg; 661 rl_mii_readreg(sc, &frame); 662 RL_UNLOCK(sc); 663 664 return(frame.mii_data); 665} 666 667static int 668rl_miibus_writereg(dev, phy, reg, data) 669 device_t dev; 670 int phy, reg, data; 671{ 672 struct rl_softc *sc; 673 struct rl_mii_frame frame; 674 u_int16_t rl8139_reg = 0; 675 676 sc = device_get_softc(dev); 677 RL_LOCK(sc); 678 679 if (sc->rl_type == RL_8139) { 680 /* Pretend the internal PHY is only at address 0 */ 681 if (phy) { 682 RL_UNLOCK(sc); 683 return(0); 684 } 685 switch(reg) { 686 case MII_BMCR: 687 rl8139_reg = RL_BMCR; 688 break; 689 case MII_BMSR: 690 rl8139_reg = RL_BMSR; 691 break; 692 case MII_ANAR: 693 rl8139_reg = RL_ANAR; 694 break; 695 case MII_ANER: 696 rl8139_reg = RL_ANER; 697 break; 698 case MII_ANLPAR: 699 rl8139_reg = RL_LPAR; 700 break; 701 case MII_PHYIDR1: 702 case MII_PHYIDR2: 703 RL_UNLOCK(sc); 704 return(0); 705 break; 706 default: 707 printf("rl%d: bad phy register\n", sc->rl_unit); 708 RL_UNLOCK(sc); 709 return(0); 710 } 711 CSR_WRITE_2(sc, rl8139_reg, data); 712 RL_UNLOCK(sc); 713 return(0); 714 } 715 716 bzero((char *)&frame, sizeof(frame)); 717 718 frame.mii_phyaddr = phy; 719 frame.mii_regaddr = reg; 720 frame.mii_data = data; 721 722 rl_mii_writereg(sc, &frame); 723 724 RL_UNLOCK(sc); 725 return(0); 726} 727 728static void 729rl_miibus_statchg(dev) 730 device_t dev; 731{ 732 return; 733} 734 735/* 736 * Calculate CRC of a multicast group address, return the upper 6 bits. 737 */ 738static u_int32_t 739rl_mchash(addr) 740 const uint8_t *addr; 741{ 742 uint32_t crc, carry; 743 int idx, bit; 744 uint8_t data; 745 746 /* Compute CRC for the address value. */ 747 crc = 0xFFFFFFFF; /* initial value */ 748 749 for (idx = 0; idx < 6; idx++) { 750 for (data = *addr++, bit = 0; bit < 8; bit++, data >>=1 ) { 751 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 752 crc <<= 1; 753 if (carry) 754 crc = (crc ^ 0x04c11db6) | carry; 755 } 756 } 757 758 /* return the filter bit position */ 759 return(crc >> 26); 760} 761 762/* 763 * Program the 64-bit multicast hash filter. 764 */ 765static void 766rl_setmulti(sc) 767 struct rl_softc *sc; 768{ 769 struct ifnet *ifp; 770 int h = 0; 771 u_int32_t hashes[2] = { 0, 0 }; 772 struct ifmultiaddr *ifma; 773 u_int32_t rxfilt; 774 int mcnt = 0; 775 776 ifp = &sc->arpcom.ac_if; 777 778 rxfilt = CSR_READ_4(sc, RL_RXCFG); 779 780 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 781 rxfilt |= RL_RXCFG_RX_MULTI; 782 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 783 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 784 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 785 return; 786 } 787 788 /* first, zot all the existing hash bits */ 789 CSR_WRITE_4(sc, RL_MAR0, 0); 790 CSR_WRITE_4(sc, RL_MAR4, 0); 791 792 /* now program new ones */ 793 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 794 if (ifma->ifma_addr->sa_family != AF_LINK) 795 continue; 796 h = rl_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 797 if (h < 32) 798 hashes[0] |= (1 << h); 799 else 800 hashes[1] |= (1 << (h - 32)); 801 mcnt++; 802 } 803 804 if (mcnt) 805 rxfilt |= RL_RXCFG_RX_MULTI; 806 else 807 rxfilt &= ~RL_RXCFG_RX_MULTI; 808 809 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 810 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 811 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 812 813 return; 814} 815 816static void 817rl_reset(sc) 818 struct rl_softc *sc; 819{ 820 register int i; 821 822 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 823 824 for (i = 0; i < RL_TIMEOUT; i++) { 825 DELAY(10); 826 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 827 break; 828 } 829 if (i == RL_TIMEOUT) 830 printf("rl%d: reset never completed!\n", sc->rl_unit); 831 832 return; 833} 834 835/* 836 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 837 * IDs against our list and return a device name if we find a match. 838 */ 839static int 840rl_probe(dev) 841 device_t dev; 842{ 843 struct rl_type *t; 844 struct rl_softc *sc; 845 int rid; 846 u_int32_t hwrev; 847 848 t = rl_devs; 849 sc = device_get_softc(dev); 850 851 while(t->rl_name != NULL) { 852 if ((pci_get_vendor(dev) == t->rl_vid) && 853 (pci_get_device(dev) == t->rl_did)) { 854 855 /* 856 * Temporarily map the I/O space 857 * so we can read the chip ID register. 858 */ 859 rid = RL_RID; 860 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 861 0, ~0, 1, RF_ACTIVE); 862 if (sc->rl_res == NULL) { 863 device_printf(dev, 864 "couldn't map ports/memory\n"); 865 return(ENXIO); 866 } 867 sc->rl_btag = rman_get_bustag(sc->rl_res); 868 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 869 mtx_init(&sc->rl_mtx, 870 device_get_nameunit(dev), 871 MTX_NETWORK_LOCK, MTX_DEF); 872 RL_LOCK(sc); 873 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 874 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 875 RL_UNLOCK(sc); 876 mtx_destroy(&sc->rl_mtx); 877 878 /* Don't attach to 8139C+ or 8169/8110 chips. */ 879 if (hwrev == RL_HWREV_8139CPLUS || 880 (hwrev == RL_HWREV_8169 && 881 t->rl_did == RT_DEVICEID_8169) || 882 hwrev == RL_HWREV_8169S || 883 hwrev == RL_HWREV_8110S) { 884 t++; 885 continue; 886 } 887 888 device_set_desc(dev, t->rl_name); 889 return(0); 890 } 891 t++; 892 } 893 894 return(ENXIO); 895} 896 897/* 898 * Attach the interface. Allocate softc structures, do ifmedia 899 * setup and ethernet/BPF attach. 900 */ 901static int 902rl_attach(dev) 903 device_t dev; 904{ 905 u_char eaddr[ETHER_ADDR_LEN]; 906 u_int16_t as[3]; 907 struct rl_softc *sc; 908 struct ifnet *ifp; 909 u_int16_t rl_did = 0; 910 struct rl_type *t; 911 int unit, error = 0, rid, i; 912 913 sc = device_get_softc(dev); 914 unit = device_get_unit(dev); 915 916 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 917 MTX_DEF | MTX_RECURSE); 918#ifndef BURN_BRIDGES 919 /* 920 * Handle power management nonsense. 921 */ 922 923 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 924 u_int32_t iobase, membase, irq; 925 926 /* Save important PCI config data. */ 927 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 928 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 929 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 930 931 /* Reset the power state. */ 932 printf("rl%d: chip is is in D%d power mode " 933 "-- setting to D0\n", unit, 934 pci_get_powerstate(dev)); 935 936 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 937 938 /* Restore PCI config data. */ 939 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 940 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 941 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 942 } 943#endif 944 /* 945 * Map control/status registers. 946 */ 947 pci_enable_busmaster(dev); 948 949 rid = RL_RID; 950 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 951 0, ~0, 1, RF_ACTIVE); 952 953 if (sc->rl_res == NULL) { 954 printf ("rl%d: couldn't map ports/memory\n", unit); 955 error = ENXIO; 956 goto fail; 957 } 958 959#ifdef notdef 960 /* Detect the Realtek 8139B. For some reason, this chip is very 961 * unstable when left to autoselect the media 962 * The best workaround is to set the device to the required 963 * media type or to set it to the 10 Meg speed. 964 */ 965 966 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 967 printf("rl%d: Realtek 8139B detected. Warning, " 968 "this may be unstable in autoselect mode\n", unit); 969 } 970#endif 971 972 sc->rl_btag = rman_get_bustag(sc->rl_res); 973 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 974 975 /* Allocate interrupt */ 976 rid = 0; 977 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 978 RF_SHAREABLE | RF_ACTIVE); 979 980 if (sc->rl_irq == NULL) { 981 printf("rl%d: couldn't map interrupt\n", unit); 982 error = ENXIO; 983 goto fail; 984 } 985 986 /* Reset the adapter. */ 987 rl_reset(sc); 988 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 989 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 990 if (rl_did != 0x8129) 991 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 992 993 /* 994 * Get station address from the EEPROM. 995 */ 996 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 997 for (i = 0; i < 3; i++) { 998 eaddr[(i * 2) + 0] = as[i] & 0xff; 999 eaddr[(i * 2) + 1] = as[i] >> 8; 1000 } 1001 1002 /* 1003 * A RealTek chip was detected. Inform the world. 1004 */ 1005 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1006 1007 sc->rl_unit = unit; 1008 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1009 1010 /* 1011 * Now read the exact device type from the EEPROM to find 1012 * out if it's an 8129 or 8139. 1013 */ 1014 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1015 1016 t = rl_devs; 1017 sc->rl_type = 0; 1018 while(t->rl_name != NULL) { 1019 if (rl_did == t->rl_did) { 1020 sc->rl_type = t->rl_basetype; 1021 break; 1022 } 1023 t++; 1024 } 1025 1026 if (sc->rl_type == 0) { 1027 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1028 error = ENXIO; 1029 goto fail; 1030 } 1031 1032 /* 1033 * Allocate the parent bus DMA tag appropriate for PCI. 1034 */ 1035#define RL_NSEG_NEW 32 1036 error = bus_dma_tag_create(NULL, /* parent */ 1037 1, 0, /* alignment, boundary */ 1038 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1039 BUS_SPACE_MAXADDR, /* highaddr */ 1040 NULL, NULL, /* filter, filterarg */ 1041 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1042 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1043 BUS_DMA_ALLOCNOW, /* flags */ 1044 NULL, NULL, /* lockfunc, lockarg */ 1045 &sc->rl_parent_tag); 1046 if (error) 1047 goto fail; 1048 1049 /* 1050 * Now allocate a tag for the DMA descriptor lists. 1051 * All of our lists are allocated as a contiguous block 1052 * of memory. 1053 */ 1054 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1055 1, 0, /* alignment, boundary */ 1056 BUS_SPACE_MAXADDR, /* lowaddr */ 1057 BUS_SPACE_MAXADDR, /* highaddr */ 1058 NULL, NULL, /* filter, filterarg */ 1059 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1060 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1061 BUS_DMA_ALLOCNOW, /* flags */ 1062 NULL, NULL, /* lockfunc, lockarg */ 1063 &sc->rl_tag); 1064 if (error) 1065 goto fail; 1066 1067 /* 1068 * Now allocate a chunk of DMA-able memory based on the 1069 * tag we just created. 1070 */ 1071 error = bus_dmamem_alloc(sc->rl_tag, 1072 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1073 &sc->rl_cdata.rl_rx_dmamap); 1074 1075 if (error) { 1076 printf("rl%d: no memory for list buffers!\n", unit); 1077 bus_dma_tag_destroy(sc->rl_tag); 1078 sc->rl_tag = NULL; 1079 goto fail; 1080 } 1081 1082 /* Leave a few bytes before the start of the RX ring buffer. */ 1083 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1084 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1085 1086 /* Do MII setup */ 1087 if (mii_phy_probe(dev, &sc->rl_miibus, 1088 rl_ifmedia_upd, rl_ifmedia_sts)) { 1089 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1090 error = ENXIO; 1091 goto fail; 1092 } 1093 1094 ifp = &sc->arpcom.ac_if; 1095 ifp->if_softc = sc; 1096 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1097 ifp->if_mtu = ETHERMTU; 1098 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1099 ifp->if_ioctl = rl_ioctl; 1100 ifp->if_output = ether_output; 1101 ifp->if_start = rl_start; 1102 ifp->if_watchdog = rl_watchdog; 1103 ifp->if_init = rl_init; 1104 ifp->if_baudrate = 10000000; 1105 ifp->if_capabilities = IFCAP_VLAN_MTU; 1106 ifp->if_capenable = ifp->if_capabilities; 1107 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1108 1109 callout_handle_init(&sc->rl_stat_ch); 1110 1111 /* 1112 * Call MI attach routine. 1113 */ 1114 ether_ifattach(ifp, eaddr); 1115 1116 /* Hook interrupt last to avoid having to lock softc */ 1117 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1118 rl_intr, sc, &sc->rl_intrhand); 1119 1120 if (error) { 1121 printf("rl%d: couldn't set up irq\n", unit); 1122 ether_ifdetach(ifp); 1123 goto fail; 1124 } 1125 1126fail: 1127 if (error) 1128 rl_detach(dev); 1129 1130 return (error); 1131} 1132 1133/* 1134 * Shutdown hardware and free up resources. This can be called any 1135 * time after the mutex has been initialized. It is called in both 1136 * the error case in attach and the normal detach case so it needs 1137 * to be careful about only freeing resources that have actually been 1138 * allocated. 1139 */ 1140static int 1141rl_detach(dev) 1142 device_t dev; 1143{ 1144 struct rl_softc *sc; 1145 struct ifnet *ifp; 1146 1147 sc = device_get_softc(dev); 1148 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1149 RL_LOCK(sc); 1150 ifp = &sc->arpcom.ac_if; 1151 1152 /* These should only be active if attach succeeded */ 1153 if (device_is_attached(dev)) { 1154 rl_stop(sc); 1155 ether_ifdetach(ifp); 1156 } 1157 if (sc->rl_miibus) 1158 device_delete_child(dev, sc->rl_miibus); 1159 bus_generic_detach(dev); 1160 1161 if (sc->rl_intrhand) 1162 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1163 if (sc->rl_irq) 1164 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1165 if (sc->rl_res) 1166 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1167 1168 if (sc->rl_tag) { 1169 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1170 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1171 sc->rl_cdata.rl_rx_dmamap); 1172 bus_dma_tag_destroy(sc->rl_tag); 1173 } 1174 if (sc->rl_parent_tag) 1175 bus_dma_tag_destroy(sc->rl_parent_tag); 1176 1177 RL_UNLOCK(sc); 1178 mtx_destroy(&sc->rl_mtx); 1179 1180 return(0); 1181} 1182 1183/* 1184 * Initialize the transmit descriptors. 1185 */ 1186static int 1187rl_list_tx_init(sc) 1188 struct rl_softc *sc; 1189{ 1190 struct rl_chain_data *cd; 1191 int i; 1192 1193 cd = &sc->rl_cdata; 1194 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1195 cd->rl_tx_chain[i] = NULL; 1196 CSR_WRITE_4(sc, 1197 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1198 } 1199 1200 sc->rl_cdata.cur_tx = 0; 1201 sc->rl_cdata.last_tx = 0; 1202 1203 return(0); 1204} 1205 1206/* 1207 * A frame has been uploaded: pass the resulting mbuf chain up to 1208 * the higher level protocols. 1209 * 1210 * You know there's something wrong with a PCI bus-master chip design 1211 * when you have to use m_devget(). 1212 * 1213 * The receive operation is badly documented in the datasheet, so I'll 1214 * attempt to document it here. The driver provides a buffer area and 1215 * places its base address in the RX buffer start address register. 1216 * The chip then begins copying frames into the RX buffer. Each frame 1217 * is preceded by a 32-bit RX status word which specifies the length 1218 * of the frame and certain other status bits. Each frame (starting with 1219 * the status word) is also 32-bit aligned. The frame length is in the 1220 * first 16 bits of the status word; the lower 15 bits correspond with 1221 * the 'rx status register' mentioned in the datasheet. 1222 * 1223 * Note: to make the Alpha happy, the frame payload needs to be aligned 1224 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1225 * as the offset argument to m_devget(). 1226 */ 1227static void 1228rl_rxeof(sc) 1229 struct rl_softc *sc; 1230{ 1231 struct mbuf *m; 1232 struct ifnet *ifp; 1233 int total_len = 0; 1234 u_int32_t rxstat; 1235 caddr_t rxbufpos; 1236 int wrap = 0; 1237 u_int16_t cur_rx; 1238 u_int16_t limit; 1239 u_int16_t rx_bytes = 0, max_bytes; 1240 1241 RL_LOCK_ASSERT(sc); 1242 1243 ifp = &sc->arpcom.ac_if; 1244 1245 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1246 BUS_DMASYNC_POSTREAD); 1247 1248 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1249 1250 /* Do not try to read past this point. */ 1251 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1252 1253 if (limit < cur_rx) 1254 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1255 else 1256 max_bytes = limit - cur_rx; 1257 1258 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1259#ifdef DEVICE_POLLING 1260 if (ifp->if_flags & IFF_POLLING) { 1261 if (sc->rxcycles <= 0) 1262 break; 1263 sc->rxcycles--; 1264 } 1265#endif /* DEVICE_POLLING */ 1266 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1267 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1268 1269 /* 1270 * Here's a totally undocumented fact for you. When the 1271 * RealTek chip is in the process of copying a packet into 1272 * RAM for you, the length will be 0xfff0. If you spot a 1273 * packet header with this value, you need to stop. The 1274 * datasheet makes absolutely no mention of this and 1275 * RealTek should be shot for this. 1276 */ 1277 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1278 break; 1279 1280 if (!(rxstat & RL_RXSTAT_RXOK)) { 1281 ifp->if_ierrors++; 1282 rl_init(sc); 1283 return; 1284 } 1285 1286 /* No errors; receive the packet. */ 1287 total_len = rxstat >> 16; 1288 rx_bytes += total_len + 4; 1289 1290 /* 1291 * XXX The RealTek chip includes the CRC with every 1292 * received frame, and there's no way to turn this 1293 * behavior off (at least, I can't find anything in 1294 * the manual that explains how to do it) so we have 1295 * to trim off the CRC manually. 1296 */ 1297 total_len -= ETHER_CRC_LEN; 1298 1299 /* 1300 * Avoid trying to read more bytes than we know 1301 * the chip has prepared for us. 1302 */ 1303 if (rx_bytes > max_bytes) 1304 break; 1305 1306 rxbufpos = sc->rl_cdata.rl_rx_buf + 1307 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1308 1309 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1310 rxbufpos = sc->rl_cdata.rl_rx_buf; 1311 1312 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1313 1314 if (total_len > wrap) { 1315 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1316 NULL); 1317 if (m == NULL) { 1318 ifp->if_ierrors++; 1319 } else { 1320 m_copyback(m, wrap, total_len - wrap, 1321 sc->rl_cdata.rl_rx_buf); 1322 } 1323 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1324 } else { 1325 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1326 NULL); 1327 if (m == NULL) { 1328 ifp->if_ierrors++; 1329 } 1330 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1331 } 1332 1333 /* 1334 * Round up to 32-bit boundary. 1335 */ 1336 cur_rx = (cur_rx + 3) & ~3; 1337 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1338 1339 if (m == NULL) 1340 continue; 1341 1342 ifp->if_ipackets++; 1343 RL_UNLOCK(sc); 1344 (*ifp->if_input)(ifp, m); 1345 RL_LOCK(sc); 1346 } 1347 1348 return; 1349} 1350 1351/* 1352 * A frame was downloaded to the chip. It's safe for us to clean up 1353 * the list buffers. 1354 */ 1355static void 1356rl_txeof(sc) 1357 struct rl_softc *sc; 1358{ 1359 struct ifnet *ifp; 1360 u_int32_t txstat; 1361 1362 ifp = &sc->arpcom.ac_if; 1363 1364 /* 1365 * Go through our tx list and free mbufs for those 1366 * frames that have been uploaded. 1367 */ 1368 do { 1369 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1370 if (!(txstat & (RL_TXSTAT_TX_OK| 1371 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1372 break; 1373 1374 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1375 1376 if (RL_LAST_TXMBUF(sc) != NULL) { 1377 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1378 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1379 m_freem(RL_LAST_TXMBUF(sc)); 1380 RL_LAST_TXMBUF(sc) = NULL; 1381 } 1382 if (txstat & RL_TXSTAT_TX_OK) 1383 ifp->if_opackets++; 1384 else { 1385 int oldthresh; 1386 ifp->if_oerrors++; 1387 if ((txstat & RL_TXSTAT_TXABRT) || 1388 (txstat & RL_TXSTAT_OUTOFWIN)) 1389 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1390 oldthresh = sc->rl_txthresh; 1391 /* error recovery */ 1392 rl_reset(sc); 1393 rl_init(sc); 1394 /* 1395 * If there was a transmit underrun, 1396 * bump the TX threshold. 1397 */ 1398 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1399 sc->rl_txthresh = oldthresh + 32; 1400 return; 1401 } 1402 RL_INC(sc->rl_cdata.last_tx); 1403 ifp->if_flags &= ~IFF_OACTIVE; 1404 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1405 1406 ifp->if_timer = 1407 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1408 1409 return; 1410} 1411 1412static void 1413rl_tick(xsc) 1414 void *xsc; 1415{ 1416 struct rl_softc *sc; 1417 struct mii_data *mii; 1418 1419 sc = xsc; 1420 RL_LOCK(sc); 1421 mii = device_get_softc(sc->rl_miibus); 1422 1423 mii_tick(mii); 1424 1425 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1426 RL_UNLOCK(sc); 1427 1428 return; 1429} 1430 1431#ifdef DEVICE_POLLING 1432static void 1433rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1434{ 1435 struct rl_softc *sc = ifp->if_softc; 1436 1437 RL_LOCK(sc); 1438 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1439 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1440 goto done; 1441 } 1442 1443 sc->rxcycles = count; 1444 rl_rxeof(sc); 1445 rl_txeof(sc); 1446 if (ifp->if_snd.ifq_head != NULL) 1447 rl_start(ifp); 1448 1449 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1450 u_int16_t status; 1451 1452 status = CSR_READ_2(sc, RL_ISR); 1453 if (status == 0xffff) 1454 goto done; 1455 if (status) 1456 CSR_WRITE_2(sc, RL_ISR, status); 1457 1458 /* 1459 * XXX check behaviour on receiver stalls. 1460 */ 1461 1462 if (status & RL_ISR_SYSTEM_ERR) { 1463 rl_reset(sc); 1464 rl_init(sc); 1465 } 1466 } 1467done: 1468 RL_UNLOCK(sc); 1469} 1470#endif /* DEVICE_POLLING */ 1471 1472static void 1473rl_intr(arg) 1474 void *arg; 1475{ 1476 struct rl_softc *sc; 1477 struct ifnet *ifp; 1478 u_int16_t status; 1479 1480 sc = arg; 1481 1482 if (sc->suspended) { 1483 return; 1484 } 1485 1486 RL_LOCK(sc); 1487 ifp = &sc->arpcom.ac_if; 1488 1489#ifdef DEVICE_POLLING 1490 if (ifp->if_flags & IFF_POLLING) 1491 goto done; 1492 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1493 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1494 rl_poll(ifp, 0, 1); 1495 goto done; 1496 } 1497#endif /* DEVICE_POLLING */ 1498 1499 for (;;) { 1500 1501 status = CSR_READ_2(sc, RL_ISR); 1502 /* If the card has gone away the read returns 0xffff. */ 1503 if (status == 0xffff) 1504 break; 1505 if (status) 1506 CSR_WRITE_2(sc, RL_ISR, status); 1507 1508 if ((status & RL_INTRS) == 0) 1509 break; 1510 1511 if (status & RL_ISR_RX_OK) 1512 rl_rxeof(sc); 1513 1514 if (status & RL_ISR_RX_ERR) 1515 rl_rxeof(sc); 1516 1517 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1518 rl_txeof(sc); 1519 1520 if (status & RL_ISR_SYSTEM_ERR) { 1521 rl_reset(sc); 1522 rl_init(sc); 1523 } 1524 1525 } 1526 1527 if (ifp->if_snd.ifq_head != NULL) 1528 rl_start(ifp); 1529 1530#ifdef DEVICE_POLLING 1531done: 1532#endif 1533 RL_UNLOCK(sc); 1534 1535 return; 1536} 1537 1538/* 1539 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1540 * pointers to the fragment pointers. 1541 */ 1542static int 1543rl_encap(sc, m_head) 1544 struct rl_softc *sc; 1545 struct mbuf *m_head; 1546{ 1547 struct mbuf *m_new = NULL; 1548 1549 /* 1550 * The RealTek is brain damaged and wants longword-aligned 1551 * TX buffers, plus we can only have one fragment buffer 1552 * per packet. We have to copy pretty much all the time. 1553 */ 1554 m_new = m_defrag(m_head, M_DONTWAIT); 1555 1556 if (m_new == NULL) { 1557 m_freem(m_head); 1558 return(1); 1559 } 1560 m_head = m_new; 1561 1562 /* Pad frames to at least 60 bytes. */ 1563 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1564 /* 1565 * Make security concious people happy: zero out the 1566 * bytes in the pad area, since we don't know what 1567 * this mbuf cluster buffer's previous user might 1568 * have left in it. 1569 */ 1570 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1571 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1572 m_head->m_pkthdr.len += 1573 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1574 m_head->m_len = m_head->m_pkthdr.len; 1575 } 1576 1577 RL_CUR_TXMBUF(sc) = m_head; 1578 1579 return(0); 1580} 1581 1582/* 1583 * Main transmit routine. 1584 */ 1585 1586static void 1587rl_start(ifp) 1588 struct ifnet *ifp; 1589{ 1590 struct rl_softc *sc; 1591 struct mbuf *m_head = NULL; 1592 1593 sc = ifp->if_softc; 1594 RL_LOCK(sc); 1595 1596 while(RL_CUR_TXMBUF(sc) == NULL) { 1597 IF_DEQUEUE(&ifp->if_snd, m_head); 1598 if (m_head == NULL) 1599 break; 1600 1601 if (rl_encap(sc, m_head)) { 1602 break; 1603 } 1604 1605 /* 1606 * If there's a BPF listener, bounce a copy of this frame 1607 * to him. 1608 */ 1609 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1610 1611 /* 1612 * Transmit the frame. 1613 */ 1614 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1615 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1616 mtod(RL_CUR_TXMBUF(sc), void *), 1617 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1618 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1619 BUS_DMASYNC_PREREAD); 1620 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1621 RL_TXTHRESH(sc->rl_txthresh) | 1622 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1623 1624 RL_INC(sc->rl_cdata.cur_tx); 1625 1626 /* 1627 * Set a timeout in case the chip goes out to lunch. 1628 */ 1629 ifp->if_timer = 5; 1630 } 1631 1632 /* 1633 * We broke out of the loop because all our TX slots are 1634 * full. Mark the NIC as busy until it drains some of the 1635 * packets from the queue. 1636 */ 1637 if (RL_CUR_TXMBUF(sc) != NULL) 1638 ifp->if_flags |= IFF_OACTIVE; 1639 1640 RL_UNLOCK(sc); 1641 1642 return; 1643} 1644 1645static void 1646rl_init(xsc) 1647 void *xsc; 1648{ 1649 struct rl_softc *sc = xsc; 1650 struct ifnet *ifp = &sc->arpcom.ac_if; 1651 struct mii_data *mii; 1652 u_int32_t rxcfg = 0; 1653 1654 RL_LOCK(sc); 1655 mii = device_get_softc(sc->rl_miibus); 1656 1657 /* 1658 * Cancel pending I/O and free all RX/TX buffers. 1659 */ 1660 rl_stop(sc); 1661 1662 /* 1663 * Init our MAC address. Even though the chipset 1664 * documentation doesn't mention it, we need to enter "Config 1665 * register write enable" mode to modify the ID registers. 1666 */ 1667 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1668 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1669 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1670 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1671 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1672 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1673 1674 /* Init the RX buffer pointer register. */ 1675 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1676 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1677 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1678 BUS_DMASYNC_PREWRITE); 1679 1680 /* Init TX descriptors. */ 1681 rl_list_tx_init(sc); 1682 1683 /* 1684 * Enable transmit and receive. 1685 */ 1686 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1687 1688 /* 1689 * Set the initial TX and RX configuration. 1690 */ 1691 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1692 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1693 1694 /* Set the individual bit to receive frames for this host only. */ 1695 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1696 rxcfg |= RL_RXCFG_RX_INDIV; 1697 1698 /* If we want promiscuous mode, set the allframes bit. */ 1699 if (ifp->if_flags & IFF_PROMISC) { 1700 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1701 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1702 } else { 1703 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1704 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1705 } 1706 1707 /* 1708 * Set capture broadcast bit to capture broadcast frames. 1709 */ 1710 if (ifp->if_flags & IFF_BROADCAST) { 1711 rxcfg |= RL_RXCFG_RX_BROAD; 1712 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1713 } else { 1714 rxcfg &= ~RL_RXCFG_RX_BROAD; 1715 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1716 } 1717 1718 /* 1719 * Program the multicast filter, if necessary. 1720 */ 1721 rl_setmulti(sc); 1722 1723#ifdef DEVICE_POLLING 1724 /* 1725 * Disable interrupts if we are polling. 1726 */ 1727 if (ifp->if_flags & IFF_POLLING) 1728 CSR_WRITE_2(sc, RL_IMR, 0); 1729 else /* otherwise ... */ 1730#endif /* DEVICE_POLLING */ 1731 /* 1732 * Enable interrupts. 1733 */ 1734 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1735 1736 /* Set initial TX threshold */ 1737 sc->rl_txthresh = RL_TX_THRESH_INIT; 1738 1739 /* Start RX/TX process. */ 1740 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1741 1742 /* Enable receiver and transmitter. */ 1743 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1744 1745 mii_mediachg(mii); 1746 1747 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1748 1749 ifp->if_flags |= IFF_RUNNING; 1750 ifp->if_flags &= ~IFF_OACTIVE; 1751 1752 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1753 RL_UNLOCK(sc); 1754 1755 return; 1756} 1757 1758/* 1759 * Set media options. 1760 */ 1761static int 1762rl_ifmedia_upd(ifp) 1763 struct ifnet *ifp; 1764{ 1765 struct rl_softc *sc; 1766 struct mii_data *mii; 1767 1768 sc = ifp->if_softc; 1769 mii = device_get_softc(sc->rl_miibus); 1770 mii_mediachg(mii); 1771 1772 return(0); 1773} 1774 1775/* 1776 * Report current media status. 1777 */ 1778static void 1779rl_ifmedia_sts(ifp, ifmr) 1780 struct ifnet *ifp; 1781 struct ifmediareq *ifmr; 1782{ 1783 struct rl_softc *sc; 1784 struct mii_data *mii; 1785 1786 sc = ifp->if_softc; 1787 mii = device_get_softc(sc->rl_miibus); 1788 1789 mii_pollstat(mii); 1790 ifmr->ifm_active = mii->mii_media_active; 1791 ifmr->ifm_status = mii->mii_media_status; 1792 1793 return; 1794} 1795 1796static int 1797rl_ioctl(ifp, command, data) 1798 struct ifnet *ifp; 1799 u_long command; 1800 caddr_t data; 1801{ 1802 struct rl_softc *sc = ifp->if_softc; 1803 struct ifreq *ifr = (struct ifreq *) data; 1804 struct mii_data *mii; 1805 int error = 0; 1806 1807 RL_LOCK(sc); 1808 1809 switch(command) { 1810 case SIOCSIFFLAGS: 1811 if (ifp->if_flags & IFF_UP) { 1812 rl_init(sc); 1813 } else { 1814 if (ifp->if_flags & IFF_RUNNING) 1815 rl_stop(sc); 1816 } 1817 error = 0; 1818 break; 1819 case SIOCADDMULTI: 1820 case SIOCDELMULTI: 1821 rl_setmulti(sc); 1822 error = 0; 1823 break; 1824 case SIOCGIFMEDIA: 1825 case SIOCSIFMEDIA: 1826 mii = device_get_softc(sc->rl_miibus); 1827 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1828 break; 1829 default: 1830 error = ether_ioctl(ifp, command, data); 1831 break; 1832 } 1833 1834 RL_UNLOCK(sc); 1835 1836 return(error); 1837} 1838 1839static void 1840rl_watchdog(ifp) 1841 struct ifnet *ifp; 1842{ 1843 struct rl_softc *sc; 1844 1845 sc = ifp->if_softc; 1846 RL_LOCK(sc); 1847 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1848 ifp->if_oerrors++; 1849 1850 rl_txeof(sc); 1851 rl_rxeof(sc); 1852 rl_init(sc); 1853 RL_UNLOCK(sc); 1854 1855 return; 1856} 1857 1858/* 1859 * Stop the adapter and free any mbufs allocated to the 1860 * RX and TX lists. 1861 */ 1862static void 1863rl_stop(sc) 1864 struct rl_softc *sc; 1865{ 1866 register int i; 1867 struct ifnet *ifp; 1868 1869 RL_LOCK(sc); 1870 ifp = &sc->arpcom.ac_if; 1871 ifp->if_timer = 0; 1872 1873 untimeout(rl_tick, sc, sc->rl_stat_ch); 1874 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1875#ifdef DEVICE_POLLING 1876 ether_poll_deregister(ifp); 1877#endif /* DEVICE_POLLING */ 1878 1879 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1880 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1881 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1882 1883 /* 1884 * Free the TX list buffers. 1885 */ 1886 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1887 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1888 bus_dmamap_unload(sc->rl_tag, 1889 sc->rl_cdata.rl_tx_dmamap[i]); 1890 bus_dmamap_destroy(sc->rl_tag, 1891 sc->rl_cdata.rl_tx_dmamap[i]); 1892 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1893 sc->rl_cdata.rl_tx_chain[i] = NULL; 1894 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)), 1895 0x0000000); 1896 } 1897 } 1898 1899 RL_UNLOCK(sc); 1900 return; 1901} 1902 1903/* 1904 * Device suspend routine. Stop the interface and save some PCI 1905 * settings in case the BIOS doesn't restore them properly on 1906 * resume. 1907 */ 1908static int 1909rl_suspend(dev) 1910 device_t dev; 1911{ 1912 register int i; 1913 struct rl_softc *sc; 1914 1915 sc = device_get_softc(dev); 1916 1917 rl_stop(sc); 1918 1919 for (i = 0; i < 5; i++) 1920 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1921 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1922 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1923 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1924 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1925 1926 sc->suspended = 1; 1927 1928 return (0); 1929} 1930 1931/* 1932 * Device resume routine. Restore some PCI settings in case the BIOS 1933 * doesn't, re-enable busmastering, and restart the interface if 1934 * appropriate. 1935 */ 1936static int 1937rl_resume(dev) 1938 device_t dev; 1939{ 1940 register int i; 1941 struct rl_softc *sc; 1942 struct ifnet *ifp; 1943 1944 sc = device_get_softc(dev); 1945 ifp = &sc->arpcom.ac_if; 1946 1947 /* better way to do this? */ 1948 for (i = 0; i < 5; i++) 1949 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1950 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1951 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1952 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1953 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1954 1955 /* reenable busmastering */ 1956 pci_enable_busmaster(dev); 1957 pci_enable_io(dev, RL_RES); 1958 1959 /* reinitialize interface if necessary */ 1960 if (ifp->if_flags & IFF_UP) 1961 rl_init(sc); 1962 1963 sc->suspended = 0; 1964 1965 return (0); 1966} 1967 1968/* 1969 * Stop all chip I/O so that the kernel's probe routines don't 1970 * get confused by errant DMAs when rebooting. 1971 */ 1972static void 1973rl_shutdown(dev) 1974 device_t dev; 1975{ 1976 struct rl_softc *sc; 1977 1978 sc = device_get_softc(dev); 1979 1980 rl_stop(sc); 1981 1982 return; 1983} 1984