if_rl.c revision 119977
140516Swpaul/* 2119868Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul */ 3240516Swpaul 3340516Swpaul/* 34119868Swpaul * RealTek 8129/8139 PCI NIC driver 3540516Swpaul * 36119868Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 37119868Swpaul * the RealTek chipset. Datasheets can be obtained from 3840516Swpaul * www.realtek.com.tw. 3940516Swpaul * 40119868Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 41119868Swpaul * Electrical Engineering Department 42119868Swpaul * Columbia University, New York City 4340516Swpaul */ 4440516Swpaul 4540516Swpaul/* 4640516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4740516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 4840516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 4940516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5040516Swpaul * gains that bus-master DMA usually offers. 5140516Swpaul * 5240516Swpaul * For transmission, the chip offers a series of four TX descriptor 5340516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5441569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5540516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5640516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5740516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 5840516Swpaul * four descriptor registers means that we can never have more than four 5940516Swpaul * packets queued for transmission at any one time. 6040516Swpaul * 6140516Swpaul * Reception is not much better. The driver has to allocate a single large 6240516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6340516Swpaul * frames. Because we don't know where within this region received packets 6440516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6540516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6640516Swpaul * levels. 6740516Swpaul * 6840516Swpaul * It's impossible given this rotten design to really achieve decent 6940516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7040516Swpaul * some equally overmuscled CPU to drive it. 7140516Swpaul * 7240516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7340516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7440516Swpaul * PHY registers are directly accessible through the 8139's register 7540516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7640516Swpaul * filter. 7740516Swpaul * 7840516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 7940516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8040516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8140516Swpaul * to select which interface to use depending on the chip type. 8240516Swpaul */ 8340516Swpaul 84116192Sobrien#include <sys/cdefs.h> 85116192Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 119977 2003-09-11 04:05:01Z wpaul $"); 86116192Sobrien 8740516Swpaul#include <sys/param.h> 88108729Sjake#include <sys/endian.h> 8940516Swpaul#include <sys/systm.h> 9040516Swpaul#include <sys/sockio.h> 9140516Swpaul#include <sys/mbuf.h> 9240516Swpaul#include <sys/malloc.h> 9340516Swpaul#include <sys/kernel.h> 9440516Swpaul#include <sys/socket.h> 9540516Swpaul 9640516Swpaul#include <net/if.h> 9740516Swpaul#include <net/if_arp.h> 9840516Swpaul#include <net/ethernet.h> 9940516Swpaul#include <net/if_dl.h> 10040516Swpaul#include <net/if_media.h> 10140516Swpaul 10240516Swpaul#include <net/bpf.h> 10340516Swpaul 10441569Swpaul#include <machine/bus_pio.h> 10541569Swpaul#include <machine/bus_memio.h> 10641569Swpaul#include <machine/bus.h> 10750703Swpaul#include <machine/resource.h> 10850703Swpaul#include <sys/bus.h> 10950703Swpaul#include <sys/rman.h> 11040516Swpaul 11150703Swpaul#include <dev/mii/mii.h> 11250703Swpaul#include <dev/mii/miivar.h> 11350703Swpaul 114119871Swpaul#include <dev/pci/pcireg.h> 115119871Swpaul#include <dev/pci/pcivar.h> 11640516Swpaul 117113506SmdoddMODULE_DEPEND(rl, pci, 1, 1, 1); 118113506SmdoddMODULE_DEPEND(rl, ether, 1, 1, 1); 11959758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 12059758Speter 12151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12250703Swpaul#include "miibus_if.h" 12350703Swpaul 12440516Swpaul/* 12540516Swpaul * Default to using PIO access for this driver. On SMP systems, 12640516Swpaul * there appear to be problems with memory mapped mode: it looks like 12740516Swpaul * doing too many memory mapped access back to back in rapid succession 12840516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12940516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 13040516Swpaul * uniprocessor systems though. 13140516Swpaul */ 13240516Swpaul#define RL_USEIOSPACE 13340516Swpaul 13440516Swpaul#include <pci/if_rlreg.h> 13540516Swpaul 13640516Swpaul/* 13740516Swpaul * Various supported device vendors/types and their names. 13840516Swpaul */ 13940516Swpaulstatic struct rl_type rl_devs[] = { 140117388Swpaul { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 14140516Swpaul "RealTek 8129 10/100BaseTX" }, 142117388Swpaul { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 14340516Swpaul "RealTek 8139 10/100BaseTX" }, 144117388Swpaul { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 14567771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 146118978Swpaul { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 147118978Swpaul "RealTek 8100 10/100BaseTX" }, 148117388Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 14941243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 150117388Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 15144238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 152117388Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 15344238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 154117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 15572813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 156117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 15796112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 158117388Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 15994400Swpaul "Nortel Networks 10/100BaseTX" }, 160117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 161103020Siwasaki "Corega FEther CB-TXD" }, 162117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 163109095Ssanpei "Corega FEtherII CB-TXD" }, 164117388Swpaul { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 165111381Sdan "Peppercon AG ROL-F" }, 166117388Swpaul { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 167112379Ssanpei "Planex FNW-3800-TX" }, 168117388Swpaul { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 169117388Swpaul "Compaq HNE-300" }, 170117388Swpaul { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 171117388Swpaul "LevelOne FPC-0106TX" }, 172117388Swpaul { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 173117388Swpaul "Edimax EP-4103DL CardBus" }, 17440516Swpaul { 0, 0, NULL } 17540516Swpaul}; 17640516Swpaul 17792739Salfredstatic int rl_probe (device_t); 17892739Salfredstatic int rl_attach (device_t); 17992739Salfredstatic int rl_detach (device_t); 18040516Swpaul 181119868Swpaulstatic int rl_encap (struct rl_softc *, struct mbuf * ); 18240516Swpaul 18392739Salfredstatic void rl_rxeof (struct rl_softc *); 18492739Salfredstatic void rl_txeof (struct rl_softc *); 18592739Salfredstatic void rl_intr (void *); 18692739Salfredstatic void rl_tick (void *); 18792739Salfredstatic void rl_start (struct ifnet *); 18892739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 18992739Salfredstatic void rl_init (void *); 19092739Salfredstatic void rl_stop (struct rl_softc *); 19192739Salfredstatic void rl_watchdog (struct ifnet *); 19292739Salfredstatic int rl_suspend (device_t); 19392739Salfredstatic int rl_resume (device_t); 19492739Salfredstatic void rl_shutdown (device_t); 19592739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 19692739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 19740516Swpaul 19892739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 19992739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 20092739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 20192739Salfredstatic void rl_mii_sync (struct rl_softc *); 20292739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 20392739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 20492739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 20540516Swpaul 20692739Salfredstatic int rl_miibus_readreg (device_t, int, int); 20792739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 20892739Salfredstatic void rl_miibus_statchg (device_t); 20940516Swpaul 21092739Salfredstatic u_int8_t rl_calchash (caddr_t); 21192739Salfredstatic void rl_setmulti (struct rl_softc *); 21292739Salfredstatic void rl_reset (struct rl_softc *); 21392739Salfredstatic int rl_list_tx_init (struct rl_softc *); 21440516Swpaul 21592739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 21692739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 21781713Swpaul 21850703Swpaul#ifdef RL_USEIOSPACE 21950703Swpaul#define RL_RES SYS_RES_IOPORT 22050703Swpaul#define RL_RID RL_PCI_LOIO 22150703Swpaul#else 22250703Swpaul#define RL_RES SYS_RES_MEMORY 22350703Swpaul#define RL_RID RL_PCI_LOMEM 22450703Swpaul#endif 22550703Swpaul 22650703Swpaulstatic device_method_t rl_methods[] = { 22750703Swpaul /* Device interface */ 22850703Swpaul DEVMETHOD(device_probe, rl_probe), 22950703Swpaul DEVMETHOD(device_attach, rl_attach), 23050703Swpaul DEVMETHOD(device_detach, rl_detach), 23186822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 23286822Siwasaki DEVMETHOD(device_resume, rl_resume), 23350703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 23450703Swpaul 23550703Swpaul /* bus interface */ 23650703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 23750703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 23850703Swpaul 23950703Swpaul /* MII interface */ 24050703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 24150703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 24250703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 24350703Swpaul 24450703Swpaul { 0, 0 } 24550703Swpaul}; 24650703Swpaul 24750703Swpaulstatic driver_t rl_driver = { 24851455Swpaul "rl", 24950703Swpaul rl_methods, 25050703Swpaul sizeof(struct rl_softc) 25150703Swpaul}; 25250703Swpaul 25350703Swpaulstatic devclass_t rl_devclass; 25450703Swpaul 255113506SmdoddDRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 256113506SmdoddDRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 25751473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 25850703Swpaul 25940516Swpaul#define EE_SET(x) \ 26040516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 26140516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 26240516Swpaul 26340516Swpaul#define EE_CLR(x) \ 26440516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 26540516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 26640516Swpaul 26781713Swpaulstatic void 26881713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 26981713Swpaul void *arg; 27081713Swpaul bus_dma_segment_t *segs; 27181713Swpaul int nseg, error; 27281713Swpaul{ 27381713Swpaul struct rl_softc *sc; 27481713Swpaul 27581713Swpaul sc = arg; 27681713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 27781713Swpaul 27881713Swpaul return; 27981713Swpaul} 28081713Swpaul 28181713Swpaulstatic void 28281713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 28381713Swpaul void *arg; 28481713Swpaul bus_dma_segment_t *segs; 28581713Swpaul int nseg, error; 28681713Swpaul{ 28781713Swpaul struct rl_softc *sc; 28881713Swpaul 28981713Swpaul sc = arg; 29081713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 29181713Swpaul 29281713Swpaul return; 29381713Swpaul} 29481713Swpaul 29540516Swpaul/* 29640516Swpaul * Send a read command and address to the EEPROM, check for ACK. 29740516Swpaul */ 298102335Salfredstatic void 299102335Salfredrl_eeprom_putbyte(sc, addr) 30040516Swpaul struct rl_softc *sc; 30141656Swpaul int addr; 30240516Swpaul{ 30340516Swpaul register int d, i; 30440516Swpaul 30567931Swpaul d = addr | sc->rl_eecmd_read; 30640516Swpaul 30740516Swpaul /* 30855170Sbillf * Feed in each bit and strobe the clock. 30940516Swpaul */ 31040516Swpaul for (i = 0x400; i; i >>= 1) { 31140516Swpaul if (d & i) { 31240516Swpaul EE_SET(RL_EE_DATAIN); 31340516Swpaul } else { 31440516Swpaul EE_CLR(RL_EE_DATAIN); 31540516Swpaul } 31640516Swpaul DELAY(100); 31740516Swpaul EE_SET(RL_EE_CLK); 31840516Swpaul DELAY(150); 31940516Swpaul EE_CLR(RL_EE_CLK); 32040516Swpaul DELAY(100); 32140516Swpaul } 32240516Swpaul 32340516Swpaul return; 32440516Swpaul} 32540516Swpaul 32640516Swpaul/* 32740516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 32840516Swpaul */ 329102335Salfredstatic void 330102335Salfredrl_eeprom_getword(sc, addr, dest) 33140516Swpaul struct rl_softc *sc; 33241656Swpaul int addr; 33340516Swpaul u_int16_t *dest; 33440516Swpaul{ 33540516Swpaul register int i; 33640516Swpaul u_int16_t word = 0; 33740516Swpaul 33840516Swpaul /* Enter EEPROM access mode. */ 33940516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 34040516Swpaul 34140516Swpaul /* 34240516Swpaul * Send address of word we want to read. 34340516Swpaul */ 34440516Swpaul rl_eeprom_putbyte(sc, addr); 34540516Swpaul 34640516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 34740516Swpaul 34840516Swpaul /* 34940516Swpaul * Start reading bits from EEPROM. 35040516Swpaul */ 35140516Swpaul for (i = 0x8000; i; i >>= 1) { 35240516Swpaul EE_SET(RL_EE_CLK); 35340516Swpaul DELAY(100); 35440516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 35540516Swpaul word |= i; 35640516Swpaul EE_CLR(RL_EE_CLK); 35740516Swpaul DELAY(100); 35840516Swpaul } 35940516Swpaul 36040516Swpaul /* Turn off EEPROM access mode. */ 36140516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 36240516Swpaul 36340516Swpaul *dest = word; 36440516Swpaul 36540516Swpaul return; 36640516Swpaul} 36740516Swpaul 36840516Swpaul/* 36940516Swpaul * Read a sequence of words from the EEPROM. 37040516Swpaul */ 371102335Salfredstatic void 372102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 37340516Swpaul struct rl_softc *sc; 37440516Swpaul caddr_t dest; 37540516Swpaul int off; 37640516Swpaul int cnt; 37740516Swpaul int swap; 37840516Swpaul{ 37940516Swpaul int i; 38040516Swpaul u_int16_t word = 0, *ptr; 38140516Swpaul 38240516Swpaul for (i = 0; i < cnt; i++) { 38340516Swpaul rl_eeprom_getword(sc, off + i, &word); 38440516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 38540516Swpaul if (swap) 38640516Swpaul *ptr = ntohs(word); 38740516Swpaul else 38840516Swpaul *ptr = word; 38940516Swpaul } 39040516Swpaul 39140516Swpaul return; 39240516Swpaul} 39340516Swpaul 39440516Swpaul 39540516Swpaul/* 39640516Swpaul * MII access routines are provided for the 8129, which 39740516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 39840516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 39940516Swpaul * direct access PHY registers. 40040516Swpaul */ 40140516Swpaul#define MII_SET(x) \ 40240516Swpaul CSR_WRITE_1(sc, RL_MII, \ 403105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 40440516Swpaul 40540516Swpaul#define MII_CLR(x) \ 40640516Swpaul CSR_WRITE_1(sc, RL_MII, \ 407105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 40840516Swpaul 40940516Swpaul/* 41040516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 41140516Swpaul */ 412102335Salfredstatic void 413102335Salfredrl_mii_sync(sc) 41440516Swpaul struct rl_softc *sc; 41540516Swpaul{ 41640516Swpaul register int i; 41740516Swpaul 41840516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 41940516Swpaul 42040516Swpaul for (i = 0; i < 32; i++) { 42140516Swpaul MII_SET(RL_MII_CLK); 42240516Swpaul DELAY(1); 42340516Swpaul MII_CLR(RL_MII_CLK); 42440516Swpaul DELAY(1); 42540516Swpaul } 42640516Swpaul 42740516Swpaul return; 42840516Swpaul} 42940516Swpaul 43040516Swpaul/* 43140516Swpaul * Clock a series of bits through the MII. 43240516Swpaul */ 433102335Salfredstatic void 434102335Salfredrl_mii_send(sc, bits, cnt) 43540516Swpaul struct rl_softc *sc; 43640516Swpaul u_int32_t bits; 43740516Swpaul int cnt; 43840516Swpaul{ 43940516Swpaul int i; 44040516Swpaul 44140516Swpaul MII_CLR(RL_MII_CLK); 44240516Swpaul 44340516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 444109109Sdes if (bits & i) { 44540516Swpaul MII_SET(RL_MII_DATAOUT); 446109109Sdes } else { 44740516Swpaul MII_CLR(RL_MII_DATAOUT); 448109109Sdes } 44940516Swpaul DELAY(1); 45040516Swpaul MII_CLR(RL_MII_CLK); 45140516Swpaul DELAY(1); 45240516Swpaul MII_SET(RL_MII_CLK); 45340516Swpaul } 45440516Swpaul} 45540516Swpaul 45640516Swpaul/* 45740516Swpaul * Read an PHY register through the MII. 45840516Swpaul */ 459102335Salfredstatic int 460102335Salfredrl_mii_readreg(sc, frame) 46140516Swpaul struct rl_softc *sc; 46240516Swpaul struct rl_mii_frame *frame; 463109109Sdes 46440516Swpaul{ 46567087Swpaul int i, ack; 46640516Swpaul 46767087Swpaul RL_LOCK(sc); 46840516Swpaul 46940516Swpaul /* 47040516Swpaul * Set up frame for RX. 47140516Swpaul */ 47240516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 47340516Swpaul frame->mii_opcode = RL_MII_READOP; 47440516Swpaul frame->mii_turnaround = 0; 47540516Swpaul frame->mii_data = 0; 476109109Sdes 47740516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 47840516Swpaul 47940516Swpaul /* 480109109Sdes * Turn on data xmit. 48140516Swpaul */ 48240516Swpaul MII_SET(RL_MII_DIR); 48340516Swpaul 48440516Swpaul rl_mii_sync(sc); 48540516Swpaul 48640516Swpaul /* 48740516Swpaul * Send command/address info. 48840516Swpaul */ 48940516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 49040516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 49140516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 49240516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 49340516Swpaul 49440516Swpaul /* Idle bit */ 49540516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 49640516Swpaul DELAY(1); 49740516Swpaul MII_SET(RL_MII_CLK); 49840516Swpaul DELAY(1); 49940516Swpaul 50040516Swpaul /* Turn off xmit. */ 50140516Swpaul MII_CLR(RL_MII_DIR); 50240516Swpaul 50340516Swpaul /* Check for ack */ 50440516Swpaul MII_CLR(RL_MII_CLK); 50540516Swpaul DELAY(1); 506109058Smbr ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 50740516Swpaul MII_SET(RL_MII_CLK); 50840516Swpaul DELAY(1); 50940516Swpaul 51040516Swpaul /* 51140516Swpaul * Now try reading data bits. If the ack failed, we still 51240516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 51340516Swpaul */ 51440516Swpaul if (ack) { 51540516Swpaul for(i = 0; i < 16; i++) { 51640516Swpaul MII_CLR(RL_MII_CLK); 51740516Swpaul DELAY(1); 51840516Swpaul MII_SET(RL_MII_CLK); 51940516Swpaul DELAY(1); 52040516Swpaul } 52140516Swpaul goto fail; 52240516Swpaul } 52340516Swpaul 52440516Swpaul for (i = 0x8000; i; i >>= 1) { 52540516Swpaul MII_CLR(RL_MII_CLK); 52640516Swpaul DELAY(1); 52740516Swpaul if (!ack) { 52840516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 52940516Swpaul frame->mii_data |= i; 53040516Swpaul DELAY(1); 53140516Swpaul } 53240516Swpaul MII_SET(RL_MII_CLK); 53340516Swpaul DELAY(1); 53440516Swpaul } 53540516Swpaul 53640516Swpaulfail: 53740516Swpaul 53840516Swpaul MII_CLR(RL_MII_CLK); 53940516Swpaul DELAY(1); 54040516Swpaul MII_SET(RL_MII_CLK); 54140516Swpaul DELAY(1); 54240516Swpaul 54367087Swpaul RL_UNLOCK(sc); 54440516Swpaul 54540516Swpaul if (ack) 54640516Swpaul return(1); 54740516Swpaul return(0); 54840516Swpaul} 54940516Swpaul 55040516Swpaul/* 55140516Swpaul * Write to a PHY register through the MII. 55240516Swpaul */ 553102335Salfredstatic int 554102335Salfredrl_mii_writereg(sc, frame) 55540516Swpaul struct rl_softc *sc; 55640516Swpaul struct rl_mii_frame *frame; 557109109Sdes 55840516Swpaul{ 55967087Swpaul RL_LOCK(sc); 56040516Swpaul 56140516Swpaul /* 56240516Swpaul * Set up frame for TX. 56340516Swpaul */ 56440516Swpaul 56540516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 56640516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 56740516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 568109109Sdes 56940516Swpaul /* 570109109Sdes * Turn on data output. 57140516Swpaul */ 57240516Swpaul MII_SET(RL_MII_DIR); 57340516Swpaul 57440516Swpaul rl_mii_sync(sc); 57540516Swpaul 57640516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 57740516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 57840516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 57940516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 58040516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 58140516Swpaul rl_mii_send(sc, frame->mii_data, 16); 58240516Swpaul 58340516Swpaul /* Idle bit. */ 58440516Swpaul MII_SET(RL_MII_CLK); 58540516Swpaul DELAY(1); 58640516Swpaul MII_CLR(RL_MII_CLK); 58740516Swpaul DELAY(1); 58840516Swpaul 58940516Swpaul /* 59040516Swpaul * Turn off xmit. 59140516Swpaul */ 59240516Swpaul MII_CLR(RL_MII_DIR); 59340516Swpaul 59467087Swpaul RL_UNLOCK(sc); 59540516Swpaul 59640516Swpaul return(0); 59740516Swpaul} 59840516Swpaul 599102335Salfredstatic int 600102335Salfredrl_miibus_readreg(dev, phy, reg) 60150703Swpaul device_t dev; 60250703Swpaul int phy, reg; 60350703Swpaul{ 60440516Swpaul struct rl_softc *sc; 60540516Swpaul struct rl_mii_frame frame; 60640516Swpaul u_int16_t rval = 0; 60740516Swpaul u_int16_t rl8139_reg = 0; 60840516Swpaul 60950703Swpaul sc = device_get_softc(dev); 61067087Swpaul RL_LOCK(sc); 61150703Swpaul 612119868Swpaul if (sc->rl_type == RL_8139) { 61350703Swpaul /* Pretend the internal PHY is only at address 0 */ 61467087Swpaul if (phy) { 61567087Swpaul RL_UNLOCK(sc); 61650703Swpaul return(0); 61767087Swpaul } 61840516Swpaul switch(reg) { 61950703Swpaul case MII_BMCR: 62040516Swpaul rl8139_reg = RL_BMCR; 62140516Swpaul break; 62250703Swpaul case MII_BMSR: 62340516Swpaul rl8139_reg = RL_BMSR; 62440516Swpaul break; 62550703Swpaul case MII_ANAR: 62640516Swpaul rl8139_reg = RL_ANAR; 62740516Swpaul break; 62850703Swpaul case MII_ANER: 62950703Swpaul rl8139_reg = RL_ANER; 63050703Swpaul break; 63150703Swpaul case MII_ANLPAR: 63240516Swpaul rl8139_reg = RL_LPAR; 63340516Swpaul break; 63450703Swpaul case MII_PHYIDR1: 63550703Swpaul case MII_PHYIDR2: 63667087Swpaul RL_UNLOCK(sc); 63750703Swpaul return(0); 63894149Swpaul /* 63994149Swpaul * Allow the rlphy driver to read the media status 64094149Swpaul * register. If we have a link partner which does not 64194149Swpaul * support NWAY, this is the register which will tell 64294149Swpaul * us the results of parallel detection. 64394149Swpaul */ 64494149Swpaul case RL_MEDIASTAT: 64594149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 64694149Swpaul RL_UNLOCK(sc); 64794149Swpaul return(rval); 64840516Swpaul default: 64940516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 65067087Swpaul RL_UNLOCK(sc); 65140516Swpaul return(0); 65240516Swpaul } 65340516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 65467087Swpaul RL_UNLOCK(sc); 65540516Swpaul return(rval); 65640516Swpaul } 65740516Swpaul 65840516Swpaul bzero((char *)&frame, sizeof(frame)); 65940516Swpaul 66050703Swpaul frame.mii_phyaddr = phy; 66140516Swpaul frame.mii_regaddr = reg; 66240516Swpaul rl_mii_readreg(sc, &frame); 66367087Swpaul RL_UNLOCK(sc); 66440516Swpaul 66540516Swpaul return(frame.mii_data); 66640516Swpaul} 66740516Swpaul 668102335Salfredstatic int 669102335Salfredrl_miibus_writereg(dev, phy, reg, data) 67050703Swpaul device_t dev; 67150703Swpaul int phy, reg, data; 67250703Swpaul{ 67340516Swpaul struct rl_softc *sc; 67440516Swpaul struct rl_mii_frame frame; 67540516Swpaul u_int16_t rl8139_reg = 0; 67640516Swpaul 67750703Swpaul sc = device_get_softc(dev); 67867087Swpaul RL_LOCK(sc); 67950703Swpaul 680119868Swpaul if (sc->rl_type == RL_8139) { 68150703Swpaul /* Pretend the internal PHY is only at address 0 */ 68267087Swpaul if (phy) { 68367087Swpaul RL_UNLOCK(sc); 68450703Swpaul return(0); 68567087Swpaul } 68640516Swpaul switch(reg) { 68750703Swpaul case MII_BMCR: 68840516Swpaul rl8139_reg = RL_BMCR; 68940516Swpaul break; 69050703Swpaul case MII_BMSR: 69140516Swpaul rl8139_reg = RL_BMSR; 69240516Swpaul break; 69350703Swpaul case MII_ANAR: 69440516Swpaul rl8139_reg = RL_ANAR; 69540516Swpaul break; 69650703Swpaul case MII_ANER: 69750703Swpaul rl8139_reg = RL_ANER; 69850703Swpaul break; 69950703Swpaul case MII_ANLPAR: 70040516Swpaul rl8139_reg = RL_LPAR; 70140516Swpaul break; 70250703Swpaul case MII_PHYIDR1: 70350703Swpaul case MII_PHYIDR2: 70467087Swpaul RL_UNLOCK(sc); 70550703Swpaul return(0); 70650703Swpaul break; 70740516Swpaul default: 70840516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 70967087Swpaul RL_UNLOCK(sc); 71050703Swpaul return(0); 71140516Swpaul } 71240516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 71367087Swpaul RL_UNLOCK(sc); 71450703Swpaul return(0); 71540516Swpaul } 71640516Swpaul 71740516Swpaul bzero((char *)&frame, sizeof(frame)); 71840516Swpaul 71950703Swpaul frame.mii_phyaddr = phy; 72040516Swpaul frame.mii_regaddr = reg; 72140516Swpaul frame.mii_data = data; 72240516Swpaul 72340516Swpaul rl_mii_writereg(sc, &frame); 72440516Swpaul 72567087Swpaul RL_UNLOCK(sc); 72650703Swpaul return(0); 72750703Swpaul} 72850703Swpaul 729102335Salfredstatic void 730102335Salfredrl_miibus_statchg(dev) 73150703Swpaul device_t dev; 73250703Swpaul{ 73340516Swpaul return; 73440516Swpaul} 73540516Swpaul 73640516Swpaul/* 73743062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 73840516Swpaul */ 739102335Salfredstatic u_int8_t 740102335Salfredrl_calchash(addr) 74141656Swpaul caddr_t addr; 74240516Swpaul{ 74340516Swpaul u_int32_t crc, carry; 74440516Swpaul int i, j; 74540516Swpaul u_int8_t c; 74640516Swpaul 74740516Swpaul /* Compute CRC for the address value. */ 74840516Swpaul crc = 0xFFFFFFFF; /* initial value */ 74940516Swpaul 75040516Swpaul for (i = 0; i < 6; i++) { 75140516Swpaul c = *(addr + i); 75240516Swpaul for (j = 0; j < 8; j++) { 75340516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 75440516Swpaul crc <<= 1; 75540516Swpaul c >>= 1; 75640516Swpaul if (carry) 75740516Swpaul crc = (crc ^ 0x04c11db6) | carry; 75840516Swpaul } 75940516Swpaul } 76040516Swpaul 76140516Swpaul /* return the filter bit position */ 76243062Swpaul return(crc >> 26); 76340516Swpaul} 76440516Swpaul 76540516Swpaul/* 76640516Swpaul * Program the 64-bit multicast hash filter. 76740516Swpaul */ 768102335Salfredstatic void 769102335Salfredrl_setmulti(sc) 77040516Swpaul struct rl_softc *sc; 77140516Swpaul{ 77240516Swpaul struct ifnet *ifp; 77340516Swpaul int h = 0; 77440516Swpaul u_int32_t hashes[2] = { 0, 0 }; 77540516Swpaul struct ifmultiaddr *ifma; 77640516Swpaul u_int32_t rxfilt; 77740516Swpaul int mcnt = 0; 77840516Swpaul 77940516Swpaul ifp = &sc->arpcom.ac_if; 78040516Swpaul 78140516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 78240516Swpaul 78343062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 78440516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 78540516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 78640516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 78740516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 78840516Swpaul return; 78940516Swpaul } 79040516Swpaul 79140516Swpaul /* first, zot all the existing hash bits */ 79240516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 79340516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 79440516Swpaul 79540516Swpaul /* now program new ones */ 79672084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 79740516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 79840516Swpaul continue; 79940516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 80040516Swpaul if (h < 32) 80140516Swpaul hashes[0] |= (1 << h); 80240516Swpaul else 80340516Swpaul hashes[1] |= (1 << (h - 32)); 80440516Swpaul mcnt++; 80540516Swpaul } 80640516Swpaul 80740516Swpaul if (mcnt) 80840516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 80940516Swpaul else 81040516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 81140516Swpaul 81240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 81340516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 81440516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 81540516Swpaul 81640516Swpaul return; 81740516Swpaul} 81840516Swpaul 819102335Salfredstatic void 820102335Salfredrl_reset(sc) 82140516Swpaul struct rl_softc *sc; 82240516Swpaul{ 82340516Swpaul register int i; 82440516Swpaul 82540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 82640516Swpaul 82740516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 82840516Swpaul DELAY(10); 82940516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 83040516Swpaul break; 83140516Swpaul } 83240516Swpaul if (i == RL_TIMEOUT) 83340516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 83440516Swpaul 835109109Sdes return; 83640516Swpaul} 83740516Swpaul 83840516Swpaul/* 83940516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 84040516Swpaul * IDs against our list and return a device name if we find a match. 84140516Swpaul */ 842102335Salfredstatic int 843102335Salfredrl_probe(dev) 84450703Swpaul device_t dev; 84540516Swpaul{ 84640516Swpaul struct rl_type *t; 847119868Swpaul struct rl_softc *sc; 848117388Swpaul int rid; 849117388Swpaul u_int32_t hwrev; 85040516Swpaul 85140516Swpaul t = rl_devs; 852117388Swpaul sc = device_get_softc(dev); 85340516Swpaul 85440516Swpaul while(t->rl_name != NULL) { 85550703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 85650703Swpaul (pci_get_device(dev) == t->rl_did)) { 857117388Swpaul 858117388Swpaul /* 859117388Swpaul * Temporarily map the I/O space 860117388Swpaul * so we can read the chip ID register. 861117388Swpaul */ 862117388Swpaul rid = RL_RID; 863117388Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 864117388Swpaul 0, ~0, 1, RF_ACTIVE); 865117388Swpaul if (sc->rl_res == NULL) { 866117388Swpaul device_printf(dev, 867117388Swpaul "couldn't map ports/memory\n"); 868117388Swpaul return(ENXIO); 869117388Swpaul } 870117388Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 871117388Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 872117388Swpaul mtx_init(&sc->rl_mtx, 873117388Swpaul device_get_nameunit(dev), 874117388Swpaul MTX_NETWORK_LOCK, MTX_DEF); 875119868Swpaul RL_LOCK(sc); 876119868Swpaul hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 877119868Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 878117388Swpaul RL_UNLOCK(sc); 879117388Swpaul mtx_destroy(&sc->rl_mtx); 880119868Swpaul 881119868Swpaul /* Don't attach to 8139C+ or 8169/8110 chips. */ 882119868Swpaul if (hwrev == RL_HWREV_8139CPLUS || 883119868Swpaul hwrev == RL_HWREV_8169 || 884119954Swpaul hwrev == RL_HWREV_8169S || 885119954Swpaul hwrev == RL_HWREV_8110S) { 886119868Swpaul t++; 887119868Swpaul continue; 888119868Swpaul } 889119868Swpaul 890119868Swpaul device_set_desc(dev, t->rl_name); 89150703Swpaul return(0); 89240516Swpaul } 89340516Swpaul t++; 89440516Swpaul } 89540516Swpaul 89650703Swpaul return(ENXIO); 89740516Swpaul} 89840516Swpaul 89940516Swpaul/* 90040516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 90140516Swpaul * setup and ethernet/BPF attach. 90240516Swpaul */ 903102335Salfredstatic int 904102335Salfredrl_attach(dev) 90550703Swpaul device_t dev; 90640516Swpaul{ 90740516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 908108729Sjake u_int16_t as[3]; 90940516Swpaul struct rl_softc *sc; 91040516Swpaul struct ifnet *ifp; 911119868Swpaul u_int16_t rl_did = 0; 912117388Swpaul struct rl_type *t; 913108729Sjake int unit, error = 0, rid, i; 91440516Swpaul 91550703Swpaul sc = device_get_softc(dev); 91650703Swpaul unit = device_get_unit(dev); 91740516Swpaul 91893818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 91993818Sjhb MTX_DEF | MTX_RECURSE); 920117208Simp#ifndef BURN_BRIDGES 92140516Swpaul /* 92240516Swpaul * Handle power management nonsense. 92340516Swpaul */ 92440516Swpaul 92570167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 92670167Swpaul u_int32_t iobase, membase, irq; 92740516Swpaul 92870167Swpaul /* Save important PCI config data. */ 92970167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 93070167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 93170167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 93240516Swpaul 93370167Swpaul /* Reset the power state. */ 93470167Swpaul printf("rl%d: chip is is in D%d power mode " 93570167Swpaul "-- setting to D0\n", unit, 93670167Swpaul pci_get_powerstate(dev)); 93740516Swpaul 93870167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 93940516Swpaul 94070167Swpaul /* Restore PCI config data. */ 94170167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 94270167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 94370167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 94440516Swpaul } 945117208Simp#endif 94640516Swpaul /* 94740516Swpaul * Map control/status registers. 94840516Swpaul */ 94972813Swpaul pci_enable_busmaster(dev); 95040516Swpaul 951109109Sdes rid = RL_RID; 95250703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 95350703Swpaul 0, ~0, 1, RF_ACTIVE); 95450703Swpaul 95550703Swpaul if (sc->rl_res == NULL) { 95650703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 95750703Swpaul error = ENXIO; 95840516Swpaul goto fail; 95940516Swpaul } 96040516Swpaul 961117388Swpaul#ifdef notdef 96269127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 96369127Sroger * unstable when left to autoselect the media 96469127Sroger * The best workaround is to set the device to the required 96569127Sroger * media type or to set it to the 10 Meg speed. 96669127Sroger */ 96769127Sroger 96869127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 969119868Swpaul printf("rl%d: Realtek 8139B detected. Warning, " 970119868Swpaul "this may be unstable in autoselect mode\n", unit); 97169127Sroger } 972117388Swpaul#endif 97369127Sroger 97450703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 97550703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 97650703Swpaul 977112872Snjl /* Allocate interrupt */ 97850703Swpaul rid = 0; 97950703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 98050703Swpaul RF_SHAREABLE | RF_ACTIVE); 98150703Swpaul 98250703Swpaul if (sc->rl_irq == NULL) { 98340516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 98450703Swpaul error = ENXIO; 98540516Swpaul goto fail; 98640516Swpaul } 98740516Swpaul 98840516Swpaul /* Reset the adapter. */ 98940516Swpaul rl_reset(sc); 99067931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 99167931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 99268215Swpaul if (rl_did != 0x8129) 99367931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 99440516Swpaul 99540516Swpaul /* 99640516Swpaul * Get station address from the EEPROM. 99740516Swpaul */ 998108729Sjake rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 999108729Sjake for (i = 0; i < 3; i++) { 1000108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 1001108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 1002108729Sjake } 100340516Swpaul 100440516Swpaul /* 100540516Swpaul * A RealTek chip was detected. Inform the world. 100640516Swpaul */ 100740516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 100840516Swpaul 100940516Swpaul sc->rl_unit = unit; 101040516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 101140516Swpaul 101240516Swpaul /* 101340516Swpaul * Now read the exact device type from the EEPROM to find 101440516Swpaul * out if it's an 8129 or 8139. 101540516Swpaul */ 101640516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 101740516Swpaul 1018117388Swpaul t = rl_devs; 1019119868Swpaul sc->rl_type = 0; 1020117388Swpaul while(t->rl_name != NULL) { 1021117388Swpaul if (rl_did == t->rl_did) { 1022117388Swpaul sc->rl_type = t->rl_basetype; 1023117388Swpaul break; 1024117388Swpaul } 1025117388Swpaul t++; 1026117388Swpaul } 1027119868Swpaul 1028119868Swpaul if (sc->rl_type == 0) { 102940516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 103050703Swpaul error = ENXIO; 103140516Swpaul goto fail; 103240516Swpaul } 103340516Swpaul 103481713Swpaul /* 103581713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 103681713Swpaul */ 103781713Swpaul#define RL_NSEG_NEW 32 1038109109Sdes error = bus_dma_tag_create(NULL, /* parent */ 103981713Swpaul 1, 0, /* alignment, boundary */ 104081713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 104181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 104281713Swpaul NULL, NULL, /* filter, filterarg */ 104381713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1044109109Sdes BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 104581713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1046117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 104781713Swpaul &sc->rl_parent_tag); 1048112872Snjl if (error) 1049112872Snjl goto fail; 105040516Swpaul 105181713Swpaul /* 1052119868Swpaul * Now allocate a tag for the DMA descriptor lists. 1053119868Swpaul * All of our lists are allocated as a contiguous block 1054119868Swpaul * of memory. 105581713Swpaul */ 1056119868Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1057119868Swpaul 1, 0, /* alignment, boundary */ 1058119868Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 1059119868Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 1060119868Swpaul NULL, NULL, /* filter, filterarg */ 1061119868Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1062119868Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1063119868Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1064119868Swpaul NULL, NULL, /* lockfunc, lockarg */ 1065119868Swpaul &sc->rl_tag); 1066112872Snjl if (error) 1067112872Snjl goto fail; 106881713Swpaul 1069119868Swpaul /* 1070119868Swpaul * Now allocate a chunk of DMA-able memory based on the 1071119868Swpaul * tag we just created. 1072119868Swpaul */ 1073119868Swpaul error = bus_dmamem_alloc(sc->rl_tag, 1074119868Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1075119868Swpaul &sc->rl_cdata.rl_rx_dmamap); 1076119868Swpaul 1077119868Swpaul if (error) { 1078119868Swpaul printf("rl%d: no memory for list buffers!\n", unit); 1079119868Swpaul bus_dma_tag_destroy(sc->rl_tag); 1080119868Swpaul sc->rl_tag = NULL; 1081119868Swpaul goto fail; 1082119868Swpaul } 1083119868Swpaul 1084119868Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 1085119868Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1086119868Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1087119868Swpaul 108850703Swpaul /* Do MII setup */ 108950703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 109050703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 109150703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 109250703Swpaul error = ENXIO; 109350703Swpaul goto fail; 109450703Swpaul } 109550703Swpaul 109640516Swpaul ifp = &sc->arpcom.ac_if; 109740516Swpaul ifp->if_softc = sc; 109840516Swpaul ifp->if_unit = unit; 109940516Swpaul ifp->if_name = "rl"; 110040516Swpaul ifp->if_mtu = ETHERMTU; 110140516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 110240516Swpaul ifp->if_ioctl = rl_ioctl; 110340516Swpaul ifp->if_output = ether_output; 1104119868Swpaul ifp->if_start = rl_start; 110540516Swpaul ifp->if_watchdog = rl_watchdog; 110640516Swpaul ifp->if_init = rl_init; 110740516Swpaul ifp->if_baudrate = 10000000; 1108119976Swpaul ifp->if_capabilities = IFCAP_VLAN_MTU; 1109119977Swpaul ifp->if_capenable = ifp->if_capabilities; 1110119868Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1111119976Swpaul 1112112872Snjl callout_handle_init(&sc->rl_stat_ch); 1113112872Snjl 111440516Swpaul /* 111563090Sarchie * Call MI attach routine. 111640516Swpaul */ 1117106936Ssam ether_ifattach(ifp, eaddr); 1118106157Simp 1119113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1120106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1121119868Swpaul rl_intr, sc, &sc->rl_intrhand); 1122106157Simp 1123106157Simp if (error) { 1124106157Simp printf("rl%d: couldn't set up irq\n", unit); 1125113609Snjl ether_ifdetach(ifp); 1126106157Simp goto fail; 1127106157Simp } 1128106157Simp 112940516Swpaulfail: 1130112872Snjl if (error) 1131112872Snjl rl_detach(dev); 1132112872Snjl 1133110601Snjl return (error); 113440516Swpaul} 113540516Swpaul 1136113609Snjl/* 1137113609Snjl * Shutdown hardware and free up resources. This can be called any 1138113609Snjl * time after the mutex has been initialized. It is called in both 1139113609Snjl * the error case in attach and the normal detach case so it needs 1140113609Snjl * to be careful about only freeing resources that have actually been 1141113609Snjl * allocated. 1142113609Snjl */ 1143102335Salfredstatic int 1144102335Salfredrl_detach(dev) 114550703Swpaul device_t dev; 114650703Swpaul{ 114750703Swpaul struct rl_softc *sc; 114850703Swpaul struct ifnet *ifp; 114950703Swpaul 115050703Swpaul sc = device_get_softc(dev); 1151112880Sjhb KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 115267087Swpaul RL_LOCK(sc); 115350703Swpaul ifp = &sc->arpcom.ac_if; 115450703Swpaul 1155113609Snjl /* These should only be active if attach succeeded */ 1156113812Simp if (device_is_attached(dev)) { 1157113609Snjl rl_stop(sc); 1158112872Snjl ether_ifdetach(ifp); 1159113609Snjl } 1160113609Snjl if (sc->rl_miibus) 1161112872Snjl device_delete_child(dev, sc->rl_miibus); 1162113609Snjl bus_generic_detach(dev); 116350703Swpaul 1164112872Snjl if (sc->rl_intrhand) 1165112872Snjl bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1166112872Snjl if (sc->rl_irq) 1167112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1168112872Snjl if (sc->rl_res) 1169112872Snjl bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 117050703Swpaul 1171119868Swpaul if (sc->rl_tag) { 1172119868Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1173119868Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1174119868Swpaul sc->rl_cdata.rl_rx_dmamap); 1175119868Swpaul bus_dma_tag_destroy(sc->rl_tag); 1176112872Snjl } 1177112872Snjl if (sc->rl_parent_tag) 1178112872Snjl bus_dma_tag_destroy(sc->rl_parent_tag); 117950703Swpaul 118067087Swpaul RL_UNLOCK(sc); 118167087Swpaul mtx_destroy(&sc->rl_mtx); 118250703Swpaul 118350703Swpaul return(0); 118450703Swpaul} 118550703Swpaul 118640516Swpaul/* 118740516Swpaul * Initialize the transmit descriptors. 118840516Swpaul */ 1189102335Salfredstatic int 1190102335Salfredrl_list_tx_init(sc) 119140516Swpaul struct rl_softc *sc; 119240516Swpaul{ 119340516Swpaul struct rl_chain_data *cd; 119440516Swpaul int i; 119540516Swpaul 119640516Swpaul cd = &sc->rl_cdata; 119740516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 119845633Swpaul cd->rl_tx_chain[i] = NULL; 119948028Swpaul CSR_WRITE_4(sc, 120048028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 120140516Swpaul } 120240516Swpaul 120345633Swpaul sc->rl_cdata.cur_tx = 0; 120445633Swpaul sc->rl_cdata.last_tx = 0; 120540516Swpaul 120640516Swpaul return(0); 120740516Swpaul} 120840516Swpaul 120940516Swpaul/* 121040516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 121140516Swpaul * the higher level protocols. 121240516Swpaul * 121340516Swpaul * You know there's something wrong with a PCI bus-master chip design 121440516Swpaul * when you have to use m_devget(). 121540516Swpaul * 121640516Swpaul * The receive operation is badly documented in the datasheet, so I'll 121740516Swpaul * attempt to document it here. The driver provides a buffer area and 121840516Swpaul * places its base address in the RX buffer start address register. 121940516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 122072645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 122140516Swpaul * of the frame and certain other status bits. Each frame (starting with 122240516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 122340516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 122440516Swpaul * the 'rx status register' mentioned in the datasheet. 122548028Swpaul * 122648028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 122778508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1228109109Sdes * as the offset argument to m_devget(). 122940516Swpaul */ 1230102335Salfredstatic void 1231102335Salfredrl_rxeof(sc) 123240516Swpaul struct rl_softc *sc; 123340516Swpaul{ 1234109109Sdes struct mbuf *m; 1235109109Sdes struct ifnet *ifp; 123640516Swpaul int total_len = 0; 123740516Swpaul u_int32_t rxstat; 123840516Swpaul caddr_t rxbufpos; 123940516Swpaul int wrap = 0; 124040516Swpaul u_int16_t cur_rx; 124140516Swpaul u_int16_t limit; 124240516Swpaul u_int16_t rx_bytes = 0, max_bytes; 124340516Swpaul 124440516Swpaul ifp = &sc->arpcom.ac_if; 124540516Swpaul 124681713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1247108729Sjake BUS_DMASYNC_POSTREAD); 124881713Swpaul 124940516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 125040516Swpaul 125140516Swpaul /* Do not try to read past this point. */ 125240516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 125340516Swpaul 125440516Swpaul if (limit < cur_rx) 125540516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 125640516Swpaul else 125740516Swpaul max_bytes = limit - cur_rx; 125840516Swpaul 125942738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 126094883Sluigi#ifdef DEVICE_POLLING 1261102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 126294883Sluigi if (sc->rxcycles <= 0) 126394883Sluigi break; 126494883Sluigi sc->rxcycles--; 126594883Sluigi } 126694883Sluigi#endif /* DEVICE_POLLING */ 126740516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1268108729Sjake rxstat = le32toh(*(u_int32_t *)rxbufpos); 126940516Swpaul 127040516Swpaul /* 127140516Swpaul * Here's a totally undocumented fact for you. When the 127240516Swpaul * RealTek chip is in the process of copying a packet into 127340516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 127440516Swpaul * packet header with this value, you need to stop. The 127540516Swpaul * datasheet makes absolutely no mention of this and 127640516Swpaul * RealTek should be shot for this. 127740516Swpaul */ 127840516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 127940516Swpaul break; 1280109109Sdes 128140516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 128240516Swpaul ifp->if_ierrors++; 128350703Swpaul rl_init(sc); 128450703Swpaul return; 128540516Swpaul } 128640516Swpaul 1287109109Sdes /* No errors; receive the packet. */ 128840516Swpaul total_len = rxstat >> 16; 128940516Swpaul rx_bytes += total_len + 4; 129040516Swpaul 129140516Swpaul /* 129242051Swpaul * XXX The RealTek chip includes the CRC with every 129342051Swpaul * received frame, and there's no way to turn this 129442051Swpaul * behavior off (at least, I can't find anything in 1295109109Sdes * the manual that explains how to do it) so we have 129642051Swpaul * to trim off the CRC manually. 129742051Swpaul */ 129842051Swpaul total_len -= ETHER_CRC_LEN; 129942051Swpaul 130042051Swpaul /* 130140516Swpaul * Avoid trying to read more bytes than we know 130240516Swpaul * the chip has prepared for us. 130340516Swpaul */ 130440516Swpaul if (rx_bytes > max_bytes) 130540516Swpaul break; 130640516Swpaul 130740516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 130840516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 130940516Swpaul 131040516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 131140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 131240516Swpaul 131340516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 131440516Swpaul 131540516Swpaul if (total_len > wrap) { 131678508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 131778508Sbmilekic NULL); 131840516Swpaul if (m == NULL) { 131940516Swpaul ifp->if_ierrors++; 132052426Swpaul } else { 132140516Swpaul m_copyback(m, wrap, total_len - wrap, 132240516Swpaul sc->rl_cdata.rl_rx_buf); 132348028Swpaul } 132442051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 132540516Swpaul } else { 132678508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 132778508Sbmilekic NULL); 132840516Swpaul if (m == NULL) { 132940516Swpaul ifp->if_ierrors++; 133078508Sbmilekic } 133142051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 133240516Swpaul } 133340516Swpaul 133440516Swpaul /* 133540516Swpaul * Round up to 32-bit boundary. 133640516Swpaul */ 133740516Swpaul cur_rx = (cur_rx + 3) & ~3; 133840516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 133940516Swpaul 134040516Swpaul if (m == NULL) 134140516Swpaul continue; 134240516Swpaul 134340516Swpaul ifp->if_ipackets++; 1344106936Ssam (*ifp->if_input)(ifp, m); 134540516Swpaul } 134640516Swpaul 134740516Swpaul return; 134840516Swpaul} 134940516Swpaul 135040516Swpaul/* 135140516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 135240516Swpaul * the list buffers. 135340516Swpaul */ 1354102335Salfredstatic void 1355102335Salfredrl_txeof(sc) 135640516Swpaul struct rl_softc *sc; 135740516Swpaul{ 135840516Swpaul struct ifnet *ifp; 135940516Swpaul u_int32_t txstat; 136040516Swpaul 136140516Swpaul ifp = &sc->arpcom.ac_if; 136240516Swpaul 136340516Swpaul /* 136440516Swpaul * Go through our tx list and free mbufs for those 136540516Swpaul * frames that have been uploaded. 136640516Swpaul */ 136745633Swpaul do { 136845633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 136945633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 137045633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 137140516Swpaul break; 137240516Swpaul 137345633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 137440516Swpaul 137545633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 137681713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 137781713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 137845633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 137945633Swpaul RL_LAST_TXMBUF(sc) = NULL; 138045633Swpaul } 138145633Swpaul if (txstat & RL_TXSTAT_TX_OK) 138245633Swpaul ifp->if_opackets++; 138345633Swpaul else { 138452426Swpaul int oldthresh; 138545633Swpaul ifp->if_oerrors++; 138645633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 138745633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 138845633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 138952426Swpaul oldthresh = sc->rl_txthresh; 139052426Swpaul /* error recovery */ 139152426Swpaul rl_reset(sc); 139252426Swpaul rl_init(sc); 139352426Swpaul /* 139452426Swpaul * If there was a transmit underrun, 139552426Swpaul * bump the TX threshold. 139652426Swpaul */ 139752426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 139852426Swpaul sc->rl_txthresh = oldthresh + 32; 139952426Swpaul return; 140045633Swpaul } 140145633Swpaul RL_INC(sc->rl_cdata.last_tx); 140245633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 140345633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 140440516Swpaul 140599165Sluigi ifp->if_timer = 140699165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 140799165Sluigi 140850703Swpaul return; 140950703Swpaul} 141040516Swpaul 1411102335Salfredstatic void 1412102335Salfredrl_tick(xsc) 141350703Swpaul void *xsc; 141450703Swpaul{ 141550703Swpaul struct rl_softc *sc; 141650703Swpaul struct mii_data *mii; 141750703Swpaul 141850703Swpaul sc = xsc; 141967087Swpaul RL_LOCK(sc); 142050703Swpaul mii = device_get_softc(sc->rl_miibus); 142150703Swpaul 142250703Swpaul mii_tick(mii); 142350703Swpaul 142450703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 142567087Swpaul RL_UNLOCK(sc); 142650703Swpaul 142740516Swpaul return; 142840516Swpaul} 142940516Swpaul 143094883Sluigi#ifdef DEVICE_POLLING 143194883Sluigistatic void 143294883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 143394883Sluigi{ 143494883Sluigi struct rl_softc *sc = ifp->if_softc; 143594883Sluigi 143694883Sluigi RL_LOCK(sc); 143794883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1438119868Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 143994883Sluigi goto done; 144094883Sluigi } 144194883Sluigi 144294883Sluigi sc->rxcycles = count; 1443119868Swpaul rl_rxeof(sc); 1444119868Swpaul rl_txeof(sc); 144594883Sluigi if (ifp->if_snd.ifq_head != NULL) 1446119868Swpaul rl_start(ifp); 144794883Sluigi 144894883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 144994883Sluigi u_int16_t status; 145094883Sluigi 145194883Sluigi status = CSR_READ_2(sc, RL_ISR); 1452100957Sjhb if (status == 0xffff) 1453100957Sjhb goto done; 145494883Sluigi if (status) 145594883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 145694883Sluigi 145794883Sluigi /* 145894883Sluigi * XXX check behaviour on receiver stalls. 145994883Sluigi */ 146094883Sluigi 146194883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 146294883Sluigi rl_reset(sc); 146394883Sluigi rl_init(sc); 146494883Sluigi } 146594883Sluigi } 146694883Sluigidone: 146794883Sluigi RL_UNLOCK(sc); 146894883Sluigi} 146994883Sluigi#endif /* DEVICE_POLLING */ 147094883Sluigi 1471102335Salfredstatic void 1472102335Salfredrl_intr(arg) 147340516Swpaul void *arg; 147440516Swpaul{ 147540516Swpaul struct rl_softc *sc; 147640516Swpaul struct ifnet *ifp; 147740516Swpaul u_int16_t status; 147840516Swpaul 147940516Swpaul sc = arg; 148086822Siwasaki 148186822Siwasaki if (sc->suspended) { 148286822Siwasaki return; 148386822Siwasaki } 148486822Siwasaki 148567087Swpaul RL_LOCK(sc); 148640516Swpaul ifp = &sc->arpcom.ac_if; 148740516Swpaul 148894883Sluigi#ifdef DEVICE_POLLING 1489102052Ssobomax if (ifp->if_flags & IFF_POLLING) 149094883Sluigi goto done; 149194883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 149294883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 149394883Sluigi rl_poll(ifp, 0, 1); 149494883Sluigi goto done; 149594883Sluigi } 149694883Sluigi#endif /* DEVICE_POLLING */ 149740516Swpaul 149840516Swpaul for (;;) { 149940516Swpaul 150040516Swpaul status = CSR_READ_2(sc, RL_ISR); 1501100957Sjhb /* If the card has gone away the read returns 0xffff. */ 1502100957Sjhb if (status == 0xffff) 1503100957Sjhb break; 150440516Swpaul if (status) 150540516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 150640516Swpaul 150740516Swpaul if ((status & RL_INTRS) == 0) 150840516Swpaul break; 150940516Swpaul 151040516Swpaul if (status & RL_ISR_RX_OK) 151140516Swpaul rl_rxeof(sc); 151240516Swpaul 151340516Swpaul if (status & RL_ISR_RX_ERR) 151440516Swpaul rl_rxeof(sc); 151540516Swpaul 151645633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 151740516Swpaul rl_txeof(sc); 151840516Swpaul 151940516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 152040516Swpaul rl_reset(sc); 152140516Swpaul rl_init(sc); 152240516Swpaul } 152340516Swpaul 152440516Swpaul } 152540516Swpaul 152652426Swpaul if (ifp->if_snd.ifq_head != NULL) 1527119868Swpaul rl_start(ifp); 152840516Swpaul 152994883Sluigi#ifdef DEVICE_POLLING 153094883Sluigidone: 153194883Sluigi#endif 153267087Swpaul RL_UNLOCK(sc); 153367087Swpaul 153440516Swpaul return; 153540516Swpaul} 153640516Swpaul 153740516Swpaul/* 153840516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 153940516Swpaul * pointers to the fragment pointers. 154040516Swpaul */ 1541102335Salfredstatic int 1542102335Salfredrl_encap(sc, m_head) 154340516Swpaul struct rl_softc *sc; 154440516Swpaul struct mbuf *m_head; 154540516Swpaul{ 154641243Swpaul struct mbuf *m_new = NULL; 154740516Swpaul 154840516Swpaul /* 154945633Swpaul * The RealTek is brain damaged and wants longword-aligned 155045633Swpaul * TX buffers, plus we can only have one fragment buffer 155145633Swpaul * per packet. We have to copy pretty much all the time. 155240516Swpaul */ 1553112839Ssilby m_new = m_defrag(m_head, M_DONTWAIT); 155440516Swpaul 1555113496Ssilby if (m_new == NULL) { 1556113496Ssilby m_freem(m_head); 155741243Swpaul return(1); 1558113496Ssilby } 155941243Swpaul m_head = m_new; 156040516Swpaul 156140516Swpaul /* Pad frames to at least 60 bytes. */ 156241243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 156355058Swpaul /* 156455058Swpaul * Make security concious people happy: zero out the 156555058Swpaul * bytes in the pad area, since we don't know what 156655058Swpaul * this mbuf cluster buffer's previous user might 156755058Swpaul * have left in it. 1568109109Sdes */ 156955058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 157055058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 157140516Swpaul m_head->m_pkthdr.len += 157252426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 157341243Swpaul m_head->m_len = m_head->m_pkthdr.len; 157441243Swpaul } 157540516Swpaul 157645633Swpaul RL_CUR_TXMBUF(sc) = m_head; 157740516Swpaul 157840516Swpaul return(0); 157940516Swpaul} 158040516Swpaul 158140516Swpaul/* 158240516Swpaul * Main transmit routine. 158340516Swpaul */ 158440516Swpaul 1585102335Salfredstatic void 1586102335Salfredrl_start(ifp) 158740516Swpaul struct ifnet *ifp; 158840516Swpaul{ 158940516Swpaul struct rl_softc *sc; 159040516Swpaul struct mbuf *m_head = NULL; 159140516Swpaul 159240516Swpaul sc = ifp->if_softc; 159367087Swpaul RL_LOCK(sc); 159440516Swpaul 159545633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 159640516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 159740516Swpaul if (m_head == NULL) 159840516Swpaul break; 159940516Swpaul 160058801Swpaul if (rl_encap(sc, m_head)) { 160158801Swpaul break; 160258801Swpaul } 160340516Swpaul 160440516Swpaul /* 160540516Swpaul * If there's a BPF listener, bounce a copy of this frame 160640516Swpaul * to him. 160740516Swpaul */ 1608106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 160951583Swpaul 161040516Swpaul /* 161140516Swpaul * Transmit the frame. 1612109109Sdes */ 161381713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 161481713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 161581713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 1616119868Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 161781713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 161881713Swpaul BUS_DMASYNC_PREREAD); 161945633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 162052426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 162152426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 162245633Swpaul 162345633Swpaul RL_INC(sc->rl_cdata.cur_tx); 1624113237Ssilby 1625113237Ssilby /* 1626113237Ssilby * Set a timeout in case the chip goes out to lunch. 1627113237Ssilby */ 1628113237Ssilby ifp->if_timer = 5; 162940516Swpaul } 163040516Swpaul 163140516Swpaul /* 163245633Swpaul * We broke out of the loop because all our TX slots are 163345633Swpaul * full. Mark the NIC as busy until it drains some of the 163445633Swpaul * packets from the queue. 163545633Swpaul */ 163645633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 163745633Swpaul ifp->if_flags |= IFF_OACTIVE; 163845633Swpaul 163967087Swpaul RL_UNLOCK(sc); 164040516Swpaul 164140516Swpaul return; 164240516Swpaul} 164340516Swpaul 1644102335Salfredstatic void 1645102335Salfredrl_init(xsc) 164640516Swpaul void *xsc; 164740516Swpaul{ 164840516Swpaul struct rl_softc *sc = xsc; 164940516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 165050703Swpaul struct mii_data *mii; 165140516Swpaul u_int32_t rxcfg = 0; 165240516Swpaul 165367087Swpaul RL_LOCK(sc); 165450703Swpaul mii = device_get_softc(sc->rl_miibus); 165540516Swpaul 165640516Swpaul /* 165740516Swpaul * Cancel pending I/O and free all RX/TX buffers. 165840516Swpaul */ 165940516Swpaul rl_stop(sc); 166040516Swpaul 1661117029Swpaul /* 1662117029Swpaul * Init our MAC address. Even though the chipset 1663117029Swpaul * documentation doesn't mention it, we need to enter "Config 1664117029Swpaul * register write enable" mode to modify the ID registers. 1665117029Swpaul */ 1666117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1667119738Stmm CSR_WRITE_STREAM_4(sc, RL_IDR0, 1668119738Stmm *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1669119738Stmm CSR_WRITE_STREAM_4(sc, RL_IDR4, 1670119738Stmm *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1671117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 167240516Swpaul 1673119868Swpaul /* Init the RX buffer pointer register. */ 1674119868Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1675119868Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1676119868Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1677119868Swpaul BUS_DMASYNC_PREWRITE); 167840516Swpaul 1679119868Swpaul /* Init TX descriptors. */ 1680119868Swpaul rl_list_tx_init(sc); 168140516Swpaul 168240516Swpaul /* 168340516Swpaul * Enable transmit and receive. 168440516Swpaul */ 168540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 168640516Swpaul 168740516Swpaul /* 168845633Swpaul * Set the initial TX and RX configuration. 168940516Swpaul */ 169045633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 169140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 169240516Swpaul 169340516Swpaul /* Set the individual bit to receive frames for this host only. */ 169440516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 169540516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 169640516Swpaul 169740516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 169840516Swpaul if (ifp->if_flags & IFF_PROMISC) { 169940516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 170040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 170140516Swpaul } else { 170240516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 170340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 170440516Swpaul } 170540516Swpaul 170640516Swpaul /* 170740516Swpaul * Set capture broadcast bit to capture broadcast frames. 170840516Swpaul */ 170940516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 171040516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 171140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 171240516Swpaul } else { 171340516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 171440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 171540516Swpaul } 171640516Swpaul 171740516Swpaul /* 171840516Swpaul * Program the multicast filter, if necessary. 171940516Swpaul */ 172040516Swpaul rl_setmulti(sc); 172140516Swpaul 172294883Sluigi#ifdef DEVICE_POLLING 172340516Swpaul /* 172494883Sluigi * Disable interrupts if we are polling. 172594883Sluigi */ 1726102052Ssobomax if (ifp->if_flags & IFF_POLLING) 172794883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 172894883Sluigi else /* otherwise ... */ 172994883Sluigi#endif /* DEVICE_POLLING */ 173094883Sluigi /* 173140516Swpaul * Enable interrupts. 173240516Swpaul */ 1733119868Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 173440516Swpaul 173552426Swpaul /* Set initial TX threshold */ 173652426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 173752426Swpaul 173840516Swpaul /* Start RX/TX process. */ 173940516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1740119868Swpaul 174140516Swpaul /* Enable receiver and transmitter. */ 174240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 174340516Swpaul 174450703Swpaul mii_mediachg(mii); 174540516Swpaul 174640516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 174740516Swpaul 174840516Swpaul ifp->if_flags |= IFF_RUNNING; 174940516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 175040516Swpaul 175150703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 175267087Swpaul RL_UNLOCK(sc); 175350703Swpaul 175440516Swpaul return; 175540516Swpaul} 175640516Swpaul 175740516Swpaul/* 175840516Swpaul * Set media options. 175940516Swpaul */ 1760102335Salfredstatic int 1761102335Salfredrl_ifmedia_upd(ifp) 176240516Swpaul struct ifnet *ifp; 176340516Swpaul{ 176440516Swpaul struct rl_softc *sc; 176550703Swpaul struct mii_data *mii; 176640516Swpaul 176740516Swpaul sc = ifp->if_softc; 176850703Swpaul mii = device_get_softc(sc->rl_miibus); 176950703Swpaul mii_mediachg(mii); 177040516Swpaul 177140516Swpaul return(0); 177240516Swpaul} 177340516Swpaul 177440516Swpaul/* 177540516Swpaul * Report current media status. 177640516Swpaul */ 1777102335Salfredstatic void 1778102335Salfredrl_ifmedia_sts(ifp, ifmr) 177940516Swpaul struct ifnet *ifp; 178040516Swpaul struct ifmediareq *ifmr; 178140516Swpaul{ 178240516Swpaul struct rl_softc *sc; 178350703Swpaul struct mii_data *mii; 178440516Swpaul 178540516Swpaul sc = ifp->if_softc; 178650703Swpaul mii = device_get_softc(sc->rl_miibus); 178740516Swpaul 178850703Swpaul mii_pollstat(mii); 178950703Swpaul ifmr->ifm_active = mii->mii_media_active; 179050703Swpaul ifmr->ifm_status = mii->mii_media_status; 179140516Swpaul 179240516Swpaul return; 179340516Swpaul} 179440516Swpaul 1795102335Salfredstatic int 1796102335Salfredrl_ioctl(ifp, command, data) 179740516Swpaul struct ifnet *ifp; 179840516Swpaul u_long command; 179940516Swpaul caddr_t data; 180040516Swpaul{ 180140516Swpaul struct rl_softc *sc = ifp->if_softc; 180240516Swpaul struct ifreq *ifr = (struct ifreq *) data; 180350703Swpaul struct mii_data *mii; 180467087Swpaul int error = 0; 180540516Swpaul 180667087Swpaul RL_LOCK(sc); 180740516Swpaul 180840516Swpaul switch(command) { 180940516Swpaul case SIOCSIFFLAGS: 181040516Swpaul if (ifp->if_flags & IFF_UP) { 181140516Swpaul rl_init(sc); 181240516Swpaul } else { 181340516Swpaul if (ifp->if_flags & IFF_RUNNING) 181440516Swpaul rl_stop(sc); 181540516Swpaul } 181640516Swpaul error = 0; 181740516Swpaul break; 181840516Swpaul case SIOCADDMULTI: 181940516Swpaul case SIOCDELMULTI: 182040516Swpaul rl_setmulti(sc); 182140516Swpaul error = 0; 182240516Swpaul break; 182340516Swpaul case SIOCGIFMEDIA: 182440516Swpaul case SIOCSIFMEDIA: 182550703Swpaul mii = device_get_softc(sc->rl_miibus); 182650703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 182740516Swpaul break; 182840516Swpaul default: 1829106936Ssam error = ether_ioctl(ifp, command, data); 183040516Swpaul break; 183140516Swpaul } 183240516Swpaul 183367087Swpaul RL_UNLOCK(sc); 183440516Swpaul 183540516Swpaul return(error); 183640516Swpaul} 183740516Swpaul 1838102335Salfredstatic void 1839102335Salfredrl_watchdog(ifp) 184040516Swpaul struct ifnet *ifp; 184140516Swpaul{ 184240516Swpaul struct rl_softc *sc; 184340516Swpaul 184440516Swpaul sc = ifp->if_softc; 184567087Swpaul RL_LOCK(sc); 184640516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 184740516Swpaul ifp->if_oerrors++; 184850703Swpaul 1849119868Swpaul rl_txeof(sc); 1850119868Swpaul rl_rxeof(sc); 185140516Swpaul rl_init(sc); 185267087Swpaul RL_UNLOCK(sc); 185340516Swpaul 185440516Swpaul return; 185540516Swpaul} 185640516Swpaul 185740516Swpaul/* 185840516Swpaul * Stop the adapter and free any mbufs allocated to the 185940516Swpaul * RX and TX lists. 186040516Swpaul */ 1861102335Salfredstatic void 1862102335Salfredrl_stop(sc) 186340516Swpaul struct rl_softc *sc; 186440516Swpaul{ 186540516Swpaul register int i; 186640516Swpaul struct ifnet *ifp; 186740516Swpaul 186867087Swpaul RL_LOCK(sc); 186940516Swpaul ifp = &sc->arpcom.ac_if; 187040516Swpaul ifp->if_timer = 0; 187140516Swpaul 187250703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 187394883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 187494883Sluigi#ifdef DEVICE_POLLING 187594883Sluigi ether_poll_deregister(ifp); 187694883Sluigi#endif /* DEVICE_POLLING */ 187750703Swpaul 187840516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 187940516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 1880119868Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 188140516Swpaul 1882119868Swpaul /* 1883119868Swpaul * Free the TX list buffers. 1884119868Swpaul */ 1885119868Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 1886119868Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1887119868Swpaul bus_dmamap_unload(sc->rl_tag, 1888119868Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 1889119868Swpaul bus_dmamap_destroy(sc->rl_tag, 1890119868Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 1891119868Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 1892119868Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 1893119868Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 189440516Swpaul } 189540516Swpaul } 189640516Swpaul 189767087Swpaul RL_UNLOCK(sc); 189840516Swpaul return; 189940516Swpaul} 190040516Swpaul 190140516Swpaul/* 190286822Siwasaki * Device suspend routine. Stop the interface and save some PCI 190386822Siwasaki * settings in case the BIOS doesn't restore them properly on 190486822Siwasaki * resume. 190586822Siwasaki */ 1906102335Salfredstatic int 1907102335Salfredrl_suspend(dev) 190886822Siwasaki device_t dev; 190986822Siwasaki{ 191086822Siwasaki register int i; 191186822Siwasaki struct rl_softc *sc; 191286822Siwasaki 191386822Siwasaki sc = device_get_softc(dev); 191486822Siwasaki 191586822Siwasaki rl_stop(sc); 191686822Siwasaki 191786822Siwasaki for (i = 0; i < 5; i++) 1918119868Swpaul sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 191986822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 192086822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 192186822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 192286822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 192386822Siwasaki 192486822Siwasaki sc->suspended = 1; 192586822Siwasaki 192686822Siwasaki return (0); 192786822Siwasaki} 192886822Siwasaki 192986822Siwasaki/* 193086822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 193186822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 193286822Siwasaki * appropriate. 193386822Siwasaki */ 1934102335Salfredstatic int 1935102335Salfredrl_resume(dev) 193686822Siwasaki device_t dev; 193786822Siwasaki{ 193886822Siwasaki register int i; 193986822Siwasaki struct rl_softc *sc; 194086822Siwasaki struct ifnet *ifp; 194186822Siwasaki 194286822Siwasaki sc = device_get_softc(dev); 194386822Siwasaki ifp = &sc->arpcom.ac_if; 194486822Siwasaki 194586822Siwasaki /* better way to do this? */ 194686822Siwasaki for (i = 0; i < 5; i++) 1947119868Swpaul pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 194886822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 194986822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 195086822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 195186822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 195286822Siwasaki 195386822Siwasaki /* reenable busmastering */ 195486822Siwasaki pci_enable_busmaster(dev); 195586822Siwasaki pci_enable_io(dev, RL_RES); 195686822Siwasaki 1957109109Sdes /* reinitialize interface if necessary */ 1958109109Sdes if (ifp->if_flags & IFF_UP) 1959109109Sdes rl_init(sc); 196086822Siwasaki 196186822Siwasaki sc->suspended = 0; 196286822Siwasaki 196386822Siwasaki return (0); 196486822Siwasaki} 196586822Siwasaki 196686822Siwasaki/* 196740516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 196840516Swpaul * get confused by errant DMAs when rebooting. 196940516Swpaul */ 1970102335Salfredstatic void 1971102335Salfredrl_shutdown(dev) 197250703Swpaul device_t dev; 197340516Swpaul{ 197450703Swpaul struct rl_softc *sc; 197540516Swpaul 197650703Swpaul sc = device_get_softc(dev); 197750703Swpaul 197840516Swpaul rl_stop(sc); 197940516Swpaul 198040516Swpaul return; 198140516Swpaul} 1982