if_rl.c revision 118714
140516Swpaul/* 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul */ 3240516Swpaul 3340516Swpaul/* 34117388Swpaul * RealTek 8129/8139/8139C+/8169 PCI NIC driver 3540516Swpaul * 36117388Swpaul * Supports several extremely cheap PCI 10/100 and 10/100/1000 adapters 37117388Swpaul * based on RealTek chipsets. Datasheets can be obtained from 3840516Swpaul * www.realtek.com.tw. 3940516Swpaul * 40117388Swpaul * Written by Bill Paul <wpaul@windriver.com> 41117388Swpaul * Senior Networking Software Engineer 42117388Swpaul * Wind River Systems 4340516Swpaul */ 4440516Swpaul 4540516Swpaul/* 4640516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4740516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 4840516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 4940516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5040516Swpaul * gains that bus-master DMA usually offers. 5140516Swpaul * 5240516Swpaul * For transmission, the chip offers a series of four TX descriptor 5340516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5441569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5540516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5640516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5740516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 5840516Swpaul * four descriptor registers means that we can never have more than four 5940516Swpaul * packets queued for transmission at any one time. 6040516Swpaul * 6140516Swpaul * Reception is not much better. The driver has to allocate a single large 6240516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6340516Swpaul * frames. Because we don't know where within this region received packets 6440516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6540516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6640516Swpaul * levels. 6740516Swpaul * 6840516Swpaul * It's impossible given this rotten design to really achieve decent 6940516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7040516Swpaul * some equally overmuscled CPU to drive it. 7140516Swpaul * 7240516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7340516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7440516Swpaul * PHY registers are directly accessible through the 8139's register 7540516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7640516Swpaul * filter. 7740516Swpaul * 7840516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 7940516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8040516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8140516Swpaul * to select which interface to use depending on the chip type. 82117388Swpaul * 83118712Swpaul * Fast forward a few years. RealTek now has a new chip called the 84117388Swpaul * 8139C+ which at long last implements descriptor-based DMA. Not 85118712Swpaul * only that, it supports RX and TX TCP/IP checksum offload, VLAN 86117388Swpaul * tagging and insertion, TCP large send and 64-bit addressing. 87117388Swpaul * Better still, it allows arbitrary byte alignments for RX and 88117388Swpaul * TX buffers, meaning no copying is necessary on any architecture. 89117388Swpaul * There are a few limitations however: the RX and TX descriptor 90117388Swpaul * rings must be aligned on 256 byte boundaries, they must be in 91117388Swpaul * contiguous RAM, and each ring can have a maximum of 64 descriptors. 92117388Swpaul * There are two TX descriptor queues: one normal priority and one 93117388Swpaul * high. Descriptor ring addresses and DMA buffer addresses are 94117388Swpaul * 64 bits wide. The 8139C+ is also backwards compatible with the 95117388Swpaul * 8139, so the chip will still function with older drivers: C+ 96117388Swpaul * mode has to be enabled by setting the appropriate bits in the C+ 97117388Swpaul * command register. The PHY access mechanism appears to be unchanged. 98117388Swpaul * 99118712Swpaul * The 8169 is a 10/100/1000 ethernet MAC. It has almost the same 100118712Swpaul * programming API as the C+ mode of the 8139C+, with a couple of 101118712Swpaul * minor changes and additions: TX start register and timer interrupt 102118712Swpaul * register are located at different offsets, and there are additional 103118712Swpaul * registers for GMII PHY status and control, as well as TBI-mode 104118712Swpaul * status and control. There is also a maximum RX packet size 105118712Swpaul * register to allow the chip to receive jumbo frames. The 8169 106118712Swpaul * can only be programmed in C+ mode: the old 8139 programming 107117388Swpaul * method isn't supported with this chip. Also, RealTek has a LOM 108117388Swpaul * (LAN On Motherboard) gigabit MAC chip called the RTL8110S which 109118712Swpaul * I believe to be register compatible with the 8169. Unlike the 110118712Swpaul * 8139C+, the 8169 can have up to 1024 descriptors per DMA ring. 111118712Swpaul * The reference 8169 board design uses a Marvell 88E1000 'Alaska' 112118712Swpaul * copper PHY. 113117388Swpaul * 114118712Swpaul * The 8169S and 8110S are newer versions of the 8169. Available 115118712Swpaul * in both 32-bit and 64-bit forms, these devices have built-in 116118712Swpaul * copper 10/100/1000 PHYs. The 8110S is a lan-on-motherboard chip 117118712Swpaul * that is pin-for-pin compatible with the 8100. Unfortunately, 118118712Swpaul * RealTek has not released programming manuals for the 8169S and 119118712Swpaul * 8110S yet. The datasheet for the original 8169 provides most 120117388Swpaul * of the information, but you must refer to RealTek's 8169 Linux 121118712Swpaul * driver to fill in the gaps. Mostly, it appears that the built-in 122118712Swpaul * PHY requires some special initialization. The original 8169 123118712Swpaul * datasheet and the 8139C+ datasheet can be obtained from 124118712Swpaul * http://www.freebsd.org/~wpaul/RealTek. 125117388Swpaul * 126117388Swpaul * This driver now supports both the old 8139 and new 8139C+ 127118712Swpaul * programming models. We detect the 8139C+ by looking for the 128118712Swpaul * corresponding hardware rev bits, and we detect the 8169 by its 129117388Swpaul * PCI ID. Two new NIC type codes, RL_8139CPLUS and RL_8169 have 130117388Swpaul * been added to distinguish the chips at runtime. Separate RX and 131117388Swpaul * TX handling routines have been added to handle C+ mode, which 132117388Swpaul * are selected via function pointers that are initialized during 133117388Swpaul * the driver attach phase. 13440516Swpaul */ 13540516Swpaul 136116192Sobrien#include <sys/cdefs.h> 137116192Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 118714 2003-08-10 02:41:18Z wpaul $"); 138116192Sobrien 13940516Swpaul#include <sys/param.h> 140108729Sjake#include <sys/endian.h> 14140516Swpaul#include <sys/systm.h> 14240516Swpaul#include <sys/sockio.h> 14340516Swpaul#include <sys/mbuf.h> 14440516Swpaul#include <sys/malloc.h> 14540516Swpaul#include <sys/kernel.h> 14640516Swpaul#include <sys/socket.h> 14740516Swpaul 14840516Swpaul#include <net/if.h> 14940516Swpaul#include <net/if_arp.h> 15040516Swpaul#include <net/ethernet.h> 15140516Swpaul#include <net/if_dl.h> 15240516Swpaul#include <net/if_media.h> 153117388Swpaul#include <net/if_vlan_var.h> 15440516Swpaul 15540516Swpaul#include <net/bpf.h> 15640516Swpaul 15741569Swpaul#include <machine/bus_pio.h> 15841569Swpaul#include <machine/bus_memio.h> 15941569Swpaul#include <machine/bus.h> 16050703Swpaul#include <machine/resource.h> 16150703Swpaul#include <sys/bus.h> 16250703Swpaul#include <sys/rman.h> 16340516Swpaul 16450703Swpaul#include <dev/mii/mii.h> 16550703Swpaul#include <dev/mii/miivar.h> 16650703Swpaul 16740516Swpaul#include <pci/pcireg.h> 16840516Swpaul#include <pci/pcivar.h> 16940516Swpaul 170113506SmdoddMODULE_DEPEND(rl, pci, 1, 1, 1); 171113506SmdoddMODULE_DEPEND(rl, ether, 1, 1, 1); 17259758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 17359758Speter 17451089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 17550703Swpaul#include "miibus_if.h" 17650703Swpaul 17740516Swpaul/* 17840516Swpaul * Default to using PIO access for this driver. On SMP systems, 17940516Swpaul * there appear to be problems with memory mapped mode: it looks like 18040516Swpaul * doing too many memory mapped access back to back in rapid succession 18140516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 18240516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 18340516Swpaul * uniprocessor systems though. 18440516Swpaul */ 18540516Swpaul#define RL_USEIOSPACE 18640516Swpaul 18740516Swpaul#include <pci/if_rlreg.h> 18840516Swpaul 189109109Sdes__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 118714 2003-08-10 02:41:18Z wpaul $"); 19040516Swpaul 191117388Swpaul#define RL_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 192117388Swpaul 19340516Swpaul/* 19440516Swpaul * Various supported device vendors/types and their names. 19540516Swpaul */ 19640516Swpaulstatic struct rl_type rl_devs[] = { 197117388Swpaul { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 19840516Swpaul "RealTek 8129 10/100BaseTX" }, 199117388Swpaul { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 20040516Swpaul "RealTek 8139 10/100BaseTX" }, 201118586Swpaul { RT_VENDORID, RT_DEVICEID_8169, RL_8169, 202118586Swpaul "RealTek 8169 10/100/1000BaseTX" }, 203117388Swpaul { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 20467771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 205117388Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 20641243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 207117388Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 20844238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 209117388Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 21044238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 211117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 21272813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 213117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 21496112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 215117388Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 21694400Swpaul "Nortel Networks 10/100BaseTX" }, 217117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 218103020Siwasaki "Corega FEther CB-TXD" }, 219117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 220109095Ssanpei "Corega FEtherII CB-TXD" }, 221117388Swpaul /* XXX what type of realtek is PEPPERCON_DEVICEID_ROLF ? */ 222117388Swpaul { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 223111381Sdan "Peppercon AG ROL-F" }, 224117388Swpaul { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 225112379Ssanpei "Planex FNW-3800-TX" }, 226117388Swpaul { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 227117388Swpaul "Compaq HNE-300" }, 228117388Swpaul { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 229117388Swpaul "LevelOne FPC-0106TX" }, 230117388Swpaul { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 231117388Swpaul "Edimax EP-4103DL CardBus" }, 232117388Swpaul { 0, 0, 0, NULL } 233117388Swpaul}; 234117388Swpaul 235117388Swpaulstatic struct rl_hwrev rl_hwrevs[] = { 236117388Swpaul { RL_HWREV_8139, RL_8139, "" }, 237117388Swpaul { RL_HWREV_8139A, RL_8139, "A" }, 238117388Swpaul { RL_HWREV_8139AG, RL_8139, "A-G" }, 239117388Swpaul { RL_HWREV_8139B, RL_8139, "B" }, 240117388Swpaul { RL_HWREV_8130, RL_8139, "8130" }, 241117388Swpaul { RL_HWREV_8139C, RL_8139, "C" }, 242118586Swpaul { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 243117388Swpaul { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 244118586Swpaul { RL_HWREV_8169, RL_8169, "8169"}, 245118586Swpaul { RL_HWREV_8110, RL_8169, "8169S/8110S"}, 246118586Swpaul { RL_HWREV_8100, RL_8139, "8100"}, 247118586Swpaul { RL_HWREV_8101, RL_8139, "8101"}, 24840516Swpaul { 0, 0, NULL } 24940516Swpaul}; 25040516Swpaul 25192739Salfredstatic int rl_probe (device_t); 25292739Salfredstatic int rl_attach (device_t); 25392739Salfredstatic int rl_detach (device_t); 25440516Swpaul 255117388Swpaulstatic int rl_encap (struct rl_softc *, struct mbuf *); 256117388Swpaulstatic int rl_encapcplus (struct rl_softc *, struct mbuf *, int *); 25740516Swpaul 258117388Swpaulstatic void rl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 259117388Swpaulstatic void rl_dma_map_desc (void *, bus_dma_segment_t *, int, 260117388Swpaul bus_size_t, int); 261117388Swpaulstatic int rl_allocmem (device_t, struct rl_softc *); 262117388Swpaulstatic int rl_allocmemcplus (device_t, struct rl_softc *); 263117388Swpaulstatic int rl_newbuf (struct rl_softc *, int, struct mbuf *); 264117388Swpaulstatic int rl_rx_list_init (struct rl_softc *); 265117388Swpaulstatic int rl_tx_list_init (struct rl_softc *); 26692739Salfredstatic void rl_rxeof (struct rl_softc *); 267117388Swpaulstatic void rl_rxeofcplus (struct rl_softc *); 26892739Salfredstatic void rl_txeof (struct rl_softc *); 269117388Swpaulstatic void rl_txeofcplus (struct rl_softc *); 27092739Salfredstatic void rl_intr (void *); 271117388Swpaulstatic void rl_intrcplus (void *); 27292739Salfredstatic void rl_tick (void *); 27392739Salfredstatic void rl_start (struct ifnet *); 274117388Swpaulstatic void rl_startcplus (struct ifnet *); 27592739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 27692739Salfredstatic void rl_init (void *); 27792739Salfredstatic void rl_stop (struct rl_softc *); 27892739Salfredstatic void rl_watchdog (struct ifnet *); 27992739Salfredstatic int rl_suspend (device_t); 28092739Salfredstatic int rl_resume (device_t); 28192739Salfredstatic void rl_shutdown (device_t); 28292739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 28392739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 28440516Swpaul 28592739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 28692739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 28792739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 28892739Salfredstatic void rl_mii_sync (struct rl_softc *); 28992739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 29092739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 29192739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 292118586Swpaulstatic int rl_gmii_readreg (device_t, int, int); 293118586Swpaulstatic int rl_gmii_writereg (device_t, int, int, int); 29440516Swpaul 29592739Salfredstatic int rl_miibus_readreg (device_t, int, int); 29692739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 29792739Salfredstatic void rl_miibus_statchg (device_t); 29840516Swpaul 29992739Salfredstatic u_int8_t rl_calchash (caddr_t); 30092739Salfredstatic void rl_setmulti (struct rl_softc *); 30192739Salfredstatic void rl_reset (struct rl_softc *); 30292739Salfredstatic int rl_list_tx_init (struct rl_softc *); 30340516Swpaul 30492739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 30592739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 30681713Swpaul 30750703Swpaul#ifdef RL_USEIOSPACE 30850703Swpaul#define RL_RES SYS_RES_IOPORT 30950703Swpaul#define RL_RID RL_PCI_LOIO 31050703Swpaul#else 31150703Swpaul#define RL_RES SYS_RES_MEMORY 31250703Swpaul#define RL_RID RL_PCI_LOMEM 31350703Swpaul#endif 31450703Swpaul 31550703Swpaulstatic device_method_t rl_methods[] = { 31650703Swpaul /* Device interface */ 31750703Swpaul DEVMETHOD(device_probe, rl_probe), 31850703Swpaul DEVMETHOD(device_attach, rl_attach), 31950703Swpaul DEVMETHOD(device_detach, rl_detach), 32086822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 32186822Siwasaki DEVMETHOD(device_resume, rl_resume), 32250703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 32350703Swpaul 32450703Swpaul /* bus interface */ 32550703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 32650703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 32750703Swpaul 32850703Swpaul /* MII interface */ 32950703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 33050703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 33150703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 33250703Swpaul 33350703Swpaul { 0, 0 } 33450703Swpaul}; 33550703Swpaul 33650703Swpaulstatic driver_t rl_driver = { 33751455Swpaul "rl", 33850703Swpaul rl_methods, 33950703Swpaul sizeof(struct rl_softc) 34050703Swpaul}; 34150703Swpaul 34250703Swpaulstatic devclass_t rl_devclass; 34350703Swpaul 344113506SmdoddDRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 345113506SmdoddDRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 34651473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 34750703Swpaul 34840516Swpaul#define EE_SET(x) \ 34940516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 35040516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 35140516Swpaul 35240516Swpaul#define EE_CLR(x) \ 35340516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 35440516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 35540516Swpaul 35681713Swpaulstatic void 35781713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 35881713Swpaul void *arg; 35981713Swpaul bus_dma_segment_t *segs; 36081713Swpaul int nseg, error; 36181713Swpaul{ 36281713Swpaul struct rl_softc *sc; 36381713Swpaul 36481713Swpaul sc = arg; 36581713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 36681713Swpaul 36781713Swpaul return; 36881713Swpaul} 36981713Swpaul 37081713Swpaulstatic void 37181713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 37281713Swpaul void *arg; 37381713Swpaul bus_dma_segment_t *segs; 37481713Swpaul int nseg, error; 37581713Swpaul{ 37681713Swpaul struct rl_softc *sc; 37781713Swpaul 37881713Swpaul sc = arg; 37981713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 38081713Swpaul 38181713Swpaul return; 38281713Swpaul} 38381713Swpaul 38440516Swpaul/* 38540516Swpaul * Send a read command and address to the EEPROM, check for ACK. 38640516Swpaul */ 387102335Salfredstatic void 388102335Salfredrl_eeprom_putbyte(sc, addr) 38940516Swpaul struct rl_softc *sc; 39041656Swpaul int addr; 39140516Swpaul{ 39240516Swpaul register int d, i; 39340516Swpaul 39467931Swpaul d = addr | sc->rl_eecmd_read; 39540516Swpaul 39640516Swpaul /* 39755170Sbillf * Feed in each bit and strobe the clock. 39840516Swpaul */ 39940516Swpaul for (i = 0x400; i; i >>= 1) { 40040516Swpaul if (d & i) { 40140516Swpaul EE_SET(RL_EE_DATAIN); 40240516Swpaul } else { 40340516Swpaul EE_CLR(RL_EE_DATAIN); 40440516Swpaul } 40540516Swpaul DELAY(100); 40640516Swpaul EE_SET(RL_EE_CLK); 40740516Swpaul DELAY(150); 40840516Swpaul EE_CLR(RL_EE_CLK); 40940516Swpaul DELAY(100); 41040516Swpaul } 41140516Swpaul 41240516Swpaul return; 41340516Swpaul} 41440516Swpaul 41540516Swpaul/* 41640516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 41740516Swpaul */ 418102335Salfredstatic void 419102335Salfredrl_eeprom_getword(sc, addr, dest) 42040516Swpaul struct rl_softc *sc; 42141656Swpaul int addr; 42240516Swpaul u_int16_t *dest; 42340516Swpaul{ 42440516Swpaul register int i; 42540516Swpaul u_int16_t word = 0; 42640516Swpaul 42740516Swpaul /* Enter EEPROM access mode. */ 42840516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 42940516Swpaul 43040516Swpaul /* 43140516Swpaul * Send address of word we want to read. 43240516Swpaul */ 43340516Swpaul rl_eeprom_putbyte(sc, addr); 43440516Swpaul 43540516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 43640516Swpaul 43740516Swpaul /* 43840516Swpaul * Start reading bits from EEPROM. 43940516Swpaul */ 44040516Swpaul for (i = 0x8000; i; i >>= 1) { 44140516Swpaul EE_SET(RL_EE_CLK); 44240516Swpaul DELAY(100); 44340516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 44440516Swpaul word |= i; 44540516Swpaul EE_CLR(RL_EE_CLK); 44640516Swpaul DELAY(100); 44740516Swpaul } 44840516Swpaul 44940516Swpaul /* Turn off EEPROM access mode. */ 45040516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 45140516Swpaul 45240516Swpaul *dest = word; 45340516Swpaul 45440516Swpaul return; 45540516Swpaul} 45640516Swpaul 45740516Swpaul/* 45840516Swpaul * Read a sequence of words from the EEPROM. 45940516Swpaul */ 460102335Salfredstatic void 461102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 46240516Swpaul struct rl_softc *sc; 46340516Swpaul caddr_t dest; 46440516Swpaul int off; 46540516Swpaul int cnt; 46640516Swpaul int swap; 46740516Swpaul{ 46840516Swpaul int i; 46940516Swpaul u_int16_t word = 0, *ptr; 47040516Swpaul 47140516Swpaul for (i = 0; i < cnt; i++) { 47240516Swpaul rl_eeprom_getword(sc, off + i, &word); 47340516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 47440516Swpaul if (swap) 47540516Swpaul *ptr = ntohs(word); 47640516Swpaul else 47740516Swpaul *ptr = word; 47840516Swpaul } 47940516Swpaul 48040516Swpaul return; 48140516Swpaul} 48240516Swpaul 48340516Swpaul 48440516Swpaul/* 48540516Swpaul * MII access routines are provided for the 8129, which 48640516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 48740516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 48840516Swpaul * direct access PHY registers. 48940516Swpaul */ 49040516Swpaul#define MII_SET(x) \ 49140516Swpaul CSR_WRITE_1(sc, RL_MII, \ 492105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 49340516Swpaul 49440516Swpaul#define MII_CLR(x) \ 49540516Swpaul CSR_WRITE_1(sc, RL_MII, \ 496105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 49740516Swpaul 49840516Swpaul/* 49940516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 50040516Swpaul */ 501102335Salfredstatic void 502102335Salfredrl_mii_sync(sc) 50340516Swpaul struct rl_softc *sc; 50440516Swpaul{ 50540516Swpaul register int i; 50640516Swpaul 50740516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 50840516Swpaul 50940516Swpaul for (i = 0; i < 32; i++) { 51040516Swpaul MII_SET(RL_MII_CLK); 51140516Swpaul DELAY(1); 51240516Swpaul MII_CLR(RL_MII_CLK); 51340516Swpaul DELAY(1); 51440516Swpaul } 51540516Swpaul 51640516Swpaul return; 51740516Swpaul} 51840516Swpaul 51940516Swpaul/* 52040516Swpaul * Clock a series of bits through the MII. 52140516Swpaul */ 522102335Salfredstatic void 523102335Salfredrl_mii_send(sc, bits, cnt) 52440516Swpaul struct rl_softc *sc; 52540516Swpaul u_int32_t bits; 52640516Swpaul int cnt; 52740516Swpaul{ 52840516Swpaul int i; 52940516Swpaul 53040516Swpaul MII_CLR(RL_MII_CLK); 53140516Swpaul 53240516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 533109109Sdes if (bits & i) { 53440516Swpaul MII_SET(RL_MII_DATAOUT); 535109109Sdes } else { 53640516Swpaul MII_CLR(RL_MII_DATAOUT); 537109109Sdes } 53840516Swpaul DELAY(1); 53940516Swpaul MII_CLR(RL_MII_CLK); 54040516Swpaul DELAY(1); 54140516Swpaul MII_SET(RL_MII_CLK); 54240516Swpaul } 54340516Swpaul} 54440516Swpaul 54540516Swpaul/* 54640516Swpaul * Read an PHY register through the MII. 54740516Swpaul */ 548102335Salfredstatic int 549102335Salfredrl_mii_readreg(sc, frame) 55040516Swpaul struct rl_softc *sc; 55140516Swpaul struct rl_mii_frame *frame; 552109109Sdes 55340516Swpaul{ 55467087Swpaul int i, ack; 55540516Swpaul 55667087Swpaul RL_LOCK(sc); 55740516Swpaul 55840516Swpaul /* 55940516Swpaul * Set up frame for RX. 56040516Swpaul */ 56140516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 56240516Swpaul frame->mii_opcode = RL_MII_READOP; 56340516Swpaul frame->mii_turnaround = 0; 56440516Swpaul frame->mii_data = 0; 565109109Sdes 56640516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 56740516Swpaul 56840516Swpaul /* 569109109Sdes * Turn on data xmit. 57040516Swpaul */ 57140516Swpaul MII_SET(RL_MII_DIR); 57240516Swpaul 57340516Swpaul rl_mii_sync(sc); 57440516Swpaul 57540516Swpaul /* 57640516Swpaul * Send command/address info. 57740516Swpaul */ 57840516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 57940516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 58040516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 58140516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 58240516Swpaul 58340516Swpaul /* Idle bit */ 58440516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 58540516Swpaul DELAY(1); 58640516Swpaul MII_SET(RL_MII_CLK); 58740516Swpaul DELAY(1); 58840516Swpaul 58940516Swpaul /* Turn off xmit. */ 59040516Swpaul MII_CLR(RL_MII_DIR); 59140516Swpaul 59240516Swpaul /* Check for ack */ 59340516Swpaul MII_CLR(RL_MII_CLK); 59440516Swpaul DELAY(1); 595109058Smbr ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 59640516Swpaul MII_SET(RL_MII_CLK); 59740516Swpaul DELAY(1); 59840516Swpaul 59940516Swpaul /* 60040516Swpaul * Now try reading data bits. If the ack failed, we still 60140516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 60240516Swpaul */ 60340516Swpaul if (ack) { 60440516Swpaul for(i = 0; i < 16; i++) { 60540516Swpaul MII_CLR(RL_MII_CLK); 60640516Swpaul DELAY(1); 60740516Swpaul MII_SET(RL_MII_CLK); 60840516Swpaul DELAY(1); 60940516Swpaul } 61040516Swpaul goto fail; 61140516Swpaul } 61240516Swpaul 61340516Swpaul for (i = 0x8000; i; i >>= 1) { 61440516Swpaul MII_CLR(RL_MII_CLK); 61540516Swpaul DELAY(1); 61640516Swpaul if (!ack) { 61740516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 61840516Swpaul frame->mii_data |= i; 61940516Swpaul DELAY(1); 62040516Swpaul } 62140516Swpaul MII_SET(RL_MII_CLK); 62240516Swpaul DELAY(1); 62340516Swpaul } 62440516Swpaul 62540516Swpaulfail: 62640516Swpaul 62740516Swpaul MII_CLR(RL_MII_CLK); 62840516Swpaul DELAY(1); 62940516Swpaul MII_SET(RL_MII_CLK); 63040516Swpaul DELAY(1); 63140516Swpaul 63267087Swpaul RL_UNLOCK(sc); 63340516Swpaul 63440516Swpaul if (ack) 63540516Swpaul return(1); 63640516Swpaul return(0); 63740516Swpaul} 63840516Swpaul 63940516Swpaul/* 64040516Swpaul * Write to a PHY register through the MII. 64140516Swpaul */ 642102335Salfredstatic int 643102335Salfredrl_mii_writereg(sc, frame) 64440516Swpaul struct rl_softc *sc; 64540516Swpaul struct rl_mii_frame *frame; 646109109Sdes 64740516Swpaul{ 64867087Swpaul RL_LOCK(sc); 64940516Swpaul 65040516Swpaul /* 65140516Swpaul * Set up frame for TX. 65240516Swpaul */ 65340516Swpaul 65440516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 65540516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 65640516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 657109109Sdes 65840516Swpaul /* 659109109Sdes * Turn on data output. 66040516Swpaul */ 66140516Swpaul MII_SET(RL_MII_DIR); 66240516Swpaul 66340516Swpaul rl_mii_sync(sc); 66440516Swpaul 66540516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 66640516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 66740516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 66840516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 66940516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 67040516Swpaul rl_mii_send(sc, frame->mii_data, 16); 67140516Swpaul 67240516Swpaul /* Idle bit. */ 67340516Swpaul MII_SET(RL_MII_CLK); 67440516Swpaul DELAY(1); 67540516Swpaul MII_CLR(RL_MII_CLK); 67640516Swpaul DELAY(1); 67740516Swpaul 67840516Swpaul /* 67940516Swpaul * Turn off xmit. 68040516Swpaul */ 68140516Swpaul MII_CLR(RL_MII_DIR); 68240516Swpaul 68367087Swpaul RL_UNLOCK(sc); 68440516Swpaul 68540516Swpaul return(0); 68640516Swpaul} 68740516Swpaul 688102335Salfredstatic int 689118586Swpaulrl_gmii_readreg(dev, phy, reg) 690118586Swpaul device_t dev; 691118586Swpaul int phy, reg; 692118586Swpaul{ 693118586Swpaul struct rl_softc *sc; 694118586Swpaul u_int32_t rval; 695118586Swpaul int i; 696118586Swpaul 697118586Swpaul if (phy != 1) 698118586Swpaul return(0); 699118586Swpaul 700118586Swpaul sc = device_get_softc(dev); 701118586Swpaul 702118586Swpaul CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 703118586Swpaul DELAY(1000); 704118586Swpaul 705118586Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 706118586Swpaul rval = CSR_READ_4(sc, RL_PHYAR); 707118586Swpaul if (rval & RL_PHYAR_BUSY) 708118586Swpaul break; 709118586Swpaul DELAY(100); 710118586Swpaul } 711118586Swpaul 712118586Swpaul if (i == RL_TIMEOUT) { 713118586Swpaul printf ("rl%d: PHY read failed\n", sc->rl_unit); 714118586Swpaul return (0); 715118586Swpaul } 716118586Swpaul 717118586Swpaul return (rval & RL_PHYAR_PHYDATA); 718118586Swpaul} 719118586Swpaul 720118586Swpaulstatic int 721118586Swpaulrl_gmii_writereg(dev, phy, reg, data) 722118586Swpaul device_t dev; 723118586Swpaul int phy, reg, data; 724118586Swpaul{ 725118586Swpaul struct rl_softc *sc; 726118586Swpaul u_int32_t rval; 727118586Swpaul int i; 728118586Swpaul 729118586Swpaul if (phy > 0) 730118586Swpaul return(0); 731118586Swpaul 732118586Swpaul sc = device_get_softc(dev); 733118586Swpaul 734118586Swpaul CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 735118586Swpaul (data | RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 736118586Swpaul DELAY(1000); 737118586Swpaul 738118586Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 739118586Swpaul rval = CSR_READ_4(sc, RL_PHYAR); 740118586Swpaul if (!(rval & RL_PHYAR_BUSY)) 741118586Swpaul break; 742118586Swpaul DELAY(100); 743118586Swpaul } 744118586Swpaul 745118586Swpaul if (i == RL_TIMEOUT) { 746118586Swpaul printf ("rl%d: PHY write failed\n", sc->rl_unit); 747118586Swpaul return (0); 748118586Swpaul } 749118586Swpaul 750118586Swpaul return (0); 751118586Swpaul} 752118586Swpaul 753118586Swpaulstatic int 754102335Salfredrl_miibus_readreg(dev, phy, reg) 75550703Swpaul device_t dev; 75650703Swpaul int phy, reg; 75750703Swpaul{ 75840516Swpaul struct rl_softc *sc; 75940516Swpaul struct rl_mii_frame frame; 76040516Swpaul u_int16_t rval = 0; 76140516Swpaul u_int16_t rl8139_reg = 0; 76240516Swpaul 76350703Swpaul sc = device_get_softc(dev); 76467087Swpaul RL_LOCK(sc); 76550703Swpaul 766118586Swpaul if (sc->rl_type == RL_8169) { 767118586Swpaul rval = rl_gmii_readreg(dev, phy, reg); 768118586Swpaul RL_UNLOCK(sc); 769118586Swpaul return (rval); 770118586Swpaul } 771118586Swpaul 772117388Swpaul if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) { 77350703Swpaul /* Pretend the internal PHY is only at address 0 */ 77467087Swpaul if (phy) { 77567087Swpaul RL_UNLOCK(sc); 77650703Swpaul return(0); 77767087Swpaul } 77840516Swpaul switch(reg) { 77950703Swpaul case MII_BMCR: 78040516Swpaul rl8139_reg = RL_BMCR; 78140516Swpaul break; 78250703Swpaul case MII_BMSR: 78340516Swpaul rl8139_reg = RL_BMSR; 78440516Swpaul break; 78550703Swpaul case MII_ANAR: 78640516Swpaul rl8139_reg = RL_ANAR; 78740516Swpaul break; 78850703Swpaul case MII_ANER: 78950703Swpaul rl8139_reg = RL_ANER; 79050703Swpaul break; 79150703Swpaul case MII_ANLPAR: 79240516Swpaul rl8139_reg = RL_LPAR; 79340516Swpaul break; 79450703Swpaul case MII_PHYIDR1: 79550703Swpaul case MII_PHYIDR2: 79667087Swpaul RL_UNLOCK(sc); 79750703Swpaul return(0); 79894149Swpaul /* 79994149Swpaul * Allow the rlphy driver to read the media status 80094149Swpaul * register. If we have a link partner which does not 80194149Swpaul * support NWAY, this is the register which will tell 80294149Swpaul * us the results of parallel detection. 80394149Swpaul */ 80494149Swpaul case RL_MEDIASTAT: 80594149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 80694149Swpaul RL_UNLOCK(sc); 80794149Swpaul return(rval); 80840516Swpaul default: 80940516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 81067087Swpaul RL_UNLOCK(sc); 81140516Swpaul return(0); 81240516Swpaul } 81340516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 81467087Swpaul RL_UNLOCK(sc); 81540516Swpaul return(rval); 81640516Swpaul } 81740516Swpaul 81840516Swpaul bzero((char *)&frame, sizeof(frame)); 81940516Swpaul 82050703Swpaul frame.mii_phyaddr = phy; 82140516Swpaul frame.mii_regaddr = reg; 82240516Swpaul rl_mii_readreg(sc, &frame); 82367087Swpaul RL_UNLOCK(sc); 82440516Swpaul 82540516Swpaul return(frame.mii_data); 82640516Swpaul} 82740516Swpaul 828102335Salfredstatic int 829102335Salfredrl_miibus_writereg(dev, phy, reg, data) 83050703Swpaul device_t dev; 83150703Swpaul int phy, reg, data; 83250703Swpaul{ 83340516Swpaul struct rl_softc *sc; 83440516Swpaul struct rl_mii_frame frame; 83540516Swpaul u_int16_t rl8139_reg = 0; 836118586Swpaul int rval = 0; 83740516Swpaul 83850703Swpaul sc = device_get_softc(dev); 83967087Swpaul RL_LOCK(sc); 84050703Swpaul 841118586Swpaul if (sc->rl_type == RL_8169) { 842118586Swpaul rval = rl_gmii_writereg(dev, phy, reg, data); 843118586Swpaul RL_UNLOCK(sc); 844118586Swpaul return (rval); 845118586Swpaul } 846118586Swpaul 847117388Swpaul if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) { 84850703Swpaul /* Pretend the internal PHY is only at address 0 */ 84967087Swpaul if (phy) { 85067087Swpaul RL_UNLOCK(sc); 85150703Swpaul return(0); 85267087Swpaul } 85340516Swpaul switch(reg) { 85450703Swpaul case MII_BMCR: 85540516Swpaul rl8139_reg = RL_BMCR; 85640516Swpaul break; 85750703Swpaul case MII_BMSR: 85840516Swpaul rl8139_reg = RL_BMSR; 85940516Swpaul break; 86050703Swpaul case MII_ANAR: 86140516Swpaul rl8139_reg = RL_ANAR; 86240516Swpaul break; 86350703Swpaul case MII_ANER: 86450703Swpaul rl8139_reg = RL_ANER; 86550703Swpaul break; 86650703Swpaul case MII_ANLPAR: 86740516Swpaul rl8139_reg = RL_LPAR; 86840516Swpaul break; 86950703Swpaul case MII_PHYIDR1: 87050703Swpaul case MII_PHYIDR2: 87167087Swpaul RL_UNLOCK(sc); 87250703Swpaul return(0); 87350703Swpaul break; 87440516Swpaul default: 87540516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 87667087Swpaul RL_UNLOCK(sc); 87750703Swpaul return(0); 87840516Swpaul } 87940516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 88067087Swpaul RL_UNLOCK(sc); 88150703Swpaul return(0); 88240516Swpaul } 88340516Swpaul 88440516Swpaul bzero((char *)&frame, sizeof(frame)); 88540516Swpaul 88650703Swpaul frame.mii_phyaddr = phy; 88740516Swpaul frame.mii_regaddr = reg; 88840516Swpaul frame.mii_data = data; 88940516Swpaul 89040516Swpaul rl_mii_writereg(sc, &frame); 89140516Swpaul 89267087Swpaul RL_UNLOCK(sc); 89350703Swpaul return(0); 89450703Swpaul} 89550703Swpaul 896102335Salfredstatic void 897102335Salfredrl_miibus_statchg(dev) 89850703Swpaul device_t dev; 89950703Swpaul{ 90040516Swpaul return; 90140516Swpaul} 90240516Swpaul 90340516Swpaul/* 90443062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 90540516Swpaul */ 906102335Salfredstatic u_int8_t 907102335Salfredrl_calchash(addr) 90841656Swpaul caddr_t addr; 90940516Swpaul{ 91040516Swpaul u_int32_t crc, carry; 91140516Swpaul int i, j; 91240516Swpaul u_int8_t c; 91340516Swpaul 91440516Swpaul /* Compute CRC for the address value. */ 91540516Swpaul crc = 0xFFFFFFFF; /* initial value */ 91640516Swpaul 91740516Swpaul for (i = 0; i < 6; i++) { 91840516Swpaul c = *(addr + i); 91940516Swpaul for (j = 0; j < 8; j++) { 92040516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 92140516Swpaul crc <<= 1; 92240516Swpaul c >>= 1; 92340516Swpaul if (carry) 92440516Swpaul crc = (crc ^ 0x04c11db6) | carry; 92540516Swpaul } 92640516Swpaul } 92740516Swpaul 92840516Swpaul /* return the filter bit position */ 92943062Swpaul return(crc >> 26); 93040516Swpaul} 93140516Swpaul 93240516Swpaul/* 93340516Swpaul * Program the 64-bit multicast hash filter. 93440516Swpaul */ 935102335Salfredstatic void 936102335Salfredrl_setmulti(sc) 93740516Swpaul struct rl_softc *sc; 93840516Swpaul{ 93940516Swpaul struct ifnet *ifp; 94040516Swpaul int h = 0; 94140516Swpaul u_int32_t hashes[2] = { 0, 0 }; 94240516Swpaul struct ifmultiaddr *ifma; 94340516Swpaul u_int32_t rxfilt; 94440516Swpaul int mcnt = 0; 94540516Swpaul 94640516Swpaul ifp = &sc->arpcom.ac_if; 94740516Swpaul 94840516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 94940516Swpaul 95043062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 95140516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 95240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 95340516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 95440516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 95540516Swpaul return; 95640516Swpaul } 95740516Swpaul 95840516Swpaul /* first, zot all the existing hash bits */ 95940516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 96040516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 96140516Swpaul 96240516Swpaul /* now program new ones */ 96372084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 96440516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 96540516Swpaul continue; 96640516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 96740516Swpaul if (h < 32) 96840516Swpaul hashes[0] |= (1 << h); 96940516Swpaul else 97040516Swpaul hashes[1] |= (1 << (h - 32)); 97140516Swpaul mcnt++; 97240516Swpaul } 97340516Swpaul 97440516Swpaul if (mcnt) 97540516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 97640516Swpaul else 97740516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 97840516Swpaul 97940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 98040516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 98140516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 98240516Swpaul 98340516Swpaul return; 98440516Swpaul} 98540516Swpaul 986102335Salfredstatic void 987102335Salfredrl_reset(sc) 98840516Swpaul struct rl_softc *sc; 98940516Swpaul{ 99040516Swpaul register int i; 99140516Swpaul 99240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 99340516Swpaul 99440516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 99540516Swpaul DELAY(10); 99640516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 99740516Swpaul break; 99840516Swpaul } 99940516Swpaul if (i == RL_TIMEOUT) 100040516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 100140516Swpaul 1002118586Swpaul CSR_WRITE_1(sc, 0x82, 1); 1003118586Swpaul 1004109109Sdes return; 100540516Swpaul} 100640516Swpaul 100740516Swpaul/* 100840516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 100940516Swpaul * IDs against our list and return a device name if we find a match. 101040516Swpaul */ 1011102335Salfredstatic int 1012102335Salfredrl_probe(dev) 101350703Swpaul device_t dev; 101440516Swpaul{ 101540516Swpaul struct rl_type *t; 1016117388Swpaul struct rl_softc *sc; 1017117388Swpaul struct rl_hwrev *hw_rev; 1018117388Swpaul int rid; 1019117388Swpaul u_int32_t hwrev; 1020117388Swpaul char desc[64]; 102140516Swpaul 102240516Swpaul t = rl_devs; 1023117388Swpaul sc = device_get_softc(dev); 102440516Swpaul 102540516Swpaul while(t->rl_name != NULL) { 102650703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 102750703Swpaul (pci_get_device(dev) == t->rl_did)) { 1028117388Swpaul 1029117388Swpaul /* 1030117388Swpaul * Temporarily map the I/O space 1031117388Swpaul * so we can read the chip ID register. 1032117388Swpaul */ 1033117388Swpaul rid = RL_RID; 1034117388Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 1035117388Swpaul 0, ~0, 1, RF_ACTIVE); 1036117388Swpaul if (sc->rl_res == NULL) { 1037117388Swpaul device_printf(dev, 1038117388Swpaul "couldn't map ports/memory\n"); 1039117388Swpaul return(ENXIO); 1040117388Swpaul } 1041117388Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 1042117388Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1043117388Swpaul mtx_init(&sc->rl_mtx, 1044117388Swpaul device_get_nameunit(dev), 1045117388Swpaul MTX_NETWORK_LOCK, MTX_DEF); 1046117388Swpaul RL_LOCK(sc); 1047117388Swpaul if (t->rl_basetype == RL_8139) { 1048117388Swpaul hwrev = CSR_READ_4(sc, RL_TXCFG) & 1049117388Swpaul RL_TXCFG_HWREV; 1050117388Swpaul hw_rev = rl_hwrevs; 1051117388Swpaul while (hw_rev->rl_desc != NULL) { 1052117388Swpaul if (hw_rev->rl_rev == hwrev) { 1053117388Swpaul sprintf(desc, "%s, rev. %s", 1054117388Swpaul t->rl_name, 1055117388Swpaul hw_rev->rl_desc); 1056117388Swpaul sc->rl_type = hw_rev->rl_type; 1057117388Swpaul break; 1058117388Swpaul } 1059117388Swpaul hw_rev++; 1060117388Swpaul } 1061117388Swpaul if (hw_rev->rl_desc == NULL) 1062117388Swpaul sprintf(desc, "%s, rev. %s", 1063117388Swpaul t->rl_name, "unknown"); 1064118586Swpaul } else 1065118586Swpaul sprintf(desc, "%s", t->rl_name); 1066117388Swpaul bus_release_resource(dev, RL_RES, 1067117388Swpaul RL_RID, sc->rl_res); 1068117388Swpaul RL_UNLOCK(sc); 1069117388Swpaul mtx_destroy(&sc->rl_mtx); 1070117388Swpaul device_set_desc_copy(dev, desc); 107150703Swpaul return(0); 107240516Swpaul } 107340516Swpaul t++; 107440516Swpaul } 107540516Swpaul 107650703Swpaul return(ENXIO); 107740516Swpaul} 107840516Swpaul 107940516Swpaul/* 1080117388Swpaul * This routine takes the segment list provided as the result of 1081117388Swpaul * a bus_dma_map_load() operation and assigns the addresses/lengths 1082117388Swpaul * to RealTek DMA descriptors. This can be called either by the RX 1083117388Swpaul * code or the TX code. In the RX case, we'll probably wind up mapping 1084117388Swpaul * at most one segment. For the TX case, there could be any number of 1085117388Swpaul * segments since TX packets may span multiple mbufs. In either case, 1086117388Swpaul * if the number of segments is larger than the rl_maxsegs limit 1087117388Swpaul * specified by the caller, we abort the mapping operation. Sadly, 1088117388Swpaul * whoever designed the buffer mapping API did not provide a way to 1089117388Swpaul * return an error from here, so we have to fake it a bit. 1090117388Swpaul */ 1091117388Swpaul 1092117388Swpaulstatic void 1093117388Swpaulrl_dma_map_desc(arg, segs, nseg, mapsize, error) 1094117388Swpaul void *arg; 1095117388Swpaul bus_dma_segment_t *segs; 1096117388Swpaul int nseg; 1097117388Swpaul bus_size_t mapsize; 1098117388Swpaul int error; 1099117388Swpaul{ 1100117388Swpaul struct rl_dmaload_arg *ctx; 1101117388Swpaul struct rl_desc *d = NULL; 1102117388Swpaul int i = 0, idx; 1103117388Swpaul 1104117388Swpaul if (error) 1105117388Swpaul return; 1106117388Swpaul 1107117388Swpaul ctx = arg; 1108117388Swpaul 1109117388Swpaul /* Signal error to caller if there's too many segments */ 1110117388Swpaul if (nseg > ctx->rl_maxsegs) { 1111117388Swpaul ctx->rl_maxsegs = 0; 1112117388Swpaul return; 1113117388Swpaul } 1114117388Swpaul 1115117388Swpaul /* 1116117388Swpaul * Map the segment array into descriptors. Note that we set the 1117117388Swpaul * start-of-frame and end-of-frame markers for either TX or RX, but 1118117388Swpaul * they really only have meaning in the TX case. (In the RX case, 1119117388Swpaul * it's the chip that tells us where packets begin and end.) 1120117388Swpaul * We also keep track of the end of the ring and set the 1121117388Swpaul * end-of-ring bits as needed, and we set the ownership bits 1122117388Swpaul * in all except the very first descriptor. (The caller will 1123117388Swpaul * set this descriptor later when it start transmission or 1124117388Swpaul * reception.) 1125117388Swpaul */ 1126117388Swpaul idx = ctx->rl_idx; 1127117388Swpaul while(1) { 1128117388Swpaul u_int32_t cmdstat; 1129117388Swpaul d = &ctx->rl_ring[idx]; 1130117388Swpaul if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 1131117388Swpaul ctx->rl_maxsegs = 0; 1132117388Swpaul return; 1133117388Swpaul } 1134117388Swpaul cmdstat = segs[i].ds_len; 1135118712Swpaul d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 1136118712Swpaul d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 1137117388Swpaul if (i == 0) 1138117388Swpaul cmdstat |= RL_TDESC_CMD_SOF; 1139117388Swpaul else 1140117388Swpaul cmdstat |= RL_TDESC_CMD_OWN; 1141118586Swpaul if (idx == (RL_RX_DESC_CNT - 1)) 1142117388Swpaul cmdstat |= RL_TDESC_CMD_EOR; 1143117388Swpaul d->rl_cmdstat = htole32(cmdstat); 1144117388Swpaul i++; 1145117388Swpaul if (i == nseg) 1146117388Swpaul break; 1147117388Swpaul RL_DESC_INC(idx); 1148117388Swpaul } 1149117388Swpaul 1150117388Swpaul d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1151117388Swpaul ctx->rl_maxsegs = nseg; 1152117388Swpaul ctx->rl_idx = idx; 1153117388Swpaul 1154117388Swpaul return; 1155117388Swpaul} 1156117388Swpaul 1157117388Swpaul/* 1158117388Swpaul * Map a single buffer address. 1159117388Swpaul */ 1160117388Swpaul 1161117388Swpaulstatic void 1162117388Swpaulrl_dma_map_addr(arg, segs, nseg, error) 1163117388Swpaul void *arg; 1164117388Swpaul bus_dma_segment_t *segs; 1165117388Swpaul int nseg; 1166117388Swpaul int error; 1167117388Swpaul{ 1168117388Swpaul u_int32_t *addr; 1169117388Swpaul 1170117388Swpaul if (error) 1171117388Swpaul return; 1172117388Swpaul 1173117388Swpaul KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1174117388Swpaul addr = arg; 1175117388Swpaul *addr = segs->ds_addr; 1176117388Swpaul 1177117388Swpaul return; 1178117388Swpaul} 1179117388Swpaul 1180117388Swpaulstatic int 1181117388Swpaulrl_allocmem(dev, sc) 1182117388Swpaul device_t dev; 1183117388Swpaul struct rl_softc *sc; 1184117388Swpaul{ 1185117388Swpaul int error; 1186117388Swpaul 1187117388Swpaul /* 1188117388Swpaul * Now allocate a tag for the DMA descriptor lists. 1189117388Swpaul * All of our lists are allocated as a contiguous block 1190117388Swpaul * of memory. 1191117388Swpaul */ 1192117388Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1193117388Swpaul 1, 0, /* alignment, boundary */ 1194117388Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 1195117388Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 1196117388Swpaul NULL, NULL, /* filter, filterarg */ 1197117388Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1198117388Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1199117388Swpaul 0, /* flags */ 1200117388Swpaul NULL, NULL, /* lockfunc, lockarg */ 1201117388Swpaul &sc->rl_tag); 1202117388Swpaul if (error) 1203117388Swpaul return(error); 1204117388Swpaul 1205117388Swpaul /* 1206117388Swpaul * Now allocate a chunk of DMA-able memory based on the 1207117388Swpaul * tag we just created. 1208117388Swpaul */ 1209117388Swpaul error = bus_dmamem_alloc(sc->rl_tag, 1210117388Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1211117388Swpaul &sc->rl_cdata.rl_rx_dmamap); 1212117388Swpaul 1213117388Swpaul if (error) { 1214117388Swpaul printf("rl%d: no memory for list buffers!\n", sc->rl_unit); 1215117388Swpaul bus_dma_tag_destroy(sc->rl_tag); 1216117388Swpaul sc->rl_tag = NULL; 1217117388Swpaul return(error); 1218117388Swpaul } 1219117388Swpaul 1220117388Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 1221117388Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1222117388Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1223117388Swpaul 1224117388Swpaul return(0); 1225117388Swpaul} 1226117388Swpaul 1227117388Swpaulstatic int 1228117388Swpaulrl_allocmemcplus(dev, sc) 1229117388Swpaul device_t dev; 1230117388Swpaul struct rl_softc *sc; 1231117388Swpaul{ 1232117388Swpaul int error; 1233117388Swpaul int nseg; 1234117388Swpaul int i; 1235117388Swpaul 1236117388Swpaul /* 1237117388Swpaul * Allocate map for RX mbufs. 1238117388Swpaul */ 1239117388Swpaul nseg = 32; 1240117388Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1241117388Swpaul BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1242117388Swpaul NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL, 1243117388Swpaul &sc->rl_ldata.rl_mtag); 1244117388Swpaul if (error) { 1245117388Swpaul device_printf(dev, "could not allocate dma tag\n"); 1246117388Swpaul return (ENOMEM); 1247117388Swpaul } 1248117388Swpaul 1249117388Swpaul /* 1250117388Swpaul * Allocate map for TX descriptor list. 1251117388Swpaul */ 1252117388Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1253117388Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1254117388Swpaul NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL, 1255117388Swpaul &sc->rl_ldata.rl_tx_list_tag); 1256117388Swpaul if (error) { 1257117388Swpaul device_printf(dev, "could not allocate dma tag\n"); 1258117388Swpaul return (ENOMEM); 1259117388Swpaul } 1260117388Swpaul 1261117388Swpaul /* Allocate DMA'able memory for the TX ring */ 1262117388Swpaul 1263117388Swpaul error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1264118089Smux (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1265117388Swpaul &sc->rl_ldata.rl_tx_list_map); 1266117388Swpaul if (error) 1267117388Swpaul return (ENOMEM); 1268117388Swpaul 1269117388Swpaul /* Load the map for the TX ring. */ 1270117388Swpaul 1271117388Swpaul error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1272117388Swpaul sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1273117388Swpaul RL_TX_LIST_SZ, rl_dma_map_addr, 1274117388Swpaul &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1275117388Swpaul 1276117388Swpaul /* Create DMA maps for TX buffers */ 1277117388Swpaul 1278117388Swpaul for (i = 0; i < RL_TX_DESC_CNT; i++) { 1279117388Swpaul error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1280117388Swpaul &sc->rl_ldata.rl_tx_dmamap[i]); 1281117388Swpaul if (error) { 1282117388Swpaul device_printf(dev, "can't create DMA map for TX\n"); 1283117388Swpaul return(ENOMEM); 1284117388Swpaul } 1285117388Swpaul } 1286117388Swpaul 1287117388Swpaul /* 1288117388Swpaul * Allocate map for RX descriptor list. 1289117388Swpaul */ 1290117388Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1291117388Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1292117388Swpaul NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL, 1293117388Swpaul &sc->rl_ldata.rl_rx_list_tag); 1294117388Swpaul if (error) { 1295117388Swpaul device_printf(dev, "could not allocate dma tag\n"); 1296117388Swpaul return (ENOMEM); 1297117388Swpaul } 1298117388Swpaul 1299117388Swpaul /* Allocate DMA'able memory for the RX ring */ 1300117388Swpaul 1301117388Swpaul error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1302118089Smux (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1303117388Swpaul &sc->rl_ldata.rl_rx_list_map); 1304117388Swpaul if (error) 1305117388Swpaul return (ENOMEM); 1306117388Swpaul 1307117388Swpaul /* Load the map for the RX ring. */ 1308117388Swpaul 1309117388Swpaul error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1310117388Swpaul sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1311117388Swpaul RL_TX_LIST_SZ, rl_dma_map_addr, 1312117388Swpaul &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1313117388Swpaul 1314117388Swpaul /* Create DMA maps for RX buffers */ 1315117388Swpaul 1316117388Swpaul for (i = 0; i < RL_RX_DESC_CNT; i++) { 1317117388Swpaul error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1318117388Swpaul &sc->rl_ldata.rl_rx_dmamap[i]); 1319117388Swpaul if (error) { 1320117388Swpaul device_printf(dev, "can't create DMA map for RX\n"); 1321117388Swpaul return(ENOMEM); 1322117388Swpaul } 1323117388Swpaul } 1324117388Swpaul 1325117388Swpaul return(0); 1326117388Swpaul} 1327117388Swpaul 1328117388Swpaul/* 132940516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 133040516Swpaul * setup and ethernet/BPF attach. 133140516Swpaul */ 1332102335Salfredstatic int 1333102335Salfredrl_attach(dev) 133450703Swpaul device_t dev; 133540516Swpaul{ 133640516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 1337108729Sjake u_int16_t as[3]; 133840516Swpaul struct rl_softc *sc; 133940516Swpaul struct ifnet *ifp; 1340117388Swpaul struct rl_type *t; 1341117388Swpaul struct rl_hwrev *hw_rev; 1342117388Swpaul int hwrev; 134340516Swpaul u_int16_t rl_did = 0; 1344108729Sjake int unit, error = 0, rid, i; 134540516Swpaul 134650703Swpaul sc = device_get_softc(dev); 134750703Swpaul unit = device_get_unit(dev); 134840516Swpaul 134993818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 135093818Sjhb MTX_DEF | MTX_RECURSE); 1351117208Simp#ifndef BURN_BRIDGES 135240516Swpaul /* 135340516Swpaul * Handle power management nonsense. 135440516Swpaul */ 135540516Swpaul 135670167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 135770167Swpaul u_int32_t iobase, membase, irq; 135840516Swpaul 135970167Swpaul /* Save important PCI config data. */ 136070167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 136170167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 136270167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 136340516Swpaul 136470167Swpaul /* Reset the power state. */ 136570167Swpaul printf("rl%d: chip is is in D%d power mode " 136670167Swpaul "-- setting to D0\n", unit, 136770167Swpaul pci_get_powerstate(dev)); 136840516Swpaul 136970167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 137040516Swpaul 137170167Swpaul /* Restore PCI config data. */ 137270167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 137370167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 137470167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 137540516Swpaul } 1376117208Simp#endif 137740516Swpaul /* 137840516Swpaul * Map control/status registers. 137940516Swpaul */ 138072813Swpaul pci_enable_busmaster(dev); 138140516Swpaul 1382109109Sdes rid = RL_RID; 138350703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 138450703Swpaul 0, ~0, 1, RF_ACTIVE); 138550703Swpaul 138650703Swpaul if (sc->rl_res == NULL) { 138750703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 138850703Swpaul error = ENXIO; 138940516Swpaul goto fail; 139040516Swpaul } 139140516Swpaul 1392117388Swpaul#ifdef notdef 139369127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 139469127Sroger * unstable when left to autoselect the media 139569127Sroger * The best workaround is to set the device to the required 139669127Sroger * media type or to set it to the 10 Meg speed. 139769127Sroger */ 139869127Sroger 139969127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 1400117388Swpaul printf("rl%d: Realtek 8139B detected. Warning," 1401117388Swpaul " this may be unstable in autoselect mode\n", unit); 140269127Sroger } 1403117388Swpaul#endif 140469127Sroger 140550703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 140650703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 140750703Swpaul 1408112872Snjl /* Allocate interrupt */ 140950703Swpaul rid = 0; 141050703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 141150703Swpaul RF_SHAREABLE | RF_ACTIVE); 141250703Swpaul 141350703Swpaul if (sc->rl_irq == NULL) { 141440516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 141550703Swpaul error = ENXIO; 141640516Swpaul goto fail; 141740516Swpaul } 141840516Swpaul 141940516Swpaul /* Reset the adapter. */ 142040516Swpaul rl_reset(sc); 142167931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 142267931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 142368215Swpaul if (rl_did != 0x8129) 142467931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 142540516Swpaul 142640516Swpaul /* 142740516Swpaul * Get station address from the EEPROM. 142840516Swpaul */ 1429108729Sjake rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1430108729Sjake for (i = 0; i < 3; i++) { 1431108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 1432108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 1433108729Sjake } 143440516Swpaul 143540516Swpaul /* 143640516Swpaul * A RealTek chip was detected. Inform the world. 143740516Swpaul */ 143840516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 143940516Swpaul 144040516Swpaul sc->rl_unit = unit; 144140516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 144240516Swpaul 144340516Swpaul /* 144440516Swpaul * Now read the exact device type from the EEPROM to find 144540516Swpaul * out if it's an 8129 or 8139. 144640516Swpaul */ 144740516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 144840516Swpaul 1449117388Swpaul t = rl_devs; 1450117388Swpaul while(t->rl_name != NULL) { 1451117388Swpaul if (rl_did == t->rl_did) { 1452117388Swpaul sc->rl_type = t->rl_basetype; 1453117388Swpaul break; 1454117388Swpaul } 1455117388Swpaul t++; 1456117388Swpaul } 1457117388Swpaul if (t->rl_name == NULL) { 145840516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 145950703Swpaul error = ENXIO; 146040516Swpaul goto fail; 146140516Swpaul } 1462117388Swpaul if (sc->rl_type == RL_8139) { 1463117388Swpaul hw_rev = rl_hwrevs; 1464117388Swpaul hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1465117388Swpaul while (hw_rev->rl_desc != NULL) { 1466117388Swpaul if (hw_rev->rl_rev == hwrev) { 1467117388Swpaul sc->rl_type = hw_rev->rl_type; 1468117388Swpaul break; 1469117388Swpaul } 1470117388Swpaul hw_rev++; 1471117388Swpaul } 1472117388Swpaul if (hw_rev->rl_desc == NULL) { 1473117388Swpaul printf("rl%d: unknown hwrev: %x\n", unit, hwrev); 1474117388Swpaul } 1475117388Swpaul } else if (rl_did == RT_DEVICEID_8129) { 1476117388Swpaul sc->rl_type = RL_8129; 1477117388Swpaul } else if (rl_did == RT_DEVICEID_8169) { 1478117388Swpaul sc->rl_type = RL_8169; 1479117388Swpaul } 148040516Swpaul 148181713Swpaul /* 148281713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 148381713Swpaul */ 148481713Swpaul#define RL_NSEG_NEW 32 1485109109Sdes error = bus_dma_tag_create(NULL, /* parent */ 148681713Swpaul 1, 0, /* alignment, boundary */ 148781713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 148881713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 148981713Swpaul NULL, NULL, /* filter, filterarg */ 149081713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1491109109Sdes BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 149281713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1493117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 149481713Swpaul &sc->rl_parent_tag); 1495112872Snjl if (error) 1496112872Snjl goto fail; 149740516Swpaul 149881713Swpaul /* 1499117388Swpaul * If this is an 8139C+ or 8169 chip, we have to allocate 1500117388Swpaul * our busdma tags/memory differently. We need to allocate 1501117388Swpaul * a chunk of DMA'able memory for the RX and TX descriptor 1502117388Swpaul * lists. 150381713Swpaul */ 1504117388Swpaul if (sc->rl_type == RL_8139CPLUS || sc->rl_type == RL_8169) 1505117388Swpaul error = rl_allocmemcplus(dev, sc); 1506117388Swpaul else 1507117388Swpaul error = rl_allocmem(dev, sc); 1508117388Swpaul 1509112872Snjl if (error) 1510112872Snjl goto fail; 151181713Swpaul 151250703Swpaul /* Do MII setup */ 151350703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 151450703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 151550703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 151650703Swpaul error = ENXIO; 151750703Swpaul goto fail; 151850703Swpaul } 151950703Swpaul 152040516Swpaul ifp = &sc->arpcom.ac_if; 152140516Swpaul ifp->if_softc = sc; 152240516Swpaul ifp->if_unit = unit; 152340516Swpaul ifp->if_name = "rl"; 152440516Swpaul ifp->if_mtu = ETHERMTU; 152540516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 152640516Swpaul ifp->if_ioctl = rl_ioctl; 152740516Swpaul ifp->if_output = ether_output; 1528117388Swpaul ifp->if_capabilities = IFCAP_VLAN_MTU; 1529117388Swpaul if (RL_ISCPLUS(sc)) { 1530117388Swpaul ifp->if_start = rl_startcplus; 1531117388Swpaul ifp->if_hwassist = RL_CSUM_FEATURES; 1532117388Swpaul ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1533117388Swpaul } else 1534117388Swpaul ifp->if_start = rl_start; 153540516Swpaul ifp->if_watchdog = rl_watchdog; 153640516Swpaul ifp->if_init = rl_init; 153740516Swpaul ifp->if_baudrate = 10000000; 1538117388Swpaul ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1539117388Swpaul ifp->if_capenable = ifp->if_capabilities; 154040516Swpaul 1541112872Snjl callout_handle_init(&sc->rl_stat_ch); 1542112872Snjl 154340516Swpaul /* 154463090Sarchie * Call MI attach routine. 154540516Swpaul */ 1546106936Ssam ether_ifattach(ifp, eaddr); 1547106157Simp 1548113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1549106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1550117388Swpaul RL_ISCPLUS(sc) ? rl_intrcplus : rl_intr, sc, &sc->rl_intrhand); 1551106157Simp 1552106157Simp if (error) { 1553106157Simp printf("rl%d: couldn't set up irq\n", unit); 1554113609Snjl ether_ifdetach(ifp); 1555106157Simp goto fail; 1556106157Simp } 1557106157Simp 155840516Swpaulfail: 1559112872Snjl if (error) 1560112872Snjl rl_detach(dev); 1561112872Snjl 1562110601Snjl return (error); 156340516Swpaul} 156440516Swpaul 1565113609Snjl/* 1566113609Snjl * Shutdown hardware and free up resources. This can be called any 1567113609Snjl * time after the mutex has been initialized. It is called in both 1568113609Snjl * the error case in attach and the normal detach case so it needs 1569113609Snjl * to be careful about only freeing resources that have actually been 1570113609Snjl * allocated. 1571113609Snjl */ 1572102335Salfredstatic int 1573102335Salfredrl_detach(dev) 157450703Swpaul device_t dev; 157550703Swpaul{ 157650703Swpaul struct rl_softc *sc; 157750703Swpaul struct ifnet *ifp; 1578117388Swpaul int i; 157950703Swpaul 158050703Swpaul sc = device_get_softc(dev); 1581112880Sjhb KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 158267087Swpaul RL_LOCK(sc); 158350703Swpaul ifp = &sc->arpcom.ac_if; 158450703Swpaul 1585113609Snjl /* These should only be active if attach succeeded */ 1586113812Simp if (device_is_attached(dev)) { 1587113609Snjl rl_stop(sc); 1588112872Snjl ether_ifdetach(ifp); 1589113609Snjl } 1590113609Snjl if (sc->rl_miibus) 1591112872Snjl device_delete_child(dev, sc->rl_miibus); 1592113609Snjl bus_generic_detach(dev); 159350703Swpaul 1594112872Snjl if (sc->rl_intrhand) 1595112872Snjl bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1596112872Snjl if (sc->rl_irq) 1597112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1598112872Snjl if (sc->rl_res) 1599112872Snjl bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 160050703Swpaul 1601117388Swpaul if (RL_ISCPLUS(sc)) { 1602117388Swpaul 1603117388Swpaul /* Unload and free the RX DMA ring memory and map */ 1604117388Swpaul 1605117388Swpaul if (sc->rl_ldata.rl_rx_list_tag) { 1606117388Swpaul bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1607117388Swpaul sc->rl_ldata.rl_rx_list_map); 1608117388Swpaul bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1609117388Swpaul sc->rl_ldata.rl_rx_list, 1610117388Swpaul sc->rl_ldata.rl_rx_list_map); 1611117388Swpaul bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1612117388Swpaul } 1613117388Swpaul 1614117388Swpaul /* Unload and free the TX DMA ring memory and map */ 1615117388Swpaul 1616117388Swpaul if (sc->rl_ldata.rl_tx_list_tag) { 1617117388Swpaul bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1618117388Swpaul sc->rl_ldata.rl_tx_list_map); 1619117388Swpaul bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1620117388Swpaul sc->rl_ldata.rl_tx_list, 1621117388Swpaul sc->rl_ldata.rl_tx_list_map); 1622117388Swpaul bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1623117388Swpaul } 1624117388Swpaul 1625117388Swpaul /* Destroy all the RX and TX buffer maps */ 1626117388Swpaul 1627117388Swpaul if (sc->rl_ldata.rl_mtag) { 1628117388Swpaul for (i = 0; i < RL_TX_DESC_CNT; i++) 1629117388Swpaul bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1630117388Swpaul sc->rl_ldata.rl_tx_dmamap[i]); 1631117388Swpaul for (i = 0; i < RL_RX_DESC_CNT; i++) 1632117388Swpaul bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1633117388Swpaul sc->rl_ldata.rl_rx_dmamap[i]); 1634117388Swpaul bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1635117388Swpaul } 1636117388Swpaul 1637117388Swpaul /* Unload and free the stats buffer and map */ 1638117388Swpaul 1639117388Swpaul if (sc->rl_ldata.rl_stag) { 1640117388Swpaul bus_dmamap_unload(sc->rl_ldata.rl_stag, 1641117388Swpaul sc->rl_ldata.rl_rx_list_map); 1642117388Swpaul bus_dmamem_free(sc->rl_ldata.rl_stag, 1643117388Swpaul sc->rl_ldata.rl_stats, 1644117388Swpaul sc->rl_ldata.rl_smap); 1645117388Swpaul bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1646117388Swpaul } 1647117388Swpaul 1648117388Swpaul } else { 1649117388Swpaul if (sc->rl_tag) { 1650117388Swpaul bus_dmamap_unload(sc->rl_tag, 1651117388Swpaul sc->rl_cdata.rl_rx_dmamap); 1652117388Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1653117388Swpaul sc->rl_cdata.rl_rx_dmamap); 1654117388Swpaul bus_dma_tag_destroy(sc->rl_tag); 1655117388Swpaul } 1656112872Snjl } 1657117388Swpaul 1658112872Snjl if (sc->rl_parent_tag) 1659112872Snjl bus_dma_tag_destroy(sc->rl_parent_tag); 166050703Swpaul 166167087Swpaul RL_UNLOCK(sc); 166267087Swpaul mtx_destroy(&sc->rl_mtx); 166350703Swpaul 166450703Swpaul return(0); 166550703Swpaul} 166650703Swpaul 166740516Swpaul/* 166840516Swpaul * Initialize the transmit descriptors. 166940516Swpaul */ 1670102335Salfredstatic int 1671102335Salfredrl_list_tx_init(sc) 167240516Swpaul struct rl_softc *sc; 167340516Swpaul{ 167440516Swpaul struct rl_chain_data *cd; 167540516Swpaul int i; 167640516Swpaul 167740516Swpaul cd = &sc->rl_cdata; 167840516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 167945633Swpaul cd->rl_tx_chain[i] = NULL; 168048028Swpaul CSR_WRITE_4(sc, 168148028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 168240516Swpaul } 168340516Swpaul 168445633Swpaul sc->rl_cdata.cur_tx = 0; 168545633Swpaul sc->rl_cdata.last_tx = 0; 168640516Swpaul 168740516Swpaul return(0); 168840516Swpaul} 168940516Swpaul 1690117388Swpaulstatic int 1691117388Swpaulrl_newbuf (sc, idx, m) 1692117388Swpaul struct rl_softc *sc; 1693117388Swpaul int idx; 1694117388Swpaul struct mbuf *m; 1695117388Swpaul{ 1696117388Swpaul struct rl_dmaload_arg arg; 1697117388Swpaul struct mbuf *n = NULL; 1698117388Swpaul int error; 1699117388Swpaul 1700117388Swpaul if (m == NULL) { 1701117388Swpaul n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1702117388Swpaul if (n == NULL) 1703117388Swpaul return(ENOBUFS); 1704117388Swpaul m = n; 1705117388Swpaul } else 1706117388Swpaul m->m_data = m->m_ext.ext_buf; 1707117388Swpaul 1708117388Swpaul /* 1709117388Swpaul * Initialize mbuf length fields and fixup 1710117388Swpaul * alignment so that the frame payload is 1711117388Swpaul * longword aligned. 1712117388Swpaul */ 1713117388Swpaul m->m_len = m->m_pkthdr.len = 1536; 1714117388Swpaul m_adj(m, ETHER_ALIGN); 1715117388Swpaul 1716117388Swpaul arg.sc = sc; 1717117388Swpaul arg.rl_idx = idx; 1718117388Swpaul arg.rl_maxsegs = 1; 1719117388Swpaul arg.rl_ring = sc->rl_ldata.rl_rx_list; 1720117388Swpaul 1721117388Swpaul error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1722117388Swpaul sc->rl_ldata.rl_rx_dmamap[idx], m, rl_dma_map_desc, 1723117388Swpaul &arg, BUS_DMA_NOWAIT); 1724117388Swpaul if (error || arg.rl_maxsegs != 1) { 1725117388Swpaul if (n != NULL) 1726117388Swpaul m_freem(n); 1727117388Swpaul return (ENOMEM); 1728117388Swpaul } 1729117388Swpaul 1730117388Swpaul sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1731117388Swpaul sc->rl_ldata.rl_rx_mbuf[idx] = m; 1732117388Swpaul 1733117388Swpaul bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1734117388Swpaul sc->rl_ldata.rl_rx_dmamap[idx], 1735117388Swpaul BUS_DMASYNC_PREREAD); 1736117388Swpaul 1737117388Swpaul return(0); 1738117388Swpaul} 1739117388Swpaul 1740117388Swpaulstatic int 1741117388Swpaulrl_tx_list_init(sc) 1742117388Swpaul struct rl_softc *sc; 1743117388Swpaul{ 1744117388Swpaul bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1745117388Swpaul bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1746117388Swpaul (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1747117388Swpaul 1748117388Swpaul bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1749117388Swpaul sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1750117388Swpaul sc->rl_ldata.rl_tx_prodidx = 0; 1751117388Swpaul sc->rl_ldata.rl_tx_considx = 0; 1752117388Swpaul sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1753117388Swpaul 1754117388Swpaul return(0); 1755117388Swpaul} 1756117388Swpaul 1757117388Swpaulstatic int 1758117388Swpaulrl_rx_list_init(sc) 1759117388Swpaul struct rl_softc *sc; 1760117388Swpaul{ 1761117388Swpaul int i; 1762117388Swpaul 1763117388Swpaul bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1764117388Swpaul bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1765117388Swpaul (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1766117388Swpaul 1767117388Swpaul for (i = 0; i < RL_RX_DESC_CNT; i++) { 1768117388Swpaul if (rl_newbuf(sc, i, NULL) == ENOBUFS) 1769117388Swpaul return(ENOBUFS); 1770117388Swpaul } 1771117388Swpaul 1772117388Swpaul /* Flush the RX descriptors */ 1773117388Swpaul 1774117388Swpaul bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1775117388Swpaul sc->rl_ldata.rl_rx_list_map, 1776117388Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1777117388Swpaul 1778117388Swpaul sc->rl_ldata.rl_rx_prodidx = 0; 1779117388Swpaul 1780117388Swpaul return(0); 1781117388Swpaul} 1782117388Swpaul 178340516Swpaul/* 1784117388Swpaul * RX handler for C+. This is pretty much like any other 1785117388Swpaul * descriptor-based RX handler. 1786117388Swpaul */ 1787117388Swpaulstatic void 1788117388Swpaulrl_rxeofcplus(sc) 1789117388Swpaul struct rl_softc *sc; 1790117388Swpaul{ 1791117388Swpaul struct mbuf *m; 1792117388Swpaul struct ifnet *ifp; 1793117388Swpaul int i, total_len; 1794117388Swpaul struct rl_desc *cur_rx; 1795117388Swpaul u_int32_t rxstat, rxvlan; 1796117388Swpaul 1797117388Swpaul ifp = &sc->arpcom.ac_if; 1798117388Swpaul i = sc->rl_ldata.rl_rx_prodidx; 1799117388Swpaul 1800117388Swpaul /* Invalidate the descriptor memory */ 1801117388Swpaul 1802117748Swpaul bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1803117388Swpaul sc->rl_ldata.rl_rx_list_map, 1804117388Swpaul BUS_DMASYNC_POSTREAD); 1805117388Swpaul 1806117388Swpaul while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1807117388Swpaul 1808117388Swpaul cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1809117388Swpaul m = sc->rl_ldata.rl_rx_mbuf[i]; 1810117388Swpaul total_len = RL_RXBYTES(cur_rx) - ETHER_CRC_LEN; 1811117388Swpaul rxstat = le32toh(cur_rx->rl_cmdstat); 1812117388Swpaul rxvlan = le32toh(cur_rx->rl_vlanctl); 1813117388Swpaul 1814117388Swpaul /* Invalidate the RX mbuf and unload its map */ 1815117388Swpaul 1816117388Swpaul bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1817117388Swpaul sc->rl_ldata.rl_rx_dmamap[i], 1818117388Swpaul BUS_DMASYNC_POSTREAD); 1819117388Swpaul bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1820117388Swpaul sc->rl_ldata.rl_rx_dmamap[i]); 1821117388Swpaul 1822118714Swpaul /* 1823118714Swpaul * NOTE: For some reason that I can't comprehend, 1824118714Swpaul * the RealTek engineers decided not to implement 1825118714Swpaul * the 'frame alignment error' bit in the 8169's 1826118714Swpaul * status word. Unfortunately, rather than simply 1827118714Swpaul * mark the bit as 'reserved,' they took it away 1828118714Swpaul * completely and shifted the other status bits 1829118714Swpaul * over one slot. The OWN, EOR, FS and LS bits are 1830118714Swpaul * still in the same places, as is the frame length 1831118714Swpaul * field. We have already extracted the frame length 1832118714Swpaul * and checked the OWN bit, so to work around this 1833118714Swpaul * problem, we shift the status bits one space to 1834118714Swpaul * the right so that we can evaluate everything else 1835118714Swpaul * correctly. 1836118714Swpaul */ 1837118714Swpaul if (sc->rl_type == RL_8169) 1838118714Swpaul rxstat >>= 1; 1839118714Swpaul 1840117388Swpaul if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1841117388Swpaul ifp->if_ierrors++; 1842117388Swpaul rl_newbuf(sc, i, m); 1843117388Swpaul RL_DESC_INC(i); 1844117388Swpaul continue; 1845117388Swpaul } 1846117388Swpaul 1847117388Swpaul /* 1848117388Swpaul * If allocating a replacement mbuf fails, 1849117388Swpaul * reload the current one. 1850117388Swpaul */ 1851117388Swpaul 1852117388Swpaul if (rl_newbuf(sc, i, NULL)) { 1853117388Swpaul ifp->if_ierrors++; 1854117388Swpaul rl_newbuf(sc, i, m); 1855117388Swpaul RL_DESC_INC(i); 1856117388Swpaul continue; 1857117388Swpaul } 1858117388Swpaul 1859117388Swpaul RL_DESC_INC(i); 1860117388Swpaul 1861117388Swpaul ifp->if_ipackets++; 1862117388Swpaul m->m_pkthdr.len = m->m_len = total_len; 1863117388Swpaul m->m_pkthdr.rcvif = ifp; 1864117388Swpaul 1865118712Swpaul /* Do RX checksumming if enabled */ 1866117388Swpaul 1867118712Swpaul if (ifp->if_capenable & IFCAP_RXCSUM) { 1868118712Swpaul 1869118712Swpaul /* Check IP header checksum */ 1870118712Swpaul if (rxstat & RL_RDESC_STAT_PROTOID) 1871118712Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1872118712Swpaul if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1873118712Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1874118712Swpaul 1875118712Swpaul /* Check TCP/UDP checksum */ 1876118712Swpaul if ((RL_TCPPKT(rxstat) && 1877118712Swpaul !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1878118712Swpaul (RL_UDPPKT(rxstat) && 1879118712Swpaul !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1880118712Swpaul m->m_pkthdr.csum_flags |= 1881118712Swpaul CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1882118712Swpaul m->m_pkthdr.csum_data = 0xffff; 1883118712Swpaul } 1884117388Swpaul } 1885117388Swpaul 1886117388Swpaul if (rxvlan & RL_RDESC_VLANCTL_TAG) 1887117388Swpaul VLAN_INPUT_TAG(ifp, m, 1888117388Swpaul ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1889117388Swpaul (*ifp->if_input)(ifp, m); 1890117388Swpaul } 1891117388Swpaul 1892117388Swpaul /* Flush the RX DMA ring */ 1893117388Swpaul 1894117388Swpaul bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1895117388Swpaul sc->rl_ldata.rl_rx_list_map, 1896117388Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1897117388Swpaul 1898117388Swpaul sc->rl_ldata.rl_rx_prodidx = i; 1899117388Swpaul 1900117388Swpaul return; 1901117388Swpaul} 1902117388Swpaul 1903117388Swpaul/* 190440516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 190540516Swpaul * the higher level protocols. 190640516Swpaul * 190740516Swpaul * You know there's something wrong with a PCI bus-master chip design 190840516Swpaul * when you have to use m_devget(). 190940516Swpaul * 191040516Swpaul * The receive operation is badly documented in the datasheet, so I'll 191140516Swpaul * attempt to document it here. The driver provides a buffer area and 191240516Swpaul * places its base address in the RX buffer start address register. 191340516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 191472645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 191540516Swpaul * of the frame and certain other status bits. Each frame (starting with 191640516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 191740516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 191840516Swpaul * the 'rx status register' mentioned in the datasheet. 191948028Swpaul * 192048028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 192178508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1922109109Sdes * as the offset argument to m_devget(). 192340516Swpaul */ 1924102335Salfredstatic void 1925102335Salfredrl_rxeof(sc) 192640516Swpaul struct rl_softc *sc; 192740516Swpaul{ 1928109109Sdes struct mbuf *m; 1929109109Sdes struct ifnet *ifp; 193040516Swpaul int total_len = 0; 193140516Swpaul u_int32_t rxstat; 193240516Swpaul caddr_t rxbufpos; 193340516Swpaul int wrap = 0; 193440516Swpaul u_int16_t cur_rx; 193540516Swpaul u_int16_t limit; 193640516Swpaul u_int16_t rx_bytes = 0, max_bytes; 193740516Swpaul 193840516Swpaul ifp = &sc->arpcom.ac_if; 193940516Swpaul 194081713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1941108729Sjake BUS_DMASYNC_POSTREAD); 194281713Swpaul 194340516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 194440516Swpaul 194540516Swpaul /* Do not try to read past this point. */ 194640516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 194740516Swpaul 194840516Swpaul if (limit < cur_rx) 194940516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 195040516Swpaul else 195140516Swpaul max_bytes = limit - cur_rx; 195240516Swpaul 195342738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 195494883Sluigi#ifdef DEVICE_POLLING 1955102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 195694883Sluigi if (sc->rxcycles <= 0) 195794883Sluigi break; 195894883Sluigi sc->rxcycles--; 195994883Sluigi } 196094883Sluigi#endif /* DEVICE_POLLING */ 196140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1962108729Sjake rxstat = le32toh(*(u_int32_t *)rxbufpos); 196340516Swpaul 196440516Swpaul /* 196540516Swpaul * Here's a totally undocumented fact for you. When the 196640516Swpaul * RealTek chip is in the process of copying a packet into 196740516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 196840516Swpaul * packet header with this value, you need to stop. The 196940516Swpaul * datasheet makes absolutely no mention of this and 197040516Swpaul * RealTek should be shot for this. 197140516Swpaul */ 197240516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 197340516Swpaul break; 1974109109Sdes 197540516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 197640516Swpaul ifp->if_ierrors++; 197750703Swpaul rl_init(sc); 197850703Swpaul return; 197940516Swpaul } 198040516Swpaul 1981109109Sdes /* No errors; receive the packet. */ 198240516Swpaul total_len = rxstat >> 16; 198340516Swpaul rx_bytes += total_len + 4; 198440516Swpaul 198540516Swpaul /* 198642051Swpaul * XXX The RealTek chip includes the CRC with every 198742051Swpaul * received frame, and there's no way to turn this 198842051Swpaul * behavior off (at least, I can't find anything in 1989109109Sdes * the manual that explains how to do it) so we have 199042051Swpaul * to trim off the CRC manually. 199142051Swpaul */ 199242051Swpaul total_len -= ETHER_CRC_LEN; 199342051Swpaul 199442051Swpaul /* 199540516Swpaul * Avoid trying to read more bytes than we know 199640516Swpaul * the chip has prepared for us. 199740516Swpaul */ 199840516Swpaul if (rx_bytes > max_bytes) 199940516Swpaul break; 200040516Swpaul 200140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 200240516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 200340516Swpaul 200440516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 200540516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 200640516Swpaul 200740516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 200840516Swpaul 200940516Swpaul if (total_len > wrap) { 201078508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 201178508Sbmilekic NULL); 201240516Swpaul if (m == NULL) { 201340516Swpaul ifp->if_ierrors++; 201452426Swpaul } else { 201540516Swpaul m_copyback(m, wrap, total_len - wrap, 201640516Swpaul sc->rl_cdata.rl_rx_buf); 201748028Swpaul } 201842051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 201940516Swpaul } else { 202078508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 202178508Sbmilekic NULL); 202240516Swpaul if (m == NULL) { 202340516Swpaul ifp->if_ierrors++; 202478508Sbmilekic } 202542051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 202640516Swpaul } 202740516Swpaul 202840516Swpaul /* 202940516Swpaul * Round up to 32-bit boundary. 203040516Swpaul */ 203140516Swpaul cur_rx = (cur_rx + 3) & ~3; 203240516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 203340516Swpaul 203440516Swpaul if (m == NULL) 203540516Swpaul continue; 203640516Swpaul 203740516Swpaul ifp->if_ipackets++; 2038106936Ssam (*ifp->if_input)(ifp, m); 203940516Swpaul } 204040516Swpaul 204140516Swpaul return; 204240516Swpaul} 204340516Swpaul 2044117388Swpaulstatic void 2045117388Swpaulrl_txeofcplus(sc) 2046117388Swpaul struct rl_softc *sc; 2047117388Swpaul{ 2048117388Swpaul struct ifnet *ifp; 2049117388Swpaul u_int32_t txstat; 2050117388Swpaul int idx; 2051117388Swpaul 2052117388Swpaul ifp = &sc->arpcom.ac_if; 2053117388Swpaul idx = sc->rl_ldata.rl_tx_considx; 2054117388Swpaul 2055117388Swpaul /* Invalidate the TX descriptor list */ 2056117388Swpaul 2057117748Swpaul bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2058117388Swpaul sc->rl_ldata.rl_tx_list_map, 2059117388Swpaul BUS_DMASYNC_POSTREAD); 2060117388Swpaul 2061117388Swpaul while (idx != sc->rl_ldata.rl_tx_prodidx) { 2062117388Swpaul 2063117388Swpaul txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 2064117388Swpaul if (txstat & RL_TDESC_CMD_OWN) 2065117388Swpaul break; 2066117388Swpaul 2067117388Swpaul /* 2068117388Swpaul * We only stash mbufs in the last descriptor 2069117388Swpaul * in a fragment chain, which also happens to 2070117388Swpaul * be the only place where the TX status bits 2071117388Swpaul * are valid. 2072117388Swpaul */ 2073117388Swpaul 2074117388Swpaul if (txstat & RL_TDESC_CMD_EOF) { 2075117388Swpaul m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 2076117388Swpaul sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 2077117388Swpaul bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2078117388Swpaul sc->rl_ldata.rl_tx_dmamap[idx]); 2079117388Swpaul if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2080117388Swpaul RL_TDESC_STAT_COLCNT)) 2081117388Swpaul ifp->if_collisions++; 2082117388Swpaul if (txstat & RL_TDESC_STAT_TXERRSUM) 2083117388Swpaul ifp->if_oerrors++; 2084117388Swpaul else 2085117388Swpaul ifp->if_opackets++; 2086117388Swpaul } 2087117388Swpaul sc->rl_ldata.rl_tx_free++; 2088117388Swpaul RL_DESC_INC(idx); 2089117388Swpaul } 2090117388Swpaul 2091117388Swpaul /* No changes made to the TX ring, so no flush needed */ 2092117388Swpaul 2093117388Swpaul if (idx != sc->rl_ldata.rl_tx_considx) { 2094117388Swpaul sc->rl_ldata.rl_tx_considx = idx; 2095117388Swpaul ifp->if_flags &= ~IFF_OACTIVE; 2096117388Swpaul ifp->if_timer = 0; 2097117388Swpaul } 2098117388Swpaul 2099117388Swpaul return; 2100117388Swpaul} 2101117388Swpaul 210240516Swpaul/* 210340516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 210440516Swpaul * the list buffers. 210540516Swpaul */ 2106102335Salfredstatic void 2107102335Salfredrl_txeof(sc) 210840516Swpaul struct rl_softc *sc; 210940516Swpaul{ 211040516Swpaul struct ifnet *ifp; 211140516Swpaul u_int32_t txstat; 211240516Swpaul 211340516Swpaul ifp = &sc->arpcom.ac_if; 211440516Swpaul 211540516Swpaul /* 211640516Swpaul * Go through our tx list and free mbufs for those 211740516Swpaul * frames that have been uploaded. 211840516Swpaul */ 211945633Swpaul do { 212045633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 212145633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 212245633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 212340516Swpaul break; 212440516Swpaul 212545633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 212640516Swpaul 212745633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 212881713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 212981713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 213045633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 213145633Swpaul RL_LAST_TXMBUF(sc) = NULL; 213245633Swpaul } 213345633Swpaul if (txstat & RL_TXSTAT_TX_OK) 213445633Swpaul ifp->if_opackets++; 213545633Swpaul else { 213652426Swpaul int oldthresh; 213745633Swpaul ifp->if_oerrors++; 213845633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 213945633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 214045633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 214152426Swpaul oldthresh = sc->rl_txthresh; 214252426Swpaul /* error recovery */ 214352426Swpaul rl_reset(sc); 214452426Swpaul rl_init(sc); 214552426Swpaul /* 214652426Swpaul * If there was a transmit underrun, 214752426Swpaul * bump the TX threshold. 214852426Swpaul */ 214952426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 215052426Swpaul sc->rl_txthresh = oldthresh + 32; 215152426Swpaul return; 215245633Swpaul } 215345633Swpaul RL_INC(sc->rl_cdata.last_tx); 215445633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 215545633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 215640516Swpaul 215799165Sluigi ifp->if_timer = 215899165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 215999165Sluigi 216050703Swpaul return; 216150703Swpaul} 216240516Swpaul 2163102335Salfredstatic void 2164102335Salfredrl_tick(xsc) 216550703Swpaul void *xsc; 216650703Swpaul{ 216750703Swpaul struct rl_softc *sc; 216850703Swpaul struct mii_data *mii; 216950703Swpaul 217050703Swpaul sc = xsc; 217167087Swpaul RL_LOCK(sc); 217250703Swpaul mii = device_get_softc(sc->rl_miibus); 217350703Swpaul 217450703Swpaul mii_tick(mii); 217550703Swpaul 217650703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 217767087Swpaul RL_UNLOCK(sc); 217850703Swpaul 217940516Swpaul return; 218040516Swpaul} 218140516Swpaul 218294883Sluigi#ifdef DEVICE_POLLING 218394883Sluigistatic void 218494883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 218594883Sluigi{ 218694883Sluigi struct rl_softc *sc = ifp->if_softc; 218794883Sluigi 218894883Sluigi RL_LOCK(sc); 218994883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2190117388Swpaul if (RL_ISCPLUS(sc)) 2191117388Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2192117388Swpaul else 2193117388Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 219494883Sluigi goto done; 219594883Sluigi } 219694883Sluigi 219794883Sluigi sc->rxcycles = count; 2198117388Swpaul if (RL_ISCPLUS(sc)) { 2199117388Swpaul rl_rxeofcplus(sc); 2200117388Swpaul rl_txeofcplus(sc); 2201117388Swpaul } else { 2202117388Swpaul rl_rxeof(sc); 2203117388Swpaul rl_txeof(sc); 2204117388Swpaul } 2205117388Swpaul 220694883Sluigi if (ifp->if_snd.ifq_head != NULL) 2207117388Swpaul (*ifp->if_start)(ifp); 220894883Sluigi 220994883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 221094883Sluigi u_int16_t status; 221194883Sluigi 221294883Sluigi status = CSR_READ_2(sc, RL_ISR); 2213100957Sjhb if (status == 0xffff) 2214100957Sjhb goto done; 221594883Sluigi if (status) 221694883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 221794883Sluigi 221894883Sluigi /* 221994883Sluigi * XXX check behaviour on receiver stalls. 222094883Sluigi */ 222194883Sluigi 222294883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 222394883Sluigi rl_reset(sc); 222494883Sluigi rl_init(sc); 222594883Sluigi } 222694883Sluigi } 222794883Sluigidone: 222894883Sluigi RL_UNLOCK(sc); 222994883Sluigi} 223094883Sluigi#endif /* DEVICE_POLLING */ 223194883Sluigi 2232102335Salfredstatic void 2233117388Swpaulrl_intrcplus(arg) 2234117388Swpaul void *arg; 2235117388Swpaul{ 2236117388Swpaul struct rl_softc *sc; 2237117388Swpaul struct ifnet *ifp; 2238117388Swpaul u_int16_t status; 2239117388Swpaul 2240117388Swpaul sc = arg; 2241117388Swpaul 2242117388Swpaul if (sc->suspended) { 2243117388Swpaul return; 2244117388Swpaul } 2245117388Swpaul 2246117388Swpaul RL_LOCK(sc); 2247117388Swpaul ifp = &sc->arpcom.ac_if; 2248117388Swpaul 2249117388Swpaul#ifdef DEVICE_POLLING 2250117388Swpaul if (ifp->if_flags & IFF_POLLING) 2251117388Swpaul goto done; 2252117388Swpaul if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 2253117388Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 2254117388Swpaul rl_poll(ifp, 0, 1); 2255117388Swpaul goto done; 2256117388Swpaul } 2257117388Swpaul#endif /* DEVICE_POLLING */ 2258117388Swpaul 2259117388Swpaul for (;;) { 2260117388Swpaul 2261117388Swpaul status = CSR_READ_2(sc, RL_ISR); 2262117388Swpaul /* If the card has gone away the read returns 0xffff. */ 2263117388Swpaul if (status == 0xffff) 2264117388Swpaul break; 2265117388Swpaul if (status) 2266117388Swpaul CSR_WRITE_2(sc, RL_ISR, status); 2267117388Swpaul 2268117388Swpaul if ((status & RL_INTRS_CPLUS) == 0) 2269117388Swpaul break; 2270117388Swpaul 2271117388Swpaul if (status & RL_ISR_RX_OK) 2272117388Swpaul rl_rxeofcplus(sc); 2273117388Swpaul 2274117388Swpaul if (status & RL_ISR_RX_ERR) 2275117388Swpaul rl_rxeofcplus(sc); 2276117388Swpaul 2277117388Swpaul if ((status & RL_ISR_TIMEOUT_EXPIRED) || 2278117388Swpaul (status & RL_ISR_TX_ERR) || 2279117388Swpaul (status & RL_ISR_TX_DESC_UNAVAIL)) 2280117388Swpaul rl_txeofcplus(sc); 2281117388Swpaul 2282117388Swpaul if (status & RL_ISR_SYSTEM_ERR) { 2283117388Swpaul rl_reset(sc); 2284117388Swpaul rl_init(sc); 2285117388Swpaul } 2286117388Swpaul 2287117388Swpaul } 2288117388Swpaul 2289117388Swpaul if (ifp->if_snd.ifq_head != NULL) 2290117388Swpaul (*ifp->if_start)(ifp); 2291117388Swpaul 2292117388Swpaul#ifdef DEVICE_POLLING 2293117388Swpauldone: 2294117388Swpaul#endif 2295117388Swpaul RL_UNLOCK(sc); 2296117388Swpaul 2297117388Swpaul return; 2298117388Swpaul} 2299117388Swpaul 2300117388Swpaulstatic void 2301102335Salfredrl_intr(arg) 230240516Swpaul void *arg; 230340516Swpaul{ 230440516Swpaul struct rl_softc *sc; 230540516Swpaul struct ifnet *ifp; 230640516Swpaul u_int16_t status; 230740516Swpaul 230840516Swpaul sc = arg; 230986822Siwasaki 231086822Siwasaki if (sc->suspended) { 231186822Siwasaki return; 231286822Siwasaki } 231386822Siwasaki 231467087Swpaul RL_LOCK(sc); 231540516Swpaul ifp = &sc->arpcom.ac_if; 231640516Swpaul 231794883Sluigi#ifdef DEVICE_POLLING 2318102052Ssobomax if (ifp->if_flags & IFF_POLLING) 231994883Sluigi goto done; 232094883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 232194883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 232294883Sluigi rl_poll(ifp, 0, 1); 232394883Sluigi goto done; 232494883Sluigi } 232594883Sluigi#endif /* DEVICE_POLLING */ 232640516Swpaul 232740516Swpaul for (;;) { 232840516Swpaul 232940516Swpaul status = CSR_READ_2(sc, RL_ISR); 2330100957Sjhb /* If the card has gone away the read returns 0xffff. */ 2331100957Sjhb if (status == 0xffff) 2332100957Sjhb break; 233340516Swpaul if (status) 233440516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 233540516Swpaul 233640516Swpaul if ((status & RL_INTRS) == 0) 233740516Swpaul break; 233840516Swpaul 233940516Swpaul if (status & RL_ISR_RX_OK) 234040516Swpaul rl_rxeof(sc); 234140516Swpaul 234240516Swpaul if (status & RL_ISR_RX_ERR) 234340516Swpaul rl_rxeof(sc); 234440516Swpaul 234545633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 234640516Swpaul rl_txeof(sc); 234740516Swpaul 234840516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 234940516Swpaul rl_reset(sc); 235040516Swpaul rl_init(sc); 235140516Swpaul } 235240516Swpaul 235340516Swpaul } 235440516Swpaul 235552426Swpaul if (ifp->if_snd.ifq_head != NULL) 2356117388Swpaul (*ifp->if_start)(ifp); 235740516Swpaul 235894883Sluigi#ifdef DEVICE_POLLING 235994883Sluigidone: 236094883Sluigi#endif 236167087Swpaul RL_UNLOCK(sc); 236267087Swpaul 236340516Swpaul return; 236440516Swpaul} 236540516Swpaul 2366117388Swpaulstatic int 2367117388Swpaulrl_encapcplus(sc, m_head, idx) 2368117388Swpaul struct rl_softc *sc; 2369117388Swpaul struct mbuf *m_head; 2370117388Swpaul int *idx; 2371117388Swpaul{ 2372117388Swpaul struct mbuf *m_new = NULL; 2373117388Swpaul struct rl_dmaload_arg arg; 2374117388Swpaul bus_dmamap_t map; 2375117388Swpaul int error; 2376117388Swpaul u_int32_t csumcmd = RL_TDESC_CMD_OWN; 2377117388Swpaul struct m_tag *mtag; 2378117388Swpaul 2379117388Swpaul if (sc->rl_ldata.rl_tx_free < 4) 2380117388Swpaul return(EFBIG); 2381117388Swpaul 2382117388Swpaul arg.sc = sc; 2383117388Swpaul arg.rl_idx = *idx; 2384117388Swpaul arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2385117388Swpaul arg.rl_ring = sc->rl_ldata.rl_tx_list; 2386117388Swpaul 2387117388Swpaul map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2388117388Swpaul error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2389117388Swpaul m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2390117388Swpaul 2391117388Swpaul if (error && error != EFBIG) { 2392117388Swpaul printf("rl%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 2393117388Swpaul return(ENOBUFS); 2394117388Swpaul } 2395117388Swpaul 2396117388Swpaul /* Too many segments to map, coalesce into a single mbuf */ 2397117388Swpaul 2398117388Swpaul if (error || arg.rl_maxsegs == 0) { 2399117388Swpaul m_new = m_defrag(m_head, M_DONTWAIT); 2400117388Swpaul if (m_new == NULL) 2401117388Swpaul return(1); 2402117388Swpaul else 2403117388Swpaul m_head = m_new; 2404117388Swpaul 2405117388Swpaul arg.sc = sc; 2406117388Swpaul arg.rl_idx = *idx; 2407117388Swpaul arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2408117388Swpaul arg.rl_ring = sc->rl_ldata.rl_tx_list; 2409117388Swpaul 2410117388Swpaul error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2411117388Swpaul m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2412117388Swpaul if (error) { 2413117388Swpaul printf("rl%d: can't map mbuf (error %d)\n", 2414117388Swpaul sc->rl_unit, error); 2415117388Swpaul return(EFBIG); 2416117388Swpaul } 2417117388Swpaul } 2418117388Swpaul 2419117388Swpaul /* 2420117388Swpaul * Insure that the map for this transmission 2421117388Swpaul * is placed at the array index of the last descriptor 2422117388Swpaul * in this chain. 2423117388Swpaul */ 2424117388Swpaul sc->rl_ldata.rl_tx_dmamap[*idx] = 2425117388Swpaul sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2426117388Swpaul sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2427117388Swpaul 2428117388Swpaul sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 2429117388Swpaul sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2430117388Swpaul 2431117388Swpaul /* 2432117388Swpaul * Set up hardware VLAN tagging. Note: vlan tag info must 2433117388Swpaul * appear in the first descriptor of a multi-descriptor 2434117388Swpaul * transmission attempt. 2435117388Swpaul */ 2436117388Swpaul 2437117388Swpaul mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 2438117388Swpaul if (mtag != NULL) 2439117388Swpaul sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2440117388Swpaul htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 2441117388Swpaul 2442117388Swpaul /* 2443117388Swpaul * Set up checksum offload. Note: checksum offload bits must 2444117388Swpaul * appear in the first descriptor of a multi-descriptor 2445117388Swpaul * transmission attempt. 2446117388Swpaul */ 2447117388Swpaul 2448117388Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2449117388Swpaul csumcmd |= RL_TDESC_CMD_IPCSUM; 2450117388Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2451117388Swpaul csumcmd |= RL_TDESC_CMD_TCPCSUM; 2452117388Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2453117388Swpaul csumcmd |= RL_TDESC_CMD_UDPCSUM; 2454117388Swpaul 2455117388Swpaul /* Transfer ownership of packet to the chip. */ 2456117388Swpaul 2457117388Swpaul sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= htole32(csumcmd); 2458117388Swpaul if (*idx != arg.rl_idx) 2459117388Swpaul sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= htole32(csumcmd); 2460117388Swpaul 2461117388Swpaul RL_DESC_INC(arg.rl_idx); 2462117388Swpaul *idx = arg.rl_idx; 2463117388Swpaul 2464117388Swpaul return(0); 2465117388Swpaul} 2466117388Swpaul 246740516Swpaul/* 2468117388Swpaul * Main transmit routine for C+ and gigE NICs. 2469117388Swpaul */ 2470117388Swpaul 2471117388Swpaulstatic void 2472117388Swpaulrl_startcplus(ifp) 2473117388Swpaul struct ifnet *ifp; 2474117388Swpaul{ 2475117388Swpaul struct rl_softc *sc; 2476117388Swpaul struct mbuf *m_head = NULL; 2477117388Swpaul int idx; 2478117388Swpaul 2479117388Swpaul sc = ifp->if_softc; 2480117388Swpaul RL_LOCK(sc); 2481117388Swpaul 2482117388Swpaul idx = sc->rl_ldata.rl_tx_prodidx; 2483117388Swpaul 2484117388Swpaul while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2485117388Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 2486117388Swpaul if (m_head == NULL) 2487117388Swpaul break; 2488117388Swpaul 2489117388Swpaul if (rl_encapcplus(sc, m_head, &idx)) { 2490117388Swpaul IF_PREPEND(&ifp->if_snd, m_head); 2491117388Swpaul ifp->if_flags |= IFF_OACTIVE; 2492117388Swpaul break; 2493117388Swpaul } 2494117388Swpaul 2495117388Swpaul /* 2496117388Swpaul * If there's a BPF listener, bounce a copy of this frame 2497117388Swpaul * to him. 2498117388Swpaul */ 2499117388Swpaul BPF_MTAP(ifp, m_head); 2500117388Swpaul } 2501117388Swpaul 2502117388Swpaul /* Flush the TX descriptors */ 2503117388Swpaul 2504117748Swpaul bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2505117388Swpaul sc->rl_ldata.rl_tx_list_map, 2506117388Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2507117388Swpaul 2508117388Swpaul sc->rl_ldata.rl_tx_prodidx = idx; 2509117388Swpaul 2510117388Swpaul /* 2511117388Swpaul * RealTek put the TX poll request register in a different 2512117388Swpaul * location on the 8169 gigE chip. I don't know why. 2513117388Swpaul */ 2514117388Swpaul 2515117388Swpaul if (sc->rl_type == RL_8169) 2516117388Swpaul CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2517117388Swpaul else 2518117388Swpaul CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2519117388Swpaul 2520117388Swpaul /* 2521117388Swpaul * Use the countdown timer for interrupt moderation. 2522117388Swpaul * 'TX done' interrupts are disabled. Instead, we reset the 2523117388Swpaul * countdown timer, which will begin counting until it hits 2524117388Swpaul * the value in the TIMERINT register, and then trigger an 2525117388Swpaul * interrupt. Each time we write to the TIMERCNT register, 2526117388Swpaul * the timer count is reset to 0. 2527117388Swpaul */ 2528117388Swpaul CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2529117388Swpaul 2530117388Swpaul RL_UNLOCK(sc); 2531117388Swpaul 2532117388Swpaul /* 2533117388Swpaul * Set a timeout in case the chip goes out to lunch. 2534117388Swpaul */ 2535117388Swpaul ifp->if_timer = 5; 2536117388Swpaul 2537117388Swpaul return; 2538117388Swpaul} 2539117388Swpaul 2540117388Swpaul/* 254140516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 254240516Swpaul * pointers to the fragment pointers. 254340516Swpaul */ 2544102335Salfredstatic int 2545102335Salfredrl_encap(sc, m_head) 254640516Swpaul struct rl_softc *sc; 254740516Swpaul struct mbuf *m_head; 254840516Swpaul{ 254941243Swpaul struct mbuf *m_new = NULL; 255040516Swpaul 255140516Swpaul /* 255245633Swpaul * The RealTek is brain damaged and wants longword-aligned 255345633Swpaul * TX buffers, plus we can only have one fragment buffer 255445633Swpaul * per packet. We have to copy pretty much all the time. 255540516Swpaul */ 2556112839Ssilby m_new = m_defrag(m_head, M_DONTWAIT); 255740516Swpaul 2558113496Ssilby if (m_new == NULL) { 2559113496Ssilby m_freem(m_head); 256041243Swpaul return(1); 2561113496Ssilby } 256241243Swpaul m_head = m_new; 256340516Swpaul 256440516Swpaul /* Pad frames to at least 60 bytes. */ 256541243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 256655058Swpaul /* 256755058Swpaul * Make security concious people happy: zero out the 256855058Swpaul * bytes in the pad area, since we don't know what 256955058Swpaul * this mbuf cluster buffer's previous user might 257055058Swpaul * have left in it. 2571109109Sdes */ 257255058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 257355058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 257440516Swpaul m_head->m_pkthdr.len += 257552426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 257641243Swpaul m_head->m_len = m_head->m_pkthdr.len; 257741243Swpaul } 257840516Swpaul 257945633Swpaul RL_CUR_TXMBUF(sc) = m_head; 258040516Swpaul 258140516Swpaul return(0); 258240516Swpaul} 258340516Swpaul 258440516Swpaul/* 258540516Swpaul * Main transmit routine. 258640516Swpaul */ 258740516Swpaul 2588102335Salfredstatic void 2589102335Salfredrl_start(ifp) 259040516Swpaul struct ifnet *ifp; 259140516Swpaul{ 259240516Swpaul struct rl_softc *sc; 259340516Swpaul struct mbuf *m_head = NULL; 259440516Swpaul 259540516Swpaul sc = ifp->if_softc; 259667087Swpaul RL_LOCK(sc); 259740516Swpaul 259845633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 259940516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 260040516Swpaul if (m_head == NULL) 260140516Swpaul break; 260240516Swpaul 260358801Swpaul if (rl_encap(sc, m_head)) { 260458801Swpaul break; 260558801Swpaul } 260640516Swpaul 260740516Swpaul /* 260840516Swpaul * If there's a BPF listener, bounce a copy of this frame 260940516Swpaul * to him. 261040516Swpaul */ 2611106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 261251583Swpaul 261340516Swpaul /* 261440516Swpaul * Transmit the frame. 2615109109Sdes */ 261681713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 261781713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 261881713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 2619117388Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, 2620117388Swpaul sc, BUS_DMA_NOWAIT); 262181713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 262281713Swpaul BUS_DMASYNC_PREREAD); 262345633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 262452426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 262552426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 262645633Swpaul 262745633Swpaul RL_INC(sc->rl_cdata.cur_tx); 2628113237Ssilby 2629113237Ssilby /* 2630113237Ssilby * Set a timeout in case the chip goes out to lunch. 2631113237Ssilby */ 2632113237Ssilby ifp->if_timer = 5; 263340516Swpaul } 263440516Swpaul 263540516Swpaul /* 263645633Swpaul * We broke out of the loop because all our TX slots are 263745633Swpaul * full. Mark the NIC as busy until it drains some of the 263845633Swpaul * packets from the queue. 263945633Swpaul */ 264045633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 264145633Swpaul ifp->if_flags |= IFF_OACTIVE; 264245633Swpaul 264367087Swpaul RL_UNLOCK(sc); 264440516Swpaul 264540516Swpaul return; 264640516Swpaul} 264740516Swpaul 2648102335Salfredstatic void 2649102335Salfredrl_init(xsc) 265040516Swpaul void *xsc; 265140516Swpaul{ 265240516Swpaul struct rl_softc *sc = xsc; 265340516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 265450703Swpaul struct mii_data *mii; 265540516Swpaul u_int32_t rxcfg = 0; 265640516Swpaul 265767087Swpaul RL_LOCK(sc); 265850703Swpaul mii = device_get_softc(sc->rl_miibus); 265940516Swpaul 266040516Swpaul /* 266140516Swpaul * Cancel pending I/O and free all RX/TX buffers. 266240516Swpaul */ 266340516Swpaul rl_stop(sc); 266440516Swpaul 2665117029Swpaul /* 2666117029Swpaul * Init our MAC address. Even though the chipset 2667117029Swpaul * documentation doesn't mention it, we need to enter "Config 2668117029Swpaul * register write enable" mode to modify the ID registers. 2669117029Swpaul */ 2670117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2671117029Swpaul CSR_WRITE_4(sc, RL_IDR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2672117029Swpaul CSR_WRITE_4(sc, RL_IDR4, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2673117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 267440516Swpaul 2675117388Swpaul /* 2676117388Swpaul * For C+ mode, initialize the RX descriptors and mbufs. 2677117388Swpaul */ 2678117388Swpaul if (RL_ISCPLUS(sc)) { 2679117388Swpaul rl_rx_list_init(sc); 2680117388Swpaul rl_tx_list_init(sc); 2681117388Swpaul } else { 268240516Swpaul 2683117388Swpaul /* Init the RX buffer pointer register. */ 2684117388Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 2685117388Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, 2686117388Swpaul rl_dma_map_rxbuf, sc, BUS_DMA_NOWAIT); 2687117388Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 2688117388Swpaul BUS_DMASYNC_PREWRITE); 268940516Swpaul 2690117388Swpaul /* Init TX descriptors. */ 2691117388Swpaul rl_list_tx_init(sc); 2692117388Swpaul } 2693117388Swpaul 269440516Swpaul /* 269540516Swpaul * Enable transmit and receive. 269640516Swpaul */ 269740516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 269840516Swpaul 269940516Swpaul /* 270045633Swpaul * Set the initial TX and RX configuration. 270140516Swpaul */ 270245633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 270340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 270440516Swpaul 270540516Swpaul /* Set the individual bit to receive frames for this host only. */ 270640516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 270740516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 270840516Swpaul 270940516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 271040516Swpaul if (ifp->if_flags & IFF_PROMISC) { 271140516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 271240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 271340516Swpaul } else { 271440516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 271540516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 271640516Swpaul } 271740516Swpaul 271840516Swpaul /* 271940516Swpaul * Set capture broadcast bit to capture broadcast frames. 272040516Swpaul */ 272140516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 272240516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 272340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 272440516Swpaul } else { 272540516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 272640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 272740516Swpaul } 272840516Swpaul 272940516Swpaul /* 273040516Swpaul * Program the multicast filter, if necessary. 273140516Swpaul */ 273240516Swpaul rl_setmulti(sc); 273340516Swpaul 273494883Sluigi#ifdef DEVICE_POLLING 273540516Swpaul /* 273694883Sluigi * Disable interrupts if we are polling. 273794883Sluigi */ 2738102052Ssobomax if (ifp->if_flags & IFF_POLLING) 273994883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 274094883Sluigi else /* otherwise ... */ 274194883Sluigi#endif /* DEVICE_POLLING */ 274294883Sluigi /* 274340516Swpaul * Enable interrupts. 274440516Swpaul */ 2745117388Swpaul if (RL_ISCPLUS(sc)) 2746117388Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2747117388Swpaul else 2748117388Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 274940516Swpaul 275052426Swpaul /* Set initial TX threshold */ 275152426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 275252426Swpaul 275340516Swpaul /* Start RX/TX process. */ 275440516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2755117388Swpaul#ifdef notdef 275640516Swpaul /* Enable receiver and transmitter. */ 275740516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2758117388Swpaul#endif 2759117388Swpaul /* 2760117388Swpaul * If this is a C+ capable chip, enable C+ RX and TX mode, 2761117388Swpaul * and load the addresses of the RX and TX lists into the chip. 2762117388Swpaul */ 2763117388Swpaul if (RL_ISCPLUS(sc)) { 2764117388Swpaul CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2765117388Swpaul RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2766117388Swpaul RL_CPLUSCMD_VLANSTRIP| 2767117388Swpaul (ifp->if_capenable & IFCAP_RXCSUM ? 2768117388Swpaul RL_CPLUSCMD_RXCSUM_ENB : 0)); 276940516Swpaul 2770118712Swpaul CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2771118712Swpaul RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2772117388Swpaul CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2773118712Swpaul RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2774117388Swpaul 2775118712Swpaul CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2776118712Swpaul RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2777117388Swpaul CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2778118712Swpaul RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2779117388Swpaul 2780117388Swpaul CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT); 2781117388Swpaul 2782117388Swpaul /* 2783117388Swpaul * Initialize the timer interrupt register so that 2784117388Swpaul * a timer interrupt will be generated once the timer 2785117388Swpaul * reaches a certain number of ticks. The timer is 2786117388Swpaul * reloaded on each transmit. This gives us TX interrupt 2787117388Swpaul * moderation, which dramatically improves TX frame rate. 2788117388Swpaul */ 2789117388Swpaul 2790118586Swpaul if (sc->rl_type == RL_8169) 2791118712Swpaul CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2792118586Swpaul else 2793118586Swpaul CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2794117388Swpaul 2795117388Swpaul /* 2796117388Swpaul * For 8169 gigE NICs, set the max allowed RX packet 2797117388Swpaul * size so we can receive jumbo frames. 2798117388Swpaul */ 2799117388Swpaul if (sc->rl_type == RL_8169) 2800117388Swpaul CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RL_PKTSZ(16384)); 2801117388Swpaul 2802117388Swpaul } 2803117388Swpaul 280450703Swpaul mii_mediachg(mii); 280540516Swpaul 280640516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 280740516Swpaul 280840516Swpaul ifp->if_flags |= IFF_RUNNING; 280940516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 281040516Swpaul 281150703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 281267087Swpaul RL_UNLOCK(sc); 281350703Swpaul 281440516Swpaul return; 281540516Swpaul} 281640516Swpaul 281740516Swpaul/* 281840516Swpaul * Set media options. 281940516Swpaul */ 2820102335Salfredstatic int 2821102335Salfredrl_ifmedia_upd(ifp) 282240516Swpaul struct ifnet *ifp; 282340516Swpaul{ 282440516Swpaul struct rl_softc *sc; 282550703Swpaul struct mii_data *mii; 282640516Swpaul 282740516Swpaul sc = ifp->if_softc; 282850703Swpaul mii = device_get_softc(sc->rl_miibus); 282950703Swpaul mii_mediachg(mii); 283040516Swpaul 283140516Swpaul return(0); 283240516Swpaul} 283340516Swpaul 283440516Swpaul/* 283540516Swpaul * Report current media status. 283640516Swpaul */ 2837102335Salfredstatic void 2838102335Salfredrl_ifmedia_sts(ifp, ifmr) 283940516Swpaul struct ifnet *ifp; 284040516Swpaul struct ifmediareq *ifmr; 284140516Swpaul{ 284240516Swpaul struct rl_softc *sc; 284350703Swpaul struct mii_data *mii; 284440516Swpaul 284540516Swpaul sc = ifp->if_softc; 284650703Swpaul mii = device_get_softc(sc->rl_miibus); 284740516Swpaul 284850703Swpaul mii_pollstat(mii); 284950703Swpaul ifmr->ifm_active = mii->mii_media_active; 285050703Swpaul ifmr->ifm_status = mii->mii_media_status; 285140516Swpaul 285240516Swpaul return; 285340516Swpaul} 285440516Swpaul 2855102335Salfredstatic int 2856102335Salfredrl_ioctl(ifp, command, data) 285740516Swpaul struct ifnet *ifp; 285840516Swpaul u_long command; 285940516Swpaul caddr_t data; 286040516Swpaul{ 286140516Swpaul struct rl_softc *sc = ifp->if_softc; 286240516Swpaul struct ifreq *ifr = (struct ifreq *) data; 286350703Swpaul struct mii_data *mii; 286467087Swpaul int error = 0; 286540516Swpaul 286667087Swpaul RL_LOCK(sc); 286740516Swpaul 286840516Swpaul switch(command) { 286940516Swpaul case SIOCSIFFLAGS: 287040516Swpaul if (ifp->if_flags & IFF_UP) { 287140516Swpaul rl_init(sc); 287240516Swpaul } else { 287340516Swpaul if (ifp->if_flags & IFF_RUNNING) 287440516Swpaul rl_stop(sc); 287540516Swpaul } 287640516Swpaul error = 0; 287740516Swpaul break; 287840516Swpaul case SIOCADDMULTI: 287940516Swpaul case SIOCDELMULTI: 288040516Swpaul rl_setmulti(sc); 288140516Swpaul error = 0; 288240516Swpaul break; 288340516Swpaul case SIOCGIFMEDIA: 288440516Swpaul case SIOCSIFMEDIA: 288550703Swpaul mii = device_get_softc(sc->rl_miibus); 288650703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 288740516Swpaul break; 2888117388Swpaul case SIOCSIFCAP: 2889117388Swpaul ifp->if_capenable = ifr->ifr_reqcap; 2890117388Swpaul if (ifp->if_capenable & IFCAP_TXCSUM) 2891117388Swpaul ifp->if_hwassist = RL_CSUM_FEATURES; 2892117388Swpaul else 2893117388Swpaul ifp->if_hwassist = 0; 2894117388Swpaul if (ifp->if_flags & IFF_RUNNING) 2895117388Swpaul rl_init(sc); 2896117388Swpaul break; 289740516Swpaul default: 2898106936Ssam error = ether_ioctl(ifp, command, data); 289940516Swpaul break; 290040516Swpaul } 290140516Swpaul 290267087Swpaul RL_UNLOCK(sc); 290340516Swpaul 290440516Swpaul return(error); 290540516Swpaul} 290640516Swpaul 2907102335Salfredstatic void 2908102335Salfredrl_watchdog(ifp) 290940516Swpaul struct ifnet *ifp; 291040516Swpaul{ 291140516Swpaul struct rl_softc *sc; 291240516Swpaul 291340516Swpaul sc = ifp->if_softc; 291467087Swpaul RL_LOCK(sc); 291540516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 291640516Swpaul ifp->if_oerrors++; 291750703Swpaul 2918117388Swpaul if (RL_ISCPLUS(sc)) { 2919117388Swpaul rl_txeofcplus(sc); 2920117388Swpaul rl_rxeofcplus(sc); 2921117388Swpaul } else { 2922117388Swpaul rl_txeof(sc); 2923117388Swpaul rl_rxeof(sc); 2924117388Swpaul } 2925117388Swpaul 292640516Swpaul rl_init(sc); 2927117388Swpaul 292867087Swpaul RL_UNLOCK(sc); 292940516Swpaul 293040516Swpaul return; 293140516Swpaul} 293240516Swpaul 293340516Swpaul/* 293440516Swpaul * Stop the adapter and free any mbufs allocated to the 293540516Swpaul * RX and TX lists. 293640516Swpaul */ 2937102335Salfredstatic void 2938102335Salfredrl_stop(sc) 293940516Swpaul struct rl_softc *sc; 294040516Swpaul{ 294140516Swpaul register int i; 294240516Swpaul struct ifnet *ifp; 294340516Swpaul 294467087Swpaul RL_LOCK(sc); 294540516Swpaul ifp = &sc->arpcom.ac_if; 294640516Swpaul ifp->if_timer = 0; 294740516Swpaul 294850703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 294994883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 295094883Sluigi#ifdef DEVICE_POLLING 295194883Sluigi ether_poll_deregister(ifp); 295294883Sluigi#endif /* DEVICE_POLLING */ 295350703Swpaul 295440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 295540516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 295640516Swpaul 2957117388Swpaul if (RL_ISCPLUS(sc)) { 2958117388Swpaul 2959117388Swpaul /* Free the TX list buffers. */ 2960117388Swpaul 2961117388Swpaul for (i = 0; i < RL_TX_DESC_CNT; i++) { 2962117388Swpaul if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2963117388Swpaul bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2964117388Swpaul sc->rl_ldata.rl_tx_dmamap[i]); 2965117388Swpaul m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2966117388Swpaul sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2967117388Swpaul } 296840516Swpaul } 2969117388Swpaul 2970117388Swpaul /* Free the RX list buffers. */ 2971117388Swpaul 2972117388Swpaul for (i = 0; i < RL_RX_DESC_CNT; i++) { 2973117388Swpaul if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2974117388Swpaul bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2975117388Swpaul sc->rl_ldata.rl_rx_dmamap[i]); 2976117388Swpaul m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2977117388Swpaul sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2978117388Swpaul } 2979117388Swpaul } 2980117388Swpaul 2981117388Swpaul } else { 2982117388Swpaul 2983117388Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 2984117388Swpaul 2985117388Swpaul /* 2986117388Swpaul * Free the TX list buffers. 2987117388Swpaul */ 2988117388Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 2989117388Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 2990117388Swpaul bus_dmamap_unload(sc->rl_tag, 2991117388Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 2992117388Swpaul bus_dmamap_destroy(sc->rl_tag, 2993117388Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 2994117388Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 2995117388Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 2996117388Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 2997117388Swpaul } 2998117388Swpaul } 299940516Swpaul } 300040516Swpaul 300167087Swpaul RL_UNLOCK(sc); 300240516Swpaul return; 300340516Swpaul} 300440516Swpaul 300540516Swpaul/* 300686822Siwasaki * Device suspend routine. Stop the interface and save some PCI 300786822Siwasaki * settings in case the BIOS doesn't restore them properly on 300886822Siwasaki * resume. 300986822Siwasaki */ 3010102335Salfredstatic int 3011102335Salfredrl_suspend(dev) 301286822Siwasaki device_t dev; 301386822Siwasaki{ 301486822Siwasaki register int i; 301586822Siwasaki struct rl_softc *sc; 301686822Siwasaki 301786822Siwasaki sc = device_get_softc(dev); 301886822Siwasaki 301986822Siwasaki rl_stop(sc); 302086822Siwasaki 302186822Siwasaki for (i = 0; i < 5; i++) 302286822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 302386822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 302486822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 302586822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 302686822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 302786822Siwasaki 302886822Siwasaki sc->suspended = 1; 302986822Siwasaki 303086822Siwasaki return (0); 303186822Siwasaki} 303286822Siwasaki 303386822Siwasaki/* 303486822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 303586822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 303686822Siwasaki * appropriate. 303786822Siwasaki */ 3038102335Salfredstatic int 3039102335Salfredrl_resume(dev) 304086822Siwasaki device_t dev; 304186822Siwasaki{ 304286822Siwasaki register int i; 304386822Siwasaki struct rl_softc *sc; 304486822Siwasaki struct ifnet *ifp; 304586822Siwasaki 304686822Siwasaki sc = device_get_softc(dev); 304786822Siwasaki ifp = &sc->arpcom.ac_if; 304886822Siwasaki 304986822Siwasaki /* better way to do this? */ 305086822Siwasaki for (i = 0; i < 5; i++) 305186822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 305286822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 305386822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 305486822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 305586822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 305686822Siwasaki 305786822Siwasaki /* reenable busmastering */ 305886822Siwasaki pci_enable_busmaster(dev); 305986822Siwasaki pci_enable_io(dev, RL_RES); 306086822Siwasaki 3061109109Sdes /* reinitialize interface if necessary */ 3062109109Sdes if (ifp->if_flags & IFF_UP) 3063109109Sdes rl_init(sc); 306486822Siwasaki 306586822Siwasaki sc->suspended = 0; 306686822Siwasaki 306786822Siwasaki return (0); 306886822Siwasaki} 306986822Siwasaki 307086822Siwasaki/* 307140516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 307240516Swpaul * get confused by errant DMAs when rebooting. 307340516Swpaul */ 3074102335Salfredstatic void 3075102335Salfredrl_shutdown(dev) 307650703Swpaul device_t dev; 307740516Swpaul{ 307850703Swpaul struct rl_softc *sc; 307940516Swpaul 308050703Swpaul sc = device_get_softc(dev); 308150703Swpaul 308240516Swpaul rl_stop(sc); 308340516Swpaul 308440516Swpaul return; 308540516Swpaul} 3086