if_rl.c revision 117208
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8129/8139 PCI NIC driver 35 * 36 * Supports several extremely cheap PCI 10/100 adapters based on 37 * the RealTek chipset. Datasheets can be obtained from 38 * www.realtek.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 47 * probably the worst PCI ethernet controller ever made, with the possible 48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 49 * DMA, but it has a terrible interface that nullifies any performance 50 * gains that bus-master DMA usually offers. 51 * 52 * For transmission, the chip offers a series of four TX descriptor 53 * registers. Each transmit frame must be in a contiguous buffer, aligned 54 * on a longword (32-bit) boundary. This means we almost always have to 55 * do mbuf copies in order to transmit a frame, except in the unlikely 56 * case where a) the packet fits into a single mbuf, and b) the packet 57 * is 32-bit aligned within the mbuf's data area. The presence of only 58 * four descriptor registers means that we can never have more than four 59 * packets queued for transmission at any one time. 60 * 61 * Reception is not much better. The driver has to allocate a single large 62 * buffer area (up to 64K in size) into which the chip will DMA received 63 * frames. Because we don't know where within this region received packets 64 * will begin or end, we have no choice but to copy data from the buffer 65 * area into mbufs in order to pass the packets up to the higher protocol 66 * levels. 67 * 68 * It's impossible given this rotten design to really achieve decent 69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 70 * some equally overmuscled CPU to drive it. 71 * 72 * On the bright side, the 8139 does have a built-in PHY, although 73 * rather than using an MDIO serial interface like most other NICs, the 74 * PHY registers are directly accessible through the 8139's register 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 */ 83 84#include <sys/cdefs.h> 85__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 117208 2003-07-03 21:39:53Z imp $"); 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117MODULE_DEPEND(rl, pci, 1, 1, 1); 118MODULE_DEPEND(rl, ether, 1, 1, 1); 119MODULE_DEPEND(rl, miibus, 1, 1, 1); 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124/* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132#define RL_USEIOSPACE 133 134#include <pci/if_rlreg.h> 135 136__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 117208 2003-07-03 21:39:53Z imp $"); 137 138/* 139 * Various supported device vendors/types and their names. 140 */ 141static struct rl_type rl_devs[] = { 142 { RT_VENDORID, RT_DEVICEID_8129, 143 "RealTek 8129 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8139, 145 "RealTek 8139 10/100BaseTX" }, 146 { RT_VENDORID, RT_DEVICEID_8138, 147 "RealTek 8139 10/100BaseTX CardBus" }, 148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { DELTA_VENDORID, DELTA_DEVICEID_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 153 "Addtron Technolgy 8139 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 157 "D-Link DFE-690TXD 10/100BaseTX" }, 158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 159 "Nortel Networks 10/100BaseTX" }, 160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 161 "Corega FEther CB-TXD" }, 162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 163 "Corega FEtherII CB-TXD" }, 164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 165 "Peppercon AG ROL-F" }, 166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 167 "Planex FNW-3800-TX" }, 168 { 0, 0, NULL } 169}; 170 171static int rl_probe (device_t); 172static int rl_attach (device_t); 173static int rl_detach (device_t); 174 175static int rl_encap (struct rl_softc *, struct mbuf * ); 176 177static void rl_rxeof (struct rl_softc *); 178static void rl_txeof (struct rl_softc *); 179static void rl_intr (void *); 180static void rl_tick (void *); 181static void rl_start (struct ifnet *); 182static int rl_ioctl (struct ifnet *, u_long, caddr_t); 183static void rl_init (void *); 184static void rl_stop (struct rl_softc *); 185static void rl_watchdog (struct ifnet *); 186static int rl_suspend (device_t); 187static int rl_resume (device_t); 188static void rl_shutdown (device_t); 189static int rl_ifmedia_upd (struct ifnet *); 190static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 191 192static void rl_eeprom_putbyte (struct rl_softc *, int); 193static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 194static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 195static void rl_mii_sync (struct rl_softc *); 196static void rl_mii_send (struct rl_softc *, u_int32_t, int); 197static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 198static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 199 200static int rl_miibus_readreg (device_t, int, int); 201static int rl_miibus_writereg (device_t, int, int, int); 202static void rl_miibus_statchg (device_t); 203 204static u_int8_t rl_calchash (caddr_t); 205static void rl_setmulti (struct rl_softc *); 206static void rl_reset (struct rl_softc *); 207static int rl_list_tx_init (struct rl_softc *); 208 209static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 210static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 211 212#ifdef RL_USEIOSPACE 213#define RL_RES SYS_RES_IOPORT 214#define RL_RID RL_PCI_LOIO 215#else 216#define RL_RES SYS_RES_MEMORY 217#define RL_RID RL_PCI_LOMEM 218#endif 219 220static device_method_t rl_methods[] = { 221 /* Device interface */ 222 DEVMETHOD(device_probe, rl_probe), 223 DEVMETHOD(device_attach, rl_attach), 224 DEVMETHOD(device_detach, rl_detach), 225 DEVMETHOD(device_suspend, rl_suspend), 226 DEVMETHOD(device_resume, rl_resume), 227 DEVMETHOD(device_shutdown, rl_shutdown), 228 229 /* bus interface */ 230 DEVMETHOD(bus_print_child, bus_generic_print_child), 231 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 232 233 /* MII interface */ 234 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 235 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 236 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 237 238 { 0, 0 } 239}; 240 241static driver_t rl_driver = { 242 "rl", 243 rl_methods, 244 sizeof(struct rl_softc) 245}; 246 247static devclass_t rl_devclass; 248 249DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 250DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 251DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 252 253#define EE_SET(x) \ 254 CSR_WRITE_1(sc, RL_EECMD, \ 255 CSR_READ_1(sc, RL_EECMD) | x) 256 257#define EE_CLR(x) \ 258 CSR_WRITE_1(sc, RL_EECMD, \ 259 CSR_READ_1(sc, RL_EECMD) & ~x) 260 261static void 262rl_dma_map_rxbuf(arg, segs, nseg, error) 263 void *arg; 264 bus_dma_segment_t *segs; 265 int nseg, error; 266{ 267 struct rl_softc *sc; 268 269 sc = arg; 270 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 271 272 return; 273} 274 275static void 276rl_dma_map_txbuf(arg, segs, nseg, error) 277 void *arg; 278 bus_dma_segment_t *segs; 279 int nseg, error; 280{ 281 struct rl_softc *sc; 282 283 sc = arg; 284 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 285 286 return; 287} 288 289/* 290 * Send a read command and address to the EEPROM, check for ACK. 291 */ 292static void 293rl_eeprom_putbyte(sc, addr) 294 struct rl_softc *sc; 295 int addr; 296{ 297 register int d, i; 298 299 d = addr | sc->rl_eecmd_read; 300 301 /* 302 * Feed in each bit and strobe the clock. 303 */ 304 for (i = 0x400; i; i >>= 1) { 305 if (d & i) { 306 EE_SET(RL_EE_DATAIN); 307 } else { 308 EE_CLR(RL_EE_DATAIN); 309 } 310 DELAY(100); 311 EE_SET(RL_EE_CLK); 312 DELAY(150); 313 EE_CLR(RL_EE_CLK); 314 DELAY(100); 315 } 316 317 return; 318} 319 320/* 321 * Read a word of data stored in the EEPROM at address 'addr.' 322 */ 323static void 324rl_eeprom_getword(sc, addr, dest) 325 struct rl_softc *sc; 326 int addr; 327 u_int16_t *dest; 328{ 329 register int i; 330 u_int16_t word = 0; 331 332 /* Enter EEPROM access mode. */ 333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 334 335 /* 336 * Send address of word we want to read. 337 */ 338 rl_eeprom_putbyte(sc, addr); 339 340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 341 342 /* 343 * Start reading bits from EEPROM. 344 */ 345 for (i = 0x8000; i; i >>= 1) { 346 EE_SET(RL_EE_CLK); 347 DELAY(100); 348 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 349 word |= i; 350 EE_CLR(RL_EE_CLK); 351 DELAY(100); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 356 357 *dest = word; 358 359 return; 360} 361 362/* 363 * Read a sequence of words from the EEPROM. 364 */ 365static void 366rl_read_eeprom(sc, dest, off, cnt, swap) 367 struct rl_softc *sc; 368 caddr_t dest; 369 int off; 370 int cnt; 371 int swap; 372{ 373 int i; 374 u_int16_t word = 0, *ptr; 375 376 for (i = 0; i < cnt; i++) { 377 rl_eeprom_getword(sc, off + i, &word); 378 ptr = (u_int16_t *)(dest + (i * 2)); 379 if (swap) 380 *ptr = ntohs(word); 381 else 382 *ptr = word; 383 } 384 385 return; 386} 387 388 389/* 390 * MII access routines are provided for the 8129, which 391 * doesn't have a built-in PHY. For the 8139, we fake things 392 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 393 * direct access PHY registers. 394 */ 395#define MII_SET(x) \ 396 CSR_WRITE_1(sc, RL_MII, \ 397 CSR_READ_1(sc, RL_MII) | (x)) 398 399#define MII_CLR(x) \ 400 CSR_WRITE_1(sc, RL_MII, \ 401 CSR_READ_1(sc, RL_MII) & ~(x)) 402 403/* 404 * Sync the PHYs by setting data bit and strobing the clock 32 times. 405 */ 406static void 407rl_mii_sync(sc) 408 struct rl_softc *sc; 409{ 410 register int i; 411 412 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 413 414 for (i = 0; i < 32; i++) { 415 MII_SET(RL_MII_CLK); 416 DELAY(1); 417 MII_CLR(RL_MII_CLK); 418 DELAY(1); 419 } 420 421 return; 422} 423 424/* 425 * Clock a series of bits through the MII. 426 */ 427static void 428rl_mii_send(sc, bits, cnt) 429 struct rl_softc *sc; 430 u_int32_t bits; 431 int cnt; 432{ 433 int i; 434 435 MII_CLR(RL_MII_CLK); 436 437 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 438 if (bits & i) { 439 MII_SET(RL_MII_DATAOUT); 440 } else { 441 MII_CLR(RL_MII_DATAOUT); 442 } 443 DELAY(1); 444 MII_CLR(RL_MII_CLK); 445 DELAY(1); 446 MII_SET(RL_MII_CLK); 447 } 448} 449 450/* 451 * Read an PHY register through the MII. 452 */ 453static int 454rl_mii_readreg(sc, frame) 455 struct rl_softc *sc; 456 struct rl_mii_frame *frame; 457 458{ 459 int i, ack; 460 461 RL_LOCK(sc); 462 463 /* 464 * Set up frame for RX. 465 */ 466 frame->mii_stdelim = RL_MII_STARTDELIM; 467 frame->mii_opcode = RL_MII_READOP; 468 frame->mii_turnaround = 0; 469 frame->mii_data = 0; 470 471 CSR_WRITE_2(sc, RL_MII, 0); 472 473 /* 474 * Turn on data xmit. 475 */ 476 MII_SET(RL_MII_DIR); 477 478 rl_mii_sync(sc); 479 480 /* 481 * Send command/address info. 482 */ 483 rl_mii_send(sc, frame->mii_stdelim, 2); 484 rl_mii_send(sc, frame->mii_opcode, 2); 485 rl_mii_send(sc, frame->mii_phyaddr, 5); 486 rl_mii_send(sc, frame->mii_regaddr, 5); 487 488 /* Idle bit */ 489 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 490 DELAY(1); 491 MII_SET(RL_MII_CLK); 492 DELAY(1); 493 494 /* Turn off xmit. */ 495 MII_CLR(RL_MII_DIR); 496 497 /* Check for ack */ 498 MII_CLR(RL_MII_CLK); 499 DELAY(1); 500 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 501 MII_SET(RL_MII_CLK); 502 DELAY(1); 503 504 /* 505 * Now try reading data bits. If the ack failed, we still 506 * need to clock through 16 cycles to keep the PHY(s) in sync. 507 */ 508 if (ack) { 509 for(i = 0; i < 16; i++) { 510 MII_CLR(RL_MII_CLK); 511 DELAY(1); 512 MII_SET(RL_MII_CLK); 513 DELAY(1); 514 } 515 goto fail; 516 } 517 518 for (i = 0x8000; i; i >>= 1) { 519 MII_CLR(RL_MII_CLK); 520 DELAY(1); 521 if (!ack) { 522 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 523 frame->mii_data |= i; 524 DELAY(1); 525 } 526 MII_SET(RL_MII_CLK); 527 DELAY(1); 528 } 529 530fail: 531 532 MII_CLR(RL_MII_CLK); 533 DELAY(1); 534 MII_SET(RL_MII_CLK); 535 DELAY(1); 536 537 RL_UNLOCK(sc); 538 539 if (ack) 540 return(1); 541 return(0); 542} 543 544/* 545 * Write to a PHY register through the MII. 546 */ 547static int 548rl_mii_writereg(sc, frame) 549 struct rl_softc *sc; 550 struct rl_mii_frame *frame; 551 552{ 553 RL_LOCK(sc); 554 555 /* 556 * Set up frame for TX. 557 */ 558 559 frame->mii_stdelim = RL_MII_STARTDELIM; 560 frame->mii_opcode = RL_MII_WRITEOP; 561 frame->mii_turnaround = RL_MII_TURNAROUND; 562 563 /* 564 * Turn on data output. 565 */ 566 MII_SET(RL_MII_DIR); 567 568 rl_mii_sync(sc); 569 570 rl_mii_send(sc, frame->mii_stdelim, 2); 571 rl_mii_send(sc, frame->mii_opcode, 2); 572 rl_mii_send(sc, frame->mii_phyaddr, 5); 573 rl_mii_send(sc, frame->mii_regaddr, 5); 574 rl_mii_send(sc, frame->mii_turnaround, 2); 575 rl_mii_send(sc, frame->mii_data, 16); 576 577 /* Idle bit. */ 578 MII_SET(RL_MII_CLK); 579 DELAY(1); 580 MII_CLR(RL_MII_CLK); 581 DELAY(1); 582 583 /* 584 * Turn off xmit. 585 */ 586 MII_CLR(RL_MII_DIR); 587 588 RL_UNLOCK(sc); 589 590 return(0); 591} 592 593static int 594rl_miibus_readreg(dev, phy, reg) 595 device_t dev; 596 int phy, reg; 597{ 598 struct rl_softc *sc; 599 struct rl_mii_frame frame; 600 u_int16_t rval = 0; 601 u_int16_t rl8139_reg = 0; 602 603 sc = device_get_softc(dev); 604 RL_LOCK(sc); 605 606 if (sc->rl_type == RL_8139) { 607 /* Pretend the internal PHY is only at address 0 */ 608 if (phy) { 609 RL_UNLOCK(sc); 610 return(0); 611 } 612 switch(reg) { 613 case MII_BMCR: 614 rl8139_reg = RL_BMCR; 615 break; 616 case MII_BMSR: 617 rl8139_reg = RL_BMSR; 618 break; 619 case MII_ANAR: 620 rl8139_reg = RL_ANAR; 621 break; 622 case MII_ANER: 623 rl8139_reg = RL_ANER; 624 break; 625 case MII_ANLPAR: 626 rl8139_reg = RL_LPAR; 627 break; 628 case MII_PHYIDR1: 629 case MII_PHYIDR2: 630 RL_UNLOCK(sc); 631 return(0); 632 /* 633 * Allow the rlphy driver to read the media status 634 * register. If we have a link partner which does not 635 * support NWAY, this is the register which will tell 636 * us the results of parallel detection. 637 */ 638 case RL_MEDIASTAT: 639 rval = CSR_READ_1(sc, RL_MEDIASTAT); 640 RL_UNLOCK(sc); 641 return(rval); 642 default: 643 printf("rl%d: bad phy register\n", sc->rl_unit); 644 RL_UNLOCK(sc); 645 return(0); 646 } 647 rval = CSR_READ_2(sc, rl8139_reg); 648 RL_UNLOCK(sc); 649 return(rval); 650 } 651 652 bzero((char *)&frame, sizeof(frame)); 653 654 frame.mii_phyaddr = phy; 655 frame.mii_regaddr = reg; 656 rl_mii_readreg(sc, &frame); 657 RL_UNLOCK(sc); 658 659 return(frame.mii_data); 660} 661 662static int 663rl_miibus_writereg(dev, phy, reg, data) 664 device_t dev; 665 int phy, reg, data; 666{ 667 struct rl_softc *sc; 668 struct rl_mii_frame frame; 669 u_int16_t rl8139_reg = 0; 670 671 sc = device_get_softc(dev); 672 RL_LOCK(sc); 673 674 if (sc->rl_type == RL_8139) { 675 /* Pretend the internal PHY is only at address 0 */ 676 if (phy) { 677 RL_UNLOCK(sc); 678 return(0); 679 } 680 switch(reg) { 681 case MII_BMCR: 682 rl8139_reg = RL_BMCR; 683 break; 684 case MII_BMSR: 685 rl8139_reg = RL_BMSR; 686 break; 687 case MII_ANAR: 688 rl8139_reg = RL_ANAR; 689 break; 690 case MII_ANER: 691 rl8139_reg = RL_ANER; 692 break; 693 case MII_ANLPAR: 694 rl8139_reg = RL_LPAR; 695 break; 696 case MII_PHYIDR1: 697 case MII_PHYIDR2: 698 RL_UNLOCK(sc); 699 return(0); 700 break; 701 default: 702 printf("rl%d: bad phy register\n", sc->rl_unit); 703 RL_UNLOCK(sc); 704 return(0); 705 } 706 CSR_WRITE_2(sc, rl8139_reg, data); 707 RL_UNLOCK(sc); 708 return(0); 709 } 710 711 bzero((char *)&frame, sizeof(frame)); 712 713 frame.mii_phyaddr = phy; 714 frame.mii_regaddr = reg; 715 frame.mii_data = data; 716 717 rl_mii_writereg(sc, &frame); 718 719 RL_UNLOCK(sc); 720 return(0); 721} 722 723static void 724rl_miibus_statchg(dev) 725 device_t dev; 726{ 727 return; 728} 729 730/* 731 * Calculate CRC of a multicast group address, return the upper 6 bits. 732 */ 733static u_int8_t 734rl_calchash(addr) 735 caddr_t addr; 736{ 737 u_int32_t crc, carry; 738 int i, j; 739 u_int8_t c; 740 741 /* Compute CRC for the address value. */ 742 crc = 0xFFFFFFFF; /* initial value */ 743 744 for (i = 0; i < 6; i++) { 745 c = *(addr + i); 746 for (j = 0; j < 8; j++) { 747 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 748 crc <<= 1; 749 c >>= 1; 750 if (carry) 751 crc = (crc ^ 0x04c11db6) | carry; 752 } 753 } 754 755 /* return the filter bit position */ 756 return(crc >> 26); 757} 758 759/* 760 * Program the 64-bit multicast hash filter. 761 */ 762static void 763rl_setmulti(sc) 764 struct rl_softc *sc; 765{ 766 struct ifnet *ifp; 767 int h = 0; 768 u_int32_t hashes[2] = { 0, 0 }; 769 struct ifmultiaddr *ifma; 770 u_int32_t rxfilt; 771 int mcnt = 0; 772 773 ifp = &sc->arpcom.ac_if; 774 775 rxfilt = CSR_READ_4(sc, RL_RXCFG); 776 777 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 778 rxfilt |= RL_RXCFG_RX_MULTI; 779 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 780 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 781 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 782 return; 783 } 784 785 /* first, zot all the existing hash bits */ 786 CSR_WRITE_4(sc, RL_MAR0, 0); 787 CSR_WRITE_4(sc, RL_MAR4, 0); 788 789 /* now program new ones */ 790 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 791 if (ifma->ifma_addr->sa_family != AF_LINK) 792 continue; 793 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 794 if (h < 32) 795 hashes[0] |= (1 << h); 796 else 797 hashes[1] |= (1 << (h - 32)); 798 mcnt++; 799 } 800 801 if (mcnt) 802 rxfilt |= RL_RXCFG_RX_MULTI; 803 else 804 rxfilt &= ~RL_RXCFG_RX_MULTI; 805 806 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 807 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 808 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 809 810 return; 811} 812 813static void 814rl_reset(sc) 815 struct rl_softc *sc; 816{ 817 register int i; 818 819 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 820 821 for (i = 0; i < RL_TIMEOUT; i++) { 822 DELAY(10); 823 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 824 break; 825 } 826 if (i == RL_TIMEOUT) 827 printf("rl%d: reset never completed!\n", sc->rl_unit); 828 829 return; 830} 831 832/* 833 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 834 * IDs against our list and return a device name if we find a match. 835 */ 836static int 837rl_probe(dev) 838 device_t dev; 839{ 840 struct rl_type *t; 841 842 t = rl_devs; 843 844 while(t->rl_name != NULL) { 845 if ((pci_get_vendor(dev) == t->rl_vid) && 846 (pci_get_device(dev) == t->rl_did)) { 847 device_set_desc(dev, t->rl_name); 848 return(0); 849 } 850 t++; 851 } 852 853 return(ENXIO); 854} 855 856/* 857 * Attach the interface. Allocate softc structures, do ifmedia 858 * setup and ethernet/BPF attach. 859 */ 860static int 861rl_attach(dev) 862 device_t dev; 863{ 864 u_char eaddr[ETHER_ADDR_LEN]; 865 u_int16_t as[3]; 866 struct rl_softc *sc; 867 struct ifnet *ifp; 868 u_int16_t rl_did = 0; 869 int unit, error = 0, rid, i; 870 871 sc = device_get_softc(dev); 872 unit = device_get_unit(dev); 873 874 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 875 MTX_DEF | MTX_RECURSE); 876#ifndef BURN_BRIDGES 877 /* 878 * Handle power management nonsense. 879 */ 880 881 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 882 u_int32_t iobase, membase, irq; 883 884 /* Save important PCI config data. */ 885 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 886 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 887 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 888 889 /* Reset the power state. */ 890 printf("rl%d: chip is is in D%d power mode " 891 "-- setting to D0\n", unit, 892 pci_get_powerstate(dev)); 893 894 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 895 896 /* Restore PCI config data. */ 897 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 898 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 899 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 900 } 901#endif 902 /* 903 * Map control/status registers. 904 */ 905 pci_enable_busmaster(dev); 906 907 rid = RL_RID; 908 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 909 0, ~0, 1, RF_ACTIVE); 910 911 if (sc->rl_res == NULL) { 912 printf ("rl%d: couldn't map ports/memory\n", unit); 913 error = ENXIO; 914 goto fail; 915 } 916 917 /* Detect the Realtek 8139B. For some reason, this chip is very 918 * unstable when left to autoselect the media 919 * The best workaround is to set the device to the required 920 * media type or to set it to the 10 Meg speed. 921 */ 922 923 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 924 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 925 } 926 927 sc->rl_btag = rman_get_bustag(sc->rl_res); 928 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 929 930 /* Allocate interrupt */ 931 rid = 0; 932 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 933 RF_SHAREABLE | RF_ACTIVE); 934 935 if (sc->rl_irq == NULL) { 936 printf("rl%d: couldn't map interrupt\n", unit); 937 error = ENXIO; 938 goto fail; 939 } 940 941 /* Reset the adapter. */ 942 rl_reset(sc); 943 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 944 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 945 if (rl_did != 0x8129) 946 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 947 948 /* 949 * Get station address from the EEPROM. 950 */ 951 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 952 for (i = 0; i < 3; i++) { 953 eaddr[(i * 2) + 0] = as[i] & 0xff; 954 eaddr[(i * 2) + 1] = as[i] >> 8; 955 } 956 957 /* 958 * A RealTek chip was detected. Inform the world. 959 */ 960 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 961 962 sc->rl_unit = unit; 963 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 964 965 /* 966 * Now read the exact device type from the EEPROM to find 967 * out if it's an 8129 or 8139. 968 */ 969 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 970 971 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 972 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 973 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 974 rl_did == DLINK_DEVICEID_690TXD || 975 rl_did == COREGA_DEVICEID_FETHERCBTXD || 976 rl_did == COREGA_DEVICEID_FETHERIICBTXD || 977 rl_did == PLANEX_DEVICEID_FNW3800TX) 978 sc->rl_type = RL_8139; 979 else if (rl_did == RT_DEVICEID_8129) 980 sc->rl_type = RL_8129; 981 else { 982 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 983 error = ENXIO; 984 goto fail; 985 } 986 987 /* 988 * Allocate the parent bus DMA tag appropriate for PCI. 989 */ 990#define RL_NSEG_NEW 32 991 error = bus_dma_tag_create(NULL, /* parent */ 992 1, 0, /* alignment, boundary */ 993 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 994 BUS_SPACE_MAXADDR, /* highaddr */ 995 NULL, NULL, /* filter, filterarg */ 996 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 997 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 998 BUS_DMA_ALLOCNOW, /* flags */ 999 NULL, NULL, /* lockfunc, lockarg */ 1000 &sc->rl_parent_tag); 1001 if (error) 1002 goto fail; 1003 1004 /* 1005 * Now allocate a tag for the DMA descriptor lists. 1006 * All of our lists are allocated as a contiguous block 1007 * of memory. 1008 */ 1009 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1010 1, 0, /* alignment, boundary */ 1011 BUS_SPACE_MAXADDR, /* lowaddr */ 1012 BUS_SPACE_MAXADDR, /* highaddr */ 1013 NULL, NULL, /* filter, filterarg */ 1014 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1015 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1016 0, /* flags */ 1017 busdma_lock_mutex, /* lockfunc */ 1018 &Giant, /* lockarg */ 1019 &sc->rl_tag); 1020 if (error) 1021 goto fail; 1022 1023 /* 1024 * Now allocate a chunk of DMA-able memory based on the 1025 * tag we just created. 1026 */ 1027 error = bus_dmamem_alloc(sc->rl_tag, 1028 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1029 &sc->rl_cdata.rl_rx_dmamap); 1030 1031 if (error) { 1032 printf("rl%d: no memory for list buffers!\n", unit); 1033 bus_dma_tag_destroy(sc->rl_tag); 1034 sc->rl_tag = NULL; 1035 goto fail; 1036 } 1037 1038 /* Leave a few bytes before the start of the RX ring buffer. */ 1039 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1040 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1041 1042 /* Do MII setup */ 1043 if (mii_phy_probe(dev, &sc->rl_miibus, 1044 rl_ifmedia_upd, rl_ifmedia_sts)) { 1045 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1046 error = ENXIO; 1047 goto fail; 1048 } 1049 1050 ifp = &sc->arpcom.ac_if; 1051 ifp->if_softc = sc; 1052 ifp->if_unit = unit; 1053 ifp->if_name = "rl"; 1054 ifp->if_mtu = ETHERMTU; 1055 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1056 ifp->if_ioctl = rl_ioctl; 1057 ifp->if_output = ether_output; 1058 ifp->if_start = rl_start; 1059 ifp->if_watchdog = rl_watchdog; 1060 ifp->if_init = rl_init; 1061 ifp->if_baudrate = 10000000; 1062 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1063 1064 callout_handle_init(&sc->rl_stat_ch); 1065 1066 /* 1067 * Call MI attach routine. 1068 */ 1069 ether_ifattach(ifp, eaddr); 1070 1071 /* Hook interrupt last to avoid having to lock softc */ 1072 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1073 rl_intr, sc, &sc->rl_intrhand); 1074 1075 if (error) { 1076 printf("rl%d: couldn't set up irq\n", unit); 1077 ether_ifdetach(ifp); 1078 goto fail; 1079 } 1080 1081fail: 1082 if (error) 1083 rl_detach(dev); 1084 1085 return (error); 1086} 1087 1088/* 1089 * Shutdown hardware and free up resources. This can be called any 1090 * time after the mutex has been initialized. It is called in both 1091 * the error case in attach and the normal detach case so it needs 1092 * to be careful about only freeing resources that have actually been 1093 * allocated. 1094 */ 1095static int 1096rl_detach(dev) 1097 device_t dev; 1098{ 1099 struct rl_softc *sc; 1100 struct ifnet *ifp; 1101 1102 sc = device_get_softc(dev); 1103 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1104 RL_LOCK(sc); 1105 ifp = &sc->arpcom.ac_if; 1106 1107 /* These should only be active if attach succeeded */ 1108 if (device_is_attached(dev)) { 1109 rl_stop(sc); 1110 ether_ifdetach(ifp); 1111 } 1112 if (sc->rl_miibus) 1113 device_delete_child(dev, sc->rl_miibus); 1114 bus_generic_detach(dev); 1115 1116 if (sc->rl_intrhand) 1117 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1118 if (sc->rl_irq) 1119 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1120 if (sc->rl_res) 1121 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1122 1123 if (sc->rl_tag) { 1124 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1125 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1126 sc->rl_cdata.rl_rx_dmamap); 1127 bus_dma_tag_destroy(sc->rl_tag); 1128 } 1129 if (sc->rl_parent_tag) 1130 bus_dma_tag_destroy(sc->rl_parent_tag); 1131 1132 RL_UNLOCK(sc); 1133 mtx_destroy(&sc->rl_mtx); 1134 1135 return(0); 1136} 1137 1138/* 1139 * Initialize the transmit descriptors. 1140 */ 1141static int 1142rl_list_tx_init(sc) 1143 struct rl_softc *sc; 1144{ 1145 struct rl_chain_data *cd; 1146 int i; 1147 1148 cd = &sc->rl_cdata; 1149 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1150 cd->rl_tx_chain[i] = NULL; 1151 CSR_WRITE_4(sc, 1152 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1153 } 1154 1155 sc->rl_cdata.cur_tx = 0; 1156 sc->rl_cdata.last_tx = 0; 1157 1158 return(0); 1159} 1160 1161/* 1162 * A frame has been uploaded: pass the resulting mbuf chain up to 1163 * the higher level protocols. 1164 * 1165 * You know there's something wrong with a PCI bus-master chip design 1166 * when you have to use m_devget(). 1167 * 1168 * The receive operation is badly documented in the datasheet, so I'll 1169 * attempt to document it here. The driver provides a buffer area and 1170 * places its base address in the RX buffer start address register. 1171 * The chip then begins copying frames into the RX buffer. Each frame 1172 * is preceded by a 32-bit RX status word which specifies the length 1173 * of the frame and certain other status bits. Each frame (starting with 1174 * the status word) is also 32-bit aligned. The frame length is in the 1175 * first 16 bits of the status word; the lower 15 bits correspond with 1176 * the 'rx status register' mentioned in the datasheet. 1177 * 1178 * Note: to make the Alpha happy, the frame payload needs to be aligned 1179 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1180 * as the offset argument to m_devget(). 1181 */ 1182static void 1183rl_rxeof(sc) 1184 struct rl_softc *sc; 1185{ 1186 struct mbuf *m; 1187 struct ifnet *ifp; 1188 int total_len = 0; 1189 u_int32_t rxstat; 1190 caddr_t rxbufpos; 1191 int wrap = 0; 1192 u_int16_t cur_rx; 1193 u_int16_t limit; 1194 u_int16_t rx_bytes = 0, max_bytes; 1195 1196 ifp = &sc->arpcom.ac_if; 1197 1198 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1199 BUS_DMASYNC_POSTREAD); 1200 1201 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1202 1203 /* Do not try to read past this point. */ 1204 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1205 1206 if (limit < cur_rx) 1207 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1208 else 1209 max_bytes = limit - cur_rx; 1210 1211 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1212#ifdef DEVICE_POLLING 1213 if (ifp->if_flags & IFF_POLLING) { 1214 if (sc->rxcycles <= 0) 1215 break; 1216 sc->rxcycles--; 1217 } 1218#endif /* DEVICE_POLLING */ 1219 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1220 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1221 1222 /* 1223 * Here's a totally undocumented fact for you. When the 1224 * RealTek chip is in the process of copying a packet into 1225 * RAM for you, the length will be 0xfff0. If you spot a 1226 * packet header with this value, you need to stop. The 1227 * datasheet makes absolutely no mention of this and 1228 * RealTek should be shot for this. 1229 */ 1230 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1231 break; 1232 1233 if (!(rxstat & RL_RXSTAT_RXOK)) { 1234 ifp->if_ierrors++; 1235 rl_init(sc); 1236 return; 1237 } 1238 1239 /* No errors; receive the packet. */ 1240 total_len = rxstat >> 16; 1241 rx_bytes += total_len + 4; 1242 1243 /* 1244 * XXX The RealTek chip includes the CRC with every 1245 * received frame, and there's no way to turn this 1246 * behavior off (at least, I can't find anything in 1247 * the manual that explains how to do it) so we have 1248 * to trim off the CRC manually. 1249 */ 1250 total_len -= ETHER_CRC_LEN; 1251 1252 /* 1253 * Avoid trying to read more bytes than we know 1254 * the chip has prepared for us. 1255 */ 1256 if (rx_bytes > max_bytes) 1257 break; 1258 1259 rxbufpos = sc->rl_cdata.rl_rx_buf + 1260 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1261 1262 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1263 rxbufpos = sc->rl_cdata.rl_rx_buf; 1264 1265 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1266 1267 if (total_len > wrap) { 1268 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1269 NULL); 1270 if (m == NULL) { 1271 ifp->if_ierrors++; 1272 } else { 1273 m_copyback(m, wrap, total_len - wrap, 1274 sc->rl_cdata.rl_rx_buf); 1275 } 1276 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1277 } else { 1278 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1279 NULL); 1280 if (m == NULL) { 1281 ifp->if_ierrors++; 1282 } 1283 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1284 } 1285 1286 /* 1287 * Round up to 32-bit boundary. 1288 */ 1289 cur_rx = (cur_rx + 3) & ~3; 1290 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1291 1292 if (m == NULL) 1293 continue; 1294 1295 ifp->if_ipackets++; 1296 (*ifp->if_input)(ifp, m); 1297 } 1298 1299 return; 1300} 1301 1302/* 1303 * A frame was downloaded to the chip. It's safe for us to clean up 1304 * the list buffers. 1305 */ 1306static void 1307rl_txeof(sc) 1308 struct rl_softc *sc; 1309{ 1310 struct ifnet *ifp; 1311 u_int32_t txstat; 1312 1313 ifp = &sc->arpcom.ac_if; 1314 1315 /* 1316 * Go through our tx list and free mbufs for those 1317 * frames that have been uploaded. 1318 */ 1319 do { 1320 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1321 if (!(txstat & (RL_TXSTAT_TX_OK| 1322 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1323 break; 1324 1325 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1326 1327 if (RL_LAST_TXMBUF(sc) != NULL) { 1328 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1329 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1330 m_freem(RL_LAST_TXMBUF(sc)); 1331 RL_LAST_TXMBUF(sc) = NULL; 1332 } 1333 if (txstat & RL_TXSTAT_TX_OK) 1334 ifp->if_opackets++; 1335 else { 1336 int oldthresh; 1337 ifp->if_oerrors++; 1338 if ((txstat & RL_TXSTAT_TXABRT) || 1339 (txstat & RL_TXSTAT_OUTOFWIN)) 1340 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1341 oldthresh = sc->rl_txthresh; 1342 /* error recovery */ 1343 rl_reset(sc); 1344 rl_init(sc); 1345 /* 1346 * If there was a transmit underrun, 1347 * bump the TX threshold. 1348 */ 1349 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1350 sc->rl_txthresh = oldthresh + 32; 1351 return; 1352 } 1353 RL_INC(sc->rl_cdata.last_tx); 1354 ifp->if_flags &= ~IFF_OACTIVE; 1355 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1356 1357 ifp->if_timer = 1358 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1359 1360 return; 1361} 1362 1363static void 1364rl_tick(xsc) 1365 void *xsc; 1366{ 1367 struct rl_softc *sc; 1368 struct mii_data *mii; 1369 1370 sc = xsc; 1371 RL_LOCK(sc); 1372 mii = device_get_softc(sc->rl_miibus); 1373 1374 mii_tick(mii); 1375 1376 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1377 RL_UNLOCK(sc); 1378 1379 return; 1380} 1381 1382#ifdef DEVICE_POLLING 1383static void 1384rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1385{ 1386 struct rl_softc *sc = ifp->if_softc; 1387 1388 RL_LOCK(sc); 1389 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1390 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1391 goto done; 1392 } 1393 1394 sc->rxcycles = count; 1395 rl_rxeof(sc); 1396 rl_txeof(sc); 1397 if (ifp->if_snd.ifq_head != NULL) 1398 rl_start(ifp); 1399 1400 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1401 u_int16_t status; 1402 1403 status = CSR_READ_2(sc, RL_ISR); 1404 if (status == 0xffff) 1405 goto done; 1406 if (status) 1407 CSR_WRITE_2(sc, RL_ISR, status); 1408 1409 /* 1410 * XXX check behaviour on receiver stalls. 1411 */ 1412 1413 if (status & RL_ISR_SYSTEM_ERR) { 1414 rl_reset(sc); 1415 rl_init(sc); 1416 } 1417 } 1418done: 1419 RL_UNLOCK(sc); 1420} 1421#endif /* DEVICE_POLLING */ 1422 1423static void 1424rl_intr(arg) 1425 void *arg; 1426{ 1427 struct rl_softc *sc; 1428 struct ifnet *ifp; 1429 u_int16_t status; 1430 1431 sc = arg; 1432 1433 if (sc->suspended) { 1434 return; 1435 } 1436 1437 RL_LOCK(sc); 1438 ifp = &sc->arpcom.ac_if; 1439 1440#ifdef DEVICE_POLLING 1441 if (ifp->if_flags & IFF_POLLING) 1442 goto done; 1443 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1444 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1445 rl_poll(ifp, 0, 1); 1446 goto done; 1447 } 1448#endif /* DEVICE_POLLING */ 1449 1450 for (;;) { 1451 1452 status = CSR_READ_2(sc, RL_ISR); 1453 /* If the card has gone away the read returns 0xffff. */ 1454 if (status == 0xffff) 1455 break; 1456 if (status) 1457 CSR_WRITE_2(sc, RL_ISR, status); 1458 1459 if ((status & RL_INTRS) == 0) 1460 break; 1461 1462 if (status & RL_ISR_RX_OK) 1463 rl_rxeof(sc); 1464 1465 if (status & RL_ISR_RX_ERR) 1466 rl_rxeof(sc); 1467 1468 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1469 rl_txeof(sc); 1470 1471 if (status & RL_ISR_SYSTEM_ERR) { 1472 rl_reset(sc); 1473 rl_init(sc); 1474 } 1475 1476 } 1477 1478 if (ifp->if_snd.ifq_head != NULL) 1479 rl_start(ifp); 1480 1481#ifdef DEVICE_POLLING 1482done: 1483#endif 1484 RL_UNLOCK(sc); 1485 1486 return; 1487} 1488 1489/* 1490 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1491 * pointers to the fragment pointers. 1492 */ 1493static int 1494rl_encap(sc, m_head) 1495 struct rl_softc *sc; 1496 struct mbuf *m_head; 1497{ 1498 struct mbuf *m_new = NULL; 1499 1500 /* 1501 * The RealTek is brain damaged and wants longword-aligned 1502 * TX buffers, plus we can only have one fragment buffer 1503 * per packet. We have to copy pretty much all the time. 1504 */ 1505 m_new = m_defrag(m_head, M_DONTWAIT); 1506 1507 if (m_new == NULL) { 1508 m_freem(m_head); 1509 return(1); 1510 } 1511 m_head = m_new; 1512 1513 /* Pad frames to at least 60 bytes. */ 1514 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1515 /* 1516 * Make security concious people happy: zero out the 1517 * bytes in the pad area, since we don't know what 1518 * this mbuf cluster buffer's previous user might 1519 * have left in it. 1520 */ 1521 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1522 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1523 m_head->m_pkthdr.len += 1524 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1525 m_head->m_len = m_head->m_pkthdr.len; 1526 } 1527 1528 RL_CUR_TXMBUF(sc) = m_head; 1529 1530 return(0); 1531} 1532 1533/* 1534 * Main transmit routine. 1535 */ 1536 1537static void 1538rl_start(ifp) 1539 struct ifnet *ifp; 1540{ 1541 struct rl_softc *sc; 1542 struct mbuf *m_head = NULL; 1543 1544 sc = ifp->if_softc; 1545 RL_LOCK(sc); 1546 1547 while(RL_CUR_TXMBUF(sc) == NULL) { 1548 IF_DEQUEUE(&ifp->if_snd, m_head); 1549 if (m_head == NULL) 1550 break; 1551 1552 if (rl_encap(sc, m_head)) { 1553 break; 1554 } 1555 1556 /* 1557 * If there's a BPF listener, bounce a copy of this frame 1558 * to him. 1559 */ 1560 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1561 1562 /* 1563 * Transmit the frame. 1564 */ 1565 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1566 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1567 mtod(RL_CUR_TXMBUF(sc), void *), 1568 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1569 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1570 BUS_DMASYNC_PREREAD); 1571 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1572 RL_TXTHRESH(sc->rl_txthresh) | 1573 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1574 1575 RL_INC(sc->rl_cdata.cur_tx); 1576 1577 /* 1578 * Set a timeout in case the chip goes out to lunch. 1579 */ 1580 ifp->if_timer = 5; 1581 } 1582 1583 /* 1584 * We broke out of the loop because all our TX slots are 1585 * full. Mark the NIC as busy until it drains some of the 1586 * packets from the queue. 1587 */ 1588 if (RL_CUR_TXMBUF(sc) != NULL) 1589 ifp->if_flags |= IFF_OACTIVE; 1590 1591 RL_UNLOCK(sc); 1592 1593 return; 1594} 1595 1596static void 1597rl_init(xsc) 1598 void *xsc; 1599{ 1600 struct rl_softc *sc = xsc; 1601 struct ifnet *ifp = &sc->arpcom.ac_if; 1602 struct mii_data *mii; 1603 u_int32_t rxcfg = 0; 1604 1605 RL_LOCK(sc); 1606 mii = device_get_softc(sc->rl_miibus); 1607 1608 /* 1609 * Cancel pending I/O and free all RX/TX buffers. 1610 */ 1611 rl_stop(sc); 1612 1613 /* 1614 * Init our MAC address. Even though the chipset 1615 * documentation doesn't mention it, we need to enter "Config 1616 * register write enable" mode to modify the ID registers. 1617 */ 1618 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1619 CSR_WRITE_4(sc, RL_IDR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1620 CSR_WRITE_4(sc, RL_IDR4, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1621 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1622 1623 /* Init the RX buffer pointer register. */ 1624 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1625 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1626 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1627 BUS_DMASYNC_PREWRITE); 1628 1629 /* Init TX descriptors. */ 1630 rl_list_tx_init(sc); 1631 1632 /* 1633 * Enable transmit and receive. 1634 */ 1635 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1636 1637 /* 1638 * Set the initial TX and RX configuration. 1639 */ 1640 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1641 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1642 1643 /* Set the individual bit to receive frames for this host only. */ 1644 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1645 rxcfg |= RL_RXCFG_RX_INDIV; 1646 1647 /* If we want promiscuous mode, set the allframes bit. */ 1648 if (ifp->if_flags & IFF_PROMISC) { 1649 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1650 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1651 } else { 1652 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1653 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1654 } 1655 1656 /* 1657 * Set capture broadcast bit to capture broadcast frames. 1658 */ 1659 if (ifp->if_flags & IFF_BROADCAST) { 1660 rxcfg |= RL_RXCFG_RX_BROAD; 1661 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1662 } else { 1663 rxcfg &= ~RL_RXCFG_RX_BROAD; 1664 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1665 } 1666 1667 /* 1668 * Program the multicast filter, if necessary. 1669 */ 1670 rl_setmulti(sc); 1671 1672#ifdef DEVICE_POLLING 1673 /* 1674 * Disable interrupts if we are polling. 1675 */ 1676 if (ifp->if_flags & IFF_POLLING) 1677 CSR_WRITE_2(sc, RL_IMR, 0); 1678 else /* otherwise ... */ 1679#endif /* DEVICE_POLLING */ 1680 /* 1681 * Enable interrupts. 1682 */ 1683 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1684 1685 /* Set initial TX threshold */ 1686 sc->rl_txthresh = RL_TX_THRESH_INIT; 1687 1688 /* Start RX/TX process. */ 1689 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1690 1691 /* Enable receiver and transmitter. */ 1692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1693 1694 mii_mediachg(mii); 1695 1696 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1697 1698 ifp->if_flags |= IFF_RUNNING; 1699 ifp->if_flags &= ~IFF_OACTIVE; 1700 1701 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1702 RL_UNLOCK(sc); 1703 1704 return; 1705} 1706 1707/* 1708 * Set media options. 1709 */ 1710static int 1711rl_ifmedia_upd(ifp) 1712 struct ifnet *ifp; 1713{ 1714 struct rl_softc *sc; 1715 struct mii_data *mii; 1716 1717 sc = ifp->if_softc; 1718 mii = device_get_softc(sc->rl_miibus); 1719 mii_mediachg(mii); 1720 1721 return(0); 1722} 1723 1724/* 1725 * Report current media status. 1726 */ 1727static void 1728rl_ifmedia_sts(ifp, ifmr) 1729 struct ifnet *ifp; 1730 struct ifmediareq *ifmr; 1731{ 1732 struct rl_softc *sc; 1733 struct mii_data *mii; 1734 1735 sc = ifp->if_softc; 1736 mii = device_get_softc(sc->rl_miibus); 1737 1738 mii_pollstat(mii); 1739 ifmr->ifm_active = mii->mii_media_active; 1740 ifmr->ifm_status = mii->mii_media_status; 1741 1742 return; 1743} 1744 1745static int 1746rl_ioctl(ifp, command, data) 1747 struct ifnet *ifp; 1748 u_long command; 1749 caddr_t data; 1750{ 1751 struct rl_softc *sc = ifp->if_softc; 1752 struct ifreq *ifr = (struct ifreq *) data; 1753 struct mii_data *mii; 1754 int error = 0; 1755 1756 RL_LOCK(sc); 1757 1758 switch(command) { 1759 case SIOCSIFFLAGS: 1760 if (ifp->if_flags & IFF_UP) { 1761 rl_init(sc); 1762 } else { 1763 if (ifp->if_flags & IFF_RUNNING) 1764 rl_stop(sc); 1765 } 1766 error = 0; 1767 break; 1768 case SIOCADDMULTI: 1769 case SIOCDELMULTI: 1770 rl_setmulti(sc); 1771 error = 0; 1772 break; 1773 case SIOCGIFMEDIA: 1774 case SIOCSIFMEDIA: 1775 mii = device_get_softc(sc->rl_miibus); 1776 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1777 break; 1778 default: 1779 error = ether_ioctl(ifp, command, data); 1780 break; 1781 } 1782 1783 RL_UNLOCK(sc); 1784 1785 return(error); 1786} 1787 1788static void 1789rl_watchdog(ifp) 1790 struct ifnet *ifp; 1791{ 1792 struct rl_softc *sc; 1793 1794 sc = ifp->if_softc; 1795 RL_LOCK(sc); 1796 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1797 ifp->if_oerrors++; 1798 1799 rl_txeof(sc); 1800 rl_rxeof(sc); 1801 rl_init(sc); 1802 RL_UNLOCK(sc); 1803 1804 return; 1805} 1806 1807/* 1808 * Stop the adapter and free any mbufs allocated to the 1809 * RX and TX lists. 1810 */ 1811static void 1812rl_stop(sc) 1813 struct rl_softc *sc; 1814{ 1815 register int i; 1816 struct ifnet *ifp; 1817 1818 RL_LOCK(sc); 1819 ifp = &sc->arpcom.ac_if; 1820 ifp->if_timer = 0; 1821 1822 untimeout(rl_tick, sc, sc->rl_stat_ch); 1823 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1824#ifdef DEVICE_POLLING 1825 ether_poll_deregister(ifp); 1826#endif /* DEVICE_POLLING */ 1827 1828 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1829 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1830 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1831 1832 /* 1833 * Free the TX list buffers. 1834 */ 1835 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1836 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1837 bus_dmamap_unload(sc->rl_tag, 1838 sc->rl_cdata.rl_tx_dmamap[i]); 1839 bus_dmamap_destroy(sc->rl_tag, 1840 sc->rl_cdata.rl_tx_dmamap[i]); 1841 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1842 sc->rl_cdata.rl_tx_chain[i] = NULL; 1843 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1844 } 1845 } 1846 1847 RL_UNLOCK(sc); 1848 return; 1849} 1850 1851/* 1852 * Device suspend routine. Stop the interface and save some PCI 1853 * settings in case the BIOS doesn't restore them properly on 1854 * resume. 1855 */ 1856static int 1857rl_suspend(dev) 1858 device_t dev; 1859{ 1860 register int i; 1861 struct rl_softc *sc; 1862 1863 sc = device_get_softc(dev); 1864 1865 rl_stop(sc); 1866 1867 for (i = 0; i < 5; i++) 1868 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1869 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1870 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1871 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1872 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1873 1874 sc->suspended = 1; 1875 1876 return (0); 1877} 1878 1879/* 1880 * Device resume routine. Restore some PCI settings in case the BIOS 1881 * doesn't, re-enable busmastering, and restart the interface if 1882 * appropriate. 1883 */ 1884static int 1885rl_resume(dev) 1886 device_t dev; 1887{ 1888 register int i; 1889 struct rl_softc *sc; 1890 struct ifnet *ifp; 1891 1892 sc = device_get_softc(dev); 1893 ifp = &sc->arpcom.ac_if; 1894 1895 /* better way to do this? */ 1896 for (i = 0; i < 5; i++) 1897 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1898 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1899 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1900 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1901 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1902 1903 /* reenable busmastering */ 1904 pci_enable_busmaster(dev); 1905 pci_enable_io(dev, RL_RES); 1906 1907 /* reinitialize interface if necessary */ 1908 if (ifp->if_flags & IFF_UP) 1909 rl_init(sc); 1910 1911 sc->suspended = 0; 1912 1913 return (0); 1914} 1915 1916/* 1917 * Stop all chip I/O so that the kernel's probe routines don't 1918 * get confused by errant DMAs when rebooting. 1919 */ 1920static void 1921rl_shutdown(dev) 1922 device_t dev; 1923{ 1924 struct rl_softc *sc; 1925 1926 sc = device_get_softc(dev); 1927 1928 rl_stop(sc); 1929 1930 return; 1931} 1932