if_rl.c revision 116192
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul */ 3240516Swpaul 3340516Swpaul/* 3440516Swpaul * RealTek 8129/8139 PCI NIC driver 3540516Swpaul * 3640516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3740516Swpaul * the RealTek chipset. Datasheets can be obtained from 3840516Swpaul * www.realtek.com.tw. 3940516Swpaul * 4040516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4140516Swpaul * Electrical Engineering Department 4240516Swpaul * Columbia University, New York City 4340516Swpaul */ 4440516Swpaul 4540516Swpaul/* 4640516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4740516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 4840516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 4940516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5040516Swpaul * gains that bus-master DMA usually offers. 5140516Swpaul * 5240516Swpaul * For transmission, the chip offers a series of four TX descriptor 5340516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5441569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5540516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5640516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5740516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 5840516Swpaul * four descriptor registers means that we can never have more than four 5940516Swpaul * packets queued for transmission at any one time. 6040516Swpaul * 6140516Swpaul * Reception is not much better. The driver has to allocate a single large 6240516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6340516Swpaul * frames. Because we don't know where within this region received packets 6440516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6540516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6640516Swpaul * levels. 6740516Swpaul * 6840516Swpaul * It's impossible given this rotten design to really achieve decent 6940516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7040516Swpaul * some equally overmuscled CPU to drive it. 7140516Swpaul * 7240516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7340516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7440516Swpaul * PHY registers are directly accessible through the 8139's register 7540516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7640516Swpaul * filter. 7740516Swpaul * 7840516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 7940516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8040516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8140516Swpaul * to select which interface to use depending on the chip type. 8240516Swpaul */ 8340516Swpaul 84116192Sobrien#include <sys/cdefs.h> 85116192Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 116192 2003-06-11 06:34:30Z obrien $"); 86116192Sobrien 8740516Swpaul#include <sys/param.h> 88108729Sjake#include <sys/endian.h> 8940516Swpaul#include <sys/systm.h> 9040516Swpaul#include <sys/sockio.h> 9140516Swpaul#include <sys/mbuf.h> 9240516Swpaul#include <sys/malloc.h> 9340516Swpaul#include <sys/kernel.h> 9440516Swpaul#include <sys/socket.h> 9540516Swpaul 9640516Swpaul#include <net/if.h> 9740516Swpaul#include <net/if_arp.h> 9840516Swpaul#include <net/ethernet.h> 9940516Swpaul#include <net/if_dl.h> 10040516Swpaul#include <net/if_media.h> 10140516Swpaul 10240516Swpaul#include <net/bpf.h> 10340516Swpaul 10441569Swpaul#include <machine/bus_pio.h> 10541569Swpaul#include <machine/bus_memio.h> 10641569Swpaul#include <machine/bus.h> 10750703Swpaul#include <machine/resource.h> 10850703Swpaul#include <sys/bus.h> 10950703Swpaul#include <sys/rman.h> 11040516Swpaul 11150703Swpaul#include <dev/mii/mii.h> 11250703Swpaul#include <dev/mii/miivar.h> 11350703Swpaul 11440516Swpaul#include <pci/pcireg.h> 11540516Swpaul#include <pci/pcivar.h> 11640516Swpaul 117113506SmdoddMODULE_DEPEND(rl, pci, 1, 1, 1); 118113506SmdoddMODULE_DEPEND(rl, ether, 1, 1, 1); 11959758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 12059758Speter 12151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12250703Swpaul#include "miibus_if.h" 12350703Swpaul 12440516Swpaul/* 12540516Swpaul * Default to using PIO access for this driver. On SMP systems, 12640516Swpaul * there appear to be problems with memory mapped mode: it looks like 12740516Swpaul * doing too many memory mapped access back to back in rapid succession 12840516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12940516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 13040516Swpaul * uniprocessor systems though. 13140516Swpaul */ 13240516Swpaul#define RL_USEIOSPACE 13340516Swpaul 13440516Swpaul#include <pci/if_rlreg.h> 13540516Swpaul 136109109Sdes__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 116192 2003-06-11 06:34:30Z obrien $"); 13740516Swpaul 13840516Swpaul/* 13940516Swpaul * Various supported device vendors/types and their names. 14040516Swpaul */ 14140516Swpaulstatic struct rl_type rl_devs[] = { 14240516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14340516Swpaul "RealTek 8129 10/100BaseTX" }, 14440516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14540516Swpaul "RealTek 8139 10/100BaseTX" }, 14667771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14767771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14841243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14941243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 15044238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15144238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15244238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15344238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15472813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15572813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15696112Sjhb { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 15796112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 15894400Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 15994400Swpaul "Nortel Networks 10/100BaseTX" }, 160109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 161103020Siwasaki "Corega FEther CB-TXD" }, 162109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 163109095Ssanpei "Corega FEtherII CB-TXD" }, 164111381Sdan { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 165111381Sdan "Peppercon AG ROL-F" }, 166112379Ssanpei { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 167112379Ssanpei "Planex FNW-3800-TX" }, 16840516Swpaul { 0, 0, NULL } 16940516Swpaul}; 17040516Swpaul 17192739Salfredstatic int rl_probe (device_t); 17292739Salfredstatic int rl_attach (device_t); 17392739Salfredstatic int rl_detach (device_t); 17440516Swpaul 17592739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 17640516Swpaul 17792739Salfredstatic void rl_rxeof (struct rl_softc *); 17892739Salfredstatic void rl_txeof (struct rl_softc *); 17992739Salfredstatic void rl_intr (void *); 18092739Salfredstatic void rl_tick (void *); 18192739Salfredstatic void rl_start (struct ifnet *); 18292739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 18392739Salfredstatic void rl_init (void *); 18492739Salfredstatic void rl_stop (struct rl_softc *); 18592739Salfredstatic void rl_watchdog (struct ifnet *); 18692739Salfredstatic int rl_suspend (device_t); 18792739Salfredstatic int rl_resume (device_t); 18892739Salfredstatic void rl_shutdown (device_t); 18992739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 19092739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 19140516Swpaul 19292739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 19392739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 19492739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 19592739Salfredstatic void rl_mii_sync (struct rl_softc *); 19692739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 19792739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 19892739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 19940516Swpaul 20092739Salfredstatic int rl_miibus_readreg (device_t, int, int); 20192739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 20292739Salfredstatic void rl_miibus_statchg (device_t); 20340516Swpaul 20492739Salfredstatic u_int8_t rl_calchash (caddr_t); 20592739Salfredstatic void rl_setmulti (struct rl_softc *); 20692739Salfredstatic void rl_reset (struct rl_softc *); 20792739Salfredstatic int rl_list_tx_init (struct rl_softc *); 20840516Swpaul 20992739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 21092739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 21181713Swpaul 21250703Swpaul#ifdef RL_USEIOSPACE 21350703Swpaul#define RL_RES SYS_RES_IOPORT 21450703Swpaul#define RL_RID RL_PCI_LOIO 21550703Swpaul#else 21650703Swpaul#define RL_RES SYS_RES_MEMORY 21750703Swpaul#define RL_RID RL_PCI_LOMEM 21850703Swpaul#endif 21950703Swpaul 22050703Swpaulstatic device_method_t rl_methods[] = { 22150703Swpaul /* Device interface */ 22250703Swpaul DEVMETHOD(device_probe, rl_probe), 22350703Swpaul DEVMETHOD(device_attach, rl_attach), 22450703Swpaul DEVMETHOD(device_detach, rl_detach), 22586822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 22686822Siwasaki DEVMETHOD(device_resume, rl_resume), 22750703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 22850703Swpaul 22950703Swpaul /* bus interface */ 23050703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 23150703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 23250703Swpaul 23350703Swpaul /* MII interface */ 23450703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 23550703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 23650703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 23750703Swpaul 23850703Swpaul { 0, 0 } 23950703Swpaul}; 24050703Swpaul 24150703Swpaulstatic driver_t rl_driver = { 24251455Swpaul "rl", 24350703Swpaul rl_methods, 24450703Swpaul sizeof(struct rl_softc) 24550703Swpaul}; 24650703Swpaul 24750703Swpaulstatic devclass_t rl_devclass; 24850703Swpaul 249113506SmdoddDRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 250113506SmdoddDRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 25151473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 25250703Swpaul 25340516Swpaul#define EE_SET(x) \ 25440516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25540516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 25640516Swpaul 25740516Swpaul#define EE_CLR(x) \ 25840516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25940516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 26040516Swpaul 26181713Swpaulstatic void 26281713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 26381713Swpaul void *arg; 26481713Swpaul bus_dma_segment_t *segs; 26581713Swpaul int nseg, error; 26681713Swpaul{ 26781713Swpaul struct rl_softc *sc; 26881713Swpaul 26981713Swpaul sc = arg; 27081713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 27181713Swpaul 27281713Swpaul return; 27381713Swpaul} 27481713Swpaul 27581713Swpaulstatic void 27681713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 27781713Swpaul void *arg; 27881713Swpaul bus_dma_segment_t *segs; 27981713Swpaul int nseg, error; 28081713Swpaul{ 28181713Swpaul struct rl_softc *sc; 28281713Swpaul 28381713Swpaul sc = arg; 28481713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 28581713Swpaul 28681713Swpaul return; 28781713Swpaul} 28881713Swpaul 28940516Swpaul/* 29040516Swpaul * Send a read command and address to the EEPROM, check for ACK. 29140516Swpaul */ 292102335Salfredstatic void 293102335Salfredrl_eeprom_putbyte(sc, addr) 29440516Swpaul struct rl_softc *sc; 29541656Swpaul int addr; 29640516Swpaul{ 29740516Swpaul register int d, i; 29840516Swpaul 29967931Swpaul d = addr | sc->rl_eecmd_read; 30040516Swpaul 30140516Swpaul /* 30255170Sbillf * Feed in each bit and strobe the clock. 30340516Swpaul */ 30440516Swpaul for (i = 0x400; i; i >>= 1) { 30540516Swpaul if (d & i) { 30640516Swpaul EE_SET(RL_EE_DATAIN); 30740516Swpaul } else { 30840516Swpaul EE_CLR(RL_EE_DATAIN); 30940516Swpaul } 31040516Swpaul DELAY(100); 31140516Swpaul EE_SET(RL_EE_CLK); 31240516Swpaul DELAY(150); 31340516Swpaul EE_CLR(RL_EE_CLK); 31440516Swpaul DELAY(100); 31540516Swpaul } 31640516Swpaul 31740516Swpaul return; 31840516Swpaul} 31940516Swpaul 32040516Swpaul/* 32140516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 32240516Swpaul */ 323102335Salfredstatic void 324102335Salfredrl_eeprom_getword(sc, addr, dest) 32540516Swpaul struct rl_softc *sc; 32641656Swpaul int addr; 32740516Swpaul u_int16_t *dest; 32840516Swpaul{ 32940516Swpaul register int i; 33040516Swpaul u_int16_t word = 0; 33140516Swpaul 33240516Swpaul /* Enter EEPROM access mode. */ 33340516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33440516Swpaul 33540516Swpaul /* 33640516Swpaul * Send address of word we want to read. 33740516Swpaul */ 33840516Swpaul rl_eeprom_putbyte(sc, addr); 33940516Swpaul 34040516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 34140516Swpaul 34240516Swpaul /* 34340516Swpaul * Start reading bits from EEPROM. 34440516Swpaul */ 34540516Swpaul for (i = 0x8000; i; i >>= 1) { 34640516Swpaul EE_SET(RL_EE_CLK); 34740516Swpaul DELAY(100); 34840516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 34940516Swpaul word |= i; 35040516Swpaul EE_CLR(RL_EE_CLK); 35140516Swpaul DELAY(100); 35240516Swpaul } 35340516Swpaul 35440516Swpaul /* Turn off EEPROM access mode. */ 35540516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 35640516Swpaul 35740516Swpaul *dest = word; 35840516Swpaul 35940516Swpaul return; 36040516Swpaul} 36140516Swpaul 36240516Swpaul/* 36340516Swpaul * Read a sequence of words from the EEPROM. 36440516Swpaul */ 365102335Salfredstatic void 366102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 36740516Swpaul struct rl_softc *sc; 36840516Swpaul caddr_t dest; 36940516Swpaul int off; 37040516Swpaul int cnt; 37140516Swpaul int swap; 37240516Swpaul{ 37340516Swpaul int i; 37440516Swpaul u_int16_t word = 0, *ptr; 37540516Swpaul 37640516Swpaul for (i = 0; i < cnt; i++) { 37740516Swpaul rl_eeprom_getword(sc, off + i, &word); 37840516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 37940516Swpaul if (swap) 38040516Swpaul *ptr = ntohs(word); 38140516Swpaul else 38240516Swpaul *ptr = word; 38340516Swpaul } 38440516Swpaul 38540516Swpaul return; 38640516Swpaul} 38740516Swpaul 38840516Swpaul 38940516Swpaul/* 39040516Swpaul * MII access routines are provided for the 8129, which 39140516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 39240516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 39340516Swpaul * direct access PHY registers. 39440516Swpaul */ 39540516Swpaul#define MII_SET(x) \ 39640516Swpaul CSR_WRITE_1(sc, RL_MII, \ 397105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 39840516Swpaul 39940516Swpaul#define MII_CLR(x) \ 40040516Swpaul CSR_WRITE_1(sc, RL_MII, \ 401105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 40240516Swpaul 40340516Swpaul/* 40440516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 40540516Swpaul */ 406102335Salfredstatic void 407102335Salfredrl_mii_sync(sc) 40840516Swpaul struct rl_softc *sc; 40940516Swpaul{ 41040516Swpaul register int i; 41140516Swpaul 41240516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 41340516Swpaul 41440516Swpaul for (i = 0; i < 32; i++) { 41540516Swpaul MII_SET(RL_MII_CLK); 41640516Swpaul DELAY(1); 41740516Swpaul MII_CLR(RL_MII_CLK); 41840516Swpaul DELAY(1); 41940516Swpaul } 42040516Swpaul 42140516Swpaul return; 42240516Swpaul} 42340516Swpaul 42440516Swpaul/* 42540516Swpaul * Clock a series of bits through the MII. 42640516Swpaul */ 427102335Salfredstatic void 428102335Salfredrl_mii_send(sc, bits, cnt) 42940516Swpaul struct rl_softc *sc; 43040516Swpaul u_int32_t bits; 43140516Swpaul int cnt; 43240516Swpaul{ 43340516Swpaul int i; 43440516Swpaul 43540516Swpaul MII_CLR(RL_MII_CLK); 43640516Swpaul 43740516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 438109109Sdes if (bits & i) { 43940516Swpaul MII_SET(RL_MII_DATAOUT); 440109109Sdes } else { 44140516Swpaul MII_CLR(RL_MII_DATAOUT); 442109109Sdes } 44340516Swpaul DELAY(1); 44440516Swpaul MII_CLR(RL_MII_CLK); 44540516Swpaul DELAY(1); 44640516Swpaul MII_SET(RL_MII_CLK); 44740516Swpaul } 44840516Swpaul} 44940516Swpaul 45040516Swpaul/* 45140516Swpaul * Read an PHY register through the MII. 45240516Swpaul */ 453102335Salfredstatic int 454102335Salfredrl_mii_readreg(sc, frame) 45540516Swpaul struct rl_softc *sc; 45640516Swpaul struct rl_mii_frame *frame; 457109109Sdes 45840516Swpaul{ 45967087Swpaul int i, ack; 46040516Swpaul 46167087Swpaul RL_LOCK(sc); 46240516Swpaul 46340516Swpaul /* 46440516Swpaul * Set up frame for RX. 46540516Swpaul */ 46640516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 46740516Swpaul frame->mii_opcode = RL_MII_READOP; 46840516Swpaul frame->mii_turnaround = 0; 46940516Swpaul frame->mii_data = 0; 470109109Sdes 47140516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 47240516Swpaul 47340516Swpaul /* 474109109Sdes * Turn on data xmit. 47540516Swpaul */ 47640516Swpaul MII_SET(RL_MII_DIR); 47740516Swpaul 47840516Swpaul rl_mii_sync(sc); 47940516Swpaul 48040516Swpaul /* 48140516Swpaul * Send command/address info. 48240516Swpaul */ 48340516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 48440516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 48540516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 48640516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 48740516Swpaul 48840516Swpaul /* Idle bit */ 48940516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 49040516Swpaul DELAY(1); 49140516Swpaul MII_SET(RL_MII_CLK); 49240516Swpaul DELAY(1); 49340516Swpaul 49440516Swpaul /* Turn off xmit. */ 49540516Swpaul MII_CLR(RL_MII_DIR); 49640516Swpaul 49740516Swpaul /* Check for ack */ 49840516Swpaul MII_CLR(RL_MII_CLK); 49940516Swpaul DELAY(1); 500109058Smbr ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 50140516Swpaul MII_SET(RL_MII_CLK); 50240516Swpaul DELAY(1); 50340516Swpaul 50440516Swpaul /* 50540516Swpaul * Now try reading data bits. If the ack failed, we still 50640516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 50740516Swpaul */ 50840516Swpaul if (ack) { 50940516Swpaul for(i = 0; i < 16; i++) { 51040516Swpaul MII_CLR(RL_MII_CLK); 51140516Swpaul DELAY(1); 51240516Swpaul MII_SET(RL_MII_CLK); 51340516Swpaul DELAY(1); 51440516Swpaul } 51540516Swpaul goto fail; 51640516Swpaul } 51740516Swpaul 51840516Swpaul for (i = 0x8000; i; i >>= 1) { 51940516Swpaul MII_CLR(RL_MII_CLK); 52040516Swpaul DELAY(1); 52140516Swpaul if (!ack) { 52240516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 52340516Swpaul frame->mii_data |= i; 52440516Swpaul DELAY(1); 52540516Swpaul } 52640516Swpaul MII_SET(RL_MII_CLK); 52740516Swpaul DELAY(1); 52840516Swpaul } 52940516Swpaul 53040516Swpaulfail: 53140516Swpaul 53240516Swpaul MII_CLR(RL_MII_CLK); 53340516Swpaul DELAY(1); 53440516Swpaul MII_SET(RL_MII_CLK); 53540516Swpaul DELAY(1); 53640516Swpaul 53767087Swpaul RL_UNLOCK(sc); 53840516Swpaul 53940516Swpaul if (ack) 54040516Swpaul return(1); 54140516Swpaul return(0); 54240516Swpaul} 54340516Swpaul 54440516Swpaul/* 54540516Swpaul * Write to a PHY register through the MII. 54640516Swpaul */ 547102335Salfredstatic int 548102335Salfredrl_mii_writereg(sc, frame) 54940516Swpaul struct rl_softc *sc; 55040516Swpaul struct rl_mii_frame *frame; 551109109Sdes 55240516Swpaul{ 55367087Swpaul RL_LOCK(sc); 55440516Swpaul 55540516Swpaul /* 55640516Swpaul * Set up frame for TX. 55740516Swpaul */ 55840516Swpaul 55940516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 56040516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 56140516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 562109109Sdes 56340516Swpaul /* 564109109Sdes * Turn on data output. 56540516Swpaul */ 56640516Swpaul MII_SET(RL_MII_DIR); 56740516Swpaul 56840516Swpaul rl_mii_sync(sc); 56940516Swpaul 57040516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 57140516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 57240516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 57340516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 57440516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 57540516Swpaul rl_mii_send(sc, frame->mii_data, 16); 57640516Swpaul 57740516Swpaul /* Idle bit. */ 57840516Swpaul MII_SET(RL_MII_CLK); 57940516Swpaul DELAY(1); 58040516Swpaul MII_CLR(RL_MII_CLK); 58140516Swpaul DELAY(1); 58240516Swpaul 58340516Swpaul /* 58440516Swpaul * Turn off xmit. 58540516Swpaul */ 58640516Swpaul MII_CLR(RL_MII_DIR); 58740516Swpaul 58867087Swpaul RL_UNLOCK(sc); 58940516Swpaul 59040516Swpaul return(0); 59140516Swpaul} 59240516Swpaul 593102335Salfredstatic int 594102335Salfredrl_miibus_readreg(dev, phy, reg) 59550703Swpaul device_t dev; 59650703Swpaul int phy, reg; 59750703Swpaul{ 59840516Swpaul struct rl_softc *sc; 59940516Swpaul struct rl_mii_frame frame; 60040516Swpaul u_int16_t rval = 0; 60140516Swpaul u_int16_t rl8139_reg = 0; 60240516Swpaul 60350703Swpaul sc = device_get_softc(dev); 60467087Swpaul RL_LOCK(sc); 60550703Swpaul 60640516Swpaul if (sc->rl_type == RL_8139) { 60750703Swpaul /* Pretend the internal PHY is only at address 0 */ 60867087Swpaul if (phy) { 60967087Swpaul RL_UNLOCK(sc); 61050703Swpaul return(0); 61167087Swpaul } 61240516Swpaul switch(reg) { 61350703Swpaul case MII_BMCR: 61440516Swpaul rl8139_reg = RL_BMCR; 61540516Swpaul break; 61650703Swpaul case MII_BMSR: 61740516Swpaul rl8139_reg = RL_BMSR; 61840516Swpaul break; 61950703Swpaul case MII_ANAR: 62040516Swpaul rl8139_reg = RL_ANAR; 62140516Swpaul break; 62250703Swpaul case MII_ANER: 62350703Swpaul rl8139_reg = RL_ANER; 62450703Swpaul break; 62550703Swpaul case MII_ANLPAR: 62640516Swpaul rl8139_reg = RL_LPAR; 62740516Swpaul break; 62850703Swpaul case MII_PHYIDR1: 62950703Swpaul case MII_PHYIDR2: 63067087Swpaul RL_UNLOCK(sc); 63150703Swpaul return(0); 63294149Swpaul /* 63394149Swpaul * Allow the rlphy driver to read the media status 63494149Swpaul * register. If we have a link partner which does not 63594149Swpaul * support NWAY, this is the register which will tell 63694149Swpaul * us the results of parallel detection. 63794149Swpaul */ 63894149Swpaul case RL_MEDIASTAT: 63994149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 64094149Swpaul RL_UNLOCK(sc); 64194149Swpaul return(rval); 64240516Swpaul default: 64340516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 64467087Swpaul RL_UNLOCK(sc); 64540516Swpaul return(0); 64640516Swpaul } 64740516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 64867087Swpaul RL_UNLOCK(sc); 64940516Swpaul return(rval); 65040516Swpaul } 65140516Swpaul 65240516Swpaul bzero((char *)&frame, sizeof(frame)); 65340516Swpaul 65450703Swpaul frame.mii_phyaddr = phy; 65540516Swpaul frame.mii_regaddr = reg; 65640516Swpaul rl_mii_readreg(sc, &frame); 65767087Swpaul RL_UNLOCK(sc); 65840516Swpaul 65940516Swpaul return(frame.mii_data); 66040516Swpaul} 66140516Swpaul 662102335Salfredstatic int 663102335Salfredrl_miibus_writereg(dev, phy, reg, data) 66450703Swpaul device_t dev; 66550703Swpaul int phy, reg, data; 66650703Swpaul{ 66740516Swpaul struct rl_softc *sc; 66840516Swpaul struct rl_mii_frame frame; 66940516Swpaul u_int16_t rl8139_reg = 0; 67040516Swpaul 67150703Swpaul sc = device_get_softc(dev); 67267087Swpaul RL_LOCK(sc); 67350703Swpaul 67440516Swpaul if (sc->rl_type == RL_8139) { 67550703Swpaul /* Pretend the internal PHY is only at address 0 */ 67667087Swpaul if (phy) { 67767087Swpaul RL_UNLOCK(sc); 67850703Swpaul return(0); 67967087Swpaul } 68040516Swpaul switch(reg) { 68150703Swpaul case MII_BMCR: 68240516Swpaul rl8139_reg = RL_BMCR; 68340516Swpaul break; 68450703Swpaul case MII_BMSR: 68540516Swpaul rl8139_reg = RL_BMSR; 68640516Swpaul break; 68750703Swpaul case MII_ANAR: 68840516Swpaul rl8139_reg = RL_ANAR; 68940516Swpaul break; 69050703Swpaul case MII_ANER: 69150703Swpaul rl8139_reg = RL_ANER; 69250703Swpaul break; 69350703Swpaul case MII_ANLPAR: 69440516Swpaul rl8139_reg = RL_LPAR; 69540516Swpaul break; 69650703Swpaul case MII_PHYIDR1: 69750703Swpaul case MII_PHYIDR2: 69867087Swpaul RL_UNLOCK(sc); 69950703Swpaul return(0); 70050703Swpaul break; 70140516Swpaul default: 70240516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 70367087Swpaul RL_UNLOCK(sc); 70450703Swpaul return(0); 70540516Swpaul } 70640516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 70767087Swpaul RL_UNLOCK(sc); 70850703Swpaul return(0); 70940516Swpaul } 71040516Swpaul 71140516Swpaul bzero((char *)&frame, sizeof(frame)); 71240516Swpaul 71350703Swpaul frame.mii_phyaddr = phy; 71440516Swpaul frame.mii_regaddr = reg; 71540516Swpaul frame.mii_data = data; 71640516Swpaul 71740516Swpaul rl_mii_writereg(sc, &frame); 71840516Swpaul 71967087Swpaul RL_UNLOCK(sc); 72050703Swpaul return(0); 72150703Swpaul} 72250703Swpaul 723102335Salfredstatic void 724102335Salfredrl_miibus_statchg(dev) 72550703Swpaul device_t dev; 72650703Swpaul{ 72740516Swpaul return; 72840516Swpaul} 72940516Swpaul 73040516Swpaul/* 73143062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 73240516Swpaul */ 733102335Salfredstatic u_int8_t 734102335Salfredrl_calchash(addr) 73541656Swpaul caddr_t addr; 73640516Swpaul{ 73740516Swpaul u_int32_t crc, carry; 73840516Swpaul int i, j; 73940516Swpaul u_int8_t c; 74040516Swpaul 74140516Swpaul /* Compute CRC for the address value. */ 74240516Swpaul crc = 0xFFFFFFFF; /* initial value */ 74340516Swpaul 74440516Swpaul for (i = 0; i < 6; i++) { 74540516Swpaul c = *(addr + i); 74640516Swpaul for (j = 0; j < 8; j++) { 74740516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 74840516Swpaul crc <<= 1; 74940516Swpaul c >>= 1; 75040516Swpaul if (carry) 75140516Swpaul crc = (crc ^ 0x04c11db6) | carry; 75240516Swpaul } 75340516Swpaul } 75440516Swpaul 75540516Swpaul /* return the filter bit position */ 75643062Swpaul return(crc >> 26); 75740516Swpaul} 75840516Swpaul 75940516Swpaul/* 76040516Swpaul * Program the 64-bit multicast hash filter. 76140516Swpaul */ 762102335Salfredstatic void 763102335Salfredrl_setmulti(sc) 76440516Swpaul struct rl_softc *sc; 76540516Swpaul{ 76640516Swpaul struct ifnet *ifp; 76740516Swpaul int h = 0; 76840516Swpaul u_int32_t hashes[2] = { 0, 0 }; 76940516Swpaul struct ifmultiaddr *ifma; 77040516Swpaul u_int32_t rxfilt; 77140516Swpaul int mcnt = 0; 77240516Swpaul 77340516Swpaul ifp = &sc->arpcom.ac_if; 77440516Swpaul 77540516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 77640516Swpaul 77743062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 77840516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 77940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 78040516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 78140516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 78240516Swpaul return; 78340516Swpaul } 78440516Swpaul 78540516Swpaul /* first, zot all the existing hash bits */ 78640516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 78740516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 78840516Swpaul 78940516Swpaul /* now program new ones */ 79072084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 79140516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 79240516Swpaul continue; 79340516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 79440516Swpaul if (h < 32) 79540516Swpaul hashes[0] |= (1 << h); 79640516Swpaul else 79740516Swpaul hashes[1] |= (1 << (h - 32)); 79840516Swpaul mcnt++; 79940516Swpaul } 80040516Swpaul 80140516Swpaul if (mcnt) 80240516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 80340516Swpaul else 80440516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 80540516Swpaul 80640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 80740516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 80840516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 80940516Swpaul 81040516Swpaul return; 81140516Swpaul} 81240516Swpaul 813102335Salfredstatic void 814102335Salfredrl_reset(sc) 81540516Swpaul struct rl_softc *sc; 81640516Swpaul{ 81740516Swpaul register int i; 81840516Swpaul 81940516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 82040516Swpaul 82140516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 82240516Swpaul DELAY(10); 82340516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 82440516Swpaul break; 82540516Swpaul } 82640516Swpaul if (i == RL_TIMEOUT) 82740516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 82840516Swpaul 829109109Sdes return; 83040516Swpaul} 83140516Swpaul 83240516Swpaul/* 83340516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 83440516Swpaul * IDs against our list and return a device name if we find a match. 83540516Swpaul */ 836102335Salfredstatic int 837102335Salfredrl_probe(dev) 83850703Swpaul device_t dev; 83940516Swpaul{ 84040516Swpaul struct rl_type *t; 84140516Swpaul 84240516Swpaul t = rl_devs; 84340516Swpaul 84440516Swpaul while(t->rl_name != NULL) { 84550703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 84650703Swpaul (pci_get_device(dev) == t->rl_did)) { 84750703Swpaul device_set_desc(dev, t->rl_name); 84850703Swpaul return(0); 84940516Swpaul } 85040516Swpaul t++; 85140516Swpaul } 85240516Swpaul 85350703Swpaul return(ENXIO); 85440516Swpaul} 85540516Swpaul 85640516Swpaul/* 85740516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 85840516Swpaul * setup and ethernet/BPF attach. 85940516Swpaul */ 860102335Salfredstatic int 861102335Salfredrl_attach(dev) 86250703Swpaul device_t dev; 86340516Swpaul{ 86440516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 865108729Sjake u_int16_t as[3]; 86640516Swpaul struct rl_softc *sc; 86740516Swpaul struct ifnet *ifp; 86840516Swpaul u_int16_t rl_did = 0; 869108729Sjake int unit, error = 0, rid, i; 87040516Swpaul 87150703Swpaul sc = device_get_softc(dev); 87250703Swpaul unit = device_get_unit(dev); 87340516Swpaul 87493818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 87593818Sjhb MTX_DEF | MTX_RECURSE); 87669583Swpaul 87740516Swpaul /* 87840516Swpaul * Handle power management nonsense. 87940516Swpaul */ 88040516Swpaul 88170167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 88270167Swpaul u_int32_t iobase, membase, irq; 88340516Swpaul 88470167Swpaul /* Save important PCI config data. */ 88570167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 88670167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 88770167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 88840516Swpaul 88970167Swpaul /* Reset the power state. */ 89070167Swpaul printf("rl%d: chip is is in D%d power mode " 89170167Swpaul "-- setting to D0\n", unit, 89270167Swpaul pci_get_powerstate(dev)); 89340516Swpaul 89470167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 89540516Swpaul 89670167Swpaul /* Restore PCI config data. */ 89770167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 89870167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 89970167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 90040516Swpaul } 90140516Swpaul 90240516Swpaul /* 90340516Swpaul * Map control/status registers. 90440516Swpaul */ 90572813Swpaul pci_enable_busmaster(dev); 90640516Swpaul 907109109Sdes rid = RL_RID; 90850703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 90950703Swpaul 0, ~0, 1, RF_ACTIVE); 91050703Swpaul 91150703Swpaul if (sc->rl_res == NULL) { 91250703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 91350703Swpaul error = ENXIO; 91440516Swpaul goto fail; 91540516Swpaul } 91640516Swpaul 91769127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 91869127Sroger * unstable when left to autoselect the media 91969127Sroger * The best workaround is to set the device to the required 92069127Sroger * media type or to set it to the 10 Meg speed. 92169127Sroger */ 92269127Sroger 92369127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 92469127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 92569127Sroger } 92669127Sroger 92750703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 92850703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 92950703Swpaul 930112872Snjl /* Allocate interrupt */ 93150703Swpaul rid = 0; 93250703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 93350703Swpaul RF_SHAREABLE | RF_ACTIVE); 93450703Swpaul 93550703Swpaul if (sc->rl_irq == NULL) { 93640516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 93750703Swpaul error = ENXIO; 93840516Swpaul goto fail; 93940516Swpaul } 94040516Swpaul 94140516Swpaul /* Reset the adapter. */ 94240516Swpaul rl_reset(sc); 94367931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 94467931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 94568215Swpaul if (rl_did != 0x8129) 94667931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 94740516Swpaul 94840516Swpaul /* 94940516Swpaul * Get station address from the EEPROM. 95040516Swpaul */ 951108729Sjake rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 952108729Sjake for (i = 0; i < 3; i++) { 953108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 954108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 955108729Sjake } 95640516Swpaul 95740516Swpaul /* 95840516Swpaul * A RealTek chip was detected. Inform the world. 95940516Swpaul */ 96040516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 96140516Swpaul 96240516Swpaul sc->rl_unit = unit; 96340516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 96440516Swpaul 96540516Swpaul /* 96640516Swpaul * Now read the exact device type from the EEPROM to find 96740516Swpaul * out if it's an 8129 or 8139. 96840516Swpaul */ 96940516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 97040516Swpaul 97144238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 97267771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 97396112Sjhb rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 974109108Sdes rl_did == DLINK_DEVICEID_690TXD || 975109108Sdes rl_did == COREGA_DEVICEID_FETHERCBTXD || 976112379Ssanpei rl_did == COREGA_DEVICEID_FETHERIICBTXD || 977112379Ssanpei rl_did == PLANEX_DEVICEID_FNW3800TX) 97840516Swpaul sc->rl_type = RL_8139; 97940516Swpaul else if (rl_did == RT_DEVICEID_8129) 98040516Swpaul sc->rl_type = RL_8129; 98140516Swpaul else { 98240516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 98350703Swpaul error = ENXIO; 98440516Swpaul goto fail; 98540516Swpaul } 98640516Swpaul 98781713Swpaul /* 98881713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 98981713Swpaul */ 99081713Swpaul#define RL_NSEG_NEW 32 991109109Sdes error = bus_dma_tag_create(NULL, /* parent */ 99281713Swpaul 1, 0, /* alignment, boundary */ 99381713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 99481713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 99581713Swpaul NULL, NULL, /* filter, filterarg */ 99681713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 997109109Sdes BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 99881713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 99981713Swpaul &sc->rl_parent_tag); 1000112872Snjl if (error) 1001112872Snjl goto fail; 100240516Swpaul 100381713Swpaul /* 100481713Swpaul * Now allocate a tag for the DMA descriptor lists. 100581713Swpaul * All of our lists are allocated as a contiguous block 100681713Swpaul * of memory. 100781713Swpaul */ 100881713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 100981713Swpaul 1, 0, /* alignment, boundary */ 101081713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 101181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 101281713Swpaul NULL, NULL, /* filter, filterarg */ 101381713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 101481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 101581713Swpaul 0, /* flags */ 101681713Swpaul &sc->rl_tag); 1017112872Snjl if (error) 1018112872Snjl goto fail; 101981713Swpaul 102081713Swpaul /* 102181713Swpaul * Now allocate a chunk of DMA-able memory based on the 102281713Swpaul * tag we just created. 102381713Swpaul */ 102481713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 102581713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 102681713Swpaul &sc->rl_cdata.rl_rx_dmamap); 102781713Swpaul 1028112872Snjl if (error) { 102940516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 103081713Swpaul bus_dma_tag_destroy(sc->rl_tag); 1031112872Snjl sc->rl_tag = NULL; 103240516Swpaul goto fail; 103340516Swpaul } 103440516Swpaul 103548028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 103648028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 103748028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 103848028Swpaul 103950703Swpaul /* Do MII setup */ 104050703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 104150703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 104250703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 104350703Swpaul error = ENXIO; 104450703Swpaul goto fail; 104550703Swpaul } 104650703Swpaul 104740516Swpaul ifp = &sc->arpcom.ac_if; 104840516Swpaul ifp->if_softc = sc; 104940516Swpaul ifp->if_unit = unit; 105040516Swpaul ifp->if_name = "rl"; 105140516Swpaul ifp->if_mtu = ETHERMTU; 105240516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 105340516Swpaul ifp->if_ioctl = rl_ioctl; 105440516Swpaul ifp->if_output = ether_output; 105540516Swpaul ifp->if_start = rl_start; 105640516Swpaul ifp->if_watchdog = rl_watchdog; 105740516Swpaul ifp->if_init = rl_init; 105840516Swpaul ifp->if_baudrate = 10000000; 105945633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 106040516Swpaul 1061112872Snjl callout_handle_init(&sc->rl_stat_ch); 1062112872Snjl 106340516Swpaul /* 106463090Sarchie * Call MI attach routine. 106540516Swpaul */ 1066106936Ssam ether_ifattach(ifp, eaddr); 1067106157Simp 1068113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1069106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1070106157Simp rl_intr, sc, &sc->rl_intrhand); 1071106157Simp 1072106157Simp if (error) { 1073106157Simp printf("rl%d: couldn't set up irq\n", unit); 1074113609Snjl ether_ifdetach(ifp); 1075106157Simp goto fail; 1076106157Simp } 1077106157Simp 107840516Swpaulfail: 1079112872Snjl if (error) 1080112872Snjl rl_detach(dev); 1081112872Snjl 1082110601Snjl return (error); 108340516Swpaul} 108440516Swpaul 1085113609Snjl/* 1086113609Snjl * Shutdown hardware and free up resources. This can be called any 1087113609Snjl * time after the mutex has been initialized. It is called in both 1088113609Snjl * the error case in attach and the normal detach case so it needs 1089113609Snjl * to be careful about only freeing resources that have actually been 1090113609Snjl * allocated. 1091113609Snjl */ 1092102335Salfredstatic int 1093102335Salfredrl_detach(dev) 109450703Swpaul device_t dev; 109550703Swpaul{ 109650703Swpaul struct rl_softc *sc; 109750703Swpaul struct ifnet *ifp; 109850703Swpaul 109950703Swpaul sc = device_get_softc(dev); 1100112880Sjhb KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 110167087Swpaul RL_LOCK(sc); 110250703Swpaul ifp = &sc->arpcom.ac_if; 110350703Swpaul 1104113609Snjl /* These should only be active if attach succeeded */ 1105113812Simp if (device_is_attached(dev)) { 1106113609Snjl rl_stop(sc); 1107112872Snjl ether_ifdetach(ifp); 1108113609Snjl } 1109113609Snjl if (sc->rl_miibus) 1110112872Snjl device_delete_child(dev, sc->rl_miibus); 1111113609Snjl bus_generic_detach(dev); 111250703Swpaul 1113112872Snjl if (sc->rl_intrhand) 1114112872Snjl bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1115112872Snjl if (sc->rl_irq) 1116112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1117112872Snjl if (sc->rl_res) 1118112872Snjl bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 111950703Swpaul 1120112872Snjl if (sc->rl_tag) { 1121112872Snjl bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1122112872Snjl bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1123112872Snjl sc->rl_cdata.rl_rx_dmamap); 1124112872Snjl bus_dma_tag_destroy(sc->rl_tag); 1125112872Snjl } 1126112872Snjl if (sc->rl_parent_tag) 1127112872Snjl bus_dma_tag_destroy(sc->rl_parent_tag); 112850703Swpaul 112967087Swpaul RL_UNLOCK(sc); 113067087Swpaul mtx_destroy(&sc->rl_mtx); 113150703Swpaul 113250703Swpaul return(0); 113350703Swpaul} 113450703Swpaul 113540516Swpaul/* 113640516Swpaul * Initialize the transmit descriptors. 113740516Swpaul */ 1138102335Salfredstatic int 1139102335Salfredrl_list_tx_init(sc) 114040516Swpaul struct rl_softc *sc; 114140516Swpaul{ 114240516Swpaul struct rl_chain_data *cd; 114340516Swpaul int i; 114440516Swpaul 114540516Swpaul cd = &sc->rl_cdata; 114640516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 114745633Swpaul cd->rl_tx_chain[i] = NULL; 114848028Swpaul CSR_WRITE_4(sc, 114948028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 115040516Swpaul } 115140516Swpaul 115245633Swpaul sc->rl_cdata.cur_tx = 0; 115345633Swpaul sc->rl_cdata.last_tx = 0; 115440516Swpaul 115540516Swpaul return(0); 115640516Swpaul} 115740516Swpaul 115840516Swpaul/* 115940516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 116040516Swpaul * the higher level protocols. 116140516Swpaul * 116240516Swpaul * You know there's something wrong with a PCI bus-master chip design 116340516Swpaul * when you have to use m_devget(). 116440516Swpaul * 116540516Swpaul * The receive operation is badly documented in the datasheet, so I'll 116640516Swpaul * attempt to document it here. The driver provides a buffer area and 116740516Swpaul * places its base address in the RX buffer start address register. 116840516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 116972645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 117040516Swpaul * of the frame and certain other status bits. Each frame (starting with 117140516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 117240516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 117340516Swpaul * the 'rx status register' mentioned in the datasheet. 117448028Swpaul * 117548028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 117678508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1177109109Sdes * as the offset argument to m_devget(). 117840516Swpaul */ 1179102335Salfredstatic void 1180102335Salfredrl_rxeof(sc) 118140516Swpaul struct rl_softc *sc; 118240516Swpaul{ 1183109109Sdes struct mbuf *m; 1184109109Sdes struct ifnet *ifp; 118540516Swpaul int total_len = 0; 118640516Swpaul u_int32_t rxstat; 118740516Swpaul caddr_t rxbufpos; 118840516Swpaul int wrap = 0; 118940516Swpaul u_int16_t cur_rx; 119040516Swpaul u_int16_t limit; 119140516Swpaul u_int16_t rx_bytes = 0, max_bytes; 119240516Swpaul 119340516Swpaul ifp = &sc->arpcom.ac_if; 119440516Swpaul 119581713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1196108729Sjake BUS_DMASYNC_POSTREAD); 119781713Swpaul 119840516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 119940516Swpaul 120040516Swpaul /* Do not try to read past this point. */ 120140516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 120240516Swpaul 120340516Swpaul if (limit < cur_rx) 120440516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 120540516Swpaul else 120640516Swpaul max_bytes = limit - cur_rx; 120740516Swpaul 120842738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 120994883Sluigi#ifdef DEVICE_POLLING 1210102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 121194883Sluigi if (sc->rxcycles <= 0) 121294883Sluigi break; 121394883Sluigi sc->rxcycles--; 121494883Sluigi } 121594883Sluigi#endif /* DEVICE_POLLING */ 121640516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1217108729Sjake rxstat = le32toh(*(u_int32_t *)rxbufpos); 121840516Swpaul 121940516Swpaul /* 122040516Swpaul * Here's a totally undocumented fact for you. When the 122140516Swpaul * RealTek chip is in the process of copying a packet into 122240516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 122340516Swpaul * packet header with this value, you need to stop. The 122440516Swpaul * datasheet makes absolutely no mention of this and 122540516Swpaul * RealTek should be shot for this. 122640516Swpaul */ 122740516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 122840516Swpaul break; 1229109109Sdes 123040516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 123140516Swpaul ifp->if_ierrors++; 123250703Swpaul rl_init(sc); 123350703Swpaul return; 123440516Swpaul } 123540516Swpaul 1236109109Sdes /* No errors; receive the packet. */ 123740516Swpaul total_len = rxstat >> 16; 123840516Swpaul rx_bytes += total_len + 4; 123940516Swpaul 124040516Swpaul /* 124142051Swpaul * XXX The RealTek chip includes the CRC with every 124242051Swpaul * received frame, and there's no way to turn this 124342051Swpaul * behavior off (at least, I can't find anything in 1244109109Sdes * the manual that explains how to do it) so we have 124542051Swpaul * to trim off the CRC manually. 124642051Swpaul */ 124742051Swpaul total_len -= ETHER_CRC_LEN; 124842051Swpaul 124942051Swpaul /* 125040516Swpaul * Avoid trying to read more bytes than we know 125140516Swpaul * the chip has prepared for us. 125240516Swpaul */ 125340516Swpaul if (rx_bytes > max_bytes) 125440516Swpaul break; 125540516Swpaul 125640516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 125740516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 125840516Swpaul 125940516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 126040516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 126140516Swpaul 126240516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 126340516Swpaul 126440516Swpaul if (total_len > wrap) { 126578508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 126678508Sbmilekic NULL); 126740516Swpaul if (m == NULL) { 126840516Swpaul ifp->if_ierrors++; 126952426Swpaul } else { 127040516Swpaul m_copyback(m, wrap, total_len - wrap, 127140516Swpaul sc->rl_cdata.rl_rx_buf); 127248028Swpaul } 127342051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 127440516Swpaul } else { 127578508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 127678508Sbmilekic NULL); 127740516Swpaul if (m == NULL) { 127840516Swpaul ifp->if_ierrors++; 127978508Sbmilekic } 128042051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 128140516Swpaul } 128240516Swpaul 128340516Swpaul /* 128440516Swpaul * Round up to 32-bit boundary. 128540516Swpaul */ 128640516Swpaul cur_rx = (cur_rx + 3) & ~3; 128740516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 128840516Swpaul 128940516Swpaul if (m == NULL) 129040516Swpaul continue; 129140516Swpaul 129240516Swpaul ifp->if_ipackets++; 1293106936Ssam (*ifp->if_input)(ifp, m); 129440516Swpaul } 129540516Swpaul 129640516Swpaul return; 129740516Swpaul} 129840516Swpaul 129940516Swpaul/* 130040516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 130140516Swpaul * the list buffers. 130240516Swpaul */ 1303102335Salfredstatic void 1304102335Salfredrl_txeof(sc) 130540516Swpaul struct rl_softc *sc; 130640516Swpaul{ 130740516Swpaul struct ifnet *ifp; 130840516Swpaul u_int32_t txstat; 130940516Swpaul 131040516Swpaul ifp = &sc->arpcom.ac_if; 131140516Swpaul 131240516Swpaul /* 131340516Swpaul * Go through our tx list and free mbufs for those 131440516Swpaul * frames that have been uploaded. 131540516Swpaul */ 131645633Swpaul do { 131745633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 131845633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 131945633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 132040516Swpaul break; 132140516Swpaul 132245633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 132340516Swpaul 132445633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 132581713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 132681713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 132745633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 132845633Swpaul RL_LAST_TXMBUF(sc) = NULL; 132945633Swpaul } 133045633Swpaul if (txstat & RL_TXSTAT_TX_OK) 133145633Swpaul ifp->if_opackets++; 133245633Swpaul else { 133352426Swpaul int oldthresh; 133445633Swpaul ifp->if_oerrors++; 133545633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 133645633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 133745633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 133852426Swpaul oldthresh = sc->rl_txthresh; 133952426Swpaul /* error recovery */ 134052426Swpaul rl_reset(sc); 134152426Swpaul rl_init(sc); 134252426Swpaul /* 134352426Swpaul * If there was a transmit underrun, 134452426Swpaul * bump the TX threshold. 134552426Swpaul */ 134652426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 134752426Swpaul sc->rl_txthresh = oldthresh + 32; 134852426Swpaul return; 134945633Swpaul } 135045633Swpaul RL_INC(sc->rl_cdata.last_tx); 135145633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 135245633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 135340516Swpaul 135499165Sluigi ifp->if_timer = 135599165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 135699165Sluigi 135750703Swpaul return; 135850703Swpaul} 135940516Swpaul 1360102335Salfredstatic void 1361102335Salfredrl_tick(xsc) 136250703Swpaul void *xsc; 136350703Swpaul{ 136450703Swpaul struct rl_softc *sc; 136550703Swpaul struct mii_data *mii; 136650703Swpaul 136750703Swpaul sc = xsc; 136867087Swpaul RL_LOCK(sc); 136950703Swpaul mii = device_get_softc(sc->rl_miibus); 137050703Swpaul 137150703Swpaul mii_tick(mii); 137250703Swpaul 137350703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 137467087Swpaul RL_UNLOCK(sc); 137550703Swpaul 137640516Swpaul return; 137740516Swpaul} 137840516Swpaul 137994883Sluigi#ifdef DEVICE_POLLING 138094883Sluigistatic void 138194883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 138294883Sluigi{ 138394883Sluigi struct rl_softc *sc = ifp->if_softc; 138494883Sluigi 138594883Sluigi RL_LOCK(sc); 138694883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 138794883Sluigi CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 138894883Sluigi goto done; 138994883Sluigi } 139094883Sluigi 139194883Sluigi sc->rxcycles = count; 139294883Sluigi rl_rxeof(sc); 139394883Sluigi rl_txeof(sc); 139494883Sluigi if (ifp->if_snd.ifq_head != NULL) 139594883Sluigi rl_start(ifp); 139694883Sluigi 139794883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 139894883Sluigi u_int16_t status; 139994883Sluigi 140094883Sluigi status = CSR_READ_2(sc, RL_ISR); 1401100957Sjhb if (status == 0xffff) 1402100957Sjhb goto done; 140394883Sluigi if (status) 140494883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 140594883Sluigi 140694883Sluigi /* 140794883Sluigi * XXX check behaviour on receiver stalls. 140894883Sluigi */ 140994883Sluigi 141094883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 141194883Sluigi rl_reset(sc); 141294883Sluigi rl_init(sc); 141394883Sluigi } 141494883Sluigi } 141594883Sluigidone: 141694883Sluigi RL_UNLOCK(sc); 141794883Sluigi} 141894883Sluigi#endif /* DEVICE_POLLING */ 141994883Sluigi 1420102335Salfredstatic void 1421102335Salfredrl_intr(arg) 142240516Swpaul void *arg; 142340516Swpaul{ 142440516Swpaul struct rl_softc *sc; 142540516Swpaul struct ifnet *ifp; 142640516Swpaul u_int16_t status; 142740516Swpaul 142840516Swpaul sc = arg; 142986822Siwasaki 143086822Siwasaki if (sc->suspended) { 143186822Siwasaki return; 143286822Siwasaki } 143386822Siwasaki 143467087Swpaul RL_LOCK(sc); 143540516Swpaul ifp = &sc->arpcom.ac_if; 143640516Swpaul 143794883Sluigi#ifdef DEVICE_POLLING 1438102052Ssobomax if (ifp->if_flags & IFF_POLLING) 143994883Sluigi goto done; 144094883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 144194883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 144294883Sluigi rl_poll(ifp, 0, 1); 144394883Sluigi goto done; 144494883Sluigi } 144594883Sluigi#endif /* DEVICE_POLLING */ 144640516Swpaul 144740516Swpaul for (;;) { 144840516Swpaul 144940516Swpaul status = CSR_READ_2(sc, RL_ISR); 1450100957Sjhb /* If the card has gone away the read returns 0xffff. */ 1451100957Sjhb if (status == 0xffff) 1452100957Sjhb break; 145340516Swpaul if (status) 145440516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 145540516Swpaul 145640516Swpaul if ((status & RL_INTRS) == 0) 145740516Swpaul break; 145840516Swpaul 145940516Swpaul if (status & RL_ISR_RX_OK) 146040516Swpaul rl_rxeof(sc); 146140516Swpaul 146240516Swpaul if (status & RL_ISR_RX_ERR) 146340516Swpaul rl_rxeof(sc); 146440516Swpaul 146545633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 146640516Swpaul rl_txeof(sc); 146740516Swpaul 146840516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 146940516Swpaul rl_reset(sc); 147040516Swpaul rl_init(sc); 147140516Swpaul } 147240516Swpaul 147340516Swpaul } 147440516Swpaul 147552426Swpaul if (ifp->if_snd.ifq_head != NULL) 147640516Swpaul rl_start(ifp); 147740516Swpaul 147894883Sluigi#ifdef DEVICE_POLLING 147994883Sluigidone: 148094883Sluigi#endif 148167087Swpaul RL_UNLOCK(sc); 148267087Swpaul 148340516Swpaul return; 148440516Swpaul} 148540516Swpaul 148640516Swpaul/* 148740516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 148840516Swpaul * pointers to the fragment pointers. 148940516Swpaul */ 1490102335Salfredstatic int 1491102335Salfredrl_encap(sc, m_head) 149240516Swpaul struct rl_softc *sc; 149340516Swpaul struct mbuf *m_head; 149440516Swpaul{ 149541243Swpaul struct mbuf *m_new = NULL; 149640516Swpaul 149740516Swpaul /* 149845633Swpaul * The RealTek is brain damaged and wants longword-aligned 149945633Swpaul * TX buffers, plus we can only have one fragment buffer 150045633Swpaul * per packet. We have to copy pretty much all the time. 150140516Swpaul */ 1502112839Ssilby m_new = m_defrag(m_head, M_DONTWAIT); 150340516Swpaul 1504113496Ssilby if (m_new == NULL) { 1505113496Ssilby m_freem(m_head); 150641243Swpaul return(1); 1507113496Ssilby } 150841243Swpaul m_head = m_new; 150940516Swpaul 151040516Swpaul /* Pad frames to at least 60 bytes. */ 151141243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 151255058Swpaul /* 151355058Swpaul * Make security concious people happy: zero out the 151455058Swpaul * bytes in the pad area, since we don't know what 151555058Swpaul * this mbuf cluster buffer's previous user might 151655058Swpaul * have left in it. 1517109109Sdes */ 151855058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 151955058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 152040516Swpaul m_head->m_pkthdr.len += 152152426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 152241243Swpaul m_head->m_len = m_head->m_pkthdr.len; 152341243Swpaul } 152440516Swpaul 152545633Swpaul RL_CUR_TXMBUF(sc) = m_head; 152640516Swpaul 152740516Swpaul return(0); 152840516Swpaul} 152940516Swpaul 153040516Swpaul/* 153140516Swpaul * Main transmit routine. 153240516Swpaul */ 153340516Swpaul 1534102335Salfredstatic void 1535102335Salfredrl_start(ifp) 153640516Swpaul struct ifnet *ifp; 153740516Swpaul{ 153840516Swpaul struct rl_softc *sc; 153940516Swpaul struct mbuf *m_head = NULL; 154040516Swpaul 154140516Swpaul sc = ifp->if_softc; 154267087Swpaul RL_LOCK(sc); 154340516Swpaul 154445633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 154540516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 154640516Swpaul if (m_head == NULL) 154740516Swpaul break; 154840516Swpaul 154958801Swpaul if (rl_encap(sc, m_head)) { 155058801Swpaul break; 155158801Swpaul } 155240516Swpaul 155340516Swpaul /* 155440516Swpaul * If there's a BPF listener, bounce a copy of this frame 155540516Swpaul * to him. 155640516Swpaul */ 1557106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 155851583Swpaul 155940516Swpaul /* 156040516Swpaul * Transmit the frame. 1561109109Sdes */ 156281713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 156381713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 156481713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 156581713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 156681713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 156781713Swpaul BUS_DMASYNC_PREREAD); 156845633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 156952426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 157052426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 157145633Swpaul 157245633Swpaul RL_INC(sc->rl_cdata.cur_tx); 1573113237Ssilby 1574113237Ssilby /* 1575113237Ssilby * Set a timeout in case the chip goes out to lunch. 1576113237Ssilby */ 1577113237Ssilby ifp->if_timer = 5; 157840516Swpaul } 157940516Swpaul 158040516Swpaul /* 158145633Swpaul * We broke out of the loop because all our TX slots are 158245633Swpaul * full. Mark the NIC as busy until it drains some of the 158345633Swpaul * packets from the queue. 158445633Swpaul */ 158545633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 158645633Swpaul ifp->if_flags |= IFF_OACTIVE; 158745633Swpaul 158867087Swpaul RL_UNLOCK(sc); 158940516Swpaul 159040516Swpaul return; 159140516Swpaul} 159240516Swpaul 1593102335Salfredstatic void 1594102335Salfredrl_init(xsc) 159540516Swpaul void *xsc; 159640516Swpaul{ 159740516Swpaul struct rl_softc *sc = xsc; 159840516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 159950703Swpaul struct mii_data *mii; 160067087Swpaul int i; 160140516Swpaul u_int32_t rxcfg = 0; 160240516Swpaul 160367087Swpaul RL_LOCK(sc); 160450703Swpaul mii = device_get_softc(sc->rl_miibus); 160540516Swpaul 160640516Swpaul /* 160740516Swpaul * Cancel pending I/O and free all RX/TX buffers. 160840516Swpaul */ 160940516Swpaul rl_stop(sc); 161040516Swpaul 161140516Swpaul /* Init our MAC address */ 161240516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 161340516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 161440516Swpaul } 161540516Swpaul 161640516Swpaul /* Init the RX buffer pointer register. */ 161781713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 161881713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 161981713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 162081713Swpaul BUS_DMASYNC_PREWRITE); 162140516Swpaul 162240516Swpaul /* Init TX descriptors. */ 162340516Swpaul rl_list_tx_init(sc); 162440516Swpaul 162540516Swpaul /* 162640516Swpaul * Enable transmit and receive. 162740516Swpaul */ 162840516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 162940516Swpaul 163040516Swpaul /* 163145633Swpaul * Set the initial TX and RX configuration. 163240516Swpaul */ 163345633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 163440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 163540516Swpaul 163640516Swpaul /* Set the individual bit to receive frames for this host only. */ 163740516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 163840516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 163940516Swpaul 164040516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 164140516Swpaul if (ifp->if_flags & IFF_PROMISC) { 164240516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 164340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 164440516Swpaul } else { 164540516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 164640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 164740516Swpaul } 164840516Swpaul 164940516Swpaul /* 165040516Swpaul * Set capture broadcast bit to capture broadcast frames. 165140516Swpaul */ 165240516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 165340516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 165440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165540516Swpaul } else { 165640516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 165740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165840516Swpaul } 165940516Swpaul 166040516Swpaul /* 166140516Swpaul * Program the multicast filter, if necessary. 166240516Swpaul */ 166340516Swpaul rl_setmulti(sc); 166440516Swpaul 166594883Sluigi#ifdef DEVICE_POLLING 166640516Swpaul /* 166794883Sluigi * Disable interrupts if we are polling. 166894883Sluigi */ 1669102052Ssobomax if (ifp->if_flags & IFF_POLLING) 167094883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 167194883Sluigi else /* otherwise ... */ 167294883Sluigi#endif /* DEVICE_POLLING */ 167394883Sluigi /* 167440516Swpaul * Enable interrupts. 167540516Swpaul */ 167640516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 167740516Swpaul 167852426Swpaul /* Set initial TX threshold */ 167952426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 168052426Swpaul 168140516Swpaul /* Start RX/TX process. */ 168240516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 168340516Swpaul 168440516Swpaul /* Enable receiver and transmitter. */ 168540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 168640516Swpaul 168750703Swpaul mii_mediachg(mii); 168840516Swpaul 168940516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 169040516Swpaul 169140516Swpaul ifp->if_flags |= IFF_RUNNING; 169240516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 169340516Swpaul 169450703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 169567087Swpaul RL_UNLOCK(sc); 169650703Swpaul 169740516Swpaul return; 169840516Swpaul} 169940516Swpaul 170040516Swpaul/* 170140516Swpaul * Set media options. 170240516Swpaul */ 1703102335Salfredstatic int 1704102335Salfredrl_ifmedia_upd(ifp) 170540516Swpaul struct ifnet *ifp; 170640516Swpaul{ 170740516Swpaul struct rl_softc *sc; 170850703Swpaul struct mii_data *mii; 170940516Swpaul 171040516Swpaul sc = ifp->if_softc; 171150703Swpaul mii = device_get_softc(sc->rl_miibus); 171250703Swpaul mii_mediachg(mii); 171340516Swpaul 171440516Swpaul return(0); 171540516Swpaul} 171640516Swpaul 171740516Swpaul/* 171840516Swpaul * Report current media status. 171940516Swpaul */ 1720102335Salfredstatic void 1721102335Salfredrl_ifmedia_sts(ifp, ifmr) 172240516Swpaul struct ifnet *ifp; 172340516Swpaul struct ifmediareq *ifmr; 172440516Swpaul{ 172540516Swpaul struct rl_softc *sc; 172650703Swpaul struct mii_data *mii; 172740516Swpaul 172840516Swpaul sc = ifp->if_softc; 172950703Swpaul mii = device_get_softc(sc->rl_miibus); 173040516Swpaul 173150703Swpaul mii_pollstat(mii); 173250703Swpaul ifmr->ifm_active = mii->mii_media_active; 173350703Swpaul ifmr->ifm_status = mii->mii_media_status; 173440516Swpaul 173540516Swpaul return; 173640516Swpaul} 173740516Swpaul 1738102335Salfredstatic int 1739102335Salfredrl_ioctl(ifp, command, data) 174040516Swpaul struct ifnet *ifp; 174140516Swpaul u_long command; 174240516Swpaul caddr_t data; 174340516Swpaul{ 174440516Swpaul struct rl_softc *sc = ifp->if_softc; 174540516Swpaul struct ifreq *ifr = (struct ifreq *) data; 174650703Swpaul struct mii_data *mii; 174767087Swpaul int error = 0; 174840516Swpaul 174967087Swpaul RL_LOCK(sc); 175040516Swpaul 175140516Swpaul switch(command) { 175240516Swpaul case SIOCSIFFLAGS: 175340516Swpaul if (ifp->if_flags & IFF_UP) { 175440516Swpaul rl_init(sc); 175540516Swpaul } else { 175640516Swpaul if (ifp->if_flags & IFF_RUNNING) 175740516Swpaul rl_stop(sc); 175840516Swpaul } 175940516Swpaul error = 0; 176040516Swpaul break; 176140516Swpaul case SIOCADDMULTI: 176240516Swpaul case SIOCDELMULTI: 176340516Swpaul rl_setmulti(sc); 176440516Swpaul error = 0; 176540516Swpaul break; 176640516Swpaul case SIOCGIFMEDIA: 176740516Swpaul case SIOCSIFMEDIA: 176850703Swpaul mii = device_get_softc(sc->rl_miibus); 176950703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 177040516Swpaul break; 177140516Swpaul default: 1772106936Ssam error = ether_ioctl(ifp, command, data); 177340516Swpaul break; 177440516Swpaul } 177540516Swpaul 177667087Swpaul RL_UNLOCK(sc); 177740516Swpaul 177840516Swpaul return(error); 177940516Swpaul} 178040516Swpaul 1781102335Salfredstatic void 1782102335Salfredrl_watchdog(ifp) 178340516Swpaul struct ifnet *ifp; 178440516Swpaul{ 178540516Swpaul struct rl_softc *sc; 178640516Swpaul 178740516Swpaul sc = ifp->if_softc; 178867087Swpaul RL_LOCK(sc); 178940516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 179040516Swpaul ifp->if_oerrors++; 179150703Swpaul 179240516Swpaul rl_txeof(sc); 179340516Swpaul rl_rxeof(sc); 179440516Swpaul rl_init(sc); 179567087Swpaul RL_UNLOCK(sc); 179640516Swpaul 179740516Swpaul return; 179840516Swpaul} 179940516Swpaul 180040516Swpaul/* 180140516Swpaul * Stop the adapter and free any mbufs allocated to the 180240516Swpaul * RX and TX lists. 180340516Swpaul */ 1804102335Salfredstatic void 1805102335Salfredrl_stop(sc) 180640516Swpaul struct rl_softc *sc; 180740516Swpaul{ 180840516Swpaul register int i; 180940516Swpaul struct ifnet *ifp; 181040516Swpaul 181167087Swpaul RL_LOCK(sc); 181240516Swpaul ifp = &sc->arpcom.ac_if; 181340516Swpaul ifp->if_timer = 0; 181440516Swpaul 181550703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 181694883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 181794883Sluigi#ifdef DEVICE_POLLING 181894883Sluigi ether_poll_deregister(ifp); 181994883Sluigi#endif /* DEVICE_POLLING */ 182050703Swpaul 182140516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 182240516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 182381713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 182440516Swpaul 182540516Swpaul /* 182640516Swpaul * Free the TX list buffers. 182740516Swpaul */ 182840516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 182945633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 183081713Swpaul bus_dmamap_unload(sc->rl_tag, 183181713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 183281713Swpaul bus_dmamap_destroy(sc->rl_tag, 183381713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 183445633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 183545633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 183645633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 183740516Swpaul } 183840516Swpaul } 183940516Swpaul 184067087Swpaul RL_UNLOCK(sc); 184140516Swpaul return; 184240516Swpaul} 184340516Swpaul 184440516Swpaul/* 184586822Siwasaki * Device suspend routine. Stop the interface and save some PCI 184686822Siwasaki * settings in case the BIOS doesn't restore them properly on 184786822Siwasaki * resume. 184886822Siwasaki */ 1849102335Salfredstatic int 1850102335Salfredrl_suspend(dev) 185186822Siwasaki device_t dev; 185286822Siwasaki{ 185386822Siwasaki register int i; 185486822Siwasaki struct rl_softc *sc; 185586822Siwasaki 185686822Siwasaki sc = device_get_softc(dev); 185786822Siwasaki 185886822Siwasaki rl_stop(sc); 185986822Siwasaki 186086822Siwasaki for (i = 0; i < 5; i++) 186186822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 186286822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 186386822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 186486822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 186586822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 186686822Siwasaki 186786822Siwasaki sc->suspended = 1; 186886822Siwasaki 186986822Siwasaki return (0); 187086822Siwasaki} 187186822Siwasaki 187286822Siwasaki/* 187386822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 187486822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 187586822Siwasaki * appropriate. 187686822Siwasaki */ 1877102335Salfredstatic int 1878102335Salfredrl_resume(dev) 187986822Siwasaki device_t dev; 188086822Siwasaki{ 188186822Siwasaki register int i; 188286822Siwasaki struct rl_softc *sc; 188386822Siwasaki struct ifnet *ifp; 188486822Siwasaki 188586822Siwasaki sc = device_get_softc(dev); 188686822Siwasaki ifp = &sc->arpcom.ac_if; 188786822Siwasaki 188886822Siwasaki /* better way to do this? */ 188986822Siwasaki for (i = 0; i < 5; i++) 189086822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 189186822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 189286822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 189386822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 189486822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 189586822Siwasaki 189686822Siwasaki /* reenable busmastering */ 189786822Siwasaki pci_enable_busmaster(dev); 189886822Siwasaki pci_enable_io(dev, RL_RES); 189986822Siwasaki 1900109109Sdes /* reinitialize interface if necessary */ 1901109109Sdes if (ifp->if_flags & IFF_UP) 1902109109Sdes rl_init(sc); 190386822Siwasaki 190486822Siwasaki sc->suspended = 0; 190586822Siwasaki 190686822Siwasaki return (0); 190786822Siwasaki} 190886822Siwasaki 190986822Siwasaki/* 191040516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 191140516Swpaul * get confused by errant DMAs when rebooting. 191240516Swpaul */ 1913102335Salfredstatic void 1914102335Salfredrl_shutdown(dev) 191550703Swpaul device_t dev; 191640516Swpaul{ 191750703Swpaul struct rl_softc *sc; 191840516Swpaul 191950703Swpaul sc = device_get_softc(dev); 192050703Swpaul 192140516Swpaul rl_stop(sc); 192240516Swpaul 192340516Swpaul return; 192440516Swpaul} 1925