if_rl.c revision 113812
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8129/8139 PCI NIC driver 35 * 36 * Supports several extremely cheap PCI 10/100 adapters based on 37 * the RealTek chipset. Datasheets can be obtained from 38 * www.realtek.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 47 * probably the worst PCI ethernet controller ever made, with the possible 48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 49 * DMA, but it has a terrible interface that nullifies any performance 50 * gains that bus-master DMA usually offers. 51 * 52 * For transmission, the chip offers a series of four TX descriptor 53 * registers. Each transmit frame must be in a contiguous buffer, aligned 54 * on a longword (32-bit) boundary. This means we almost always have to 55 * do mbuf copies in order to transmit a frame, except in the unlikely 56 * case where a) the packet fits into a single mbuf, and b) the packet 57 * is 32-bit aligned within the mbuf's data area. The presence of only 58 * four descriptor registers means that we can never have more than four 59 * packets queued for transmission at any one time. 60 * 61 * Reception is not much better. The driver has to allocate a single large 62 * buffer area (up to 64K in size) into which the chip will DMA received 63 * frames. Because we don't know where within this region received packets 64 * will begin or end, we have no choice but to copy data from the buffer 65 * area into mbufs in order to pass the packets up to the higher protocol 66 * levels. 67 * 68 * It's impossible given this rotten design to really achieve decent 69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 70 * some equally overmuscled CPU to drive it. 71 * 72 * On the bright side, the 8139 does have a built-in PHY, although 73 * rather than using an MDIO serial interface like most other NICs, the 74 * PHY registers are directly accessible through the 8139's register 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 */ 83 84#include <sys/param.h> 85#include <sys/endian.h> 86#include <sys/systm.h> 87#include <sys/sockio.h> 88#include <sys/mbuf.h> 89#include <sys/malloc.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98 99#include <net/bpf.h> 100 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111#include <pci/pcireg.h> 112#include <pci/pcivar.h> 113 114MODULE_DEPEND(rl, pci, 1, 1, 1); 115MODULE_DEPEND(rl, ether, 1, 1, 1); 116MODULE_DEPEND(rl, miibus, 1, 1, 1); 117 118/* "controller miibus0" required. See GENERIC if you get errors here. */ 119#include "miibus_if.h" 120 121/* 122 * Default to using PIO access for this driver. On SMP systems, 123 * there appear to be problems with memory mapped mode: it looks like 124 * doing too many memory mapped access back to back in rapid succession 125 * can hang the bus. I'm inclined to blame this on crummy design/construction 126 * on the part of RealTek. Memory mapped mode does appear to work on 127 * uniprocessor systems though. 128 */ 129#define RL_USEIOSPACE 130 131#include <pci/if_rlreg.h> 132 133__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 113812 2003-04-21 18:34:04Z imp $"); 134 135/* 136 * Various supported device vendors/types and their names. 137 */ 138static struct rl_type rl_devs[] = { 139 { RT_VENDORID, RT_DEVICEID_8129, 140 "RealTek 8129 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8139, 142 "RealTek 8139 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8138, 144 "RealTek 8139 10/100BaseTX CardBus" }, 145 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 146 "Accton MPX 5030/5038 10/100BaseTX" }, 147 { DELTA_VENDORID, DELTA_DEVICEID_8139, 148 "Delta Electronics 8139 10/100BaseTX" }, 149 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 150 "Addtron Technolgy 8139 10/100BaseTX" }, 151 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 152 "D-Link DFE-530TX+ 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 154 "D-Link DFE-690TXD 10/100BaseTX" }, 155 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 156 "Nortel Networks 10/100BaseTX" }, 157 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 158 "Corega FEther CB-TXD" }, 159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 160 "Corega FEtherII CB-TXD" }, 161 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 162 "Peppercon AG ROL-F" }, 163 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 164 "Planex FNW-3800-TX" }, 165 { 0, 0, NULL } 166}; 167 168static int rl_probe (device_t); 169static int rl_attach (device_t); 170static int rl_detach (device_t); 171 172static int rl_encap (struct rl_softc *, struct mbuf * ); 173 174static void rl_rxeof (struct rl_softc *); 175static void rl_txeof (struct rl_softc *); 176static void rl_intr (void *); 177static void rl_tick (void *); 178static void rl_start (struct ifnet *); 179static int rl_ioctl (struct ifnet *, u_long, caddr_t); 180static void rl_init (void *); 181static void rl_stop (struct rl_softc *); 182static void rl_watchdog (struct ifnet *); 183static int rl_suspend (device_t); 184static int rl_resume (device_t); 185static void rl_shutdown (device_t); 186static int rl_ifmedia_upd (struct ifnet *); 187static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 188 189static void rl_eeprom_putbyte (struct rl_softc *, int); 190static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 191static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 192static void rl_mii_sync (struct rl_softc *); 193static void rl_mii_send (struct rl_softc *, u_int32_t, int); 194static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 195static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 196 197static int rl_miibus_readreg (device_t, int, int); 198static int rl_miibus_writereg (device_t, int, int, int); 199static void rl_miibus_statchg (device_t); 200 201static u_int8_t rl_calchash (caddr_t); 202static void rl_setmulti (struct rl_softc *); 203static void rl_reset (struct rl_softc *); 204static int rl_list_tx_init (struct rl_softc *); 205 206static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 207static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 208 209#ifdef RL_USEIOSPACE 210#define RL_RES SYS_RES_IOPORT 211#define RL_RID RL_PCI_LOIO 212#else 213#define RL_RES SYS_RES_MEMORY 214#define RL_RID RL_PCI_LOMEM 215#endif 216 217static device_method_t rl_methods[] = { 218 /* Device interface */ 219 DEVMETHOD(device_probe, rl_probe), 220 DEVMETHOD(device_attach, rl_attach), 221 DEVMETHOD(device_detach, rl_detach), 222 DEVMETHOD(device_suspend, rl_suspend), 223 DEVMETHOD(device_resume, rl_resume), 224 DEVMETHOD(device_shutdown, rl_shutdown), 225 226 /* bus interface */ 227 DEVMETHOD(bus_print_child, bus_generic_print_child), 228 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 232 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 233 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 234 235 { 0, 0 } 236}; 237 238static driver_t rl_driver = { 239 "rl", 240 rl_methods, 241 sizeof(struct rl_softc) 242}; 243 244static devclass_t rl_devclass; 245 246DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 247DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 248DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 249 250#define EE_SET(x) \ 251 CSR_WRITE_1(sc, RL_EECMD, \ 252 CSR_READ_1(sc, RL_EECMD) | x) 253 254#define EE_CLR(x) \ 255 CSR_WRITE_1(sc, RL_EECMD, \ 256 CSR_READ_1(sc, RL_EECMD) & ~x) 257 258static void 259rl_dma_map_rxbuf(arg, segs, nseg, error) 260 void *arg; 261 bus_dma_segment_t *segs; 262 int nseg, error; 263{ 264 struct rl_softc *sc; 265 266 sc = arg; 267 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 268 269 return; 270} 271 272static void 273rl_dma_map_txbuf(arg, segs, nseg, error) 274 void *arg; 275 bus_dma_segment_t *segs; 276 int nseg, error; 277{ 278 struct rl_softc *sc; 279 280 sc = arg; 281 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 282 283 return; 284} 285 286/* 287 * Send a read command and address to the EEPROM, check for ACK. 288 */ 289static void 290rl_eeprom_putbyte(sc, addr) 291 struct rl_softc *sc; 292 int addr; 293{ 294 register int d, i; 295 296 d = addr | sc->rl_eecmd_read; 297 298 /* 299 * Feed in each bit and strobe the clock. 300 */ 301 for (i = 0x400; i; i >>= 1) { 302 if (d & i) { 303 EE_SET(RL_EE_DATAIN); 304 } else { 305 EE_CLR(RL_EE_DATAIN); 306 } 307 DELAY(100); 308 EE_SET(RL_EE_CLK); 309 DELAY(150); 310 EE_CLR(RL_EE_CLK); 311 DELAY(100); 312 } 313 314 return; 315} 316 317/* 318 * Read a word of data stored in the EEPROM at address 'addr.' 319 */ 320static void 321rl_eeprom_getword(sc, addr, dest) 322 struct rl_softc *sc; 323 int addr; 324 u_int16_t *dest; 325{ 326 register int i; 327 u_int16_t word = 0; 328 329 /* Enter EEPROM access mode. */ 330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 331 332 /* 333 * Send address of word we want to read. 334 */ 335 rl_eeprom_putbyte(sc, addr); 336 337 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 338 339 /* 340 * Start reading bits from EEPROM. 341 */ 342 for (i = 0x8000; i; i >>= 1) { 343 EE_SET(RL_EE_CLK); 344 DELAY(100); 345 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 346 word |= i; 347 EE_CLR(RL_EE_CLK); 348 DELAY(100); 349 } 350 351 /* Turn off EEPROM access mode. */ 352 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 353 354 *dest = word; 355 356 return; 357} 358 359/* 360 * Read a sequence of words from the EEPROM. 361 */ 362static void 363rl_read_eeprom(sc, dest, off, cnt, swap) 364 struct rl_softc *sc; 365 caddr_t dest; 366 int off; 367 int cnt; 368 int swap; 369{ 370 int i; 371 u_int16_t word = 0, *ptr; 372 373 for (i = 0; i < cnt; i++) { 374 rl_eeprom_getword(sc, off + i, &word); 375 ptr = (u_int16_t *)(dest + (i * 2)); 376 if (swap) 377 *ptr = ntohs(word); 378 else 379 *ptr = word; 380 } 381 382 return; 383} 384 385 386/* 387 * MII access routines are provided for the 8129, which 388 * doesn't have a built-in PHY. For the 8139, we fake things 389 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 390 * direct access PHY registers. 391 */ 392#define MII_SET(x) \ 393 CSR_WRITE_1(sc, RL_MII, \ 394 CSR_READ_1(sc, RL_MII) | (x)) 395 396#define MII_CLR(x) \ 397 CSR_WRITE_1(sc, RL_MII, \ 398 CSR_READ_1(sc, RL_MII) & ~(x)) 399 400/* 401 * Sync the PHYs by setting data bit and strobing the clock 32 times. 402 */ 403static void 404rl_mii_sync(sc) 405 struct rl_softc *sc; 406{ 407 register int i; 408 409 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 410 411 for (i = 0; i < 32; i++) { 412 MII_SET(RL_MII_CLK); 413 DELAY(1); 414 MII_CLR(RL_MII_CLK); 415 DELAY(1); 416 } 417 418 return; 419} 420 421/* 422 * Clock a series of bits through the MII. 423 */ 424static void 425rl_mii_send(sc, bits, cnt) 426 struct rl_softc *sc; 427 u_int32_t bits; 428 int cnt; 429{ 430 int i; 431 432 MII_CLR(RL_MII_CLK); 433 434 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 435 if (bits & i) { 436 MII_SET(RL_MII_DATAOUT); 437 } else { 438 MII_CLR(RL_MII_DATAOUT); 439 } 440 DELAY(1); 441 MII_CLR(RL_MII_CLK); 442 DELAY(1); 443 MII_SET(RL_MII_CLK); 444 } 445} 446 447/* 448 * Read an PHY register through the MII. 449 */ 450static int 451rl_mii_readreg(sc, frame) 452 struct rl_softc *sc; 453 struct rl_mii_frame *frame; 454 455{ 456 int i, ack; 457 458 RL_LOCK(sc); 459 460 /* 461 * Set up frame for RX. 462 */ 463 frame->mii_stdelim = RL_MII_STARTDELIM; 464 frame->mii_opcode = RL_MII_READOP; 465 frame->mii_turnaround = 0; 466 frame->mii_data = 0; 467 468 CSR_WRITE_2(sc, RL_MII, 0); 469 470 /* 471 * Turn on data xmit. 472 */ 473 MII_SET(RL_MII_DIR); 474 475 rl_mii_sync(sc); 476 477 /* 478 * Send command/address info. 479 */ 480 rl_mii_send(sc, frame->mii_stdelim, 2); 481 rl_mii_send(sc, frame->mii_opcode, 2); 482 rl_mii_send(sc, frame->mii_phyaddr, 5); 483 rl_mii_send(sc, frame->mii_regaddr, 5); 484 485 /* Idle bit */ 486 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 487 DELAY(1); 488 MII_SET(RL_MII_CLK); 489 DELAY(1); 490 491 /* Turn off xmit. */ 492 MII_CLR(RL_MII_DIR); 493 494 /* Check for ack */ 495 MII_CLR(RL_MII_CLK); 496 DELAY(1); 497 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 498 MII_SET(RL_MII_CLK); 499 DELAY(1); 500 501 /* 502 * Now try reading data bits. If the ack failed, we still 503 * need to clock through 16 cycles to keep the PHY(s) in sync. 504 */ 505 if (ack) { 506 for(i = 0; i < 16; i++) { 507 MII_CLR(RL_MII_CLK); 508 DELAY(1); 509 MII_SET(RL_MII_CLK); 510 DELAY(1); 511 } 512 goto fail; 513 } 514 515 for (i = 0x8000; i; i >>= 1) { 516 MII_CLR(RL_MII_CLK); 517 DELAY(1); 518 if (!ack) { 519 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 520 frame->mii_data |= i; 521 DELAY(1); 522 } 523 MII_SET(RL_MII_CLK); 524 DELAY(1); 525 } 526 527fail: 528 529 MII_CLR(RL_MII_CLK); 530 DELAY(1); 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 534 RL_UNLOCK(sc); 535 536 if (ack) 537 return(1); 538 return(0); 539} 540 541/* 542 * Write to a PHY register through the MII. 543 */ 544static int 545rl_mii_writereg(sc, frame) 546 struct rl_softc *sc; 547 struct rl_mii_frame *frame; 548 549{ 550 RL_LOCK(sc); 551 552 /* 553 * Set up frame for TX. 554 */ 555 556 frame->mii_stdelim = RL_MII_STARTDELIM; 557 frame->mii_opcode = RL_MII_WRITEOP; 558 frame->mii_turnaround = RL_MII_TURNAROUND; 559 560 /* 561 * Turn on data output. 562 */ 563 MII_SET(RL_MII_DIR); 564 565 rl_mii_sync(sc); 566 567 rl_mii_send(sc, frame->mii_stdelim, 2); 568 rl_mii_send(sc, frame->mii_opcode, 2); 569 rl_mii_send(sc, frame->mii_phyaddr, 5); 570 rl_mii_send(sc, frame->mii_regaddr, 5); 571 rl_mii_send(sc, frame->mii_turnaround, 2); 572 rl_mii_send(sc, frame->mii_data, 16); 573 574 /* Idle bit. */ 575 MII_SET(RL_MII_CLK); 576 DELAY(1); 577 MII_CLR(RL_MII_CLK); 578 DELAY(1); 579 580 /* 581 * Turn off xmit. 582 */ 583 MII_CLR(RL_MII_DIR); 584 585 RL_UNLOCK(sc); 586 587 return(0); 588} 589 590static int 591rl_miibus_readreg(dev, phy, reg) 592 device_t dev; 593 int phy, reg; 594{ 595 struct rl_softc *sc; 596 struct rl_mii_frame frame; 597 u_int16_t rval = 0; 598 u_int16_t rl8139_reg = 0; 599 600 sc = device_get_softc(dev); 601 RL_LOCK(sc); 602 603 if (sc->rl_type == RL_8139) { 604 /* Pretend the internal PHY is only at address 0 */ 605 if (phy) { 606 RL_UNLOCK(sc); 607 return(0); 608 } 609 switch(reg) { 610 case MII_BMCR: 611 rl8139_reg = RL_BMCR; 612 break; 613 case MII_BMSR: 614 rl8139_reg = RL_BMSR; 615 break; 616 case MII_ANAR: 617 rl8139_reg = RL_ANAR; 618 break; 619 case MII_ANER: 620 rl8139_reg = RL_ANER; 621 break; 622 case MII_ANLPAR: 623 rl8139_reg = RL_LPAR; 624 break; 625 case MII_PHYIDR1: 626 case MII_PHYIDR2: 627 RL_UNLOCK(sc); 628 return(0); 629 break; 630 /* 631 * Allow the rlphy driver to read the media status 632 * register. If we have a link partner which does not 633 * support NWAY, this is the register which will tell 634 * us the results of parallel detection. 635 */ 636 case RL_MEDIASTAT: 637 rval = CSR_READ_1(sc, RL_MEDIASTAT); 638 RL_UNLOCK(sc); 639 return(rval); 640 break; 641 default: 642 printf("rl%d: bad phy register\n", sc->rl_unit); 643 RL_UNLOCK(sc); 644 return(0); 645 } 646 rval = CSR_READ_2(sc, rl8139_reg); 647 RL_UNLOCK(sc); 648 return(rval); 649 } 650 651 bzero((char *)&frame, sizeof(frame)); 652 653 frame.mii_phyaddr = phy; 654 frame.mii_regaddr = reg; 655 rl_mii_readreg(sc, &frame); 656 RL_UNLOCK(sc); 657 658 return(frame.mii_data); 659} 660 661static int 662rl_miibus_writereg(dev, phy, reg, data) 663 device_t dev; 664 int phy, reg, data; 665{ 666 struct rl_softc *sc; 667 struct rl_mii_frame frame; 668 u_int16_t rl8139_reg = 0; 669 670 sc = device_get_softc(dev); 671 RL_LOCK(sc); 672 673 if (sc->rl_type == RL_8139) { 674 /* Pretend the internal PHY is only at address 0 */ 675 if (phy) { 676 RL_UNLOCK(sc); 677 return(0); 678 } 679 switch(reg) { 680 case MII_BMCR: 681 rl8139_reg = RL_BMCR; 682 break; 683 case MII_BMSR: 684 rl8139_reg = RL_BMSR; 685 break; 686 case MII_ANAR: 687 rl8139_reg = RL_ANAR; 688 break; 689 case MII_ANER: 690 rl8139_reg = RL_ANER; 691 break; 692 case MII_ANLPAR: 693 rl8139_reg = RL_LPAR; 694 break; 695 case MII_PHYIDR1: 696 case MII_PHYIDR2: 697 RL_UNLOCK(sc); 698 return(0); 699 break; 700 default: 701 printf("rl%d: bad phy register\n", sc->rl_unit); 702 RL_UNLOCK(sc); 703 return(0); 704 } 705 CSR_WRITE_2(sc, rl8139_reg, data); 706 RL_UNLOCK(sc); 707 return(0); 708 } 709 710 bzero((char *)&frame, sizeof(frame)); 711 712 frame.mii_phyaddr = phy; 713 frame.mii_regaddr = reg; 714 frame.mii_data = data; 715 716 rl_mii_writereg(sc, &frame); 717 718 RL_UNLOCK(sc); 719 return(0); 720} 721 722static void 723rl_miibus_statchg(dev) 724 device_t dev; 725{ 726 return; 727} 728 729/* 730 * Calculate CRC of a multicast group address, return the upper 6 bits. 731 */ 732static u_int8_t 733rl_calchash(addr) 734 caddr_t addr; 735{ 736 u_int32_t crc, carry; 737 int i, j; 738 u_int8_t c; 739 740 /* Compute CRC for the address value. */ 741 crc = 0xFFFFFFFF; /* initial value */ 742 743 for (i = 0; i < 6; i++) { 744 c = *(addr + i); 745 for (j = 0; j < 8; j++) { 746 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 747 crc <<= 1; 748 c >>= 1; 749 if (carry) 750 crc = (crc ^ 0x04c11db6) | carry; 751 } 752 } 753 754 /* return the filter bit position */ 755 return(crc >> 26); 756} 757 758/* 759 * Program the 64-bit multicast hash filter. 760 */ 761static void 762rl_setmulti(sc) 763 struct rl_softc *sc; 764{ 765 struct ifnet *ifp; 766 int h = 0; 767 u_int32_t hashes[2] = { 0, 0 }; 768 struct ifmultiaddr *ifma; 769 u_int32_t rxfilt; 770 int mcnt = 0; 771 772 ifp = &sc->arpcom.ac_if; 773 774 rxfilt = CSR_READ_4(sc, RL_RXCFG); 775 776 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 777 rxfilt |= RL_RXCFG_RX_MULTI; 778 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 779 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 780 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 781 return; 782 } 783 784 /* first, zot all the existing hash bits */ 785 CSR_WRITE_4(sc, RL_MAR0, 0); 786 CSR_WRITE_4(sc, RL_MAR4, 0); 787 788 /* now program new ones */ 789 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 790 if (ifma->ifma_addr->sa_family != AF_LINK) 791 continue; 792 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 793 if (h < 32) 794 hashes[0] |= (1 << h); 795 else 796 hashes[1] |= (1 << (h - 32)); 797 mcnt++; 798 } 799 800 if (mcnt) 801 rxfilt |= RL_RXCFG_RX_MULTI; 802 else 803 rxfilt &= ~RL_RXCFG_RX_MULTI; 804 805 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 806 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 807 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 808 809 return; 810} 811 812static void 813rl_reset(sc) 814 struct rl_softc *sc; 815{ 816 register int i; 817 818 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 819 820 for (i = 0; i < RL_TIMEOUT; i++) { 821 DELAY(10); 822 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 823 break; 824 } 825 if (i == RL_TIMEOUT) 826 printf("rl%d: reset never completed!\n", sc->rl_unit); 827 828 return; 829} 830 831/* 832 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 833 * IDs against our list and return a device name if we find a match. 834 */ 835static int 836rl_probe(dev) 837 device_t dev; 838{ 839 struct rl_type *t; 840 841 t = rl_devs; 842 843 while(t->rl_name != NULL) { 844 if ((pci_get_vendor(dev) == t->rl_vid) && 845 (pci_get_device(dev) == t->rl_did)) { 846 device_set_desc(dev, t->rl_name); 847 return(0); 848 } 849 t++; 850 } 851 852 return(ENXIO); 853} 854 855/* 856 * Attach the interface. Allocate softc structures, do ifmedia 857 * setup and ethernet/BPF attach. 858 */ 859static int 860rl_attach(dev) 861 device_t dev; 862{ 863 u_char eaddr[ETHER_ADDR_LEN]; 864 u_int16_t as[3]; 865 struct rl_softc *sc; 866 struct ifnet *ifp; 867 u_int16_t rl_did = 0; 868 int unit, error = 0, rid, i; 869 870 sc = device_get_softc(dev); 871 unit = device_get_unit(dev); 872 873 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 874 MTX_DEF | MTX_RECURSE); 875 876 /* 877 * Handle power management nonsense. 878 */ 879 880 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 881 u_int32_t iobase, membase, irq; 882 883 /* Save important PCI config data. */ 884 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 885 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 886 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 887 888 /* Reset the power state. */ 889 printf("rl%d: chip is is in D%d power mode " 890 "-- setting to D0\n", unit, 891 pci_get_powerstate(dev)); 892 893 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 894 895 /* Restore PCI config data. */ 896 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 897 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 898 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 899 } 900 901 /* 902 * Map control/status registers. 903 */ 904 pci_enable_busmaster(dev); 905 906 rid = RL_RID; 907 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 908 0, ~0, 1, RF_ACTIVE); 909 910 if (sc->rl_res == NULL) { 911 printf ("rl%d: couldn't map ports/memory\n", unit); 912 error = ENXIO; 913 goto fail; 914 } 915 916 /* Detect the Realtek 8139B. For some reason, this chip is very 917 * unstable when left to autoselect the media 918 * The best workaround is to set the device to the required 919 * media type or to set it to the 10 Meg speed. 920 */ 921 922 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 923 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 924 } 925 926 sc->rl_btag = rman_get_bustag(sc->rl_res); 927 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 928 929 /* Allocate interrupt */ 930 rid = 0; 931 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 932 RF_SHAREABLE | RF_ACTIVE); 933 934 if (sc->rl_irq == NULL) { 935 printf("rl%d: couldn't map interrupt\n", unit); 936 error = ENXIO; 937 goto fail; 938 } 939 940 /* Reset the adapter. */ 941 rl_reset(sc); 942 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 943 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 944 if (rl_did != 0x8129) 945 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 946 947 /* 948 * Get station address from the EEPROM. 949 */ 950 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 951 for (i = 0; i < 3; i++) { 952 eaddr[(i * 2) + 0] = as[i] & 0xff; 953 eaddr[(i * 2) + 1] = as[i] >> 8; 954 } 955 956 /* 957 * A RealTek chip was detected. Inform the world. 958 */ 959 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 960 961 sc->rl_unit = unit; 962 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 963 964 /* 965 * Now read the exact device type from the EEPROM to find 966 * out if it's an 8129 or 8139. 967 */ 968 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 969 970 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 971 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 972 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 973 rl_did == DLINK_DEVICEID_690TXD || 974 rl_did == COREGA_DEVICEID_FETHERCBTXD || 975 rl_did == COREGA_DEVICEID_FETHERIICBTXD || 976 rl_did == PLANEX_DEVICEID_FNW3800TX) 977 sc->rl_type = RL_8139; 978 else if (rl_did == RT_DEVICEID_8129) 979 sc->rl_type = RL_8129; 980 else { 981 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 982 error = ENXIO; 983 goto fail; 984 } 985 986 /* 987 * Allocate the parent bus DMA tag appropriate for PCI. 988 */ 989#define RL_NSEG_NEW 32 990 error = bus_dma_tag_create(NULL, /* parent */ 991 1, 0, /* alignment, boundary */ 992 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 993 BUS_SPACE_MAXADDR, /* highaddr */ 994 NULL, NULL, /* filter, filterarg */ 995 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 996 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 997 BUS_DMA_ALLOCNOW, /* flags */ 998 &sc->rl_parent_tag); 999 if (error) 1000 goto fail; 1001 1002 /* 1003 * Now allocate a tag for the DMA descriptor lists. 1004 * All of our lists are allocated as a contiguous block 1005 * of memory. 1006 */ 1007 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1008 1, 0, /* alignment, boundary */ 1009 BUS_SPACE_MAXADDR, /* lowaddr */ 1010 BUS_SPACE_MAXADDR, /* highaddr */ 1011 NULL, NULL, /* filter, filterarg */ 1012 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1013 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1014 0, /* flags */ 1015 &sc->rl_tag); 1016 if (error) 1017 goto fail; 1018 1019 /* 1020 * Now allocate a chunk of DMA-able memory based on the 1021 * tag we just created. 1022 */ 1023 error = bus_dmamem_alloc(sc->rl_tag, 1024 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1025 &sc->rl_cdata.rl_rx_dmamap); 1026 1027 if (error) { 1028 printf("rl%d: no memory for list buffers!\n", unit); 1029 bus_dma_tag_destroy(sc->rl_tag); 1030 sc->rl_tag = NULL; 1031 goto fail; 1032 } 1033 1034 /* Leave a few bytes before the start of the RX ring buffer. */ 1035 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1036 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1037 1038 /* Do MII setup */ 1039 if (mii_phy_probe(dev, &sc->rl_miibus, 1040 rl_ifmedia_upd, rl_ifmedia_sts)) { 1041 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1042 error = ENXIO; 1043 goto fail; 1044 } 1045 1046 ifp = &sc->arpcom.ac_if; 1047 ifp->if_softc = sc; 1048 ifp->if_unit = unit; 1049 ifp->if_name = "rl"; 1050 ifp->if_mtu = ETHERMTU; 1051 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1052 ifp->if_ioctl = rl_ioctl; 1053 ifp->if_output = ether_output; 1054 ifp->if_start = rl_start; 1055 ifp->if_watchdog = rl_watchdog; 1056 ifp->if_init = rl_init; 1057 ifp->if_baudrate = 10000000; 1058 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1059 1060 callout_handle_init(&sc->rl_stat_ch); 1061 1062 /* 1063 * Call MI attach routine. 1064 */ 1065 ether_ifattach(ifp, eaddr); 1066 1067 /* Hook interrupt last to avoid having to lock softc */ 1068 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1069 rl_intr, sc, &sc->rl_intrhand); 1070 1071 if (error) { 1072 printf("rl%d: couldn't set up irq\n", unit); 1073 ether_ifdetach(ifp); 1074 goto fail; 1075 } 1076 1077fail: 1078 if (error) 1079 rl_detach(dev); 1080 1081 return (error); 1082} 1083 1084/* 1085 * Shutdown hardware and free up resources. This can be called any 1086 * time after the mutex has been initialized. It is called in both 1087 * the error case in attach and the normal detach case so it needs 1088 * to be careful about only freeing resources that have actually been 1089 * allocated. 1090 */ 1091static int 1092rl_detach(dev) 1093 device_t dev; 1094{ 1095 struct rl_softc *sc; 1096 struct ifnet *ifp; 1097 1098 sc = device_get_softc(dev); 1099 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1100 RL_LOCK(sc); 1101 ifp = &sc->arpcom.ac_if; 1102 1103 /* These should only be active if attach succeeded */ 1104 if (device_is_attached(dev)) { 1105 rl_stop(sc); 1106 ether_ifdetach(ifp); 1107 } 1108 if (sc->rl_miibus) 1109 device_delete_child(dev, sc->rl_miibus); 1110 bus_generic_detach(dev); 1111 1112 if (sc->rl_intrhand) 1113 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1114 if (sc->rl_irq) 1115 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1116 if (sc->rl_res) 1117 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1118 1119 if (sc->rl_tag) { 1120 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1121 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1122 sc->rl_cdata.rl_rx_dmamap); 1123 bus_dma_tag_destroy(sc->rl_tag); 1124 } 1125 if (sc->rl_parent_tag) 1126 bus_dma_tag_destroy(sc->rl_parent_tag); 1127 1128 RL_UNLOCK(sc); 1129 mtx_destroy(&sc->rl_mtx); 1130 1131 return(0); 1132} 1133 1134/* 1135 * Initialize the transmit descriptors. 1136 */ 1137static int 1138rl_list_tx_init(sc) 1139 struct rl_softc *sc; 1140{ 1141 struct rl_chain_data *cd; 1142 int i; 1143 1144 cd = &sc->rl_cdata; 1145 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1146 cd->rl_tx_chain[i] = NULL; 1147 CSR_WRITE_4(sc, 1148 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1149 } 1150 1151 sc->rl_cdata.cur_tx = 0; 1152 sc->rl_cdata.last_tx = 0; 1153 1154 return(0); 1155} 1156 1157/* 1158 * A frame has been uploaded: pass the resulting mbuf chain up to 1159 * the higher level protocols. 1160 * 1161 * You know there's something wrong with a PCI bus-master chip design 1162 * when you have to use m_devget(). 1163 * 1164 * The receive operation is badly documented in the datasheet, so I'll 1165 * attempt to document it here. The driver provides a buffer area and 1166 * places its base address in the RX buffer start address register. 1167 * The chip then begins copying frames into the RX buffer. Each frame 1168 * is preceded by a 32-bit RX status word which specifies the length 1169 * of the frame and certain other status bits. Each frame (starting with 1170 * the status word) is also 32-bit aligned. The frame length is in the 1171 * first 16 bits of the status word; the lower 15 bits correspond with 1172 * the 'rx status register' mentioned in the datasheet. 1173 * 1174 * Note: to make the Alpha happy, the frame payload needs to be aligned 1175 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1176 * as the offset argument to m_devget(). 1177 */ 1178static void 1179rl_rxeof(sc) 1180 struct rl_softc *sc; 1181{ 1182 struct mbuf *m; 1183 struct ifnet *ifp; 1184 int total_len = 0; 1185 u_int32_t rxstat; 1186 caddr_t rxbufpos; 1187 int wrap = 0; 1188 u_int16_t cur_rx; 1189 u_int16_t limit; 1190 u_int16_t rx_bytes = 0, max_bytes; 1191 1192 ifp = &sc->arpcom.ac_if; 1193 1194 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1195 BUS_DMASYNC_POSTREAD); 1196 1197 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1198 1199 /* Do not try to read past this point. */ 1200 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1201 1202 if (limit < cur_rx) 1203 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1204 else 1205 max_bytes = limit - cur_rx; 1206 1207 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1208#ifdef DEVICE_POLLING 1209 if (ifp->if_flags & IFF_POLLING) { 1210 if (sc->rxcycles <= 0) 1211 break; 1212 sc->rxcycles--; 1213 } 1214#endif /* DEVICE_POLLING */ 1215 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1216 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1217 1218 /* 1219 * Here's a totally undocumented fact for you. When the 1220 * RealTek chip is in the process of copying a packet into 1221 * RAM for you, the length will be 0xfff0. If you spot a 1222 * packet header with this value, you need to stop. The 1223 * datasheet makes absolutely no mention of this and 1224 * RealTek should be shot for this. 1225 */ 1226 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1227 break; 1228 1229 if (!(rxstat & RL_RXSTAT_RXOK)) { 1230 ifp->if_ierrors++; 1231 rl_init(sc); 1232 return; 1233 } 1234 1235 /* No errors; receive the packet. */ 1236 total_len = rxstat >> 16; 1237 rx_bytes += total_len + 4; 1238 1239 /* 1240 * XXX The RealTek chip includes the CRC with every 1241 * received frame, and there's no way to turn this 1242 * behavior off (at least, I can't find anything in 1243 * the manual that explains how to do it) so we have 1244 * to trim off the CRC manually. 1245 */ 1246 total_len -= ETHER_CRC_LEN; 1247 1248 /* 1249 * Avoid trying to read more bytes than we know 1250 * the chip has prepared for us. 1251 */ 1252 if (rx_bytes > max_bytes) 1253 break; 1254 1255 rxbufpos = sc->rl_cdata.rl_rx_buf + 1256 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1257 1258 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1259 rxbufpos = sc->rl_cdata.rl_rx_buf; 1260 1261 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1262 1263 if (total_len > wrap) { 1264 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1265 NULL); 1266 if (m == NULL) { 1267 ifp->if_ierrors++; 1268 } else { 1269 m_copyback(m, wrap, total_len - wrap, 1270 sc->rl_cdata.rl_rx_buf); 1271 } 1272 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1273 } else { 1274 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1275 NULL); 1276 if (m == NULL) { 1277 ifp->if_ierrors++; 1278 } 1279 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1280 } 1281 1282 /* 1283 * Round up to 32-bit boundary. 1284 */ 1285 cur_rx = (cur_rx + 3) & ~3; 1286 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1287 1288 if (m == NULL) 1289 continue; 1290 1291 ifp->if_ipackets++; 1292 (*ifp->if_input)(ifp, m); 1293 } 1294 1295 return; 1296} 1297 1298/* 1299 * A frame was downloaded to the chip. It's safe for us to clean up 1300 * the list buffers. 1301 */ 1302static void 1303rl_txeof(sc) 1304 struct rl_softc *sc; 1305{ 1306 struct ifnet *ifp; 1307 u_int32_t txstat; 1308 1309 ifp = &sc->arpcom.ac_if; 1310 1311 /* 1312 * Go through our tx list and free mbufs for those 1313 * frames that have been uploaded. 1314 */ 1315 do { 1316 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1317 if (!(txstat & (RL_TXSTAT_TX_OK| 1318 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1319 break; 1320 1321 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1322 1323 if (RL_LAST_TXMBUF(sc) != NULL) { 1324 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1325 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1326 m_freem(RL_LAST_TXMBUF(sc)); 1327 RL_LAST_TXMBUF(sc) = NULL; 1328 } 1329 if (txstat & RL_TXSTAT_TX_OK) 1330 ifp->if_opackets++; 1331 else { 1332 int oldthresh; 1333 ifp->if_oerrors++; 1334 if ((txstat & RL_TXSTAT_TXABRT) || 1335 (txstat & RL_TXSTAT_OUTOFWIN)) 1336 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1337 oldthresh = sc->rl_txthresh; 1338 /* error recovery */ 1339 rl_reset(sc); 1340 rl_init(sc); 1341 /* 1342 * If there was a transmit underrun, 1343 * bump the TX threshold. 1344 */ 1345 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1346 sc->rl_txthresh = oldthresh + 32; 1347 return; 1348 } 1349 RL_INC(sc->rl_cdata.last_tx); 1350 ifp->if_flags &= ~IFF_OACTIVE; 1351 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1352 1353 ifp->if_timer = 1354 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1355 1356 return; 1357} 1358 1359static void 1360rl_tick(xsc) 1361 void *xsc; 1362{ 1363 struct rl_softc *sc; 1364 struct mii_data *mii; 1365 1366 sc = xsc; 1367 RL_LOCK(sc); 1368 mii = device_get_softc(sc->rl_miibus); 1369 1370 mii_tick(mii); 1371 1372 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1373 RL_UNLOCK(sc); 1374 1375 return; 1376} 1377 1378#ifdef DEVICE_POLLING 1379static void 1380rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1381{ 1382 struct rl_softc *sc = ifp->if_softc; 1383 1384 RL_LOCK(sc); 1385 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1386 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1387 goto done; 1388 } 1389 1390 sc->rxcycles = count; 1391 rl_rxeof(sc); 1392 rl_txeof(sc); 1393 if (ifp->if_snd.ifq_head != NULL) 1394 rl_start(ifp); 1395 1396 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1397 u_int16_t status; 1398 1399 status = CSR_READ_2(sc, RL_ISR); 1400 if (status == 0xffff) 1401 goto done; 1402 if (status) 1403 CSR_WRITE_2(sc, RL_ISR, status); 1404 1405 /* 1406 * XXX check behaviour on receiver stalls. 1407 */ 1408 1409 if (status & RL_ISR_SYSTEM_ERR) { 1410 rl_reset(sc); 1411 rl_init(sc); 1412 } 1413 } 1414done: 1415 RL_UNLOCK(sc); 1416} 1417#endif /* DEVICE_POLLING */ 1418 1419static void 1420rl_intr(arg) 1421 void *arg; 1422{ 1423 struct rl_softc *sc; 1424 struct ifnet *ifp; 1425 u_int16_t status; 1426 1427 sc = arg; 1428 1429 if (sc->suspended) { 1430 return; 1431 } 1432 1433 RL_LOCK(sc); 1434 ifp = &sc->arpcom.ac_if; 1435 1436#ifdef DEVICE_POLLING 1437 if (ifp->if_flags & IFF_POLLING) 1438 goto done; 1439 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1440 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1441 rl_poll(ifp, 0, 1); 1442 goto done; 1443 } 1444#endif /* DEVICE_POLLING */ 1445 1446 for (;;) { 1447 1448 status = CSR_READ_2(sc, RL_ISR); 1449 /* If the card has gone away the read returns 0xffff. */ 1450 if (status == 0xffff) 1451 break; 1452 if (status) 1453 CSR_WRITE_2(sc, RL_ISR, status); 1454 1455 if ((status & RL_INTRS) == 0) 1456 break; 1457 1458 if (status & RL_ISR_RX_OK) 1459 rl_rxeof(sc); 1460 1461 if (status & RL_ISR_RX_ERR) 1462 rl_rxeof(sc); 1463 1464 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1465 rl_txeof(sc); 1466 1467 if (status & RL_ISR_SYSTEM_ERR) { 1468 rl_reset(sc); 1469 rl_init(sc); 1470 } 1471 1472 } 1473 1474 if (ifp->if_snd.ifq_head != NULL) 1475 rl_start(ifp); 1476 1477#ifdef DEVICE_POLLING 1478done: 1479#endif 1480 RL_UNLOCK(sc); 1481 1482 return; 1483} 1484 1485/* 1486 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1487 * pointers to the fragment pointers. 1488 */ 1489static int 1490rl_encap(sc, m_head) 1491 struct rl_softc *sc; 1492 struct mbuf *m_head; 1493{ 1494 struct mbuf *m_new = NULL; 1495 1496 /* 1497 * The RealTek is brain damaged and wants longword-aligned 1498 * TX buffers, plus we can only have one fragment buffer 1499 * per packet. We have to copy pretty much all the time. 1500 */ 1501 m_new = m_defrag(m_head, M_DONTWAIT); 1502 1503 if (m_new == NULL) { 1504 m_freem(m_head); 1505 return(1); 1506 } 1507 m_head = m_new; 1508 1509 /* Pad frames to at least 60 bytes. */ 1510 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1511 /* 1512 * Make security concious people happy: zero out the 1513 * bytes in the pad area, since we don't know what 1514 * this mbuf cluster buffer's previous user might 1515 * have left in it. 1516 */ 1517 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1518 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1519 m_head->m_pkthdr.len += 1520 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1521 m_head->m_len = m_head->m_pkthdr.len; 1522 } 1523 1524 RL_CUR_TXMBUF(sc) = m_head; 1525 1526 return(0); 1527} 1528 1529/* 1530 * Main transmit routine. 1531 */ 1532 1533static void 1534rl_start(ifp) 1535 struct ifnet *ifp; 1536{ 1537 struct rl_softc *sc; 1538 struct mbuf *m_head = NULL; 1539 1540 sc = ifp->if_softc; 1541 RL_LOCK(sc); 1542 1543 while(RL_CUR_TXMBUF(sc) == NULL) { 1544 IF_DEQUEUE(&ifp->if_snd, m_head); 1545 if (m_head == NULL) 1546 break; 1547 1548 if (rl_encap(sc, m_head)) { 1549 break; 1550 } 1551 1552 /* 1553 * If there's a BPF listener, bounce a copy of this frame 1554 * to him. 1555 */ 1556 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1557 1558 /* 1559 * Transmit the frame. 1560 */ 1561 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1562 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1563 mtod(RL_CUR_TXMBUF(sc), void *), 1564 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1565 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1566 BUS_DMASYNC_PREREAD); 1567 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1568 RL_TXTHRESH(sc->rl_txthresh) | 1569 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1570 1571 RL_INC(sc->rl_cdata.cur_tx); 1572 1573 /* 1574 * Set a timeout in case the chip goes out to lunch. 1575 */ 1576 ifp->if_timer = 5; 1577 } 1578 1579 /* 1580 * We broke out of the loop because all our TX slots are 1581 * full. Mark the NIC as busy until it drains some of the 1582 * packets from the queue. 1583 */ 1584 if (RL_CUR_TXMBUF(sc) != NULL) 1585 ifp->if_flags |= IFF_OACTIVE; 1586 1587 RL_UNLOCK(sc); 1588 1589 return; 1590} 1591 1592static void 1593rl_init(xsc) 1594 void *xsc; 1595{ 1596 struct rl_softc *sc = xsc; 1597 struct ifnet *ifp = &sc->arpcom.ac_if; 1598 struct mii_data *mii; 1599 int i; 1600 u_int32_t rxcfg = 0; 1601 1602 RL_LOCK(sc); 1603 mii = device_get_softc(sc->rl_miibus); 1604 1605 /* 1606 * Cancel pending I/O and free all RX/TX buffers. 1607 */ 1608 rl_stop(sc); 1609 1610 /* Init our MAC address */ 1611 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1612 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1613 } 1614 1615 /* Init the RX buffer pointer register. */ 1616 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1617 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1618 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1619 BUS_DMASYNC_PREWRITE); 1620 1621 /* Init TX descriptors. */ 1622 rl_list_tx_init(sc); 1623 1624 /* 1625 * Enable transmit and receive. 1626 */ 1627 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1628 1629 /* 1630 * Set the initial TX and RX configuration. 1631 */ 1632 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1633 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1634 1635 /* Set the individual bit to receive frames for this host only. */ 1636 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1637 rxcfg |= RL_RXCFG_RX_INDIV; 1638 1639 /* If we want promiscuous mode, set the allframes bit. */ 1640 if (ifp->if_flags & IFF_PROMISC) { 1641 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1642 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1643 } else { 1644 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1645 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1646 } 1647 1648 /* 1649 * Set capture broadcast bit to capture broadcast frames. 1650 */ 1651 if (ifp->if_flags & IFF_BROADCAST) { 1652 rxcfg |= RL_RXCFG_RX_BROAD; 1653 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1654 } else { 1655 rxcfg &= ~RL_RXCFG_RX_BROAD; 1656 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1657 } 1658 1659 /* 1660 * Program the multicast filter, if necessary. 1661 */ 1662 rl_setmulti(sc); 1663 1664#ifdef DEVICE_POLLING 1665 /* 1666 * Disable interrupts if we are polling. 1667 */ 1668 if (ifp->if_flags & IFF_POLLING) 1669 CSR_WRITE_2(sc, RL_IMR, 0); 1670 else /* otherwise ... */ 1671#endif /* DEVICE_POLLING */ 1672 /* 1673 * Enable interrupts. 1674 */ 1675 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1676 1677 /* Set initial TX threshold */ 1678 sc->rl_txthresh = RL_TX_THRESH_INIT; 1679 1680 /* Start RX/TX process. */ 1681 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1682 1683 /* Enable receiver and transmitter. */ 1684 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1685 1686 mii_mediachg(mii); 1687 1688 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1689 1690 ifp->if_flags |= IFF_RUNNING; 1691 ifp->if_flags &= ~IFF_OACTIVE; 1692 1693 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1694 RL_UNLOCK(sc); 1695 1696 return; 1697} 1698 1699/* 1700 * Set media options. 1701 */ 1702static int 1703rl_ifmedia_upd(ifp) 1704 struct ifnet *ifp; 1705{ 1706 struct rl_softc *sc; 1707 struct mii_data *mii; 1708 1709 sc = ifp->if_softc; 1710 mii = device_get_softc(sc->rl_miibus); 1711 mii_mediachg(mii); 1712 1713 return(0); 1714} 1715 1716/* 1717 * Report current media status. 1718 */ 1719static void 1720rl_ifmedia_sts(ifp, ifmr) 1721 struct ifnet *ifp; 1722 struct ifmediareq *ifmr; 1723{ 1724 struct rl_softc *sc; 1725 struct mii_data *mii; 1726 1727 sc = ifp->if_softc; 1728 mii = device_get_softc(sc->rl_miibus); 1729 1730 mii_pollstat(mii); 1731 ifmr->ifm_active = mii->mii_media_active; 1732 ifmr->ifm_status = mii->mii_media_status; 1733 1734 return; 1735} 1736 1737static int 1738rl_ioctl(ifp, command, data) 1739 struct ifnet *ifp; 1740 u_long command; 1741 caddr_t data; 1742{ 1743 struct rl_softc *sc = ifp->if_softc; 1744 struct ifreq *ifr = (struct ifreq *) data; 1745 struct mii_data *mii; 1746 int error = 0; 1747 1748 RL_LOCK(sc); 1749 1750 switch(command) { 1751 case SIOCSIFFLAGS: 1752 if (ifp->if_flags & IFF_UP) { 1753 rl_init(sc); 1754 } else { 1755 if (ifp->if_flags & IFF_RUNNING) 1756 rl_stop(sc); 1757 } 1758 error = 0; 1759 break; 1760 case SIOCADDMULTI: 1761 case SIOCDELMULTI: 1762 rl_setmulti(sc); 1763 error = 0; 1764 break; 1765 case SIOCGIFMEDIA: 1766 case SIOCSIFMEDIA: 1767 mii = device_get_softc(sc->rl_miibus); 1768 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1769 break; 1770 default: 1771 error = ether_ioctl(ifp, command, data); 1772 break; 1773 } 1774 1775 RL_UNLOCK(sc); 1776 1777 return(error); 1778} 1779 1780static void 1781rl_watchdog(ifp) 1782 struct ifnet *ifp; 1783{ 1784 struct rl_softc *sc; 1785 1786 sc = ifp->if_softc; 1787 RL_LOCK(sc); 1788 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1789 ifp->if_oerrors++; 1790 1791 rl_txeof(sc); 1792 rl_rxeof(sc); 1793 rl_init(sc); 1794 RL_UNLOCK(sc); 1795 1796 return; 1797} 1798 1799/* 1800 * Stop the adapter and free any mbufs allocated to the 1801 * RX and TX lists. 1802 */ 1803static void 1804rl_stop(sc) 1805 struct rl_softc *sc; 1806{ 1807 register int i; 1808 struct ifnet *ifp; 1809 1810 RL_LOCK(sc); 1811 ifp = &sc->arpcom.ac_if; 1812 ifp->if_timer = 0; 1813 1814 untimeout(rl_tick, sc, sc->rl_stat_ch); 1815 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1816#ifdef DEVICE_POLLING 1817 ether_poll_deregister(ifp); 1818#endif /* DEVICE_POLLING */ 1819 1820 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1821 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1822 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1823 1824 /* 1825 * Free the TX list buffers. 1826 */ 1827 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1828 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1829 bus_dmamap_unload(sc->rl_tag, 1830 sc->rl_cdata.rl_tx_dmamap[i]); 1831 bus_dmamap_destroy(sc->rl_tag, 1832 sc->rl_cdata.rl_tx_dmamap[i]); 1833 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1834 sc->rl_cdata.rl_tx_chain[i] = NULL; 1835 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1836 } 1837 } 1838 1839 RL_UNLOCK(sc); 1840 return; 1841} 1842 1843/* 1844 * Device suspend routine. Stop the interface and save some PCI 1845 * settings in case the BIOS doesn't restore them properly on 1846 * resume. 1847 */ 1848static int 1849rl_suspend(dev) 1850 device_t dev; 1851{ 1852 register int i; 1853 struct rl_softc *sc; 1854 1855 sc = device_get_softc(dev); 1856 1857 rl_stop(sc); 1858 1859 for (i = 0; i < 5; i++) 1860 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1861 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1862 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1863 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1864 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1865 1866 sc->suspended = 1; 1867 1868 return (0); 1869} 1870 1871/* 1872 * Device resume routine. Restore some PCI settings in case the BIOS 1873 * doesn't, re-enable busmastering, and restart the interface if 1874 * appropriate. 1875 */ 1876static int 1877rl_resume(dev) 1878 device_t dev; 1879{ 1880 register int i; 1881 struct rl_softc *sc; 1882 struct ifnet *ifp; 1883 1884 sc = device_get_softc(dev); 1885 ifp = &sc->arpcom.ac_if; 1886 1887 /* better way to do this? */ 1888 for (i = 0; i < 5; i++) 1889 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1890 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1891 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1892 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1893 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1894 1895 /* reenable busmastering */ 1896 pci_enable_busmaster(dev); 1897 pci_enable_io(dev, RL_RES); 1898 1899 /* reinitialize interface if necessary */ 1900 if (ifp->if_flags & IFF_UP) 1901 rl_init(sc); 1902 1903 sc->suspended = 0; 1904 1905 return (0); 1906} 1907 1908/* 1909 * Stop all chip I/O so that the kernel's probe routines don't 1910 * get confused by errant DMAs when rebooting. 1911 */ 1912static void 1913rl_shutdown(dev) 1914 device_t dev; 1915{ 1916 struct rl_softc *sc; 1917 1918 sc = device_get_softc(dev); 1919 1920 rl_stop(sc); 1921 1922 return; 1923} 1924