if_rl.c revision 112880
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul */ 3240516Swpaul 3340516Swpaul/* 3440516Swpaul * RealTek 8129/8139 PCI NIC driver 3540516Swpaul * 3640516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3740516Swpaul * the RealTek chipset. Datasheets can be obtained from 3840516Swpaul * www.realtek.com.tw. 3940516Swpaul * 4040516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4140516Swpaul * Electrical Engineering Department 4240516Swpaul * Columbia University, New York City 4340516Swpaul */ 4440516Swpaul 4540516Swpaul/* 4640516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4740516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 4840516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 4940516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5040516Swpaul * gains that bus-master DMA usually offers. 5140516Swpaul * 5240516Swpaul * For transmission, the chip offers a series of four TX descriptor 5340516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5441569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5540516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5640516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5740516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 5840516Swpaul * four descriptor registers means that we can never have more than four 5940516Swpaul * packets queued for transmission at any one time. 6040516Swpaul * 6140516Swpaul * Reception is not much better. The driver has to allocate a single large 6240516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6340516Swpaul * frames. Because we don't know where within this region received packets 6440516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6540516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6640516Swpaul * levels. 6740516Swpaul * 6840516Swpaul * It's impossible given this rotten design to really achieve decent 6940516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7040516Swpaul * some equally overmuscled CPU to drive it. 7140516Swpaul * 7240516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7340516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7440516Swpaul * PHY registers are directly accessible through the 8139's register 7540516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7640516Swpaul * filter. 7740516Swpaul * 7840516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 7940516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8040516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8140516Swpaul * to select which interface to use depending on the chip type. 8240516Swpaul */ 8340516Swpaul 8440516Swpaul#include <sys/param.h> 85108729Sjake#include <sys/endian.h> 8640516Swpaul#include <sys/systm.h> 8740516Swpaul#include <sys/sockio.h> 8840516Swpaul#include <sys/mbuf.h> 8940516Swpaul#include <sys/malloc.h> 9040516Swpaul#include <sys/kernel.h> 9140516Swpaul#include <sys/socket.h> 9240516Swpaul 9340516Swpaul#include <net/if.h> 9440516Swpaul#include <net/if_arp.h> 9540516Swpaul#include <net/ethernet.h> 9640516Swpaul#include <net/if_dl.h> 9740516Swpaul#include <net/if_media.h> 9840516Swpaul 9940516Swpaul#include <net/bpf.h> 10040516Swpaul 10141569Swpaul#include <machine/bus_pio.h> 10241569Swpaul#include <machine/bus_memio.h> 10341569Swpaul#include <machine/bus.h> 10450703Swpaul#include <machine/resource.h> 10550703Swpaul#include <sys/bus.h> 10650703Swpaul#include <sys/rman.h> 10740516Swpaul 10850703Swpaul#include <dev/mii/mii.h> 10950703Swpaul#include <dev/mii/miivar.h> 11050703Swpaul 11140516Swpaul#include <pci/pcireg.h> 11240516Swpaul#include <pci/pcivar.h> 11340516Swpaul 11459758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11559758Speter 11651089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11750703Swpaul#include "miibus_if.h" 11850703Swpaul 11940516Swpaul/* 12040516Swpaul * Default to using PIO access for this driver. On SMP systems, 12140516Swpaul * there appear to be problems with memory mapped mode: it looks like 12240516Swpaul * doing too many memory mapped access back to back in rapid succession 12340516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12440516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12540516Swpaul * uniprocessor systems though. 12640516Swpaul */ 12740516Swpaul#define RL_USEIOSPACE 12840516Swpaul 12940516Swpaul#include <pci/if_rlreg.h> 13040516Swpaul 131109109Sdes__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 112880 2003-03-31 20:22:00Z jhb $"); 13240516Swpaul 13340516Swpaul/* 13440516Swpaul * Various supported device vendors/types and their names. 13540516Swpaul */ 13640516Swpaulstatic struct rl_type rl_devs[] = { 13740516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 13840516Swpaul "RealTek 8129 10/100BaseTX" }, 13940516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14040516Swpaul "RealTek 8139 10/100BaseTX" }, 14167771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14267771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14341243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14441243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14544238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 14644238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 14744238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 14844238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 14972813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15072813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15196112Sjhb { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 15296112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 15394400Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 15494400Swpaul "Nortel Networks 10/100BaseTX" }, 155109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 156103020Siwasaki "Corega FEther CB-TXD" }, 157109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 158109095Ssanpei "Corega FEtherII CB-TXD" }, 159111381Sdan { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 160111381Sdan "Peppercon AG ROL-F" }, 161112379Ssanpei { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 162112379Ssanpei "Planex FNW-3800-TX" }, 16340516Swpaul { 0, 0, NULL } 16440516Swpaul}; 16540516Swpaul 16692739Salfredstatic int rl_probe (device_t); 16792739Salfredstatic int rl_attach (device_t); 16892739Salfredstatic int rl_detach (device_t); 16940516Swpaul 17092739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 17140516Swpaul 17292739Salfredstatic void rl_rxeof (struct rl_softc *); 17392739Salfredstatic void rl_txeof (struct rl_softc *); 17492739Salfredstatic void rl_intr (void *); 17592739Salfredstatic void rl_tick (void *); 17692739Salfredstatic void rl_start (struct ifnet *); 17792739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17892739Salfredstatic void rl_init (void *); 17992739Salfredstatic void rl_stop (struct rl_softc *); 18092739Salfredstatic void rl_watchdog (struct ifnet *); 18192739Salfredstatic int rl_suspend (device_t); 18292739Salfredstatic int rl_resume (device_t); 18392739Salfredstatic void rl_shutdown (device_t); 18492739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 18592739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 18640516Swpaul 18792739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18892739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 18992739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 19092739Salfredstatic void rl_mii_sync (struct rl_softc *); 19192739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 19292739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 19392739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 19440516Swpaul 19592739Salfredstatic int rl_miibus_readreg (device_t, int, int); 19692739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 19792739Salfredstatic void rl_miibus_statchg (device_t); 19840516Swpaul 19992739Salfredstatic u_int8_t rl_calchash (caddr_t); 20092739Salfredstatic void rl_setmulti (struct rl_softc *); 20192739Salfredstatic void rl_reset (struct rl_softc *); 20292739Salfredstatic int rl_list_tx_init (struct rl_softc *); 20340516Swpaul 20492739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 20592739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 20681713Swpaul 20750703Swpaul#ifdef RL_USEIOSPACE 20850703Swpaul#define RL_RES SYS_RES_IOPORT 20950703Swpaul#define RL_RID RL_PCI_LOIO 21050703Swpaul#else 21150703Swpaul#define RL_RES SYS_RES_MEMORY 21250703Swpaul#define RL_RID RL_PCI_LOMEM 21350703Swpaul#endif 21450703Swpaul 21550703Swpaulstatic device_method_t rl_methods[] = { 21650703Swpaul /* Device interface */ 21750703Swpaul DEVMETHOD(device_probe, rl_probe), 21850703Swpaul DEVMETHOD(device_attach, rl_attach), 21950703Swpaul DEVMETHOD(device_detach, rl_detach), 22086822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 22186822Siwasaki DEVMETHOD(device_resume, rl_resume), 22250703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 22350703Swpaul 22450703Swpaul /* bus interface */ 22550703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22650703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22750703Swpaul 22850703Swpaul /* MII interface */ 22950703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 23050703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 23150703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 23250703Swpaul 23350703Swpaul { 0, 0 } 23450703Swpaul}; 23550703Swpaul 23650703Swpaulstatic driver_t rl_driver = { 23751455Swpaul "rl", 23850703Swpaul rl_methods, 23950703Swpaul sizeof(struct rl_softc) 24050703Swpaul}; 24150703Swpaul 24250703Swpaulstatic devclass_t rl_devclass; 24350703Swpaul 24451533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 24567931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 24651473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 24750703Swpaul 24840516Swpaul#define EE_SET(x) \ 24940516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25040516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 25140516Swpaul 25240516Swpaul#define EE_CLR(x) \ 25340516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25440516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 25540516Swpaul 25681713Swpaulstatic void 25781713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25881713Swpaul void *arg; 25981713Swpaul bus_dma_segment_t *segs; 26081713Swpaul int nseg, error; 26181713Swpaul{ 26281713Swpaul struct rl_softc *sc; 26381713Swpaul 26481713Swpaul sc = arg; 26581713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 26681713Swpaul 26781713Swpaul return; 26881713Swpaul} 26981713Swpaul 27081713Swpaulstatic void 27181713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 27281713Swpaul void *arg; 27381713Swpaul bus_dma_segment_t *segs; 27481713Swpaul int nseg, error; 27581713Swpaul{ 27681713Swpaul struct rl_softc *sc; 27781713Swpaul 27881713Swpaul sc = arg; 27981713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 28081713Swpaul 28181713Swpaul return; 28281713Swpaul} 28381713Swpaul 28440516Swpaul/* 28540516Swpaul * Send a read command and address to the EEPROM, check for ACK. 28640516Swpaul */ 287102335Salfredstatic void 288102335Salfredrl_eeprom_putbyte(sc, addr) 28940516Swpaul struct rl_softc *sc; 29041656Swpaul int addr; 29140516Swpaul{ 29240516Swpaul register int d, i; 29340516Swpaul 29467931Swpaul d = addr | sc->rl_eecmd_read; 29540516Swpaul 29640516Swpaul /* 29755170Sbillf * Feed in each bit and strobe the clock. 29840516Swpaul */ 29940516Swpaul for (i = 0x400; i; i >>= 1) { 30040516Swpaul if (d & i) { 30140516Swpaul EE_SET(RL_EE_DATAIN); 30240516Swpaul } else { 30340516Swpaul EE_CLR(RL_EE_DATAIN); 30440516Swpaul } 30540516Swpaul DELAY(100); 30640516Swpaul EE_SET(RL_EE_CLK); 30740516Swpaul DELAY(150); 30840516Swpaul EE_CLR(RL_EE_CLK); 30940516Swpaul DELAY(100); 31040516Swpaul } 31140516Swpaul 31240516Swpaul return; 31340516Swpaul} 31440516Swpaul 31540516Swpaul/* 31640516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 31740516Swpaul */ 318102335Salfredstatic void 319102335Salfredrl_eeprom_getword(sc, addr, dest) 32040516Swpaul struct rl_softc *sc; 32141656Swpaul int addr; 32240516Swpaul u_int16_t *dest; 32340516Swpaul{ 32440516Swpaul register int i; 32540516Swpaul u_int16_t word = 0; 32640516Swpaul 32740516Swpaul /* Enter EEPROM access mode. */ 32840516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32940516Swpaul 33040516Swpaul /* 33140516Swpaul * Send address of word we want to read. 33240516Swpaul */ 33340516Swpaul rl_eeprom_putbyte(sc, addr); 33440516Swpaul 33540516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33640516Swpaul 33740516Swpaul /* 33840516Swpaul * Start reading bits from EEPROM. 33940516Swpaul */ 34040516Swpaul for (i = 0x8000; i; i >>= 1) { 34140516Swpaul EE_SET(RL_EE_CLK); 34240516Swpaul DELAY(100); 34340516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 34440516Swpaul word |= i; 34540516Swpaul EE_CLR(RL_EE_CLK); 34640516Swpaul DELAY(100); 34740516Swpaul } 34840516Swpaul 34940516Swpaul /* Turn off EEPROM access mode. */ 35040516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 35140516Swpaul 35240516Swpaul *dest = word; 35340516Swpaul 35440516Swpaul return; 35540516Swpaul} 35640516Swpaul 35740516Swpaul/* 35840516Swpaul * Read a sequence of words from the EEPROM. 35940516Swpaul */ 360102335Salfredstatic void 361102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 36240516Swpaul struct rl_softc *sc; 36340516Swpaul caddr_t dest; 36440516Swpaul int off; 36540516Swpaul int cnt; 36640516Swpaul int swap; 36740516Swpaul{ 36840516Swpaul int i; 36940516Swpaul u_int16_t word = 0, *ptr; 37040516Swpaul 37140516Swpaul for (i = 0; i < cnt; i++) { 37240516Swpaul rl_eeprom_getword(sc, off + i, &word); 37340516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 37440516Swpaul if (swap) 37540516Swpaul *ptr = ntohs(word); 37640516Swpaul else 37740516Swpaul *ptr = word; 37840516Swpaul } 37940516Swpaul 38040516Swpaul return; 38140516Swpaul} 38240516Swpaul 38340516Swpaul 38440516Swpaul/* 38540516Swpaul * MII access routines are provided for the 8129, which 38640516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 38740516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 38840516Swpaul * direct access PHY registers. 38940516Swpaul */ 39040516Swpaul#define MII_SET(x) \ 39140516Swpaul CSR_WRITE_1(sc, RL_MII, \ 392105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 39340516Swpaul 39440516Swpaul#define MII_CLR(x) \ 39540516Swpaul CSR_WRITE_1(sc, RL_MII, \ 396105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 39740516Swpaul 39840516Swpaul/* 39940516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 40040516Swpaul */ 401102335Salfredstatic void 402102335Salfredrl_mii_sync(sc) 40340516Swpaul struct rl_softc *sc; 40440516Swpaul{ 40540516Swpaul register int i; 40640516Swpaul 40740516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 40840516Swpaul 40940516Swpaul for (i = 0; i < 32; i++) { 41040516Swpaul MII_SET(RL_MII_CLK); 41140516Swpaul DELAY(1); 41240516Swpaul MII_CLR(RL_MII_CLK); 41340516Swpaul DELAY(1); 41440516Swpaul } 41540516Swpaul 41640516Swpaul return; 41740516Swpaul} 41840516Swpaul 41940516Swpaul/* 42040516Swpaul * Clock a series of bits through the MII. 42140516Swpaul */ 422102335Salfredstatic void 423102335Salfredrl_mii_send(sc, bits, cnt) 42440516Swpaul struct rl_softc *sc; 42540516Swpaul u_int32_t bits; 42640516Swpaul int cnt; 42740516Swpaul{ 42840516Swpaul int i; 42940516Swpaul 43040516Swpaul MII_CLR(RL_MII_CLK); 43140516Swpaul 43240516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 433109109Sdes if (bits & i) { 43440516Swpaul MII_SET(RL_MII_DATAOUT); 435109109Sdes } else { 43640516Swpaul MII_CLR(RL_MII_DATAOUT); 437109109Sdes } 43840516Swpaul DELAY(1); 43940516Swpaul MII_CLR(RL_MII_CLK); 44040516Swpaul DELAY(1); 44140516Swpaul MII_SET(RL_MII_CLK); 44240516Swpaul } 44340516Swpaul} 44440516Swpaul 44540516Swpaul/* 44640516Swpaul * Read an PHY register through the MII. 44740516Swpaul */ 448102335Salfredstatic int 449102335Salfredrl_mii_readreg(sc, frame) 45040516Swpaul struct rl_softc *sc; 45140516Swpaul struct rl_mii_frame *frame; 452109109Sdes 45340516Swpaul{ 45467087Swpaul int i, ack; 45540516Swpaul 45667087Swpaul RL_LOCK(sc); 45740516Swpaul 45840516Swpaul /* 45940516Swpaul * Set up frame for RX. 46040516Swpaul */ 46140516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 46240516Swpaul frame->mii_opcode = RL_MII_READOP; 46340516Swpaul frame->mii_turnaround = 0; 46440516Swpaul frame->mii_data = 0; 465109109Sdes 46640516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 46740516Swpaul 46840516Swpaul /* 469109109Sdes * Turn on data xmit. 47040516Swpaul */ 47140516Swpaul MII_SET(RL_MII_DIR); 47240516Swpaul 47340516Swpaul rl_mii_sync(sc); 47440516Swpaul 47540516Swpaul /* 47640516Swpaul * Send command/address info. 47740516Swpaul */ 47840516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 47940516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 48040516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 48140516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 48240516Swpaul 48340516Swpaul /* Idle bit */ 48440516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 48540516Swpaul DELAY(1); 48640516Swpaul MII_SET(RL_MII_CLK); 48740516Swpaul DELAY(1); 48840516Swpaul 48940516Swpaul /* Turn off xmit. */ 49040516Swpaul MII_CLR(RL_MII_DIR); 49140516Swpaul 49240516Swpaul /* Check for ack */ 49340516Swpaul MII_CLR(RL_MII_CLK); 49440516Swpaul DELAY(1); 495109058Smbr ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 49640516Swpaul MII_SET(RL_MII_CLK); 49740516Swpaul DELAY(1); 49840516Swpaul 49940516Swpaul /* 50040516Swpaul * Now try reading data bits. If the ack failed, we still 50140516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 50240516Swpaul */ 50340516Swpaul if (ack) { 50440516Swpaul for(i = 0; i < 16; i++) { 50540516Swpaul MII_CLR(RL_MII_CLK); 50640516Swpaul DELAY(1); 50740516Swpaul MII_SET(RL_MII_CLK); 50840516Swpaul DELAY(1); 50940516Swpaul } 51040516Swpaul goto fail; 51140516Swpaul } 51240516Swpaul 51340516Swpaul for (i = 0x8000; i; i >>= 1) { 51440516Swpaul MII_CLR(RL_MII_CLK); 51540516Swpaul DELAY(1); 51640516Swpaul if (!ack) { 51740516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 51840516Swpaul frame->mii_data |= i; 51940516Swpaul DELAY(1); 52040516Swpaul } 52140516Swpaul MII_SET(RL_MII_CLK); 52240516Swpaul DELAY(1); 52340516Swpaul } 52440516Swpaul 52540516Swpaulfail: 52640516Swpaul 52740516Swpaul MII_CLR(RL_MII_CLK); 52840516Swpaul DELAY(1); 52940516Swpaul MII_SET(RL_MII_CLK); 53040516Swpaul DELAY(1); 53140516Swpaul 53267087Swpaul RL_UNLOCK(sc); 53340516Swpaul 53440516Swpaul if (ack) 53540516Swpaul return(1); 53640516Swpaul return(0); 53740516Swpaul} 53840516Swpaul 53940516Swpaul/* 54040516Swpaul * Write to a PHY register through the MII. 54140516Swpaul */ 542102335Salfredstatic int 543102335Salfredrl_mii_writereg(sc, frame) 54440516Swpaul struct rl_softc *sc; 54540516Swpaul struct rl_mii_frame *frame; 546109109Sdes 54740516Swpaul{ 54867087Swpaul RL_LOCK(sc); 54940516Swpaul 55040516Swpaul /* 55140516Swpaul * Set up frame for TX. 55240516Swpaul */ 55340516Swpaul 55440516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 55540516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 55640516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 557109109Sdes 55840516Swpaul /* 559109109Sdes * Turn on data output. 56040516Swpaul */ 56140516Swpaul MII_SET(RL_MII_DIR); 56240516Swpaul 56340516Swpaul rl_mii_sync(sc); 56440516Swpaul 56540516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 56640516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 56740516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 56840516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 56940516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 57040516Swpaul rl_mii_send(sc, frame->mii_data, 16); 57140516Swpaul 57240516Swpaul /* Idle bit. */ 57340516Swpaul MII_SET(RL_MII_CLK); 57440516Swpaul DELAY(1); 57540516Swpaul MII_CLR(RL_MII_CLK); 57640516Swpaul DELAY(1); 57740516Swpaul 57840516Swpaul /* 57940516Swpaul * Turn off xmit. 58040516Swpaul */ 58140516Swpaul MII_CLR(RL_MII_DIR); 58240516Swpaul 58367087Swpaul RL_UNLOCK(sc); 58440516Swpaul 58540516Swpaul return(0); 58640516Swpaul} 58740516Swpaul 588102335Salfredstatic int 589102335Salfredrl_miibus_readreg(dev, phy, reg) 59050703Swpaul device_t dev; 59150703Swpaul int phy, reg; 59250703Swpaul{ 59340516Swpaul struct rl_softc *sc; 59440516Swpaul struct rl_mii_frame frame; 59540516Swpaul u_int16_t rval = 0; 59640516Swpaul u_int16_t rl8139_reg = 0; 59740516Swpaul 59850703Swpaul sc = device_get_softc(dev); 59967087Swpaul RL_LOCK(sc); 60050703Swpaul 60140516Swpaul if (sc->rl_type == RL_8139) { 60250703Swpaul /* Pretend the internal PHY is only at address 0 */ 60367087Swpaul if (phy) { 60467087Swpaul RL_UNLOCK(sc); 60550703Swpaul return(0); 60667087Swpaul } 60740516Swpaul switch(reg) { 60850703Swpaul case MII_BMCR: 60940516Swpaul rl8139_reg = RL_BMCR; 61040516Swpaul break; 61150703Swpaul case MII_BMSR: 61240516Swpaul rl8139_reg = RL_BMSR; 61340516Swpaul break; 61450703Swpaul case MII_ANAR: 61540516Swpaul rl8139_reg = RL_ANAR; 61640516Swpaul break; 61750703Swpaul case MII_ANER: 61850703Swpaul rl8139_reg = RL_ANER; 61950703Swpaul break; 62050703Swpaul case MII_ANLPAR: 62140516Swpaul rl8139_reg = RL_LPAR; 62240516Swpaul break; 62350703Swpaul case MII_PHYIDR1: 62450703Swpaul case MII_PHYIDR2: 62567087Swpaul RL_UNLOCK(sc); 62650703Swpaul return(0); 62750703Swpaul break; 62894149Swpaul /* 62994149Swpaul * Allow the rlphy driver to read the media status 63094149Swpaul * register. If we have a link partner which does not 63194149Swpaul * support NWAY, this is the register which will tell 63294149Swpaul * us the results of parallel detection. 63394149Swpaul */ 63494149Swpaul case RL_MEDIASTAT: 63594149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 63694149Swpaul RL_UNLOCK(sc); 63794149Swpaul return(rval); 63894149Swpaul break; 63940516Swpaul default: 64040516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 64167087Swpaul RL_UNLOCK(sc); 64240516Swpaul return(0); 64340516Swpaul } 64440516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 64567087Swpaul RL_UNLOCK(sc); 64640516Swpaul return(rval); 64740516Swpaul } 64840516Swpaul 64940516Swpaul bzero((char *)&frame, sizeof(frame)); 65040516Swpaul 65150703Swpaul frame.mii_phyaddr = phy; 65240516Swpaul frame.mii_regaddr = reg; 65340516Swpaul rl_mii_readreg(sc, &frame); 65467087Swpaul RL_UNLOCK(sc); 65540516Swpaul 65640516Swpaul return(frame.mii_data); 65740516Swpaul} 65840516Swpaul 659102335Salfredstatic int 660102335Salfredrl_miibus_writereg(dev, phy, reg, data) 66150703Swpaul device_t dev; 66250703Swpaul int phy, reg, data; 66350703Swpaul{ 66440516Swpaul struct rl_softc *sc; 66540516Swpaul struct rl_mii_frame frame; 66640516Swpaul u_int16_t rl8139_reg = 0; 66740516Swpaul 66850703Swpaul sc = device_get_softc(dev); 66967087Swpaul RL_LOCK(sc); 67050703Swpaul 67140516Swpaul if (sc->rl_type == RL_8139) { 67250703Swpaul /* Pretend the internal PHY is only at address 0 */ 67367087Swpaul if (phy) { 67467087Swpaul RL_UNLOCK(sc); 67550703Swpaul return(0); 67667087Swpaul } 67740516Swpaul switch(reg) { 67850703Swpaul case MII_BMCR: 67940516Swpaul rl8139_reg = RL_BMCR; 68040516Swpaul break; 68150703Swpaul case MII_BMSR: 68240516Swpaul rl8139_reg = RL_BMSR; 68340516Swpaul break; 68450703Swpaul case MII_ANAR: 68540516Swpaul rl8139_reg = RL_ANAR; 68640516Swpaul break; 68750703Swpaul case MII_ANER: 68850703Swpaul rl8139_reg = RL_ANER; 68950703Swpaul break; 69050703Swpaul case MII_ANLPAR: 69140516Swpaul rl8139_reg = RL_LPAR; 69240516Swpaul break; 69350703Swpaul case MII_PHYIDR1: 69450703Swpaul case MII_PHYIDR2: 69567087Swpaul RL_UNLOCK(sc); 69650703Swpaul return(0); 69750703Swpaul break; 69840516Swpaul default: 69940516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 70067087Swpaul RL_UNLOCK(sc); 70150703Swpaul return(0); 70240516Swpaul } 70340516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 70467087Swpaul RL_UNLOCK(sc); 70550703Swpaul return(0); 70640516Swpaul } 70740516Swpaul 70840516Swpaul bzero((char *)&frame, sizeof(frame)); 70940516Swpaul 71050703Swpaul frame.mii_phyaddr = phy; 71140516Swpaul frame.mii_regaddr = reg; 71240516Swpaul frame.mii_data = data; 71340516Swpaul 71440516Swpaul rl_mii_writereg(sc, &frame); 71540516Swpaul 71667087Swpaul RL_UNLOCK(sc); 71750703Swpaul return(0); 71850703Swpaul} 71950703Swpaul 720102335Salfredstatic void 721102335Salfredrl_miibus_statchg(dev) 72250703Swpaul device_t dev; 72350703Swpaul{ 72440516Swpaul return; 72540516Swpaul} 72640516Swpaul 72740516Swpaul/* 72843062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 72940516Swpaul */ 730102335Salfredstatic u_int8_t 731102335Salfredrl_calchash(addr) 73241656Swpaul caddr_t addr; 73340516Swpaul{ 73440516Swpaul u_int32_t crc, carry; 73540516Swpaul int i, j; 73640516Swpaul u_int8_t c; 73740516Swpaul 73840516Swpaul /* Compute CRC for the address value. */ 73940516Swpaul crc = 0xFFFFFFFF; /* initial value */ 74040516Swpaul 74140516Swpaul for (i = 0; i < 6; i++) { 74240516Swpaul c = *(addr + i); 74340516Swpaul for (j = 0; j < 8; j++) { 74440516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 74540516Swpaul crc <<= 1; 74640516Swpaul c >>= 1; 74740516Swpaul if (carry) 74840516Swpaul crc = (crc ^ 0x04c11db6) | carry; 74940516Swpaul } 75040516Swpaul } 75140516Swpaul 75240516Swpaul /* return the filter bit position */ 75343062Swpaul return(crc >> 26); 75440516Swpaul} 75540516Swpaul 75640516Swpaul/* 75740516Swpaul * Program the 64-bit multicast hash filter. 75840516Swpaul */ 759102335Salfredstatic void 760102335Salfredrl_setmulti(sc) 76140516Swpaul struct rl_softc *sc; 76240516Swpaul{ 76340516Swpaul struct ifnet *ifp; 76440516Swpaul int h = 0; 76540516Swpaul u_int32_t hashes[2] = { 0, 0 }; 76640516Swpaul struct ifmultiaddr *ifma; 76740516Swpaul u_int32_t rxfilt; 76840516Swpaul int mcnt = 0; 76940516Swpaul 77040516Swpaul ifp = &sc->arpcom.ac_if; 77140516Swpaul 77240516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 77340516Swpaul 77443062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 77540516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 77640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 77740516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 77840516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 77940516Swpaul return; 78040516Swpaul } 78140516Swpaul 78240516Swpaul /* first, zot all the existing hash bits */ 78340516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 78440516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 78540516Swpaul 78640516Swpaul /* now program new ones */ 78772084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 78840516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 78940516Swpaul continue; 79040516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 79140516Swpaul if (h < 32) 79240516Swpaul hashes[0] |= (1 << h); 79340516Swpaul else 79440516Swpaul hashes[1] |= (1 << (h - 32)); 79540516Swpaul mcnt++; 79640516Swpaul } 79740516Swpaul 79840516Swpaul if (mcnt) 79940516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 80040516Swpaul else 80140516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 80240516Swpaul 80340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 80440516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 80540516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 80640516Swpaul 80740516Swpaul return; 80840516Swpaul} 80940516Swpaul 810102335Salfredstatic void 811102335Salfredrl_reset(sc) 81240516Swpaul struct rl_softc *sc; 81340516Swpaul{ 81440516Swpaul register int i; 81540516Swpaul 81640516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 81740516Swpaul 81840516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 81940516Swpaul DELAY(10); 82040516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 82140516Swpaul break; 82240516Swpaul } 82340516Swpaul if (i == RL_TIMEOUT) 82440516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 82540516Swpaul 826109109Sdes return; 82740516Swpaul} 82840516Swpaul 82940516Swpaul/* 83040516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 83140516Swpaul * IDs against our list and return a device name if we find a match. 83240516Swpaul */ 833102335Salfredstatic int 834102335Salfredrl_probe(dev) 83550703Swpaul device_t dev; 83640516Swpaul{ 83740516Swpaul struct rl_type *t; 83840516Swpaul 83940516Swpaul t = rl_devs; 84040516Swpaul 84140516Swpaul while(t->rl_name != NULL) { 84250703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 84350703Swpaul (pci_get_device(dev) == t->rl_did)) { 84450703Swpaul device_set_desc(dev, t->rl_name); 84550703Swpaul return(0); 84640516Swpaul } 84740516Swpaul t++; 84840516Swpaul } 84940516Swpaul 85050703Swpaul return(ENXIO); 85140516Swpaul} 85240516Swpaul 85340516Swpaul/* 85440516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 85540516Swpaul * setup and ethernet/BPF attach. 85640516Swpaul */ 857102335Salfredstatic int 858102335Salfredrl_attach(dev) 85950703Swpaul device_t dev; 86040516Swpaul{ 86140516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 86240516Swpaul u_int32_t command; 863108729Sjake u_int16_t as[3]; 86440516Swpaul struct rl_softc *sc; 86540516Swpaul struct ifnet *ifp; 86640516Swpaul u_int16_t rl_did = 0; 867108729Sjake int unit, error = 0, rid, i; 86840516Swpaul 86950703Swpaul sc = device_get_softc(dev); 87050703Swpaul unit = device_get_unit(dev); 87140516Swpaul 87293818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 87393818Sjhb MTX_DEF | MTX_RECURSE); 87469583Swpaul 87540516Swpaul /* 87640516Swpaul * Handle power management nonsense. 87740516Swpaul */ 87840516Swpaul 87970167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 88070167Swpaul u_int32_t iobase, membase, irq; 88140516Swpaul 88270167Swpaul /* Save important PCI config data. */ 88370167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 88470167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 88570167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 88640516Swpaul 88770167Swpaul /* Reset the power state. */ 88870167Swpaul printf("rl%d: chip is is in D%d power mode " 88970167Swpaul "-- setting to D0\n", unit, 89070167Swpaul pci_get_powerstate(dev)); 89140516Swpaul 89270167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 89340516Swpaul 89470167Swpaul /* Restore PCI config data. */ 89570167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 89670167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 89770167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 89840516Swpaul } 89940516Swpaul 90040516Swpaul /* 90140516Swpaul * Map control/status registers. 90240516Swpaul */ 90372813Swpaul pci_enable_busmaster(dev); 90479472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 90579472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 90661041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 90740516Swpaul 90840516Swpaul#ifdef RL_USEIOSPACE 90940516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 91040516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 91150703Swpaul error = ENXIO; 91240516Swpaul goto fail; 91340516Swpaul } 91440516Swpaul#else 91540516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 91640516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 91750703Swpaul error = ENXIO; 91840516Swpaul goto fail; 91940516Swpaul } 92050703Swpaul#endif 92140516Swpaul 922109109Sdes rid = RL_RID; 92350703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 92450703Swpaul 0, ~0, 1, RF_ACTIVE); 92550703Swpaul 92650703Swpaul if (sc->rl_res == NULL) { 92750703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 92850703Swpaul error = ENXIO; 92940516Swpaul goto fail; 93040516Swpaul } 93140516Swpaul 93269127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 93369127Sroger * unstable when left to autoselect the media 93469127Sroger * The best workaround is to set the device to the required 93569127Sroger * media type or to set it to the 10 Meg speed. 93669127Sroger */ 93769127Sroger 93869127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 93969127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 94069127Sroger } 94169127Sroger 94250703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 94350703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 94450703Swpaul 945112872Snjl /* Allocate interrupt */ 94650703Swpaul rid = 0; 94750703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 94850703Swpaul RF_SHAREABLE | RF_ACTIVE); 94950703Swpaul 95050703Swpaul if (sc->rl_irq == NULL) { 95140516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 95250703Swpaul error = ENXIO; 95340516Swpaul goto fail; 95440516Swpaul } 95540516Swpaul 95640516Swpaul /* Reset the adapter. */ 95740516Swpaul rl_reset(sc); 95867931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 95967931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 96068215Swpaul if (rl_did != 0x8129) 96167931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 96240516Swpaul 96340516Swpaul /* 96440516Swpaul * Get station address from the EEPROM. 96540516Swpaul */ 966108729Sjake rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 967108729Sjake for (i = 0; i < 3; i++) { 968108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 969108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 970108729Sjake } 97140516Swpaul 97240516Swpaul /* 97340516Swpaul * A RealTek chip was detected. Inform the world. 97440516Swpaul */ 97540516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 97640516Swpaul 97740516Swpaul sc->rl_unit = unit; 97840516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 97940516Swpaul 98040516Swpaul /* 98140516Swpaul * Now read the exact device type from the EEPROM to find 98240516Swpaul * out if it's an 8129 or 8139. 98340516Swpaul */ 98440516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 98540516Swpaul 98644238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 98767771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 98896112Sjhb rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 989109108Sdes rl_did == DLINK_DEVICEID_690TXD || 990109108Sdes rl_did == COREGA_DEVICEID_FETHERCBTXD || 991112379Ssanpei rl_did == COREGA_DEVICEID_FETHERIICBTXD || 992112379Ssanpei rl_did == PLANEX_DEVICEID_FNW3800TX) 99340516Swpaul sc->rl_type = RL_8139; 99440516Swpaul else if (rl_did == RT_DEVICEID_8129) 99540516Swpaul sc->rl_type = RL_8129; 99640516Swpaul else { 99740516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 99850703Swpaul error = ENXIO; 99940516Swpaul goto fail; 100040516Swpaul } 100140516Swpaul 100281713Swpaul /* 100381713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 100481713Swpaul */ 100581713Swpaul#define RL_NSEG_NEW 32 1006109109Sdes error = bus_dma_tag_create(NULL, /* parent */ 100781713Swpaul 1, 0, /* alignment, boundary */ 100881713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 100981713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 101081713Swpaul NULL, NULL, /* filter, filterarg */ 101181713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1012109109Sdes BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 101381713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 101481713Swpaul &sc->rl_parent_tag); 1015112872Snjl if (error) 1016112872Snjl goto fail; 101740516Swpaul 101881713Swpaul /* 101981713Swpaul * Now allocate a tag for the DMA descriptor lists. 102081713Swpaul * All of our lists are allocated as a contiguous block 102181713Swpaul * of memory. 102281713Swpaul */ 102381713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 102481713Swpaul 1, 0, /* alignment, boundary */ 102581713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 102681713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 102781713Swpaul NULL, NULL, /* filter, filterarg */ 102881713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 102981713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 103081713Swpaul 0, /* flags */ 103181713Swpaul &sc->rl_tag); 1032112872Snjl if (error) 1033112872Snjl goto fail; 103481713Swpaul 103581713Swpaul /* 103681713Swpaul * Now allocate a chunk of DMA-able memory based on the 103781713Swpaul * tag we just created. 103881713Swpaul */ 103981713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 104081713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 104181713Swpaul &sc->rl_cdata.rl_rx_dmamap); 104281713Swpaul 1043112872Snjl if (error) { 104440516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 104581713Swpaul bus_dma_tag_destroy(sc->rl_tag); 1046112872Snjl sc->rl_tag = NULL; 104740516Swpaul goto fail; 104840516Swpaul } 104940516Swpaul 105048028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 105148028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 105248028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 105348028Swpaul 105450703Swpaul /* Do MII setup */ 105550703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 105650703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 105750703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 105850703Swpaul error = ENXIO; 105950703Swpaul goto fail; 106050703Swpaul } 106150703Swpaul 106240516Swpaul ifp = &sc->arpcom.ac_if; 106340516Swpaul ifp->if_softc = sc; 106440516Swpaul ifp->if_unit = unit; 106540516Swpaul ifp->if_name = "rl"; 106640516Swpaul ifp->if_mtu = ETHERMTU; 106740516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 106840516Swpaul ifp->if_ioctl = rl_ioctl; 106940516Swpaul ifp->if_output = ether_output; 107040516Swpaul ifp->if_start = rl_start; 107140516Swpaul ifp->if_watchdog = rl_watchdog; 107240516Swpaul ifp->if_init = rl_init; 107340516Swpaul ifp->if_baudrate = 10000000; 107445633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 107540516Swpaul 1076112872Snjl callout_handle_init(&sc->rl_stat_ch); 1077112872Snjl 107840516Swpaul /* 107963090Sarchie * Call MI attach routine. 108040516Swpaul */ 1081106936Ssam ether_ifattach(ifp, eaddr); 1082106157Simp 1083106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1084106157Simp rl_intr, sc, &sc->rl_intrhand); 1085106157Simp 1086106157Simp if (error) { 1087106157Simp printf("rl%d: couldn't set up irq\n", unit); 1088106157Simp goto fail; 1089106157Simp } 1090106157Simp 109140516Swpaulfail: 1092112872Snjl if (error) 1093112872Snjl rl_detach(dev); 1094112872Snjl 1095110601Snjl return (error); 109640516Swpaul} 109740516Swpaul 1098102335Salfredstatic int 1099102335Salfredrl_detach(dev) 110050703Swpaul device_t dev; 110150703Swpaul{ 110250703Swpaul struct rl_softc *sc; 110350703Swpaul struct ifnet *ifp; 110450703Swpaul 110550703Swpaul sc = device_get_softc(dev); 1106112880Sjhb KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 110767087Swpaul RL_LOCK(sc); 110850703Swpaul ifp = &sc->arpcom.ac_if; 110950703Swpaul 1110112872Snjl if (device_is_alive(dev)) { 1111112872Snjl if (bus_child_present(dev)) 1112112872Snjl rl_stop(sc); 1113112872Snjl ether_ifdetach(ifp); 1114112872Snjl device_delete_child(dev, sc->rl_miibus); 1115112872Snjl bus_generic_detach(dev); 1116112872Snjl } 111750703Swpaul 1118112872Snjl if (sc->rl_intrhand) 1119112872Snjl bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1120112872Snjl if (sc->rl_irq) 1121112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1122112872Snjl if (sc->rl_res) 1123112872Snjl bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 112450703Swpaul 1125112872Snjl if (sc->rl_tag) { 1126112872Snjl bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1127112872Snjl bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1128112872Snjl sc->rl_cdata.rl_rx_dmamap); 1129112872Snjl bus_dma_tag_destroy(sc->rl_tag); 1130112872Snjl } 1131112872Snjl if (sc->rl_parent_tag) 1132112872Snjl bus_dma_tag_destroy(sc->rl_parent_tag); 113350703Swpaul 113467087Swpaul RL_UNLOCK(sc); 113567087Swpaul mtx_destroy(&sc->rl_mtx); 113650703Swpaul 113750703Swpaul return(0); 113850703Swpaul} 113950703Swpaul 114040516Swpaul/* 114140516Swpaul * Initialize the transmit descriptors. 114240516Swpaul */ 1143102335Salfredstatic int 1144102335Salfredrl_list_tx_init(sc) 114540516Swpaul struct rl_softc *sc; 114640516Swpaul{ 114740516Swpaul struct rl_chain_data *cd; 114840516Swpaul int i; 114940516Swpaul 115040516Swpaul cd = &sc->rl_cdata; 115140516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 115245633Swpaul cd->rl_tx_chain[i] = NULL; 115348028Swpaul CSR_WRITE_4(sc, 115448028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 115540516Swpaul } 115640516Swpaul 115745633Swpaul sc->rl_cdata.cur_tx = 0; 115845633Swpaul sc->rl_cdata.last_tx = 0; 115940516Swpaul 116040516Swpaul return(0); 116140516Swpaul} 116240516Swpaul 116340516Swpaul/* 116440516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 116540516Swpaul * the higher level protocols. 116640516Swpaul * 116740516Swpaul * You know there's something wrong with a PCI bus-master chip design 116840516Swpaul * when you have to use m_devget(). 116940516Swpaul * 117040516Swpaul * The receive operation is badly documented in the datasheet, so I'll 117140516Swpaul * attempt to document it here. The driver provides a buffer area and 117240516Swpaul * places its base address in the RX buffer start address register. 117340516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 117472645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 117540516Swpaul * of the frame and certain other status bits. Each frame (starting with 117640516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 117740516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 117840516Swpaul * the 'rx status register' mentioned in the datasheet. 117948028Swpaul * 118048028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 118178508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1182109109Sdes * as the offset argument to m_devget(). 118340516Swpaul */ 1184102335Salfredstatic void 1185102335Salfredrl_rxeof(sc) 118640516Swpaul struct rl_softc *sc; 118740516Swpaul{ 1188109109Sdes struct mbuf *m; 1189109109Sdes struct ifnet *ifp; 119040516Swpaul int total_len = 0; 119140516Swpaul u_int32_t rxstat; 119240516Swpaul caddr_t rxbufpos; 119340516Swpaul int wrap = 0; 119440516Swpaul u_int16_t cur_rx; 119540516Swpaul u_int16_t limit; 119640516Swpaul u_int16_t rx_bytes = 0, max_bytes; 119740516Swpaul 119840516Swpaul ifp = &sc->arpcom.ac_if; 119940516Swpaul 120081713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1201108729Sjake BUS_DMASYNC_POSTREAD); 120281713Swpaul 120340516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 120440516Swpaul 120540516Swpaul /* Do not try to read past this point. */ 120640516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 120740516Swpaul 120840516Swpaul if (limit < cur_rx) 120940516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 121040516Swpaul else 121140516Swpaul max_bytes = limit - cur_rx; 121240516Swpaul 121342738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 121494883Sluigi#ifdef DEVICE_POLLING 1215102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 121694883Sluigi if (sc->rxcycles <= 0) 121794883Sluigi break; 121894883Sluigi sc->rxcycles--; 121994883Sluigi } 122094883Sluigi#endif /* DEVICE_POLLING */ 122140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1222108729Sjake rxstat = le32toh(*(u_int32_t *)rxbufpos); 122340516Swpaul 122440516Swpaul /* 122540516Swpaul * Here's a totally undocumented fact for you. When the 122640516Swpaul * RealTek chip is in the process of copying a packet into 122740516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 122840516Swpaul * packet header with this value, you need to stop. The 122940516Swpaul * datasheet makes absolutely no mention of this and 123040516Swpaul * RealTek should be shot for this. 123140516Swpaul */ 123240516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 123340516Swpaul break; 1234109109Sdes 123540516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 123640516Swpaul ifp->if_ierrors++; 123750703Swpaul rl_init(sc); 123850703Swpaul return; 123940516Swpaul } 124040516Swpaul 1241109109Sdes /* No errors; receive the packet. */ 124240516Swpaul total_len = rxstat >> 16; 124340516Swpaul rx_bytes += total_len + 4; 124440516Swpaul 124540516Swpaul /* 124642051Swpaul * XXX The RealTek chip includes the CRC with every 124742051Swpaul * received frame, and there's no way to turn this 124842051Swpaul * behavior off (at least, I can't find anything in 1249109109Sdes * the manual that explains how to do it) so we have 125042051Swpaul * to trim off the CRC manually. 125142051Swpaul */ 125242051Swpaul total_len -= ETHER_CRC_LEN; 125342051Swpaul 125442051Swpaul /* 125540516Swpaul * Avoid trying to read more bytes than we know 125640516Swpaul * the chip has prepared for us. 125740516Swpaul */ 125840516Swpaul if (rx_bytes > max_bytes) 125940516Swpaul break; 126040516Swpaul 126140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 126240516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 126340516Swpaul 126440516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 126540516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 126640516Swpaul 126740516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 126840516Swpaul 126940516Swpaul if (total_len > wrap) { 127078508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 127178508Sbmilekic NULL); 127240516Swpaul if (m == NULL) { 127340516Swpaul ifp->if_ierrors++; 127452426Swpaul } else { 127540516Swpaul m_copyback(m, wrap, total_len - wrap, 127640516Swpaul sc->rl_cdata.rl_rx_buf); 127748028Swpaul } 127842051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 127940516Swpaul } else { 128078508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 128178508Sbmilekic NULL); 128240516Swpaul if (m == NULL) { 128340516Swpaul ifp->if_ierrors++; 128478508Sbmilekic } 128542051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 128640516Swpaul } 128740516Swpaul 128840516Swpaul /* 128940516Swpaul * Round up to 32-bit boundary. 129040516Swpaul */ 129140516Swpaul cur_rx = (cur_rx + 3) & ~3; 129240516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 129340516Swpaul 129440516Swpaul if (m == NULL) 129540516Swpaul continue; 129640516Swpaul 129740516Swpaul ifp->if_ipackets++; 1298106936Ssam (*ifp->if_input)(ifp, m); 129940516Swpaul } 130040516Swpaul 130140516Swpaul return; 130240516Swpaul} 130340516Swpaul 130440516Swpaul/* 130540516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 130640516Swpaul * the list buffers. 130740516Swpaul */ 1308102335Salfredstatic void 1309102335Salfredrl_txeof(sc) 131040516Swpaul struct rl_softc *sc; 131140516Swpaul{ 131240516Swpaul struct ifnet *ifp; 131340516Swpaul u_int32_t txstat; 131440516Swpaul 131540516Swpaul ifp = &sc->arpcom.ac_if; 131640516Swpaul 131740516Swpaul /* 131840516Swpaul * Go through our tx list and free mbufs for those 131940516Swpaul * frames that have been uploaded. 132040516Swpaul */ 132145633Swpaul do { 132245633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 132345633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 132445633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 132540516Swpaul break; 132640516Swpaul 132745633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 132840516Swpaul 132945633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 133081713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 133181713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 133245633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 133345633Swpaul RL_LAST_TXMBUF(sc) = NULL; 133445633Swpaul } 133545633Swpaul if (txstat & RL_TXSTAT_TX_OK) 133645633Swpaul ifp->if_opackets++; 133745633Swpaul else { 133852426Swpaul int oldthresh; 133945633Swpaul ifp->if_oerrors++; 134045633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 134145633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 134245633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 134352426Swpaul oldthresh = sc->rl_txthresh; 134452426Swpaul /* error recovery */ 134552426Swpaul rl_reset(sc); 134652426Swpaul rl_init(sc); 134752426Swpaul /* 134852426Swpaul * If there was a transmit underrun, 134952426Swpaul * bump the TX threshold. 135052426Swpaul */ 135152426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 135252426Swpaul sc->rl_txthresh = oldthresh + 32; 135352426Swpaul return; 135445633Swpaul } 135545633Swpaul RL_INC(sc->rl_cdata.last_tx); 135645633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 135745633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 135840516Swpaul 135999165Sluigi ifp->if_timer = 136099165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 136199165Sluigi 136250703Swpaul return; 136350703Swpaul} 136440516Swpaul 1365102335Salfredstatic void 1366102335Salfredrl_tick(xsc) 136750703Swpaul void *xsc; 136850703Swpaul{ 136950703Swpaul struct rl_softc *sc; 137050703Swpaul struct mii_data *mii; 137150703Swpaul 137250703Swpaul sc = xsc; 137367087Swpaul RL_LOCK(sc); 137450703Swpaul mii = device_get_softc(sc->rl_miibus); 137550703Swpaul 137650703Swpaul mii_tick(mii); 137750703Swpaul 137850703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 137967087Swpaul RL_UNLOCK(sc); 138050703Swpaul 138140516Swpaul return; 138240516Swpaul} 138340516Swpaul 138494883Sluigi#ifdef DEVICE_POLLING 138594883Sluigistatic void 138694883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 138794883Sluigi{ 138894883Sluigi struct rl_softc *sc = ifp->if_softc; 138994883Sluigi 139094883Sluigi RL_LOCK(sc); 139194883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 139294883Sluigi CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 139394883Sluigi goto done; 139494883Sluigi } 139594883Sluigi 139694883Sluigi sc->rxcycles = count; 139794883Sluigi rl_rxeof(sc); 139894883Sluigi rl_txeof(sc); 139994883Sluigi if (ifp->if_snd.ifq_head != NULL) 140094883Sluigi rl_start(ifp); 140194883Sluigi 140294883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 140394883Sluigi u_int16_t status; 140494883Sluigi 140594883Sluigi status = CSR_READ_2(sc, RL_ISR); 1406100957Sjhb if (status == 0xffff) 1407100957Sjhb goto done; 140894883Sluigi if (status) 140994883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 141094883Sluigi 141194883Sluigi /* 141294883Sluigi * XXX check behaviour on receiver stalls. 141394883Sluigi */ 141494883Sluigi 141594883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 141694883Sluigi rl_reset(sc); 141794883Sluigi rl_init(sc); 141894883Sluigi } 141994883Sluigi } 142094883Sluigidone: 142194883Sluigi RL_UNLOCK(sc); 142294883Sluigi} 142394883Sluigi#endif /* DEVICE_POLLING */ 142494883Sluigi 1425102335Salfredstatic void 1426102335Salfredrl_intr(arg) 142740516Swpaul void *arg; 142840516Swpaul{ 142940516Swpaul struct rl_softc *sc; 143040516Swpaul struct ifnet *ifp; 143140516Swpaul u_int16_t status; 143240516Swpaul 143340516Swpaul sc = arg; 143486822Siwasaki 143586822Siwasaki if (sc->suspended) { 143686822Siwasaki return; 143786822Siwasaki } 143886822Siwasaki 143967087Swpaul RL_LOCK(sc); 144040516Swpaul ifp = &sc->arpcom.ac_if; 144140516Swpaul 144294883Sluigi#ifdef DEVICE_POLLING 1443102052Ssobomax if (ifp->if_flags & IFF_POLLING) 144494883Sluigi goto done; 144594883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 144694883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 144794883Sluigi rl_poll(ifp, 0, 1); 144894883Sluigi goto done; 144994883Sluigi } 145094883Sluigi#endif /* DEVICE_POLLING */ 145140516Swpaul 145240516Swpaul for (;;) { 145340516Swpaul 145440516Swpaul status = CSR_READ_2(sc, RL_ISR); 1455100957Sjhb /* If the card has gone away the read returns 0xffff. */ 1456100957Sjhb if (status == 0xffff) 1457100957Sjhb break; 145840516Swpaul if (status) 145940516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 146040516Swpaul 146140516Swpaul if ((status & RL_INTRS) == 0) 146240516Swpaul break; 146340516Swpaul 146440516Swpaul if (status & RL_ISR_RX_OK) 146540516Swpaul rl_rxeof(sc); 146640516Swpaul 146740516Swpaul if (status & RL_ISR_RX_ERR) 146840516Swpaul rl_rxeof(sc); 146940516Swpaul 147045633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 147140516Swpaul rl_txeof(sc); 147240516Swpaul 147340516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 147440516Swpaul rl_reset(sc); 147540516Swpaul rl_init(sc); 147640516Swpaul } 147740516Swpaul 147840516Swpaul } 147940516Swpaul 148052426Swpaul if (ifp->if_snd.ifq_head != NULL) 148140516Swpaul rl_start(ifp); 148240516Swpaul 148394883Sluigi#ifdef DEVICE_POLLING 148494883Sluigidone: 148594883Sluigi#endif 148667087Swpaul RL_UNLOCK(sc); 148767087Swpaul 148840516Swpaul return; 148940516Swpaul} 149040516Swpaul 149140516Swpaul/* 149240516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 149340516Swpaul * pointers to the fragment pointers. 149440516Swpaul */ 1495102335Salfredstatic int 1496102335Salfredrl_encap(sc, m_head) 149740516Swpaul struct rl_softc *sc; 149840516Swpaul struct mbuf *m_head; 149940516Swpaul{ 150041243Swpaul struct mbuf *m_new = NULL; 150140516Swpaul 150240516Swpaul /* 150345633Swpaul * The RealTek is brain damaged and wants longword-aligned 150445633Swpaul * TX buffers, plus we can only have one fragment buffer 150545633Swpaul * per packet. We have to copy pretty much all the time. 150640516Swpaul */ 1507112839Ssilby m_new = m_defrag(m_head, M_DONTWAIT); 150840516Swpaul 150987846Sluigi if (m_new == NULL) 151041243Swpaul return(1); 151141243Swpaul m_head = m_new; 151240516Swpaul 151340516Swpaul /* Pad frames to at least 60 bytes. */ 151441243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 151555058Swpaul /* 151655058Swpaul * Make security concious people happy: zero out the 151755058Swpaul * bytes in the pad area, since we don't know what 151855058Swpaul * this mbuf cluster buffer's previous user might 151955058Swpaul * have left in it. 1520109109Sdes */ 152155058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 152255058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 152340516Swpaul m_head->m_pkthdr.len += 152452426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 152541243Swpaul m_head->m_len = m_head->m_pkthdr.len; 152641243Swpaul } 152740516Swpaul 152845633Swpaul RL_CUR_TXMBUF(sc) = m_head; 152940516Swpaul 153040516Swpaul return(0); 153140516Swpaul} 153240516Swpaul 153340516Swpaul/* 153440516Swpaul * Main transmit routine. 153540516Swpaul */ 153640516Swpaul 1537102335Salfredstatic void 1538102335Salfredrl_start(ifp) 153940516Swpaul struct ifnet *ifp; 154040516Swpaul{ 154140516Swpaul struct rl_softc *sc; 154240516Swpaul struct mbuf *m_head = NULL; 154340516Swpaul 154440516Swpaul sc = ifp->if_softc; 154567087Swpaul RL_LOCK(sc); 154640516Swpaul 154745633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 154840516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 154940516Swpaul if (m_head == NULL) 155040516Swpaul break; 155140516Swpaul 155258801Swpaul if (rl_encap(sc, m_head)) { 155358801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 155458801Swpaul ifp->if_flags |= IFF_OACTIVE; 155558801Swpaul break; 155658801Swpaul } 155740516Swpaul 155840516Swpaul /* 155940516Swpaul * If there's a BPF listener, bounce a copy of this frame 156040516Swpaul * to him. 156140516Swpaul */ 1562106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 156351583Swpaul 156440516Swpaul /* 156540516Swpaul * Transmit the frame. 1566109109Sdes */ 156781713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 156881713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 156981713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 157081713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 157181713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 157281713Swpaul BUS_DMASYNC_PREREAD); 157345633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 157452426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 157552426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 157645633Swpaul 157745633Swpaul RL_INC(sc->rl_cdata.cur_tx); 157840516Swpaul } 157940516Swpaul 158040516Swpaul /* 158145633Swpaul * We broke out of the loop because all our TX slots are 158245633Swpaul * full. Mark the NIC as busy until it drains some of the 158345633Swpaul * packets from the queue. 158445633Swpaul */ 158545633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 158645633Swpaul ifp->if_flags |= IFF_OACTIVE; 158745633Swpaul 158845633Swpaul /* 158940516Swpaul * Set a timeout in case the chip goes out to lunch. 159040516Swpaul */ 159140516Swpaul ifp->if_timer = 5; 159267087Swpaul RL_UNLOCK(sc); 159340516Swpaul 159440516Swpaul return; 159540516Swpaul} 159640516Swpaul 1597102335Salfredstatic void 1598102335Salfredrl_init(xsc) 159940516Swpaul void *xsc; 160040516Swpaul{ 160140516Swpaul struct rl_softc *sc = xsc; 160240516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160350703Swpaul struct mii_data *mii; 160467087Swpaul int i; 160540516Swpaul u_int32_t rxcfg = 0; 160640516Swpaul 160767087Swpaul RL_LOCK(sc); 160850703Swpaul mii = device_get_softc(sc->rl_miibus); 160940516Swpaul 161040516Swpaul /* 161140516Swpaul * Cancel pending I/O and free all RX/TX buffers. 161240516Swpaul */ 161340516Swpaul rl_stop(sc); 161440516Swpaul 161540516Swpaul /* Init our MAC address */ 161640516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 161740516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 161840516Swpaul } 161940516Swpaul 162040516Swpaul /* Init the RX buffer pointer register. */ 162181713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 162281713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 162381713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 162481713Swpaul BUS_DMASYNC_PREWRITE); 162540516Swpaul 162640516Swpaul /* Init TX descriptors. */ 162740516Swpaul rl_list_tx_init(sc); 162840516Swpaul 162940516Swpaul /* 163040516Swpaul * Enable transmit and receive. 163140516Swpaul */ 163240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 163340516Swpaul 163440516Swpaul /* 163545633Swpaul * Set the initial TX and RX configuration. 163640516Swpaul */ 163745633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 163840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 163940516Swpaul 164040516Swpaul /* Set the individual bit to receive frames for this host only. */ 164140516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 164240516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 164340516Swpaul 164440516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 164540516Swpaul if (ifp->if_flags & IFF_PROMISC) { 164640516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 164740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 164840516Swpaul } else { 164940516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 165040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165140516Swpaul } 165240516Swpaul 165340516Swpaul /* 165440516Swpaul * Set capture broadcast bit to capture broadcast frames. 165540516Swpaul */ 165640516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 165740516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 165840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165940516Swpaul } else { 166040516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 166140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 166240516Swpaul } 166340516Swpaul 166440516Swpaul /* 166540516Swpaul * Program the multicast filter, if necessary. 166640516Swpaul */ 166740516Swpaul rl_setmulti(sc); 166840516Swpaul 166994883Sluigi#ifdef DEVICE_POLLING 167040516Swpaul /* 167194883Sluigi * Disable interrupts if we are polling. 167294883Sluigi */ 1673102052Ssobomax if (ifp->if_flags & IFF_POLLING) 167494883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 167594883Sluigi else /* otherwise ... */ 167694883Sluigi#endif /* DEVICE_POLLING */ 167794883Sluigi /* 167840516Swpaul * Enable interrupts. 167940516Swpaul */ 168040516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 168140516Swpaul 168252426Swpaul /* Set initial TX threshold */ 168352426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 168452426Swpaul 168540516Swpaul /* Start RX/TX process. */ 168640516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 168740516Swpaul 168840516Swpaul /* Enable receiver and transmitter. */ 168940516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 169040516Swpaul 169150703Swpaul mii_mediachg(mii); 169240516Swpaul 169340516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 169440516Swpaul 169540516Swpaul ifp->if_flags |= IFF_RUNNING; 169640516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 169740516Swpaul 169850703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 169967087Swpaul RL_UNLOCK(sc); 170050703Swpaul 170140516Swpaul return; 170240516Swpaul} 170340516Swpaul 170440516Swpaul/* 170540516Swpaul * Set media options. 170640516Swpaul */ 1707102335Salfredstatic int 1708102335Salfredrl_ifmedia_upd(ifp) 170940516Swpaul struct ifnet *ifp; 171040516Swpaul{ 171140516Swpaul struct rl_softc *sc; 171250703Swpaul struct mii_data *mii; 171340516Swpaul 171440516Swpaul sc = ifp->if_softc; 171550703Swpaul mii = device_get_softc(sc->rl_miibus); 171650703Swpaul mii_mediachg(mii); 171740516Swpaul 171840516Swpaul return(0); 171940516Swpaul} 172040516Swpaul 172140516Swpaul/* 172240516Swpaul * Report current media status. 172340516Swpaul */ 1724102335Salfredstatic void 1725102335Salfredrl_ifmedia_sts(ifp, ifmr) 172640516Swpaul struct ifnet *ifp; 172740516Swpaul struct ifmediareq *ifmr; 172840516Swpaul{ 172940516Swpaul struct rl_softc *sc; 173050703Swpaul struct mii_data *mii; 173140516Swpaul 173240516Swpaul sc = ifp->if_softc; 173350703Swpaul mii = device_get_softc(sc->rl_miibus); 173440516Swpaul 173550703Swpaul mii_pollstat(mii); 173650703Swpaul ifmr->ifm_active = mii->mii_media_active; 173750703Swpaul ifmr->ifm_status = mii->mii_media_status; 173840516Swpaul 173940516Swpaul return; 174040516Swpaul} 174140516Swpaul 1742102335Salfredstatic int 1743102335Salfredrl_ioctl(ifp, command, data) 174440516Swpaul struct ifnet *ifp; 174540516Swpaul u_long command; 174640516Swpaul caddr_t data; 174740516Swpaul{ 174840516Swpaul struct rl_softc *sc = ifp->if_softc; 174940516Swpaul struct ifreq *ifr = (struct ifreq *) data; 175050703Swpaul struct mii_data *mii; 175167087Swpaul int error = 0; 175240516Swpaul 175367087Swpaul RL_LOCK(sc); 175440516Swpaul 175540516Swpaul switch(command) { 175640516Swpaul case SIOCSIFFLAGS: 175740516Swpaul if (ifp->if_flags & IFF_UP) { 175840516Swpaul rl_init(sc); 175940516Swpaul } else { 176040516Swpaul if (ifp->if_flags & IFF_RUNNING) 176140516Swpaul rl_stop(sc); 176240516Swpaul } 176340516Swpaul error = 0; 176440516Swpaul break; 176540516Swpaul case SIOCADDMULTI: 176640516Swpaul case SIOCDELMULTI: 176740516Swpaul rl_setmulti(sc); 176840516Swpaul error = 0; 176940516Swpaul break; 177040516Swpaul case SIOCGIFMEDIA: 177140516Swpaul case SIOCSIFMEDIA: 177250703Swpaul mii = device_get_softc(sc->rl_miibus); 177350703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 177440516Swpaul break; 177540516Swpaul default: 1776106936Ssam error = ether_ioctl(ifp, command, data); 177740516Swpaul break; 177840516Swpaul } 177940516Swpaul 178067087Swpaul RL_UNLOCK(sc); 178140516Swpaul 178240516Swpaul return(error); 178340516Swpaul} 178440516Swpaul 1785102335Salfredstatic void 1786102335Salfredrl_watchdog(ifp) 178740516Swpaul struct ifnet *ifp; 178840516Swpaul{ 178940516Swpaul struct rl_softc *sc; 179040516Swpaul 179140516Swpaul sc = ifp->if_softc; 179267087Swpaul RL_LOCK(sc); 179340516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 179440516Swpaul ifp->if_oerrors++; 179550703Swpaul 179640516Swpaul rl_txeof(sc); 179740516Swpaul rl_rxeof(sc); 179840516Swpaul rl_init(sc); 179967087Swpaul RL_UNLOCK(sc); 180040516Swpaul 180140516Swpaul return; 180240516Swpaul} 180340516Swpaul 180440516Swpaul/* 180540516Swpaul * Stop the adapter and free any mbufs allocated to the 180640516Swpaul * RX and TX lists. 180740516Swpaul */ 1808102335Salfredstatic void 1809102335Salfredrl_stop(sc) 181040516Swpaul struct rl_softc *sc; 181140516Swpaul{ 181240516Swpaul register int i; 181340516Swpaul struct ifnet *ifp; 181440516Swpaul 181567087Swpaul RL_LOCK(sc); 181640516Swpaul ifp = &sc->arpcom.ac_if; 181740516Swpaul ifp->if_timer = 0; 181840516Swpaul 181950703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 182094883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 182194883Sluigi#ifdef DEVICE_POLLING 182294883Sluigi ether_poll_deregister(ifp); 182394883Sluigi#endif /* DEVICE_POLLING */ 182450703Swpaul 182540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 182640516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 182781713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 182840516Swpaul 182940516Swpaul /* 183040516Swpaul * Free the TX list buffers. 183140516Swpaul */ 183240516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 183345633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 183481713Swpaul bus_dmamap_unload(sc->rl_tag, 183581713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 183681713Swpaul bus_dmamap_destroy(sc->rl_tag, 183781713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 183845633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 183945633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 184045633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 184140516Swpaul } 184240516Swpaul } 184340516Swpaul 184467087Swpaul RL_UNLOCK(sc); 184540516Swpaul return; 184640516Swpaul} 184740516Swpaul 184840516Swpaul/* 184986822Siwasaki * Device suspend routine. Stop the interface and save some PCI 185086822Siwasaki * settings in case the BIOS doesn't restore them properly on 185186822Siwasaki * resume. 185286822Siwasaki */ 1853102335Salfredstatic int 1854102335Salfredrl_suspend(dev) 185586822Siwasaki device_t dev; 185686822Siwasaki{ 185786822Siwasaki register int i; 185886822Siwasaki struct rl_softc *sc; 185986822Siwasaki 186086822Siwasaki sc = device_get_softc(dev); 186186822Siwasaki 186286822Siwasaki rl_stop(sc); 186386822Siwasaki 186486822Siwasaki for (i = 0; i < 5; i++) 186586822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 186686822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 186786822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 186886822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 186986822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 187086822Siwasaki 187186822Siwasaki sc->suspended = 1; 187286822Siwasaki 187386822Siwasaki return (0); 187486822Siwasaki} 187586822Siwasaki 187686822Siwasaki/* 187786822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 187886822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 187986822Siwasaki * appropriate. 188086822Siwasaki */ 1881102335Salfredstatic int 1882102335Salfredrl_resume(dev) 188386822Siwasaki device_t dev; 188486822Siwasaki{ 188586822Siwasaki register int i; 188686822Siwasaki struct rl_softc *sc; 188786822Siwasaki struct ifnet *ifp; 188886822Siwasaki 188986822Siwasaki sc = device_get_softc(dev); 189086822Siwasaki ifp = &sc->arpcom.ac_if; 189186822Siwasaki 189286822Siwasaki /* better way to do this? */ 189386822Siwasaki for (i = 0; i < 5; i++) 189486822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 189586822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 189686822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 189786822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 189886822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 189986822Siwasaki 190086822Siwasaki /* reenable busmastering */ 190186822Siwasaki pci_enable_busmaster(dev); 190286822Siwasaki pci_enable_io(dev, RL_RES); 190386822Siwasaki 1904109109Sdes /* reinitialize interface if necessary */ 1905109109Sdes if (ifp->if_flags & IFF_UP) 1906109109Sdes rl_init(sc); 190786822Siwasaki 190886822Siwasaki sc->suspended = 0; 190986822Siwasaki 191086822Siwasaki return (0); 191186822Siwasaki} 191286822Siwasaki 191386822Siwasaki/* 191440516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 191540516Swpaul * get confused by errant DMAs when rebooting. 191640516Swpaul */ 1917102335Salfredstatic void 1918102335Salfredrl_shutdown(dev) 191950703Swpaul device_t dev; 192040516Swpaul{ 192150703Swpaul struct rl_softc *sc; 192240516Swpaul 192350703Swpaul sc = device_get_softc(dev); 192450703Swpaul 192540516Swpaul rl_stop(sc); 192640516Swpaul 192740516Swpaul return; 192840516Swpaul} 1929