if_rl.c revision 109109
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul */ 3240516Swpaul 3340516Swpaul/* 3440516Swpaul * RealTek 8129/8139 PCI NIC driver 3540516Swpaul * 3640516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3740516Swpaul * the RealTek chipset. Datasheets can be obtained from 3840516Swpaul * www.realtek.com.tw. 3940516Swpaul * 4040516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4140516Swpaul * Electrical Engineering Department 4240516Swpaul * Columbia University, New York City 4340516Swpaul */ 4440516Swpaul 4540516Swpaul/* 4640516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4740516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 4840516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 4940516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5040516Swpaul * gains that bus-master DMA usually offers. 5140516Swpaul * 5240516Swpaul * For transmission, the chip offers a series of four TX descriptor 5340516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5441569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5540516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5640516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5740516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 5840516Swpaul * four descriptor registers means that we can never have more than four 5940516Swpaul * packets queued for transmission at any one time. 6040516Swpaul * 6140516Swpaul * Reception is not much better. The driver has to allocate a single large 6240516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6340516Swpaul * frames. Because we don't know where within this region received packets 6440516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6540516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6640516Swpaul * levels. 6740516Swpaul * 6840516Swpaul * It's impossible given this rotten design to really achieve decent 6940516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7040516Swpaul * some equally overmuscled CPU to drive it. 7140516Swpaul * 7240516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7340516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7440516Swpaul * PHY registers are directly accessible through the 8139's register 7540516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7640516Swpaul * filter. 7740516Swpaul * 7840516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 7940516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8040516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8140516Swpaul * to select which interface to use depending on the chip type. 8240516Swpaul */ 8340516Swpaul 8440516Swpaul#include <sys/param.h> 85108729Sjake#include <sys/endian.h> 8640516Swpaul#include <sys/systm.h> 8740516Swpaul#include <sys/sockio.h> 8840516Swpaul#include <sys/mbuf.h> 8940516Swpaul#include <sys/malloc.h> 9040516Swpaul#include <sys/kernel.h> 9140516Swpaul#include <sys/socket.h> 9240516Swpaul 9340516Swpaul#include <net/if.h> 9440516Swpaul#include <net/if_arp.h> 9540516Swpaul#include <net/ethernet.h> 9640516Swpaul#include <net/if_dl.h> 9740516Swpaul#include <net/if_media.h> 9840516Swpaul 9940516Swpaul#include <net/bpf.h> 10040516Swpaul 10141569Swpaul#include <machine/bus_pio.h> 10241569Swpaul#include <machine/bus_memio.h> 10341569Swpaul#include <machine/bus.h> 10450703Swpaul#include <machine/resource.h> 10550703Swpaul#include <sys/bus.h> 10650703Swpaul#include <sys/rman.h> 10740516Swpaul 10850703Swpaul#include <dev/mii/mii.h> 10950703Swpaul#include <dev/mii/miivar.h> 11050703Swpaul 11140516Swpaul#include <pci/pcireg.h> 11240516Swpaul#include <pci/pcivar.h> 11340516Swpaul 11459758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11559758Speter 11651089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11750703Swpaul#include "miibus_if.h" 11850703Swpaul 11940516Swpaul/* 12040516Swpaul * Default to using PIO access for this driver. On SMP systems, 12140516Swpaul * there appear to be problems with memory mapped mode: it looks like 12240516Swpaul * doing too many memory mapped access back to back in rapid succession 12340516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12440516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12540516Swpaul * uniprocessor systems though. 12640516Swpaul */ 12740516Swpaul#define RL_USEIOSPACE 12840516Swpaul 12940516Swpaul#include <pci/if_rlreg.h> 13040516Swpaul 131109109Sdes__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 109109 2003-01-11 16:11:21Z des $"); 13240516Swpaul 13340516Swpaul/* 13440516Swpaul * Various supported device vendors/types and their names. 13540516Swpaul */ 13640516Swpaulstatic struct rl_type rl_devs[] = { 13740516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 13840516Swpaul "RealTek 8129 10/100BaseTX" }, 13940516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14040516Swpaul "RealTek 8139 10/100BaseTX" }, 14167771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14267771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14341243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14441243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14544238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 14644238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 14744238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 14844238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 14972813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15072813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15196112Sjhb { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 15296112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 15394400Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 15494400Swpaul "Nortel Networks 10/100BaseTX" }, 155109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 156103020Siwasaki "Corega FEther CB-TXD" }, 157109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 158109095Ssanpei "Corega FEtherII CB-TXD" }, 15940516Swpaul { 0, 0, NULL } 16040516Swpaul}; 16140516Swpaul 16292739Salfredstatic int rl_probe (device_t); 16392739Salfredstatic int rl_attach (device_t); 16492739Salfredstatic int rl_detach (device_t); 16540516Swpaul 16692739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 16740516Swpaul 16892739Salfredstatic void rl_rxeof (struct rl_softc *); 16992739Salfredstatic void rl_txeof (struct rl_softc *); 17092739Salfredstatic void rl_intr (void *); 17192739Salfredstatic void rl_tick (void *); 17292739Salfredstatic void rl_start (struct ifnet *); 17392739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17492739Salfredstatic void rl_init (void *); 17592739Salfredstatic void rl_stop (struct rl_softc *); 17692739Salfredstatic void rl_watchdog (struct ifnet *); 17792739Salfredstatic int rl_suspend (device_t); 17892739Salfredstatic int rl_resume (device_t); 17992739Salfredstatic void rl_shutdown (device_t); 18092739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 18192739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 18240516Swpaul 18392739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18492739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 18592739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 18692739Salfredstatic void rl_mii_sync (struct rl_softc *); 18792739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 18892739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 18992739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 19040516Swpaul 19192739Salfredstatic int rl_miibus_readreg (device_t, int, int); 19292739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 19392739Salfredstatic void rl_miibus_statchg (device_t); 19440516Swpaul 19592739Salfredstatic u_int8_t rl_calchash (caddr_t); 19692739Salfredstatic void rl_setmulti (struct rl_softc *); 19792739Salfredstatic void rl_reset (struct rl_softc *); 19892739Salfredstatic int rl_list_tx_init (struct rl_softc *); 19940516Swpaul 20092739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 20192739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 20281713Swpaul 20350703Swpaul#ifdef RL_USEIOSPACE 20450703Swpaul#define RL_RES SYS_RES_IOPORT 20550703Swpaul#define RL_RID RL_PCI_LOIO 20650703Swpaul#else 20750703Swpaul#define RL_RES SYS_RES_MEMORY 20850703Swpaul#define RL_RID RL_PCI_LOMEM 20950703Swpaul#endif 21050703Swpaul 21150703Swpaulstatic device_method_t rl_methods[] = { 21250703Swpaul /* Device interface */ 21350703Swpaul DEVMETHOD(device_probe, rl_probe), 21450703Swpaul DEVMETHOD(device_attach, rl_attach), 21550703Swpaul DEVMETHOD(device_detach, rl_detach), 21686822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 21786822Siwasaki DEVMETHOD(device_resume, rl_resume), 21850703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 21950703Swpaul 22050703Swpaul /* bus interface */ 22150703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22250703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22350703Swpaul 22450703Swpaul /* MII interface */ 22550703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 22650703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 22750703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 22850703Swpaul 22950703Swpaul { 0, 0 } 23050703Swpaul}; 23150703Swpaul 23250703Swpaulstatic driver_t rl_driver = { 23351455Swpaul "rl", 23450703Swpaul rl_methods, 23550703Swpaul sizeof(struct rl_softc) 23650703Swpaul}; 23750703Swpaul 23850703Swpaulstatic devclass_t rl_devclass; 23950703Swpaul 24051533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 24167931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 24251473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 24350703Swpaul 24440516Swpaul#define EE_SET(x) \ 24540516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24640516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 24740516Swpaul 24840516Swpaul#define EE_CLR(x) \ 24940516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25040516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 25140516Swpaul 25281713Swpaulstatic void 25381713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25481713Swpaul void *arg; 25581713Swpaul bus_dma_segment_t *segs; 25681713Swpaul int nseg, error; 25781713Swpaul{ 25881713Swpaul struct rl_softc *sc; 25981713Swpaul 26081713Swpaul sc = arg; 26181713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 26281713Swpaul 26381713Swpaul return; 26481713Swpaul} 26581713Swpaul 26681713Swpaulstatic void 26781713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 26881713Swpaul void *arg; 26981713Swpaul bus_dma_segment_t *segs; 27081713Swpaul int nseg, error; 27181713Swpaul{ 27281713Swpaul struct rl_softc *sc; 27381713Swpaul 27481713Swpaul sc = arg; 27581713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 27681713Swpaul 27781713Swpaul return; 27881713Swpaul} 27981713Swpaul 28040516Swpaul/* 28140516Swpaul * Send a read command and address to the EEPROM, check for ACK. 28240516Swpaul */ 283102335Salfredstatic void 284102335Salfredrl_eeprom_putbyte(sc, addr) 28540516Swpaul struct rl_softc *sc; 28641656Swpaul int addr; 28740516Swpaul{ 28840516Swpaul register int d, i; 28940516Swpaul 29067931Swpaul d = addr | sc->rl_eecmd_read; 29140516Swpaul 29240516Swpaul /* 29355170Sbillf * Feed in each bit and strobe the clock. 29440516Swpaul */ 29540516Swpaul for (i = 0x400; i; i >>= 1) { 29640516Swpaul if (d & i) { 29740516Swpaul EE_SET(RL_EE_DATAIN); 29840516Swpaul } else { 29940516Swpaul EE_CLR(RL_EE_DATAIN); 30040516Swpaul } 30140516Swpaul DELAY(100); 30240516Swpaul EE_SET(RL_EE_CLK); 30340516Swpaul DELAY(150); 30440516Swpaul EE_CLR(RL_EE_CLK); 30540516Swpaul DELAY(100); 30640516Swpaul } 30740516Swpaul 30840516Swpaul return; 30940516Swpaul} 31040516Swpaul 31140516Swpaul/* 31240516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 31340516Swpaul */ 314102335Salfredstatic void 315102335Salfredrl_eeprom_getword(sc, addr, dest) 31640516Swpaul struct rl_softc *sc; 31741656Swpaul int addr; 31840516Swpaul u_int16_t *dest; 31940516Swpaul{ 32040516Swpaul register int i; 32140516Swpaul u_int16_t word = 0; 32240516Swpaul 32340516Swpaul /* Enter EEPROM access mode. */ 32440516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32540516Swpaul 32640516Swpaul /* 32740516Swpaul * Send address of word we want to read. 32840516Swpaul */ 32940516Swpaul rl_eeprom_putbyte(sc, addr); 33040516Swpaul 33140516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33240516Swpaul 33340516Swpaul /* 33440516Swpaul * Start reading bits from EEPROM. 33540516Swpaul */ 33640516Swpaul for (i = 0x8000; i; i >>= 1) { 33740516Swpaul EE_SET(RL_EE_CLK); 33840516Swpaul DELAY(100); 33940516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 34040516Swpaul word |= i; 34140516Swpaul EE_CLR(RL_EE_CLK); 34240516Swpaul DELAY(100); 34340516Swpaul } 34440516Swpaul 34540516Swpaul /* Turn off EEPROM access mode. */ 34640516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 34740516Swpaul 34840516Swpaul *dest = word; 34940516Swpaul 35040516Swpaul return; 35140516Swpaul} 35240516Swpaul 35340516Swpaul/* 35440516Swpaul * Read a sequence of words from the EEPROM. 35540516Swpaul */ 356102335Salfredstatic void 357102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 35840516Swpaul struct rl_softc *sc; 35940516Swpaul caddr_t dest; 36040516Swpaul int off; 36140516Swpaul int cnt; 36240516Swpaul int swap; 36340516Swpaul{ 36440516Swpaul int i; 36540516Swpaul u_int16_t word = 0, *ptr; 36640516Swpaul 36740516Swpaul for (i = 0; i < cnt; i++) { 36840516Swpaul rl_eeprom_getword(sc, off + i, &word); 36940516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 37040516Swpaul if (swap) 37140516Swpaul *ptr = ntohs(word); 37240516Swpaul else 37340516Swpaul *ptr = word; 37440516Swpaul } 37540516Swpaul 37640516Swpaul return; 37740516Swpaul} 37840516Swpaul 37940516Swpaul 38040516Swpaul/* 38140516Swpaul * MII access routines are provided for the 8129, which 38240516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 38340516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 38440516Swpaul * direct access PHY registers. 38540516Swpaul */ 38640516Swpaul#define MII_SET(x) \ 38740516Swpaul CSR_WRITE_1(sc, RL_MII, \ 388105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 38940516Swpaul 39040516Swpaul#define MII_CLR(x) \ 39140516Swpaul CSR_WRITE_1(sc, RL_MII, \ 392105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 39340516Swpaul 39440516Swpaul/* 39540516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 39640516Swpaul */ 397102335Salfredstatic void 398102335Salfredrl_mii_sync(sc) 39940516Swpaul struct rl_softc *sc; 40040516Swpaul{ 40140516Swpaul register int i; 40240516Swpaul 40340516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 40440516Swpaul 40540516Swpaul for (i = 0; i < 32; i++) { 40640516Swpaul MII_SET(RL_MII_CLK); 40740516Swpaul DELAY(1); 40840516Swpaul MII_CLR(RL_MII_CLK); 40940516Swpaul DELAY(1); 41040516Swpaul } 41140516Swpaul 41240516Swpaul return; 41340516Swpaul} 41440516Swpaul 41540516Swpaul/* 41640516Swpaul * Clock a series of bits through the MII. 41740516Swpaul */ 418102335Salfredstatic void 419102335Salfredrl_mii_send(sc, bits, cnt) 42040516Swpaul struct rl_softc *sc; 42140516Swpaul u_int32_t bits; 42240516Swpaul int cnt; 42340516Swpaul{ 42440516Swpaul int i; 42540516Swpaul 42640516Swpaul MII_CLR(RL_MII_CLK); 42740516Swpaul 42840516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 429109109Sdes if (bits & i) { 43040516Swpaul MII_SET(RL_MII_DATAOUT); 431109109Sdes } else { 43240516Swpaul MII_CLR(RL_MII_DATAOUT); 433109109Sdes } 43440516Swpaul DELAY(1); 43540516Swpaul MII_CLR(RL_MII_CLK); 43640516Swpaul DELAY(1); 43740516Swpaul MII_SET(RL_MII_CLK); 43840516Swpaul } 43940516Swpaul} 44040516Swpaul 44140516Swpaul/* 44240516Swpaul * Read an PHY register through the MII. 44340516Swpaul */ 444102335Salfredstatic int 445102335Salfredrl_mii_readreg(sc, frame) 44640516Swpaul struct rl_softc *sc; 44740516Swpaul struct rl_mii_frame *frame; 448109109Sdes 44940516Swpaul{ 45067087Swpaul int i, ack; 45140516Swpaul 45267087Swpaul RL_LOCK(sc); 45340516Swpaul 45440516Swpaul /* 45540516Swpaul * Set up frame for RX. 45640516Swpaul */ 45740516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 45840516Swpaul frame->mii_opcode = RL_MII_READOP; 45940516Swpaul frame->mii_turnaround = 0; 46040516Swpaul frame->mii_data = 0; 461109109Sdes 46240516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 46340516Swpaul 46440516Swpaul /* 465109109Sdes * Turn on data xmit. 46640516Swpaul */ 46740516Swpaul MII_SET(RL_MII_DIR); 46840516Swpaul 46940516Swpaul rl_mii_sync(sc); 47040516Swpaul 47140516Swpaul /* 47240516Swpaul * Send command/address info. 47340516Swpaul */ 47440516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 47540516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 47640516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 47740516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 47840516Swpaul 47940516Swpaul /* Idle bit */ 48040516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 48140516Swpaul DELAY(1); 48240516Swpaul MII_SET(RL_MII_CLK); 48340516Swpaul DELAY(1); 48440516Swpaul 48540516Swpaul /* Turn off xmit. */ 48640516Swpaul MII_CLR(RL_MII_DIR); 48740516Swpaul 48840516Swpaul /* Check for ack */ 48940516Swpaul MII_CLR(RL_MII_CLK); 49040516Swpaul DELAY(1); 491109058Smbr ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 49240516Swpaul MII_SET(RL_MII_CLK); 49340516Swpaul DELAY(1); 49440516Swpaul 49540516Swpaul /* 49640516Swpaul * Now try reading data bits. If the ack failed, we still 49740516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 49840516Swpaul */ 49940516Swpaul if (ack) { 50040516Swpaul for(i = 0; i < 16; i++) { 50140516Swpaul MII_CLR(RL_MII_CLK); 50240516Swpaul DELAY(1); 50340516Swpaul MII_SET(RL_MII_CLK); 50440516Swpaul DELAY(1); 50540516Swpaul } 50640516Swpaul goto fail; 50740516Swpaul } 50840516Swpaul 50940516Swpaul for (i = 0x8000; i; i >>= 1) { 51040516Swpaul MII_CLR(RL_MII_CLK); 51140516Swpaul DELAY(1); 51240516Swpaul if (!ack) { 51340516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 51440516Swpaul frame->mii_data |= i; 51540516Swpaul DELAY(1); 51640516Swpaul } 51740516Swpaul MII_SET(RL_MII_CLK); 51840516Swpaul DELAY(1); 51940516Swpaul } 52040516Swpaul 52140516Swpaulfail: 52240516Swpaul 52340516Swpaul MII_CLR(RL_MII_CLK); 52440516Swpaul DELAY(1); 52540516Swpaul MII_SET(RL_MII_CLK); 52640516Swpaul DELAY(1); 52740516Swpaul 52867087Swpaul RL_UNLOCK(sc); 52940516Swpaul 53040516Swpaul if (ack) 53140516Swpaul return(1); 53240516Swpaul return(0); 53340516Swpaul} 53440516Swpaul 53540516Swpaul/* 53640516Swpaul * Write to a PHY register through the MII. 53740516Swpaul */ 538102335Salfredstatic int 539102335Salfredrl_mii_writereg(sc, frame) 54040516Swpaul struct rl_softc *sc; 54140516Swpaul struct rl_mii_frame *frame; 542109109Sdes 54340516Swpaul{ 54467087Swpaul RL_LOCK(sc); 54540516Swpaul 54640516Swpaul /* 54740516Swpaul * Set up frame for TX. 54840516Swpaul */ 54940516Swpaul 55040516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 55140516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 55240516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 553109109Sdes 55440516Swpaul /* 555109109Sdes * Turn on data output. 55640516Swpaul */ 55740516Swpaul MII_SET(RL_MII_DIR); 55840516Swpaul 55940516Swpaul rl_mii_sync(sc); 56040516Swpaul 56140516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 56240516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 56340516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 56440516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 56540516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 56640516Swpaul rl_mii_send(sc, frame->mii_data, 16); 56740516Swpaul 56840516Swpaul /* Idle bit. */ 56940516Swpaul MII_SET(RL_MII_CLK); 57040516Swpaul DELAY(1); 57140516Swpaul MII_CLR(RL_MII_CLK); 57240516Swpaul DELAY(1); 57340516Swpaul 57440516Swpaul /* 57540516Swpaul * Turn off xmit. 57640516Swpaul */ 57740516Swpaul MII_CLR(RL_MII_DIR); 57840516Swpaul 57967087Swpaul RL_UNLOCK(sc); 58040516Swpaul 58140516Swpaul return(0); 58240516Swpaul} 58340516Swpaul 584102335Salfredstatic int 585102335Salfredrl_miibus_readreg(dev, phy, reg) 58650703Swpaul device_t dev; 58750703Swpaul int phy, reg; 58850703Swpaul{ 58940516Swpaul struct rl_softc *sc; 59040516Swpaul struct rl_mii_frame frame; 59140516Swpaul u_int16_t rval = 0; 59240516Swpaul u_int16_t rl8139_reg = 0; 59340516Swpaul 59450703Swpaul sc = device_get_softc(dev); 59567087Swpaul RL_LOCK(sc); 59650703Swpaul 59740516Swpaul if (sc->rl_type == RL_8139) { 59850703Swpaul /* Pretend the internal PHY is only at address 0 */ 59967087Swpaul if (phy) { 60067087Swpaul RL_UNLOCK(sc); 60150703Swpaul return(0); 60267087Swpaul } 60340516Swpaul switch(reg) { 60450703Swpaul case MII_BMCR: 60540516Swpaul rl8139_reg = RL_BMCR; 60640516Swpaul break; 60750703Swpaul case MII_BMSR: 60840516Swpaul rl8139_reg = RL_BMSR; 60940516Swpaul break; 61050703Swpaul case MII_ANAR: 61140516Swpaul rl8139_reg = RL_ANAR; 61240516Swpaul break; 61350703Swpaul case MII_ANER: 61450703Swpaul rl8139_reg = RL_ANER; 61550703Swpaul break; 61650703Swpaul case MII_ANLPAR: 61740516Swpaul rl8139_reg = RL_LPAR; 61840516Swpaul break; 61950703Swpaul case MII_PHYIDR1: 62050703Swpaul case MII_PHYIDR2: 62167087Swpaul RL_UNLOCK(sc); 62250703Swpaul return(0); 62350703Swpaul break; 62494149Swpaul /* 62594149Swpaul * Allow the rlphy driver to read the media status 62694149Swpaul * register. If we have a link partner which does not 62794149Swpaul * support NWAY, this is the register which will tell 62894149Swpaul * us the results of parallel detection. 62994149Swpaul */ 63094149Swpaul case RL_MEDIASTAT: 63194149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 63294149Swpaul RL_UNLOCK(sc); 63394149Swpaul return(rval); 63494149Swpaul break; 63540516Swpaul default: 63640516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 63767087Swpaul RL_UNLOCK(sc); 63840516Swpaul return(0); 63940516Swpaul } 64040516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 64167087Swpaul RL_UNLOCK(sc); 64240516Swpaul return(rval); 64340516Swpaul } 64440516Swpaul 64540516Swpaul bzero((char *)&frame, sizeof(frame)); 64640516Swpaul 64750703Swpaul frame.mii_phyaddr = phy; 64840516Swpaul frame.mii_regaddr = reg; 64940516Swpaul rl_mii_readreg(sc, &frame); 65067087Swpaul RL_UNLOCK(sc); 65140516Swpaul 65240516Swpaul return(frame.mii_data); 65340516Swpaul} 65440516Swpaul 655102335Salfredstatic int 656102335Salfredrl_miibus_writereg(dev, phy, reg, data) 65750703Swpaul device_t dev; 65850703Swpaul int phy, reg, data; 65950703Swpaul{ 66040516Swpaul struct rl_softc *sc; 66140516Swpaul struct rl_mii_frame frame; 66240516Swpaul u_int16_t rl8139_reg = 0; 66340516Swpaul 66450703Swpaul sc = device_get_softc(dev); 66567087Swpaul RL_LOCK(sc); 66650703Swpaul 66740516Swpaul if (sc->rl_type == RL_8139) { 66850703Swpaul /* Pretend the internal PHY is only at address 0 */ 66967087Swpaul if (phy) { 67067087Swpaul RL_UNLOCK(sc); 67150703Swpaul return(0); 67267087Swpaul } 67340516Swpaul switch(reg) { 67450703Swpaul case MII_BMCR: 67540516Swpaul rl8139_reg = RL_BMCR; 67640516Swpaul break; 67750703Swpaul case MII_BMSR: 67840516Swpaul rl8139_reg = RL_BMSR; 67940516Swpaul break; 68050703Swpaul case MII_ANAR: 68140516Swpaul rl8139_reg = RL_ANAR; 68240516Swpaul break; 68350703Swpaul case MII_ANER: 68450703Swpaul rl8139_reg = RL_ANER; 68550703Swpaul break; 68650703Swpaul case MII_ANLPAR: 68740516Swpaul rl8139_reg = RL_LPAR; 68840516Swpaul break; 68950703Swpaul case MII_PHYIDR1: 69050703Swpaul case MII_PHYIDR2: 69167087Swpaul RL_UNLOCK(sc); 69250703Swpaul return(0); 69350703Swpaul break; 69440516Swpaul default: 69540516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 69667087Swpaul RL_UNLOCK(sc); 69750703Swpaul return(0); 69840516Swpaul } 69940516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 70067087Swpaul RL_UNLOCK(sc); 70150703Swpaul return(0); 70240516Swpaul } 70340516Swpaul 70440516Swpaul bzero((char *)&frame, sizeof(frame)); 70540516Swpaul 70650703Swpaul frame.mii_phyaddr = phy; 70740516Swpaul frame.mii_regaddr = reg; 70840516Swpaul frame.mii_data = data; 70940516Swpaul 71040516Swpaul rl_mii_writereg(sc, &frame); 71140516Swpaul 71267087Swpaul RL_UNLOCK(sc); 71350703Swpaul return(0); 71450703Swpaul} 71550703Swpaul 716102335Salfredstatic void 717102335Salfredrl_miibus_statchg(dev) 71850703Swpaul device_t dev; 71950703Swpaul{ 72040516Swpaul return; 72140516Swpaul} 72240516Swpaul 72340516Swpaul/* 72443062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 72540516Swpaul */ 726102335Salfredstatic u_int8_t 727102335Salfredrl_calchash(addr) 72841656Swpaul caddr_t addr; 72940516Swpaul{ 73040516Swpaul u_int32_t crc, carry; 73140516Swpaul int i, j; 73240516Swpaul u_int8_t c; 73340516Swpaul 73440516Swpaul /* Compute CRC for the address value. */ 73540516Swpaul crc = 0xFFFFFFFF; /* initial value */ 73640516Swpaul 73740516Swpaul for (i = 0; i < 6; i++) { 73840516Swpaul c = *(addr + i); 73940516Swpaul for (j = 0; j < 8; j++) { 74040516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 74140516Swpaul crc <<= 1; 74240516Swpaul c >>= 1; 74340516Swpaul if (carry) 74440516Swpaul crc = (crc ^ 0x04c11db6) | carry; 74540516Swpaul } 74640516Swpaul } 74740516Swpaul 74840516Swpaul /* return the filter bit position */ 74943062Swpaul return(crc >> 26); 75040516Swpaul} 75140516Swpaul 75240516Swpaul/* 75340516Swpaul * Program the 64-bit multicast hash filter. 75440516Swpaul */ 755102335Salfredstatic void 756102335Salfredrl_setmulti(sc) 75740516Swpaul struct rl_softc *sc; 75840516Swpaul{ 75940516Swpaul struct ifnet *ifp; 76040516Swpaul int h = 0; 76140516Swpaul u_int32_t hashes[2] = { 0, 0 }; 76240516Swpaul struct ifmultiaddr *ifma; 76340516Swpaul u_int32_t rxfilt; 76440516Swpaul int mcnt = 0; 76540516Swpaul 76640516Swpaul ifp = &sc->arpcom.ac_if; 76740516Swpaul 76840516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 76940516Swpaul 77043062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 77140516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 77240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 77340516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 77440516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 77540516Swpaul return; 77640516Swpaul } 77740516Swpaul 77840516Swpaul /* first, zot all the existing hash bits */ 77940516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 78040516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 78140516Swpaul 78240516Swpaul /* now program new ones */ 78372084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 78440516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 78540516Swpaul continue; 78640516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 78740516Swpaul if (h < 32) 78840516Swpaul hashes[0] |= (1 << h); 78940516Swpaul else 79040516Swpaul hashes[1] |= (1 << (h - 32)); 79140516Swpaul mcnt++; 79240516Swpaul } 79340516Swpaul 79440516Swpaul if (mcnt) 79540516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 79640516Swpaul else 79740516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 79840516Swpaul 79940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 80040516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 80140516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 80240516Swpaul 80340516Swpaul return; 80440516Swpaul} 80540516Swpaul 806102335Salfredstatic void 807102335Salfredrl_reset(sc) 80840516Swpaul struct rl_softc *sc; 80940516Swpaul{ 81040516Swpaul register int i; 81140516Swpaul 81240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 81340516Swpaul 81440516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 81540516Swpaul DELAY(10); 81640516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 81740516Swpaul break; 81840516Swpaul } 81940516Swpaul if (i == RL_TIMEOUT) 82040516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 82140516Swpaul 822109109Sdes return; 82340516Swpaul} 82440516Swpaul 82540516Swpaul/* 82640516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 82740516Swpaul * IDs against our list and return a device name if we find a match. 82840516Swpaul */ 829102335Salfredstatic int 830102335Salfredrl_probe(dev) 83150703Swpaul device_t dev; 83240516Swpaul{ 83340516Swpaul struct rl_type *t; 83440516Swpaul 83540516Swpaul t = rl_devs; 83640516Swpaul 83740516Swpaul while(t->rl_name != NULL) { 83850703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 83950703Swpaul (pci_get_device(dev) == t->rl_did)) { 84050703Swpaul device_set_desc(dev, t->rl_name); 84150703Swpaul return(0); 84240516Swpaul } 84340516Swpaul t++; 84440516Swpaul } 84540516Swpaul 84650703Swpaul return(ENXIO); 84740516Swpaul} 84840516Swpaul 84940516Swpaul/* 85040516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 85140516Swpaul * setup and ethernet/BPF attach. 85240516Swpaul */ 853102335Salfredstatic int 854102335Salfredrl_attach(dev) 85550703Swpaul device_t dev; 85640516Swpaul{ 85740516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 85840516Swpaul u_int32_t command; 859108729Sjake u_int16_t as[3]; 86040516Swpaul struct rl_softc *sc; 86140516Swpaul struct ifnet *ifp; 86240516Swpaul u_int16_t rl_did = 0; 863108729Sjake int unit, error = 0, rid, i; 86440516Swpaul 86550703Swpaul sc = device_get_softc(dev); 86650703Swpaul unit = device_get_unit(dev); 86740516Swpaul bzero(sc, sizeof(struct rl_softc)); 86840516Swpaul 86993818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 87093818Sjhb MTX_DEF | MTX_RECURSE); 87169583Swpaul 87240516Swpaul /* 87340516Swpaul * Handle power management nonsense. 87440516Swpaul */ 87540516Swpaul 87670167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 87770167Swpaul u_int32_t iobase, membase, irq; 87840516Swpaul 87970167Swpaul /* Save important PCI config data. */ 88070167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 88170167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 88270167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 88340516Swpaul 88470167Swpaul /* Reset the power state. */ 88570167Swpaul printf("rl%d: chip is is in D%d power mode " 88670167Swpaul "-- setting to D0\n", unit, 88770167Swpaul pci_get_powerstate(dev)); 88840516Swpaul 88970167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 89040516Swpaul 89170167Swpaul /* Restore PCI config data. */ 89270167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 89370167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 89470167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 89540516Swpaul } 89640516Swpaul 89740516Swpaul /* 89840516Swpaul * Map control/status registers. 89940516Swpaul */ 90072813Swpaul pci_enable_busmaster(dev); 90179472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 90279472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 90361041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 90440516Swpaul 90540516Swpaul#ifdef RL_USEIOSPACE 90640516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 90740516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 90850703Swpaul error = ENXIO; 90940516Swpaul goto fail; 91040516Swpaul } 91140516Swpaul#else 91240516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 91340516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 91450703Swpaul error = ENXIO; 91540516Swpaul goto fail; 91640516Swpaul } 91750703Swpaul#endif 91840516Swpaul 919109109Sdes rid = RL_RID; 92050703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 92150703Swpaul 0, ~0, 1, RF_ACTIVE); 92250703Swpaul 92350703Swpaul if (sc->rl_res == NULL) { 92450703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 92550703Swpaul error = ENXIO; 92640516Swpaul goto fail; 92740516Swpaul } 92840516Swpaul 92969127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 93069127Sroger * unstable when left to autoselect the media 93169127Sroger * The best workaround is to set the device to the required 93269127Sroger * media type or to set it to the 10 Meg speed. 93369127Sroger */ 93469127Sroger 93569127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 93669127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 93769127Sroger } 93869127Sroger 93950703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 94050703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 94150703Swpaul 94250703Swpaul rid = 0; 94350703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 94450703Swpaul RF_SHAREABLE | RF_ACTIVE); 94550703Swpaul 94650703Swpaul if (sc->rl_irq == NULL) { 94740516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 94850703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 94950703Swpaul error = ENXIO; 95040516Swpaul goto fail; 95140516Swpaul } 95240516Swpaul 95340516Swpaul /* Reset the adapter. */ 95440516Swpaul rl_reset(sc); 95567931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 95667931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 95768215Swpaul if (rl_did != 0x8129) 95867931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 95940516Swpaul 96040516Swpaul /* 96140516Swpaul * Get station address from the EEPROM. 96240516Swpaul */ 963108729Sjake rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 964108729Sjake for (i = 0; i < 3; i++) { 965108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 966108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 967108729Sjake } 96840516Swpaul 96940516Swpaul /* 97040516Swpaul * A RealTek chip was detected. Inform the world. 97140516Swpaul */ 97240516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 97340516Swpaul 97440516Swpaul sc->rl_unit = unit; 97540516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 97640516Swpaul 97740516Swpaul /* 97840516Swpaul * Now read the exact device type from the EEPROM to find 97940516Swpaul * out if it's an 8129 or 8139. 98040516Swpaul */ 98140516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 98240516Swpaul 98344238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 98467771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 98596112Sjhb rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 986109108Sdes rl_did == DLINK_DEVICEID_690TXD || 987109108Sdes rl_did == COREGA_DEVICEID_FETHERCBTXD || 988109108Sdes rl_did == COREGA_DEVICEID_FETHERIICBTXD) 98940516Swpaul sc->rl_type = RL_8139; 99040516Swpaul else if (rl_did == RT_DEVICEID_8129) 99140516Swpaul sc->rl_type = RL_8129; 99240516Swpaul else { 99340516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 99468215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 99550703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 99650703Swpaul error = ENXIO; 99740516Swpaul goto fail; 99840516Swpaul } 99940516Swpaul 100081713Swpaul /* 100181713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 100281713Swpaul */ 100381713Swpaul#define RL_NSEG_NEW 32 1004109109Sdes error = bus_dma_tag_create(NULL, /* parent */ 100581713Swpaul 1, 0, /* alignment, boundary */ 100681713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 100781713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 100881713Swpaul NULL, NULL, /* filter, filterarg */ 100981713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1010109109Sdes BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 101181713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 101281713Swpaul &sc->rl_parent_tag); 101340516Swpaul 101481713Swpaul /* 101581713Swpaul * Now allocate a tag for the DMA descriptor lists. 101681713Swpaul * All of our lists are allocated as a contiguous block 101781713Swpaul * of memory. 101881713Swpaul */ 101981713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 102081713Swpaul 1, 0, /* alignment, boundary */ 102181713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 102281713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 102381713Swpaul NULL, NULL, /* filter, filterarg */ 102481713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 102581713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 102681713Swpaul 0, /* flags */ 102781713Swpaul &sc->rl_tag); 102881713Swpaul 102981713Swpaul /* 103081713Swpaul * Now allocate a chunk of DMA-able memory based on the 103181713Swpaul * tag we just created. 103281713Swpaul */ 103381713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 103481713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 103581713Swpaul &sc->rl_cdata.rl_rx_dmamap); 103681713Swpaul 103740516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 103840516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 103968215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 104050703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 104181713Swpaul bus_dma_tag_destroy(sc->rl_tag); 104250703Swpaul error = ENXIO; 104340516Swpaul goto fail; 104440516Swpaul } 104540516Swpaul 104648028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 104748028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 104848028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 104948028Swpaul 105050703Swpaul /* Do MII setup */ 105150703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 105250703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 105350703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 105468215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 105550703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 105681713Swpaul bus_dmamem_free(sc->rl_tag, 105781713Swpaul sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 105881713Swpaul bus_dma_tag_destroy(sc->rl_tag); 105950703Swpaul error = ENXIO; 106050703Swpaul goto fail; 106150703Swpaul } 106250703Swpaul 106340516Swpaul ifp = &sc->arpcom.ac_if; 106440516Swpaul ifp->if_softc = sc; 106540516Swpaul ifp->if_unit = unit; 106640516Swpaul ifp->if_name = "rl"; 106740516Swpaul ifp->if_mtu = ETHERMTU; 106840516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 106940516Swpaul ifp->if_ioctl = rl_ioctl; 107040516Swpaul ifp->if_output = ether_output; 107140516Swpaul ifp->if_start = rl_start; 107240516Swpaul ifp->if_watchdog = rl_watchdog; 107340516Swpaul ifp->if_init = rl_init; 107440516Swpaul ifp->if_baudrate = 10000000; 107545633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 107640516Swpaul 107740516Swpaul /* 107863090Sarchie * Call MI attach routine. 107940516Swpaul */ 1080106936Ssam ether_ifattach(ifp, eaddr); 1081106157Simp 1082106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1083106157Simp rl_intr, sc, &sc->rl_intrhand); 1084106157Simp 1085106157Simp if (error) { 1086106157Simp printf("rl%d: couldn't set up irq\n", unit); 1087106157Simp bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1088106157Simp bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1089106157Simp bus_dmamem_free(sc->rl_tag, 1090106157Simp sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1091106157Simp bus_dma_tag_destroy(sc->rl_tag); 1092106157Simp goto fail; 1093106157Simp } 1094106157Simp 1095106157Simp callout_handle_init(&sc->rl_stat_ch); 109667087Swpaul return(0); 109740516Swpaulfail: 109867087Swpaul mtx_destroy(&sc->rl_mtx); 109950703Swpaul return(error); 110040516Swpaul} 110140516Swpaul 1102102335Salfredstatic int 1103102335Salfredrl_detach(dev) 110450703Swpaul device_t dev; 110550703Swpaul{ 110650703Swpaul struct rl_softc *sc; 110750703Swpaul struct ifnet *ifp; 110850703Swpaul 110950703Swpaul sc = device_get_softc(dev); 111067087Swpaul RL_LOCK(sc); 111150703Swpaul ifp = &sc->arpcom.ac_if; 111250703Swpaul 1113106936Ssam ether_ifdetach(ifp); 111450703Swpaul rl_stop(sc); 111550703Swpaul 111650703Swpaul bus_generic_detach(dev); 111750703Swpaul device_delete_child(dev, sc->rl_miibus); 111850703Swpaul 111950703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 112068215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 112150703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 112250703Swpaul 112381713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 112481713Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 112581713Swpaul sc->rl_cdata.rl_rx_dmamap); 112681713Swpaul bus_dma_tag_destroy(sc->rl_tag); 112781713Swpaul bus_dma_tag_destroy(sc->rl_parent_tag); 112850703Swpaul 112967087Swpaul RL_UNLOCK(sc); 113067087Swpaul mtx_destroy(&sc->rl_mtx); 113150703Swpaul 113250703Swpaul return(0); 113350703Swpaul} 113450703Swpaul 113540516Swpaul/* 113640516Swpaul * Initialize the transmit descriptors. 113740516Swpaul */ 1138102335Salfredstatic int 1139102335Salfredrl_list_tx_init(sc) 114040516Swpaul struct rl_softc *sc; 114140516Swpaul{ 114240516Swpaul struct rl_chain_data *cd; 114340516Swpaul int i; 114440516Swpaul 114540516Swpaul cd = &sc->rl_cdata; 114640516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 114745633Swpaul cd->rl_tx_chain[i] = NULL; 114848028Swpaul CSR_WRITE_4(sc, 114948028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 115040516Swpaul } 115140516Swpaul 115245633Swpaul sc->rl_cdata.cur_tx = 0; 115345633Swpaul sc->rl_cdata.last_tx = 0; 115440516Swpaul 115540516Swpaul return(0); 115640516Swpaul} 115740516Swpaul 115840516Swpaul/* 115940516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 116040516Swpaul * the higher level protocols. 116140516Swpaul * 116240516Swpaul * You know there's something wrong with a PCI bus-master chip design 116340516Swpaul * when you have to use m_devget(). 116440516Swpaul * 116540516Swpaul * The receive operation is badly documented in the datasheet, so I'll 116640516Swpaul * attempt to document it here. The driver provides a buffer area and 116740516Swpaul * places its base address in the RX buffer start address register. 116840516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 116972645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 117040516Swpaul * of the frame and certain other status bits. Each frame (starting with 117140516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 117240516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 117340516Swpaul * the 'rx status register' mentioned in the datasheet. 117448028Swpaul * 117548028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 117678508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1177109109Sdes * as the offset argument to m_devget(). 117840516Swpaul */ 1179102335Salfredstatic void 1180102335Salfredrl_rxeof(sc) 118140516Swpaul struct rl_softc *sc; 118240516Swpaul{ 1183109109Sdes struct mbuf *m; 1184109109Sdes struct ifnet *ifp; 118540516Swpaul int total_len = 0; 118640516Swpaul u_int32_t rxstat; 118740516Swpaul caddr_t rxbufpos; 118840516Swpaul int wrap = 0; 118940516Swpaul u_int16_t cur_rx; 119040516Swpaul u_int16_t limit; 119140516Swpaul u_int16_t rx_bytes = 0, max_bytes; 119240516Swpaul 119340516Swpaul ifp = &sc->arpcom.ac_if; 119440516Swpaul 119581713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1196108729Sjake BUS_DMASYNC_POSTREAD); 119781713Swpaul 119840516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 119940516Swpaul 120040516Swpaul /* Do not try to read past this point. */ 120140516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 120240516Swpaul 120340516Swpaul if (limit < cur_rx) 120440516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 120540516Swpaul else 120640516Swpaul max_bytes = limit - cur_rx; 120740516Swpaul 120842738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 120994883Sluigi#ifdef DEVICE_POLLING 1210102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 121194883Sluigi if (sc->rxcycles <= 0) 121294883Sluigi break; 121394883Sluigi sc->rxcycles--; 121494883Sluigi } 121594883Sluigi#endif /* DEVICE_POLLING */ 121640516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1217108729Sjake rxstat = le32toh(*(u_int32_t *)rxbufpos); 121840516Swpaul 121940516Swpaul /* 122040516Swpaul * Here's a totally undocumented fact for you. When the 122140516Swpaul * RealTek chip is in the process of copying a packet into 122240516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 122340516Swpaul * packet header with this value, you need to stop. The 122440516Swpaul * datasheet makes absolutely no mention of this and 122540516Swpaul * RealTek should be shot for this. 122640516Swpaul */ 122740516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 122840516Swpaul break; 1229109109Sdes 123040516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 123140516Swpaul ifp->if_ierrors++; 123250703Swpaul rl_init(sc); 123350703Swpaul return; 123440516Swpaul } 123540516Swpaul 1236109109Sdes /* No errors; receive the packet. */ 123740516Swpaul total_len = rxstat >> 16; 123840516Swpaul rx_bytes += total_len + 4; 123940516Swpaul 124040516Swpaul /* 124142051Swpaul * XXX The RealTek chip includes the CRC with every 124242051Swpaul * received frame, and there's no way to turn this 124342051Swpaul * behavior off (at least, I can't find anything in 1244109109Sdes * the manual that explains how to do it) so we have 124542051Swpaul * to trim off the CRC manually. 124642051Swpaul */ 124742051Swpaul total_len -= ETHER_CRC_LEN; 124842051Swpaul 124942051Swpaul /* 125040516Swpaul * Avoid trying to read more bytes than we know 125140516Swpaul * the chip has prepared for us. 125240516Swpaul */ 125340516Swpaul if (rx_bytes > max_bytes) 125440516Swpaul break; 125540516Swpaul 125640516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 125740516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 125840516Swpaul 125940516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 126040516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 126140516Swpaul 126240516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 126340516Swpaul 126440516Swpaul if (total_len > wrap) { 126578508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 126678508Sbmilekic NULL); 126740516Swpaul if (m == NULL) { 126840516Swpaul ifp->if_ierrors++; 126952426Swpaul } else { 127040516Swpaul m_copyback(m, wrap, total_len - wrap, 127140516Swpaul sc->rl_cdata.rl_rx_buf); 127248028Swpaul } 127342051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 127440516Swpaul } else { 127578508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 127678508Sbmilekic NULL); 127740516Swpaul if (m == NULL) { 127840516Swpaul ifp->if_ierrors++; 127978508Sbmilekic } 128042051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 128140516Swpaul } 128240516Swpaul 128340516Swpaul /* 128440516Swpaul * Round up to 32-bit boundary. 128540516Swpaul */ 128640516Swpaul cur_rx = (cur_rx + 3) & ~3; 128740516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 128840516Swpaul 128940516Swpaul if (m == NULL) 129040516Swpaul continue; 129140516Swpaul 129240516Swpaul ifp->if_ipackets++; 1293106936Ssam (*ifp->if_input)(ifp, m); 129440516Swpaul } 129540516Swpaul 129640516Swpaul return; 129740516Swpaul} 129840516Swpaul 129940516Swpaul/* 130040516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 130140516Swpaul * the list buffers. 130240516Swpaul */ 1303102335Salfredstatic void 1304102335Salfredrl_txeof(sc) 130540516Swpaul struct rl_softc *sc; 130640516Swpaul{ 130740516Swpaul struct ifnet *ifp; 130840516Swpaul u_int32_t txstat; 130940516Swpaul 131040516Swpaul ifp = &sc->arpcom.ac_if; 131140516Swpaul 131240516Swpaul /* 131340516Swpaul * Go through our tx list and free mbufs for those 131440516Swpaul * frames that have been uploaded. 131540516Swpaul */ 131645633Swpaul do { 131745633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 131845633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 131945633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 132040516Swpaul break; 132140516Swpaul 132245633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 132340516Swpaul 132445633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 132581713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 132681713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 132745633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 132845633Swpaul RL_LAST_TXMBUF(sc) = NULL; 132945633Swpaul } 133045633Swpaul if (txstat & RL_TXSTAT_TX_OK) 133145633Swpaul ifp->if_opackets++; 133245633Swpaul else { 133352426Swpaul int oldthresh; 133445633Swpaul ifp->if_oerrors++; 133545633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 133645633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 133745633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 133852426Swpaul oldthresh = sc->rl_txthresh; 133952426Swpaul /* error recovery */ 134052426Swpaul rl_reset(sc); 134152426Swpaul rl_init(sc); 134252426Swpaul /* 134352426Swpaul * If there was a transmit underrun, 134452426Swpaul * bump the TX threshold. 134552426Swpaul */ 134652426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 134752426Swpaul sc->rl_txthresh = oldthresh + 32; 134852426Swpaul return; 134945633Swpaul } 135045633Swpaul RL_INC(sc->rl_cdata.last_tx); 135145633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 135245633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 135340516Swpaul 135499165Sluigi ifp->if_timer = 135599165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 135699165Sluigi 135750703Swpaul return; 135850703Swpaul} 135940516Swpaul 1360102335Salfredstatic void 1361102335Salfredrl_tick(xsc) 136250703Swpaul void *xsc; 136350703Swpaul{ 136450703Swpaul struct rl_softc *sc; 136550703Swpaul struct mii_data *mii; 136650703Swpaul 136750703Swpaul sc = xsc; 136867087Swpaul RL_LOCK(sc); 136950703Swpaul mii = device_get_softc(sc->rl_miibus); 137050703Swpaul 137150703Swpaul mii_tick(mii); 137250703Swpaul 137350703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 137467087Swpaul RL_UNLOCK(sc); 137550703Swpaul 137640516Swpaul return; 137740516Swpaul} 137840516Swpaul 137994883Sluigi#ifdef DEVICE_POLLING 138094883Sluigistatic void 138194883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 138294883Sluigi{ 138394883Sluigi struct rl_softc *sc = ifp->if_softc; 138494883Sluigi 138594883Sluigi RL_LOCK(sc); 138694883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 138794883Sluigi CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 138894883Sluigi goto done; 138994883Sluigi } 139094883Sluigi 139194883Sluigi sc->rxcycles = count; 139294883Sluigi rl_rxeof(sc); 139394883Sluigi rl_txeof(sc); 139494883Sluigi if (ifp->if_snd.ifq_head != NULL) 139594883Sluigi rl_start(ifp); 139694883Sluigi 139794883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 139894883Sluigi u_int16_t status; 139994883Sluigi 140094883Sluigi status = CSR_READ_2(sc, RL_ISR); 1401100957Sjhb if (status == 0xffff) 1402100957Sjhb goto done; 140394883Sluigi if (status) 140494883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 140594883Sluigi 140694883Sluigi /* 140794883Sluigi * XXX check behaviour on receiver stalls. 140894883Sluigi */ 140994883Sluigi 141094883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 141194883Sluigi rl_reset(sc); 141294883Sluigi rl_init(sc); 141394883Sluigi } 141494883Sluigi } 141594883Sluigidone: 141694883Sluigi RL_UNLOCK(sc); 141794883Sluigi} 141894883Sluigi#endif /* DEVICE_POLLING */ 141994883Sluigi 1420102335Salfredstatic void 1421102335Salfredrl_intr(arg) 142240516Swpaul void *arg; 142340516Swpaul{ 142440516Swpaul struct rl_softc *sc; 142540516Swpaul struct ifnet *ifp; 142640516Swpaul u_int16_t status; 142740516Swpaul 142840516Swpaul sc = arg; 142986822Siwasaki 143086822Siwasaki if (sc->suspended) { 143186822Siwasaki return; 143286822Siwasaki } 143386822Siwasaki 143467087Swpaul RL_LOCK(sc); 143540516Swpaul ifp = &sc->arpcom.ac_if; 143640516Swpaul 143794883Sluigi#ifdef DEVICE_POLLING 1438102052Ssobomax if (ifp->if_flags & IFF_POLLING) 143994883Sluigi goto done; 144094883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 144194883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 144294883Sluigi rl_poll(ifp, 0, 1); 144394883Sluigi goto done; 144494883Sluigi } 144594883Sluigi#endif /* DEVICE_POLLING */ 144640516Swpaul 144740516Swpaul for (;;) { 144840516Swpaul 144940516Swpaul status = CSR_READ_2(sc, RL_ISR); 1450100957Sjhb /* If the card has gone away the read returns 0xffff. */ 1451100957Sjhb if (status == 0xffff) 1452100957Sjhb break; 145340516Swpaul if (status) 145440516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 145540516Swpaul 145640516Swpaul if ((status & RL_INTRS) == 0) 145740516Swpaul break; 145840516Swpaul 145940516Swpaul if (status & RL_ISR_RX_OK) 146040516Swpaul rl_rxeof(sc); 146140516Swpaul 146240516Swpaul if (status & RL_ISR_RX_ERR) 146340516Swpaul rl_rxeof(sc); 146440516Swpaul 146545633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 146640516Swpaul rl_txeof(sc); 146740516Swpaul 146840516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 146940516Swpaul rl_reset(sc); 147040516Swpaul rl_init(sc); 147140516Swpaul } 147240516Swpaul 147340516Swpaul } 147440516Swpaul 147552426Swpaul if (ifp->if_snd.ifq_head != NULL) 147640516Swpaul rl_start(ifp); 147740516Swpaul 147894883Sluigi#ifdef DEVICE_POLLING 147994883Sluigidone: 148094883Sluigi#endif 148167087Swpaul RL_UNLOCK(sc); 148267087Swpaul 148340516Swpaul return; 148440516Swpaul} 148540516Swpaul 148640516Swpaul/* 148740516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 148840516Swpaul * pointers to the fragment pointers. 148940516Swpaul */ 1490102335Salfredstatic int 1491102335Salfredrl_encap(sc, m_head) 149240516Swpaul struct rl_softc *sc; 149340516Swpaul struct mbuf *m_head; 149440516Swpaul{ 149541243Swpaul struct mbuf *m_new = NULL; 149640516Swpaul 149740516Swpaul /* 149845633Swpaul * The RealTek is brain damaged and wants longword-aligned 149945633Swpaul * TX buffers, plus we can only have one fragment buffer 150045633Swpaul * per packet. We have to copy pretty much all the time. 150140516Swpaul */ 150240516Swpaul 150341243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 150487846Sluigi if (m_new == NULL) 150541243Swpaul return(1); 150641243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 150741243Swpaul MCLGET(m_new, M_DONTWAIT); 150841243Swpaul if (!(m_new->m_flags & M_EXT)) { 150941243Swpaul m_freem(m_new); 151040516Swpaul return(1); 151140516Swpaul } 151240516Swpaul } 151352426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 151441243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 151541243Swpaul m_freem(m_head); 151641243Swpaul m_head = m_new; 151740516Swpaul 151840516Swpaul /* Pad frames to at least 60 bytes. */ 151941243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 152055058Swpaul /* 152155058Swpaul * Make security concious people happy: zero out the 152255058Swpaul * bytes in the pad area, since we don't know what 152355058Swpaul * this mbuf cluster buffer's previous user might 152455058Swpaul * have left in it. 1525109109Sdes */ 152655058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 152755058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 152840516Swpaul m_head->m_pkthdr.len += 152952426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 153041243Swpaul m_head->m_len = m_head->m_pkthdr.len; 153141243Swpaul } 153240516Swpaul 153345633Swpaul RL_CUR_TXMBUF(sc) = m_head; 153440516Swpaul 153540516Swpaul return(0); 153640516Swpaul} 153740516Swpaul 153840516Swpaul/* 153940516Swpaul * Main transmit routine. 154040516Swpaul */ 154140516Swpaul 1542102335Salfredstatic void 1543102335Salfredrl_start(ifp) 154440516Swpaul struct ifnet *ifp; 154540516Swpaul{ 154640516Swpaul struct rl_softc *sc; 154740516Swpaul struct mbuf *m_head = NULL; 154840516Swpaul 154940516Swpaul sc = ifp->if_softc; 155067087Swpaul RL_LOCK(sc); 155140516Swpaul 155245633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 155340516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 155440516Swpaul if (m_head == NULL) 155540516Swpaul break; 155640516Swpaul 155758801Swpaul if (rl_encap(sc, m_head)) { 155858801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 155958801Swpaul ifp->if_flags |= IFF_OACTIVE; 156058801Swpaul break; 156158801Swpaul } 156240516Swpaul 156340516Swpaul /* 156440516Swpaul * If there's a BPF listener, bounce a copy of this frame 156540516Swpaul * to him. 156640516Swpaul */ 1567106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 156851583Swpaul 156940516Swpaul /* 157040516Swpaul * Transmit the frame. 1571109109Sdes */ 157281713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 157381713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 157481713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 157581713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 157681713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 157781713Swpaul BUS_DMASYNC_PREREAD); 157845633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 157952426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 158052426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 158145633Swpaul 158245633Swpaul RL_INC(sc->rl_cdata.cur_tx); 158340516Swpaul } 158440516Swpaul 158540516Swpaul /* 158645633Swpaul * We broke out of the loop because all our TX slots are 158745633Swpaul * full. Mark the NIC as busy until it drains some of the 158845633Swpaul * packets from the queue. 158945633Swpaul */ 159045633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 159145633Swpaul ifp->if_flags |= IFF_OACTIVE; 159245633Swpaul 159345633Swpaul /* 159440516Swpaul * Set a timeout in case the chip goes out to lunch. 159540516Swpaul */ 159640516Swpaul ifp->if_timer = 5; 159767087Swpaul RL_UNLOCK(sc); 159840516Swpaul 159940516Swpaul return; 160040516Swpaul} 160140516Swpaul 1602102335Salfredstatic void 1603102335Salfredrl_init(xsc) 160440516Swpaul void *xsc; 160540516Swpaul{ 160640516Swpaul struct rl_softc *sc = xsc; 160740516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160850703Swpaul struct mii_data *mii; 160967087Swpaul int i; 161040516Swpaul u_int32_t rxcfg = 0; 161140516Swpaul 161267087Swpaul RL_LOCK(sc); 161350703Swpaul mii = device_get_softc(sc->rl_miibus); 161440516Swpaul 161540516Swpaul /* 161640516Swpaul * Cancel pending I/O and free all RX/TX buffers. 161740516Swpaul */ 161840516Swpaul rl_stop(sc); 161940516Swpaul 162040516Swpaul /* Init our MAC address */ 162140516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 162240516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 162340516Swpaul } 162440516Swpaul 162540516Swpaul /* Init the RX buffer pointer register. */ 162681713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 162781713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 162881713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 162981713Swpaul BUS_DMASYNC_PREWRITE); 163040516Swpaul 163140516Swpaul /* Init TX descriptors. */ 163240516Swpaul rl_list_tx_init(sc); 163340516Swpaul 163440516Swpaul /* 163540516Swpaul * Enable transmit and receive. 163640516Swpaul */ 163740516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 163840516Swpaul 163940516Swpaul /* 164045633Swpaul * Set the initial TX and RX configuration. 164140516Swpaul */ 164245633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 164340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 164440516Swpaul 164540516Swpaul /* Set the individual bit to receive frames for this host only. */ 164640516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 164740516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 164840516Swpaul 164940516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 165040516Swpaul if (ifp->if_flags & IFF_PROMISC) { 165140516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 165240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165340516Swpaul } else { 165440516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 165540516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165640516Swpaul } 165740516Swpaul 165840516Swpaul /* 165940516Swpaul * Set capture broadcast bit to capture broadcast frames. 166040516Swpaul */ 166140516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 166240516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 166340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 166440516Swpaul } else { 166540516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 166640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 166740516Swpaul } 166840516Swpaul 166940516Swpaul /* 167040516Swpaul * Program the multicast filter, if necessary. 167140516Swpaul */ 167240516Swpaul rl_setmulti(sc); 167340516Swpaul 167494883Sluigi#ifdef DEVICE_POLLING 167540516Swpaul /* 167694883Sluigi * Disable interrupts if we are polling. 167794883Sluigi */ 1678102052Ssobomax if (ifp->if_flags & IFF_POLLING) 167994883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 168094883Sluigi else /* otherwise ... */ 168194883Sluigi#endif /* DEVICE_POLLING */ 168294883Sluigi /* 168340516Swpaul * Enable interrupts. 168440516Swpaul */ 168540516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 168640516Swpaul 168752426Swpaul /* Set initial TX threshold */ 168852426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 168952426Swpaul 169040516Swpaul /* Start RX/TX process. */ 169140516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 169240516Swpaul 169340516Swpaul /* Enable receiver and transmitter. */ 169440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 169540516Swpaul 169650703Swpaul mii_mediachg(mii); 169740516Swpaul 169840516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 169940516Swpaul 170040516Swpaul ifp->if_flags |= IFF_RUNNING; 170140516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 170240516Swpaul 170350703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 170467087Swpaul RL_UNLOCK(sc); 170550703Swpaul 170640516Swpaul return; 170740516Swpaul} 170840516Swpaul 170940516Swpaul/* 171040516Swpaul * Set media options. 171140516Swpaul */ 1712102335Salfredstatic int 1713102335Salfredrl_ifmedia_upd(ifp) 171440516Swpaul struct ifnet *ifp; 171540516Swpaul{ 171640516Swpaul struct rl_softc *sc; 171750703Swpaul struct mii_data *mii; 171840516Swpaul 171940516Swpaul sc = ifp->if_softc; 172050703Swpaul mii = device_get_softc(sc->rl_miibus); 172150703Swpaul mii_mediachg(mii); 172240516Swpaul 172340516Swpaul return(0); 172440516Swpaul} 172540516Swpaul 172640516Swpaul/* 172740516Swpaul * Report current media status. 172840516Swpaul */ 1729102335Salfredstatic void 1730102335Salfredrl_ifmedia_sts(ifp, ifmr) 173140516Swpaul struct ifnet *ifp; 173240516Swpaul struct ifmediareq *ifmr; 173340516Swpaul{ 173440516Swpaul struct rl_softc *sc; 173550703Swpaul struct mii_data *mii; 173640516Swpaul 173740516Swpaul sc = ifp->if_softc; 173850703Swpaul mii = device_get_softc(sc->rl_miibus); 173940516Swpaul 174050703Swpaul mii_pollstat(mii); 174150703Swpaul ifmr->ifm_active = mii->mii_media_active; 174250703Swpaul ifmr->ifm_status = mii->mii_media_status; 174340516Swpaul 174440516Swpaul return; 174540516Swpaul} 174640516Swpaul 1747102335Salfredstatic int 1748102335Salfredrl_ioctl(ifp, command, data) 174940516Swpaul struct ifnet *ifp; 175040516Swpaul u_long command; 175140516Swpaul caddr_t data; 175240516Swpaul{ 175340516Swpaul struct rl_softc *sc = ifp->if_softc; 175440516Swpaul struct ifreq *ifr = (struct ifreq *) data; 175550703Swpaul struct mii_data *mii; 175667087Swpaul int error = 0; 175740516Swpaul 175867087Swpaul RL_LOCK(sc); 175940516Swpaul 176040516Swpaul switch(command) { 176140516Swpaul case SIOCSIFFLAGS: 176240516Swpaul if (ifp->if_flags & IFF_UP) { 176340516Swpaul rl_init(sc); 176440516Swpaul } else { 176540516Swpaul if (ifp->if_flags & IFF_RUNNING) 176640516Swpaul rl_stop(sc); 176740516Swpaul } 176840516Swpaul error = 0; 176940516Swpaul break; 177040516Swpaul case SIOCADDMULTI: 177140516Swpaul case SIOCDELMULTI: 177240516Swpaul rl_setmulti(sc); 177340516Swpaul error = 0; 177440516Swpaul break; 177540516Swpaul case SIOCGIFMEDIA: 177640516Swpaul case SIOCSIFMEDIA: 177750703Swpaul mii = device_get_softc(sc->rl_miibus); 177850703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 177940516Swpaul break; 178040516Swpaul default: 1781106936Ssam error = ether_ioctl(ifp, command, data); 178240516Swpaul break; 178340516Swpaul } 178440516Swpaul 178567087Swpaul RL_UNLOCK(sc); 178640516Swpaul 178740516Swpaul return(error); 178840516Swpaul} 178940516Swpaul 1790102335Salfredstatic void 1791102335Salfredrl_watchdog(ifp) 179240516Swpaul struct ifnet *ifp; 179340516Swpaul{ 179440516Swpaul struct rl_softc *sc; 179540516Swpaul 179640516Swpaul sc = ifp->if_softc; 179767087Swpaul RL_LOCK(sc); 179840516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 179940516Swpaul ifp->if_oerrors++; 180050703Swpaul 180140516Swpaul rl_txeof(sc); 180240516Swpaul rl_rxeof(sc); 180340516Swpaul rl_init(sc); 180467087Swpaul RL_UNLOCK(sc); 180540516Swpaul 180640516Swpaul return; 180740516Swpaul} 180840516Swpaul 180940516Swpaul/* 181040516Swpaul * Stop the adapter and free any mbufs allocated to the 181140516Swpaul * RX and TX lists. 181240516Swpaul */ 1813102335Salfredstatic void 1814102335Salfredrl_stop(sc) 181540516Swpaul struct rl_softc *sc; 181640516Swpaul{ 181740516Swpaul register int i; 181840516Swpaul struct ifnet *ifp; 181940516Swpaul 182067087Swpaul RL_LOCK(sc); 182140516Swpaul ifp = &sc->arpcom.ac_if; 182240516Swpaul ifp->if_timer = 0; 182340516Swpaul 182450703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 182594883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 182694883Sluigi#ifdef DEVICE_POLLING 182794883Sluigi ether_poll_deregister(ifp); 182894883Sluigi#endif /* DEVICE_POLLING */ 182950703Swpaul 183040516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 183140516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 183281713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 183340516Swpaul 183440516Swpaul /* 183540516Swpaul * Free the TX list buffers. 183640516Swpaul */ 183740516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 183845633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 183981713Swpaul bus_dmamap_unload(sc->rl_tag, 184081713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 184181713Swpaul bus_dmamap_destroy(sc->rl_tag, 184281713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 184345633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 184445633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 184545633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 184640516Swpaul } 184740516Swpaul } 184840516Swpaul 184967087Swpaul RL_UNLOCK(sc); 185040516Swpaul return; 185140516Swpaul} 185240516Swpaul 185340516Swpaul/* 185486822Siwasaki * Device suspend routine. Stop the interface and save some PCI 185586822Siwasaki * settings in case the BIOS doesn't restore them properly on 185686822Siwasaki * resume. 185786822Siwasaki */ 1858102335Salfredstatic int 1859102335Salfredrl_suspend(dev) 186086822Siwasaki device_t dev; 186186822Siwasaki{ 186286822Siwasaki register int i; 186386822Siwasaki struct rl_softc *sc; 186486822Siwasaki 186586822Siwasaki sc = device_get_softc(dev); 186686822Siwasaki 186786822Siwasaki rl_stop(sc); 186886822Siwasaki 186986822Siwasaki for (i = 0; i < 5; i++) 187086822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 187186822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 187286822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 187386822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 187486822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 187586822Siwasaki 187686822Siwasaki sc->suspended = 1; 187786822Siwasaki 187886822Siwasaki return (0); 187986822Siwasaki} 188086822Siwasaki 188186822Siwasaki/* 188286822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 188386822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 188486822Siwasaki * appropriate. 188586822Siwasaki */ 1886102335Salfredstatic int 1887102335Salfredrl_resume(dev) 188886822Siwasaki device_t dev; 188986822Siwasaki{ 189086822Siwasaki register int i; 189186822Siwasaki struct rl_softc *sc; 189286822Siwasaki struct ifnet *ifp; 189386822Siwasaki 189486822Siwasaki sc = device_get_softc(dev); 189586822Siwasaki ifp = &sc->arpcom.ac_if; 189686822Siwasaki 189786822Siwasaki /* better way to do this? */ 189886822Siwasaki for (i = 0; i < 5; i++) 189986822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 190086822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 190186822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 190286822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 190386822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 190486822Siwasaki 190586822Siwasaki /* reenable busmastering */ 190686822Siwasaki pci_enable_busmaster(dev); 190786822Siwasaki pci_enable_io(dev, RL_RES); 190886822Siwasaki 1909109109Sdes /* reinitialize interface if necessary */ 1910109109Sdes if (ifp->if_flags & IFF_UP) 1911109109Sdes rl_init(sc); 191286822Siwasaki 191386822Siwasaki sc->suspended = 0; 191486822Siwasaki 191586822Siwasaki return (0); 191686822Siwasaki} 191786822Siwasaki 191886822Siwasaki/* 191940516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 192040516Swpaul * get confused by errant DMAs when rebooting. 192140516Swpaul */ 1922102335Salfredstatic void 1923102335Salfredrl_shutdown(dev) 192450703Swpaul device_t dev; 192540516Swpaul{ 192650703Swpaul struct rl_softc *sc; 192740516Swpaul 192850703Swpaul sc = device_get_softc(dev); 192950703Swpaul 193040516Swpaul rl_stop(sc); 193140516Swpaul 193240516Swpaul return; 193340516Swpaul} 1934