if_rl.c revision 109095
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 109095 2003-01-11 07:10:35Z sanpei $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 87108729Sjake#include <sys/endian.h> 8840516Swpaul#include <sys/systm.h> 8940516Swpaul#include <sys/sockio.h> 9040516Swpaul#include <sys/mbuf.h> 9140516Swpaul#include <sys/malloc.h> 9240516Swpaul#include <sys/kernel.h> 9340516Swpaul#include <sys/socket.h> 9440516Swpaul 9540516Swpaul#include <net/if.h> 9640516Swpaul#include <net/if_arp.h> 9740516Swpaul#include <net/ethernet.h> 9840516Swpaul#include <net/if_dl.h> 9940516Swpaul#include <net/if_media.h> 10040516Swpaul 10140516Swpaul#include <net/bpf.h> 10240516Swpaul 10341569Swpaul#include <machine/bus_pio.h> 10441569Swpaul#include <machine/bus_memio.h> 10541569Swpaul#include <machine/bus.h> 10650703Swpaul#include <machine/resource.h> 10750703Swpaul#include <sys/bus.h> 10850703Swpaul#include <sys/rman.h> 10940516Swpaul 11050703Swpaul#include <dev/mii/mii.h> 11150703Swpaul#include <dev/mii/miivar.h> 11250703Swpaul 11340516Swpaul#include <pci/pcireg.h> 11440516Swpaul#include <pci/pcivar.h> 11540516Swpaul 11659758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11759758Speter 11851089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11950703Swpaul#include "miibus_if.h" 12050703Swpaul 12140516Swpaul/* 12240516Swpaul * Default to using PIO access for this driver. On SMP systems, 12340516Swpaul * there appear to be problems with memory mapped mode: it looks like 12440516Swpaul * doing too many memory mapped access back to back in rapid succession 12540516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12640516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12740516Swpaul * uniprocessor systems though. 12840516Swpaul */ 12940516Swpaul#define RL_USEIOSPACE 13040516Swpaul 13140516Swpaul#include <pci/if_rlreg.h> 13240516Swpaul 13340516Swpaul#ifndef lint 13441591Sarchiestatic const char rcsid[] = 13550477Speter "$FreeBSD: head/sys/pci/if_rl.c 109095 2003-01-11 07:10:35Z sanpei $"; 13640516Swpaul#endif 13740516Swpaul 13840516Swpaul/* 13940516Swpaul * Various supported device vendors/types and their names. 14040516Swpaul */ 14140516Swpaulstatic struct rl_type rl_devs[] = { 14240516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14340516Swpaul "RealTek 8129 10/100BaseTX" }, 14440516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14540516Swpaul "RealTek 8139 10/100BaseTX" }, 14667771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14767771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14841243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14941243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 15044238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15144238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15244238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15344238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15472813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15572813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15696112Sjhb { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 15796112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 15894400Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 15994400Swpaul "Nortel Networks 10/100BaseTX" }, 160109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 161103020Siwasaki "Corega FEther CB-TXD" }, 162109095Ssanpei { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 163109095Ssanpei "Corega FEtherII CB-TXD" }, 16440516Swpaul { 0, 0, NULL } 16540516Swpaul}; 16640516Swpaul 16792739Salfredstatic int rl_probe (device_t); 16892739Salfredstatic int rl_attach (device_t); 16992739Salfredstatic int rl_detach (device_t); 17040516Swpaul 17192739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 17240516Swpaul 17392739Salfredstatic void rl_rxeof (struct rl_softc *); 17492739Salfredstatic void rl_txeof (struct rl_softc *); 17592739Salfredstatic void rl_intr (void *); 17692739Salfredstatic void rl_tick (void *); 17792739Salfredstatic void rl_start (struct ifnet *); 17892739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17992739Salfredstatic void rl_init (void *); 18092739Salfredstatic void rl_stop (struct rl_softc *); 18192739Salfredstatic void rl_watchdog (struct ifnet *); 18292739Salfredstatic int rl_suspend (device_t); 18392739Salfredstatic int rl_resume (device_t); 18492739Salfredstatic void rl_shutdown (device_t); 18592739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 18692739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 18740516Swpaul 18892739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18992739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 19092739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 19192739Salfredstatic void rl_mii_sync (struct rl_softc *); 19292739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 19392739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 19492739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 19540516Swpaul 19692739Salfredstatic int rl_miibus_readreg (device_t, int, int); 19792739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 19892739Salfredstatic void rl_miibus_statchg (device_t); 19940516Swpaul 20092739Salfredstatic u_int8_t rl_calchash (caddr_t); 20192739Salfredstatic void rl_setmulti (struct rl_softc *); 20292739Salfredstatic void rl_reset (struct rl_softc *); 20392739Salfredstatic int rl_list_tx_init (struct rl_softc *); 20440516Swpaul 20592739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 20692739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 20781713Swpaul 20850703Swpaul#ifdef RL_USEIOSPACE 20950703Swpaul#define RL_RES SYS_RES_IOPORT 21050703Swpaul#define RL_RID RL_PCI_LOIO 21150703Swpaul#else 21250703Swpaul#define RL_RES SYS_RES_MEMORY 21350703Swpaul#define RL_RID RL_PCI_LOMEM 21450703Swpaul#endif 21550703Swpaul 21650703Swpaulstatic device_method_t rl_methods[] = { 21750703Swpaul /* Device interface */ 21850703Swpaul DEVMETHOD(device_probe, rl_probe), 21950703Swpaul DEVMETHOD(device_attach, rl_attach), 22050703Swpaul DEVMETHOD(device_detach, rl_detach), 22186822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 22286822Siwasaki DEVMETHOD(device_resume, rl_resume), 22350703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 22450703Swpaul 22550703Swpaul /* bus interface */ 22650703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22750703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22850703Swpaul 22950703Swpaul /* MII interface */ 23050703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 23150703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 23250703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 23350703Swpaul 23450703Swpaul { 0, 0 } 23550703Swpaul}; 23650703Swpaul 23750703Swpaulstatic driver_t rl_driver = { 23851455Swpaul "rl", 23950703Swpaul rl_methods, 24050703Swpaul sizeof(struct rl_softc) 24150703Swpaul}; 24250703Swpaul 24350703Swpaulstatic devclass_t rl_devclass; 24450703Swpaul 24551533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 24667931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 24751473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 24850703Swpaul 24940516Swpaul#define EE_SET(x) \ 25040516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25140516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 25240516Swpaul 25340516Swpaul#define EE_CLR(x) \ 25440516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25540516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 25640516Swpaul 25781713Swpaulstatic void 25881713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25981713Swpaul void *arg; 26081713Swpaul bus_dma_segment_t *segs; 26181713Swpaul int nseg, error; 26281713Swpaul{ 26381713Swpaul struct rl_softc *sc; 26481713Swpaul 26581713Swpaul sc = arg; 26681713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 26781713Swpaul 26881713Swpaul return; 26981713Swpaul} 27081713Swpaul 27181713Swpaulstatic void 27281713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 27381713Swpaul void *arg; 27481713Swpaul bus_dma_segment_t *segs; 27581713Swpaul int nseg, error; 27681713Swpaul{ 27781713Swpaul struct rl_softc *sc; 27881713Swpaul 27981713Swpaul sc = arg; 28081713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 28181713Swpaul 28281713Swpaul return; 28381713Swpaul} 28481713Swpaul 28540516Swpaul/* 28640516Swpaul * Send a read command and address to the EEPROM, check for ACK. 28740516Swpaul */ 288102335Salfredstatic void 289102335Salfredrl_eeprom_putbyte(sc, addr) 29040516Swpaul struct rl_softc *sc; 29141656Swpaul int addr; 29240516Swpaul{ 29340516Swpaul register int d, i; 29440516Swpaul 29567931Swpaul d = addr | sc->rl_eecmd_read; 29640516Swpaul 29740516Swpaul /* 29855170Sbillf * Feed in each bit and strobe the clock. 29940516Swpaul */ 30040516Swpaul for (i = 0x400; i; i >>= 1) { 30140516Swpaul if (d & i) { 30240516Swpaul EE_SET(RL_EE_DATAIN); 30340516Swpaul } else { 30440516Swpaul EE_CLR(RL_EE_DATAIN); 30540516Swpaul } 30640516Swpaul DELAY(100); 30740516Swpaul EE_SET(RL_EE_CLK); 30840516Swpaul DELAY(150); 30940516Swpaul EE_CLR(RL_EE_CLK); 31040516Swpaul DELAY(100); 31140516Swpaul } 31240516Swpaul 31340516Swpaul return; 31440516Swpaul} 31540516Swpaul 31640516Swpaul/* 31740516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 31840516Swpaul */ 319102335Salfredstatic void 320102335Salfredrl_eeprom_getword(sc, addr, dest) 32140516Swpaul struct rl_softc *sc; 32241656Swpaul int addr; 32340516Swpaul u_int16_t *dest; 32440516Swpaul{ 32540516Swpaul register int i; 32640516Swpaul u_int16_t word = 0; 32740516Swpaul 32840516Swpaul /* Enter EEPROM access mode. */ 32940516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33040516Swpaul 33140516Swpaul /* 33240516Swpaul * Send address of word we want to read. 33340516Swpaul */ 33440516Swpaul rl_eeprom_putbyte(sc, addr); 33540516Swpaul 33640516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33740516Swpaul 33840516Swpaul /* 33940516Swpaul * Start reading bits from EEPROM. 34040516Swpaul */ 34140516Swpaul for (i = 0x8000; i; i >>= 1) { 34240516Swpaul EE_SET(RL_EE_CLK); 34340516Swpaul DELAY(100); 34440516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 34540516Swpaul word |= i; 34640516Swpaul EE_CLR(RL_EE_CLK); 34740516Swpaul DELAY(100); 34840516Swpaul } 34940516Swpaul 35040516Swpaul /* Turn off EEPROM access mode. */ 35140516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 35240516Swpaul 35340516Swpaul *dest = word; 35440516Swpaul 35540516Swpaul return; 35640516Swpaul} 35740516Swpaul 35840516Swpaul/* 35940516Swpaul * Read a sequence of words from the EEPROM. 36040516Swpaul */ 361102335Salfredstatic void 362102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 36340516Swpaul struct rl_softc *sc; 36440516Swpaul caddr_t dest; 36540516Swpaul int off; 36640516Swpaul int cnt; 36740516Swpaul int swap; 36840516Swpaul{ 36940516Swpaul int i; 37040516Swpaul u_int16_t word = 0, *ptr; 37140516Swpaul 37240516Swpaul for (i = 0; i < cnt; i++) { 37340516Swpaul rl_eeprom_getword(sc, off + i, &word); 37440516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 37540516Swpaul if (swap) 37640516Swpaul *ptr = ntohs(word); 37740516Swpaul else 37840516Swpaul *ptr = word; 37940516Swpaul } 38040516Swpaul 38140516Swpaul return; 38240516Swpaul} 38340516Swpaul 38440516Swpaul 38540516Swpaul/* 38640516Swpaul * MII access routines are provided for the 8129, which 38740516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 38840516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 38940516Swpaul * direct access PHY registers. 39040516Swpaul */ 39140516Swpaul#define MII_SET(x) \ 39240516Swpaul CSR_WRITE_1(sc, RL_MII, \ 393105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 39440516Swpaul 39540516Swpaul#define MII_CLR(x) \ 39640516Swpaul CSR_WRITE_1(sc, RL_MII, \ 397105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 39840516Swpaul 39940516Swpaul/* 40040516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 40140516Swpaul */ 402102335Salfredstatic void 403102335Salfredrl_mii_sync(sc) 40440516Swpaul struct rl_softc *sc; 40540516Swpaul{ 40640516Swpaul register int i; 40740516Swpaul 40840516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 40940516Swpaul 41040516Swpaul for (i = 0; i < 32; i++) { 41140516Swpaul MII_SET(RL_MII_CLK); 41240516Swpaul DELAY(1); 41340516Swpaul MII_CLR(RL_MII_CLK); 41440516Swpaul DELAY(1); 41540516Swpaul } 41640516Swpaul 41740516Swpaul return; 41840516Swpaul} 41940516Swpaul 42040516Swpaul/* 42140516Swpaul * Clock a series of bits through the MII. 42240516Swpaul */ 423102335Salfredstatic void 424102335Salfredrl_mii_send(sc, bits, cnt) 42540516Swpaul struct rl_softc *sc; 42640516Swpaul u_int32_t bits; 42740516Swpaul int cnt; 42840516Swpaul{ 42940516Swpaul int i; 43040516Swpaul 43140516Swpaul MII_CLR(RL_MII_CLK); 43240516Swpaul 43340516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 43440516Swpaul if (bits & i) { 43540516Swpaul MII_SET(RL_MII_DATAOUT); 43640516Swpaul } else { 43740516Swpaul MII_CLR(RL_MII_DATAOUT); 43840516Swpaul } 43940516Swpaul DELAY(1); 44040516Swpaul MII_CLR(RL_MII_CLK); 44140516Swpaul DELAY(1); 44240516Swpaul MII_SET(RL_MII_CLK); 44340516Swpaul } 44440516Swpaul} 44540516Swpaul 44640516Swpaul/* 44740516Swpaul * Read an PHY register through the MII. 44840516Swpaul */ 449102335Salfredstatic int 450102335Salfredrl_mii_readreg(sc, frame) 45140516Swpaul struct rl_softc *sc; 45240516Swpaul struct rl_mii_frame *frame; 45340516Swpaul 45440516Swpaul{ 45567087Swpaul int i, ack; 45640516Swpaul 45767087Swpaul RL_LOCK(sc); 45840516Swpaul 45940516Swpaul /* 46040516Swpaul * Set up frame for RX. 46140516Swpaul */ 46240516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 46340516Swpaul frame->mii_opcode = RL_MII_READOP; 46440516Swpaul frame->mii_turnaround = 0; 46540516Swpaul frame->mii_data = 0; 46640516Swpaul 46740516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 46840516Swpaul 46940516Swpaul /* 47040516Swpaul * Turn on data xmit. 47140516Swpaul */ 47240516Swpaul MII_SET(RL_MII_DIR); 47340516Swpaul 47440516Swpaul rl_mii_sync(sc); 47540516Swpaul 47640516Swpaul /* 47740516Swpaul * Send command/address info. 47840516Swpaul */ 47940516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 48040516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 48140516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 48240516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 48340516Swpaul 48440516Swpaul /* Idle bit */ 48540516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 48640516Swpaul DELAY(1); 48740516Swpaul MII_SET(RL_MII_CLK); 48840516Swpaul DELAY(1); 48940516Swpaul 49040516Swpaul /* Turn off xmit. */ 49140516Swpaul MII_CLR(RL_MII_DIR); 49240516Swpaul 49340516Swpaul /* Check for ack */ 49440516Swpaul MII_CLR(RL_MII_CLK); 49540516Swpaul DELAY(1); 496109058Smbr ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 49740516Swpaul MII_SET(RL_MII_CLK); 49840516Swpaul DELAY(1); 49940516Swpaul 50040516Swpaul /* 50140516Swpaul * Now try reading data bits. If the ack failed, we still 50240516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 50340516Swpaul */ 50440516Swpaul if (ack) { 50540516Swpaul for(i = 0; i < 16; i++) { 50640516Swpaul MII_CLR(RL_MII_CLK); 50740516Swpaul DELAY(1); 50840516Swpaul MII_SET(RL_MII_CLK); 50940516Swpaul DELAY(1); 51040516Swpaul } 51140516Swpaul goto fail; 51240516Swpaul } 51340516Swpaul 51440516Swpaul for (i = 0x8000; i; i >>= 1) { 51540516Swpaul MII_CLR(RL_MII_CLK); 51640516Swpaul DELAY(1); 51740516Swpaul if (!ack) { 51840516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 51940516Swpaul frame->mii_data |= i; 52040516Swpaul DELAY(1); 52140516Swpaul } 52240516Swpaul MII_SET(RL_MII_CLK); 52340516Swpaul DELAY(1); 52440516Swpaul } 52540516Swpaul 52640516Swpaulfail: 52740516Swpaul 52840516Swpaul MII_CLR(RL_MII_CLK); 52940516Swpaul DELAY(1); 53040516Swpaul MII_SET(RL_MII_CLK); 53140516Swpaul DELAY(1); 53240516Swpaul 53367087Swpaul RL_UNLOCK(sc); 53440516Swpaul 53540516Swpaul if (ack) 53640516Swpaul return(1); 53740516Swpaul return(0); 53840516Swpaul} 53940516Swpaul 54040516Swpaul/* 54140516Swpaul * Write to a PHY register through the MII. 54240516Swpaul */ 543102335Salfredstatic int 544102335Salfredrl_mii_writereg(sc, frame) 54540516Swpaul struct rl_softc *sc; 54640516Swpaul struct rl_mii_frame *frame; 54740516Swpaul 54840516Swpaul{ 54967087Swpaul RL_LOCK(sc); 55040516Swpaul 55140516Swpaul /* 55240516Swpaul * Set up frame for TX. 55340516Swpaul */ 55440516Swpaul 55540516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 55640516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 55740516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 55840516Swpaul 55940516Swpaul /* 56040516Swpaul * Turn on data output. 56140516Swpaul */ 56240516Swpaul MII_SET(RL_MII_DIR); 56340516Swpaul 56440516Swpaul rl_mii_sync(sc); 56540516Swpaul 56640516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 56740516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 56840516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 56940516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 57040516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 57140516Swpaul rl_mii_send(sc, frame->mii_data, 16); 57240516Swpaul 57340516Swpaul /* Idle bit. */ 57440516Swpaul MII_SET(RL_MII_CLK); 57540516Swpaul DELAY(1); 57640516Swpaul MII_CLR(RL_MII_CLK); 57740516Swpaul DELAY(1); 57840516Swpaul 57940516Swpaul /* 58040516Swpaul * Turn off xmit. 58140516Swpaul */ 58240516Swpaul MII_CLR(RL_MII_DIR); 58340516Swpaul 58467087Swpaul RL_UNLOCK(sc); 58540516Swpaul 58640516Swpaul return(0); 58740516Swpaul} 58840516Swpaul 589102335Salfredstatic int 590102335Salfredrl_miibus_readreg(dev, phy, reg) 59150703Swpaul device_t dev; 59250703Swpaul int phy, reg; 59350703Swpaul{ 59440516Swpaul struct rl_softc *sc; 59540516Swpaul struct rl_mii_frame frame; 59640516Swpaul u_int16_t rval = 0; 59740516Swpaul u_int16_t rl8139_reg = 0; 59840516Swpaul 59950703Swpaul sc = device_get_softc(dev); 60067087Swpaul RL_LOCK(sc); 60150703Swpaul 60240516Swpaul if (sc->rl_type == RL_8139) { 60350703Swpaul /* Pretend the internal PHY is only at address 0 */ 60467087Swpaul if (phy) { 60567087Swpaul RL_UNLOCK(sc); 60650703Swpaul return(0); 60767087Swpaul } 60840516Swpaul switch(reg) { 60950703Swpaul case MII_BMCR: 61040516Swpaul rl8139_reg = RL_BMCR; 61140516Swpaul break; 61250703Swpaul case MII_BMSR: 61340516Swpaul rl8139_reg = RL_BMSR; 61440516Swpaul break; 61550703Swpaul case MII_ANAR: 61640516Swpaul rl8139_reg = RL_ANAR; 61740516Swpaul break; 61850703Swpaul case MII_ANER: 61950703Swpaul rl8139_reg = RL_ANER; 62050703Swpaul break; 62150703Swpaul case MII_ANLPAR: 62240516Swpaul rl8139_reg = RL_LPAR; 62340516Swpaul break; 62450703Swpaul case MII_PHYIDR1: 62550703Swpaul case MII_PHYIDR2: 62667087Swpaul RL_UNLOCK(sc); 62750703Swpaul return(0); 62850703Swpaul break; 62994149Swpaul /* 63094149Swpaul * Allow the rlphy driver to read the media status 63194149Swpaul * register. If we have a link partner which does not 63294149Swpaul * support NWAY, this is the register which will tell 63394149Swpaul * us the results of parallel detection. 63494149Swpaul */ 63594149Swpaul case RL_MEDIASTAT: 63694149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 63794149Swpaul RL_UNLOCK(sc); 63894149Swpaul return(rval); 63994149Swpaul break; 64040516Swpaul default: 64140516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 64267087Swpaul RL_UNLOCK(sc); 64340516Swpaul return(0); 64440516Swpaul } 64540516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 64667087Swpaul RL_UNLOCK(sc); 64740516Swpaul return(rval); 64840516Swpaul } 64940516Swpaul 65040516Swpaul bzero((char *)&frame, sizeof(frame)); 65140516Swpaul 65250703Swpaul frame.mii_phyaddr = phy; 65340516Swpaul frame.mii_regaddr = reg; 65440516Swpaul rl_mii_readreg(sc, &frame); 65567087Swpaul RL_UNLOCK(sc); 65640516Swpaul 65740516Swpaul return(frame.mii_data); 65840516Swpaul} 65940516Swpaul 660102335Salfredstatic int 661102335Salfredrl_miibus_writereg(dev, phy, reg, data) 66250703Swpaul device_t dev; 66350703Swpaul int phy, reg, data; 66450703Swpaul{ 66540516Swpaul struct rl_softc *sc; 66640516Swpaul struct rl_mii_frame frame; 66740516Swpaul u_int16_t rl8139_reg = 0; 66840516Swpaul 66950703Swpaul sc = device_get_softc(dev); 67067087Swpaul RL_LOCK(sc); 67150703Swpaul 67240516Swpaul if (sc->rl_type == RL_8139) { 67350703Swpaul /* Pretend the internal PHY is only at address 0 */ 67467087Swpaul if (phy) { 67567087Swpaul RL_UNLOCK(sc); 67650703Swpaul return(0); 67767087Swpaul } 67840516Swpaul switch(reg) { 67950703Swpaul case MII_BMCR: 68040516Swpaul rl8139_reg = RL_BMCR; 68140516Swpaul break; 68250703Swpaul case MII_BMSR: 68340516Swpaul rl8139_reg = RL_BMSR; 68440516Swpaul break; 68550703Swpaul case MII_ANAR: 68640516Swpaul rl8139_reg = RL_ANAR; 68740516Swpaul break; 68850703Swpaul case MII_ANER: 68950703Swpaul rl8139_reg = RL_ANER; 69050703Swpaul break; 69150703Swpaul case MII_ANLPAR: 69240516Swpaul rl8139_reg = RL_LPAR; 69340516Swpaul break; 69450703Swpaul case MII_PHYIDR1: 69550703Swpaul case MII_PHYIDR2: 69667087Swpaul RL_UNLOCK(sc); 69750703Swpaul return(0); 69850703Swpaul break; 69940516Swpaul default: 70040516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 70167087Swpaul RL_UNLOCK(sc); 70250703Swpaul return(0); 70340516Swpaul } 70440516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 70567087Swpaul RL_UNLOCK(sc); 70650703Swpaul return(0); 70740516Swpaul } 70840516Swpaul 70940516Swpaul bzero((char *)&frame, sizeof(frame)); 71040516Swpaul 71150703Swpaul frame.mii_phyaddr = phy; 71240516Swpaul frame.mii_regaddr = reg; 71340516Swpaul frame.mii_data = data; 71440516Swpaul 71540516Swpaul rl_mii_writereg(sc, &frame); 71640516Swpaul 71767087Swpaul RL_UNLOCK(sc); 71850703Swpaul return(0); 71950703Swpaul} 72050703Swpaul 721102335Salfredstatic void 722102335Salfredrl_miibus_statchg(dev) 72350703Swpaul device_t dev; 72450703Swpaul{ 72540516Swpaul return; 72640516Swpaul} 72740516Swpaul 72840516Swpaul/* 72943062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 73040516Swpaul */ 731102335Salfredstatic u_int8_t 732102335Salfredrl_calchash(addr) 73341656Swpaul caddr_t addr; 73440516Swpaul{ 73540516Swpaul u_int32_t crc, carry; 73640516Swpaul int i, j; 73740516Swpaul u_int8_t c; 73840516Swpaul 73940516Swpaul /* Compute CRC for the address value. */ 74040516Swpaul crc = 0xFFFFFFFF; /* initial value */ 74140516Swpaul 74240516Swpaul for (i = 0; i < 6; i++) { 74340516Swpaul c = *(addr + i); 74440516Swpaul for (j = 0; j < 8; j++) { 74540516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 74640516Swpaul crc <<= 1; 74740516Swpaul c >>= 1; 74840516Swpaul if (carry) 74940516Swpaul crc = (crc ^ 0x04c11db6) | carry; 75040516Swpaul } 75140516Swpaul } 75240516Swpaul 75340516Swpaul /* return the filter bit position */ 75443062Swpaul return(crc >> 26); 75540516Swpaul} 75640516Swpaul 75740516Swpaul/* 75840516Swpaul * Program the 64-bit multicast hash filter. 75940516Swpaul */ 760102335Salfredstatic void 761102335Salfredrl_setmulti(sc) 76240516Swpaul struct rl_softc *sc; 76340516Swpaul{ 76440516Swpaul struct ifnet *ifp; 76540516Swpaul int h = 0; 76640516Swpaul u_int32_t hashes[2] = { 0, 0 }; 76740516Swpaul struct ifmultiaddr *ifma; 76840516Swpaul u_int32_t rxfilt; 76940516Swpaul int mcnt = 0; 77040516Swpaul 77140516Swpaul ifp = &sc->arpcom.ac_if; 77240516Swpaul 77340516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 77440516Swpaul 77543062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 77640516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 77740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 77840516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 77940516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 78040516Swpaul return; 78140516Swpaul } 78240516Swpaul 78340516Swpaul /* first, zot all the existing hash bits */ 78440516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 78540516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 78640516Swpaul 78740516Swpaul /* now program new ones */ 78872084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 78940516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 79040516Swpaul continue; 79140516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 79240516Swpaul if (h < 32) 79340516Swpaul hashes[0] |= (1 << h); 79440516Swpaul else 79540516Swpaul hashes[1] |= (1 << (h - 32)); 79640516Swpaul mcnt++; 79740516Swpaul } 79840516Swpaul 79940516Swpaul if (mcnt) 80040516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 80140516Swpaul else 80240516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 80340516Swpaul 80440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 80540516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 80640516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 80740516Swpaul 80840516Swpaul return; 80940516Swpaul} 81040516Swpaul 811102335Salfredstatic void 812102335Salfredrl_reset(sc) 81340516Swpaul struct rl_softc *sc; 81440516Swpaul{ 81540516Swpaul register int i; 81640516Swpaul 81740516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 81840516Swpaul 81940516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 82040516Swpaul DELAY(10); 82140516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 82240516Swpaul break; 82340516Swpaul } 82440516Swpaul if (i == RL_TIMEOUT) 82540516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 82640516Swpaul 82740516Swpaul return; 82840516Swpaul} 82940516Swpaul 83040516Swpaul/* 83140516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 83240516Swpaul * IDs against our list and return a device name if we find a match. 83340516Swpaul */ 834102335Salfredstatic int 835102335Salfredrl_probe(dev) 83650703Swpaul device_t dev; 83740516Swpaul{ 83840516Swpaul struct rl_type *t; 83940516Swpaul 84040516Swpaul t = rl_devs; 84140516Swpaul 84240516Swpaul while(t->rl_name != NULL) { 84350703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 84450703Swpaul (pci_get_device(dev) == t->rl_did)) { 84550703Swpaul device_set_desc(dev, t->rl_name); 84650703Swpaul return(0); 84740516Swpaul } 84840516Swpaul t++; 84940516Swpaul } 85040516Swpaul 85150703Swpaul return(ENXIO); 85240516Swpaul} 85340516Swpaul 85440516Swpaul/* 85540516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 85640516Swpaul * setup and ethernet/BPF attach. 85740516Swpaul */ 858102335Salfredstatic int 859102335Salfredrl_attach(dev) 86050703Swpaul device_t dev; 86140516Swpaul{ 86240516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 86340516Swpaul u_int32_t command; 864108729Sjake u_int16_t as[3]; 86540516Swpaul struct rl_softc *sc; 86640516Swpaul struct ifnet *ifp; 86740516Swpaul u_int16_t rl_did = 0; 868108729Sjake int unit, error = 0, rid, i; 86940516Swpaul 87050703Swpaul sc = device_get_softc(dev); 87150703Swpaul unit = device_get_unit(dev); 87240516Swpaul bzero(sc, sizeof(struct rl_softc)); 87340516Swpaul 87493818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 87593818Sjhb MTX_DEF | MTX_RECURSE); 87669583Swpaul 87740516Swpaul /* 87840516Swpaul * Handle power management nonsense. 87940516Swpaul */ 88040516Swpaul 88170167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 88270167Swpaul u_int32_t iobase, membase, irq; 88340516Swpaul 88470167Swpaul /* Save important PCI config data. */ 88570167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 88670167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 88770167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 88840516Swpaul 88970167Swpaul /* Reset the power state. */ 89070167Swpaul printf("rl%d: chip is is in D%d power mode " 89170167Swpaul "-- setting to D0\n", unit, 89270167Swpaul pci_get_powerstate(dev)); 89340516Swpaul 89470167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 89540516Swpaul 89670167Swpaul /* Restore PCI config data. */ 89770167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 89870167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 89970167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 90040516Swpaul } 90140516Swpaul 90240516Swpaul /* 90340516Swpaul * Map control/status registers. 90440516Swpaul */ 90572813Swpaul pci_enable_busmaster(dev); 90679472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 90779472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 90861041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 90940516Swpaul 91040516Swpaul#ifdef RL_USEIOSPACE 91140516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 91240516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 91350703Swpaul error = ENXIO; 91440516Swpaul goto fail; 91540516Swpaul } 91640516Swpaul#else 91740516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 91840516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 91950703Swpaul error = ENXIO; 92040516Swpaul goto fail; 92140516Swpaul } 92250703Swpaul#endif 92340516Swpaul 92450703Swpaul rid = RL_RID; 92550703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 92650703Swpaul 0, ~0, 1, RF_ACTIVE); 92750703Swpaul 92850703Swpaul if (sc->rl_res == NULL) { 92950703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 93050703Swpaul error = ENXIO; 93140516Swpaul goto fail; 93240516Swpaul } 93340516Swpaul 93469127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 93569127Sroger * unstable when left to autoselect the media 93669127Sroger * The best workaround is to set the device to the required 93769127Sroger * media type or to set it to the 10 Meg speed. 93869127Sroger */ 93969127Sroger 94069127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 94169127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 94269127Sroger } 94369127Sroger 94450703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 94550703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 94650703Swpaul 94750703Swpaul rid = 0; 94850703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 94950703Swpaul RF_SHAREABLE | RF_ACTIVE); 95050703Swpaul 95150703Swpaul if (sc->rl_irq == NULL) { 95240516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 95350703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 95450703Swpaul error = ENXIO; 95540516Swpaul goto fail; 95640516Swpaul } 95740516Swpaul 95840516Swpaul /* Reset the adapter. */ 95940516Swpaul rl_reset(sc); 96067931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 96167931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 96268215Swpaul if (rl_did != 0x8129) 96367931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 96440516Swpaul 96540516Swpaul /* 96640516Swpaul * Get station address from the EEPROM. 96740516Swpaul */ 968108729Sjake rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 969108729Sjake for (i = 0; i < 3; i++) { 970108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 971108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 972108729Sjake } 97340516Swpaul 97440516Swpaul /* 97540516Swpaul * A RealTek chip was detected. Inform the world. 97640516Swpaul */ 97740516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 97840516Swpaul 97940516Swpaul sc->rl_unit = unit; 98040516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 98140516Swpaul 98240516Swpaul /* 98340516Swpaul * Now read the exact device type from the EEPROM to find 98440516Swpaul * out if it's an 8129 or 8139. 98540516Swpaul */ 98640516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 98740516Swpaul 98844238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 98967771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 99096112Sjhb rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 991109095Ssanpei rl_did == DLINK_DEVICEID_690TXD || rl_did == COREGA_DEVICEID_CBTXD || 992109095Ssanpei rl_did == COREGA_DEVICEID_CBTXD) 99340516Swpaul sc->rl_type = RL_8139; 99440516Swpaul else if (rl_did == RT_DEVICEID_8129) 99540516Swpaul sc->rl_type = RL_8129; 99640516Swpaul else { 99740516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 99868215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 99950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 100050703Swpaul error = ENXIO; 100140516Swpaul goto fail; 100240516Swpaul } 100340516Swpaul 100481713Swpaul /* 100581713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 100681713Swpaul */ 100781713Swpaul#define RL_NSEG_NEW 32 1008104324Sphk error = bus_dma_tag_create(NULL, /* parent */ 100981713Swpaul 1, 0, /* alignment, boundary */ 101081713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 101181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 101281713Swpaul NULL, NULL, /* filter, filterarg */ 101381713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 101481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 101581713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 101681713Swpaul &sc->rl_parent_tag); 101740516Swpaul 101881713Swpaul /* 101981713Swpaul * Now allocate a tag for the DMA descriptor lists. 102081713Swpaul * All of our lists are allocated as a contiguous block 102181713Swpaul * of memory. 102281713Swpaul */ 102381713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 102481713Swpaul 1, 0, /* alignment, boundary */ 102581713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 102681713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 102781713Swpaul NULL, NULL, /* filter, filterarg */ 102881713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 102981713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 103081713Swpaul 0, /* flags */ 103181713Swpaul &sc->rl_tag); 103281713Swpaul 103381713Swpaul /* 103481713Swpaul * Now allocate a chunk of DMA-able memory based on the 103581713Swpaul * tag we just created. 103681713Swpaul */ 103781713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 103881713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 103981713Swpaul &sc->rl_cdata.rl_rx_dmamap); 104081713Swpaul 104140516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 104240516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 104368215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 104450703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 104581713Swpaul bus_dma_tag_destroy(sc->rl_tag); 104650703Swpaul error = ENXIO; 104740516Swpaul goto fail; 104840516Swpaul } 104940516Swpaul 105048028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 105148028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 105248028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 105348028Swpaul 105450703Swpaul /* Do MII setup */ 105550703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 105650703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 105750703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 105868215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 105950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 106081713Swpaul bus_dmamem_free(sc->rl_tag, 106181713Swpaul sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 106281713Swpaul bus_dma_tag_destroy(sc->rl_tag); 106350703Swpaul error = ENXIO; 106450703Swpaul goto fail; 106550703Swpaul } 106650703Swpaul 106740516Swpaul ifp = &sc->arpcom.ac_if; 106840516Swpaul ifp->if_softc = sc; 106940516Swpaul ifp->if_unit = unit; 107040516Swpaul ifp->if_name = "rl"; 107140516Swpaul ifp->if_mtu = ETHERMTU; 107240516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 107340516Swpaul ifp->if_ioctl = rl_ioctl; 107440516Swpaul ifp->if_output = ether_output; 107540516Swpaul ifp->if_start = rl_start; 107640516Swpaul ifp->if_watchdog = rl_watchdog; 107740516Swpaul ifp->if_init = rl_init; 107840516Swpaul ifp->if_baudrate = 10000000; 107945633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 108040516Swpaul 108140516Swpaul /* 108263090Sarchie * Call MI attach routine. 108340516Swpaul */ 1084106936Ssam ether_ifattach(ifp, eaddr); 1085106157Simp 1086106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1087106157Simp rl_intr, sc, &sc->rl_intrhand); 1088106157Simp 1089106157Simp if (error) { 1090106157Simp printf("rl%d: couldn't set up irq\n", unit); 1091106157Simp bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1092106157Simp bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1093106157Simp bus_dmamem_free(sc->rl_tag, 1094106157Simp sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1095106157Simp bus_dma_tag_destroy(sc->rl_tag); 1096106157Simp goto fail; 1097106157Simp } 1098106157Simp 1099106157Simp callout_handle_init(&sc->rl_stat_ch); 110067087Swpaul return(0); 110140516Swpaulfail: 110267087Swpaul mtx_destroy(&sc->rl_mtx); 110350703Swpaul return(error); 110440516Swpaul} 110540516Swpaul 1106102335Salfredstatic int 1107102335Salfredrl_detach(dev) 110850703Swpaul device_t dev; 110950703Swpaul{ 111050703Swpaul struct rl_softc *sc; 111150703Swpaul struct ifnet *ifp; 111250703Swpaul 111350703Swpaul sc = device_get_softc(dev); 111467087Swpaul RL_LOCK(sc); 111550703Swpaul ifp = &sc->arpcom.ac_if; 111650703Swpaul 1117106936Ssam ether_ifdetach(ifp); 111850703Swpaul rl_stop(sc); 111950703Swpaul 112050703Swpaul bus_generic_detach(dev); 112150703Swpaul device_delete_child(dev, sc->rl_miibus); 112250703Swpaul 112350703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 112468215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 112550703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 112650703Swpaul 112781713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 112881713Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 112981713Swpaul sc->rl_cdata.rl_rx_dmamap); 113081713Swpaul bus_dma_tag_destroy(sc->rl_tag); 113181713Swpaul bus_dma_tag_destroy(sc->rl_parent_tag); 113250703Swpaul 113367087Swpaul RL_UNLOCK(sc); 113467087Swpaul mtx_destroy(&sc->rl_mtx); 113550703Swpaul 113650703Swpaul return(0); 113750703Swpaul} 113850703Swpaul 113940516Swpaul/* 114040516Swpaul * Initialize the transmit descriptors. 114140516Swpaul */ 1142102335Salfredstatic int 1143102335Salfredrl_list_tx_init(sc) 114440516Swpaul struct rl_softc *sc; 114540516Swpaul{ 114640516Swpaul struct rl_chain_data *cd; 114740516Swpaul int i; 114840516Swpaul 114940516Swpaul cd = &sc->rl_cdata; 115040516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 115145633Swpaul cd->rl_tx_chain[i] = NULL; 115248028Swpaul CSR_WRITE_4(sc, 115348028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 115440516Swpaul } 115540516Swpaul 115645633Swpaul sc->rl_cdata.cur_tx = 0; 115745633Swpaul sc->rl_cdata.last_tx = 0; 115840516Swpaul 115940516Swpaul return(0); 116040516Swpaul} 116140516Swpaul 116240516Swpaul/* 116340516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 116440516Swpaul * the higher level protocols. 116540516Swpaul * 116640516Swpaul * You know there's something wrong with a PCI bus-master chip design 116740516Swpaul * when you have to use m_devget(). 116840516Swpaul * 116940516Swpaul * The receive operation is badly documented in the datasheet, so I'll 117040516Swpaul * attempt to document it here. The driver provides a buffer area and 117140516Swpaul * places its base address in the RX buffer start address register. 117240516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 117372645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 117440516Swpaul * of the frame and certain other status bits. Each frame (starting with 117540516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 117640516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 117740516Swpaul * the 'rx status register' mentioned in the datasheet. 117848028Swpaul * 117948028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 118078508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 118178508Sbmilekic * as the offset argument to m_devget(). 118240516Swpaul */ 1183102335Salfredstatic void 1184102335Salfredrl_rxeof(sc) 118540516Swpaul struct rl_softc *sc; 118640516Swpaul{ 118740516Swpaul struct mbuf *m; 118840516Swpaul struct ifnet *ifp; 118940516Swpaul int total_len = 0; 119040516Swpaul u_int32_t rxstat; 119140516Swpaul caddr_t rxbufpos; 119240516Swpaul int wrap = 0; 119340516Swpaul u_int16_t cur_rx; 119440516Swpaul u_int16_t limit; 119540516Swpaul u_int16_t rx_bytes = 0, max_bytes; 119640516Swpaul 119740516Swpaul ifp = &sc->arpcom.ac_if; 119840516Swpaul 119981713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1200108729Sjake BUS_DMASYNC_POSTREAD); 120181713Swpaul 120240516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 120340516Swpaul 120440516Swpaul /* Do not try to read past this point. */ 120540516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 120640516Swpaul 120740516Swpaul if (limit < cur_rx) 120840516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 120940516Swpaul else 121040516Swpaul max_bytes = limit - cur_rx; 121140516Swpaul 121242738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 121394883Sluigi#ifdef DEVICE_POLLING 1214102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 121594883Sluigi if (sc->rxcycles <= 0) 121694883Sluigi break; 121794883Sluigi sc->rxcycles--; 121894883Sluigi } 121994883Sluigi#endif /* DEVICE_POLLING */ 122040516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1221108729Sjake rxstat = le32toh(*(u_int32_t *)rxbufpos); 122240516Swpaul 122340516Swpaul /* 122440516Swpaul * Here's a totally undocumented fact for you. When the 122540516Swpaul * RealTek chip is in the process of copying a packet into 122640516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 122740516Swpaul * packet header with this value, you need to stop. The 122840516Swpaul * datasheet makes absolutely no mention of this and 122940516Swpaul * RealTek should be shot for this. 123040516Swpaul */ 123140516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 123240516Swpaul break; 123340516Swpaul 123440516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 123540516Swpaul ifp->if_ierrors++; 123650703Swpaul rl_init(sc); 123750703Swpaul return; 123840516Swpaul } 123940516Swpaul 124040516Swpaul /* No errors; receive the packet. */ 124140516Swpaul total_len = rxstat >> 16; 124240516Swpaul rx_bytes += total_len + 4; 124340516Swpaul 124440516Swpaul /* 124542051Swpaul * XXX The RealTek chip includes the CRC with every 124642051Swpaul * received frame, and there's no way to turn this 124742051Swpaul * behavior off (at least, I can't find anything in 124842051Swpaul * the manual that explains how to do it) so we have 124942051Swpaul * to trim off the CRC manually. 125042051Swpaul */ 125142051Swpaul total_len -= ETHER_CRC_LEN; 125242051Swpaul 125342051Swpaul /* 125440516Swpaul * Avoid trying to read more bytes than we know 125540516Swpaul * the chip has prepared for us. 125640516Swpaul */ 125740516Swpaul if (rx_bytes > max_bytes) 125840516Swpaul break; 125940516Swpaul 126040516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 126140516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 126240516Swpaul 126340516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 126440516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 126540516Swpaul 126640516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 126740516Swpaul 126840516Swpaul if (total_len > wrap) { 126978508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 127078508Sbmilekic NULL); 127140516Swpaul if (m == NULL) { 127240516Swpaul ifp->if_ierrors++; 127352426Swpaul } else { 127440516Swpaul m_copyback(m, wrap, total_len - wrap, 127540516Swpaul sc->rl_cdata.rl_rx_buf); 127648028Swpaul } 127742051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 127840516Swpaul } else { 127978508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 128078508Sbmilekic NULL); 128140516Swpaul if (m == NULL) { 128240516Swpaul ifp->if_ierrors++; 128378508Sbmilekic } 128442051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 128540516Swpaul } 128640516Swpaul 128740516Swpaul /* 128840516Swpaul * Round up to 32-bit boundary. 128940516Swpaul */ 129040516Swpaul cur_rx = (cur_rx + 3) & ~3; 129140516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 129240516Swpaul 129340516Swpaul if (m == NULL) 129440516Swpaul continue; 129540516Swpaul 129640516Swpaul ifp->if_ipackets++; 1297106936Ssam (*ifp->if_input)(ifp, m); 129840516Swpaul } 129940516Swpaul 130040516Swpaul return; 130140516Swpaul} 130240516Swpaul 130340516Swpaul/* 130440516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 130540516Swpaul * the list buffers. 130640516Swpaul */ 1307102335Salfredstatic void 1308102335Salfredrl_txeof(sc) 130940516Swpaul struct rl_softc *sc; 131040516Swpaul{ 131140516Swpaul struct ifnet *ifp; 131240516Swpaul u_int32_t txstat; 131340516Swpaul 131440516Swpaul ifp = &sc->arpcom.ac_if; 131540516Swpaul 131640516Swpaul /* 131740516Swpaul * Go through our tx list and free mbufs for those 131840516Swpaul * frames that have been uploaded. 131940516Swpaul */ 132045633Swpaul do { 132145633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 132245633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 132345633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 132440516Swpaul break; 132540516Swpaul 132645633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 132740516Swpaul 132845633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 132981713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 133081713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 133145633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 133245633Swpaul RL_LAST_TXMBUF(sc) = NULL; 133345633Swpaul } 133445633Swpaul if (txstat & RL_TXSTAT_TX_OK) 133545633Swpaul ifp->if_opackets++; 133645633Swpaul else { 133752426Swpaul int oldthresh; 133845633Swpaul ifp->if_oerrors++; 133945633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 134045633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 134145633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 134252426Swpaul oldthresh = sc->rl_txthresh; 134352426Swpaul /* error recovery */ 134452426Swpaul rl_reset(sc); 134552426Swpaul rl_init(sc); 134652426Swpaul /* 134752426Swpaul * If there was a transmit underrun, 134852426Swpaul * bump the TX threshold. 134952426Swpaul */ 135052426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 135152426Swpaul sc->rl_txthresh = oldthresh + 32; 135252426Swpaul return; 135345633Swpaul } 135445633Swpaul RL_INC(sc->rl_cdata.last_tx); 135545633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 135645633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 135740516Swpaul 135899165Sluigi ifp->if_timer = 135999165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 136099165Sluigi 136150703Swpaul return; 136250703Swpaul} 136340516Swpaul 1364102335Salfredstatic void 1365102335Salfredrl_tick(xsc) 136650703Swpaul void *xsc; 136750703Swpaul{ 136850703Swpaul struct rl_softc *sc; 136950703Swpaul struct mii_data *mii; 137050703Swpaul 137150703Swpaul sc = xsc; 137267087Swpaul RL_LOCK(sc); 137350703Swpaul mii = device_get_softc(sc->rl_miibus); 137450703Swpaul 137550703Swpaul mii_tick(mii); 137650703Swpaul 137750703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 137867087Swpaul RL_UNLOCK(sc); 137950703Swpaul 138040516Swpaul return; 138140516Swpaul} 138240516Swpaul 138394883Sluigi#ifdef DEVICE_POLLING 138494883Sluigistatic void 138594883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 138694883Sluigi{ 138794883Sluigi struct rl_softc *sc = ifp->if_softc; 138894883Sluigi 138994883Sluigi RL_LOCK(sc); 139094883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 139194883Sluigi CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 139294883Sluigi goto done; 139394883Sluigi } 139494883Sluigi 139594883Sluigi sc->rxcycles = count; 139694883Sluigi rl_rxeof(sc); 139794883Sluigi rl_txeof(sc); 139894883Sluigi if (ifp->if_snd.ifq_head != NULL) 139994883Sluigi rl_start(ifp); 140094883Sluigi 140194883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 140294883Sluigi u_int16_t status; 140394883Sluigi 140494883Sluigi status = CSR_READ_2(sc, RL_ISR); 1405100957Sjhb if (status == 0xffff) 1406100957Sjhb goto done; 140794883Sluigi if (status) 140894883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 140994883Sluigi 141094883Sluigi /* 141194883Sluigi * XXX check behaviour on receiver stalls. 141294883Sluigi */ 141394883Sluigi 141494883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 141594883Sluigi rl_reset(sc); 141694883Sluigi rl_init(sc); 141794883Sluigi } 141894883Sluigi } 141994883Sluigidone: 142094883Sluigi RL_UNLOCK(sc); 142194883Sluigi} 142294883Sluigi#endif /* DEVICE_POLLING */ 142394883Sluigi 1424102335Salfredstatic void 1425102335Salfredrl_intr(arg) 142640516Swpaul void *arg; 142740516Swpaul{ 142840516Swpaul struct rl_softc *sc; 142940516Swpaul struct ifnet *ifp; 143040516Swpaul u_int16_t status; 143140516Swpaul 143240516Swpaul sc = arg; 143386822Siwasaki 143486822Siwasaki if (sc->suspended) { 143586822Siwasaki return; 143686822Siwasaki } 143786822Siwasaki 143867087Swpaul RL_LOCK(sc); 143940516Swpaul ifp = &sc->arpcom.ac_if; 144040516Swpaul 144194883Sluigi#ifdef DEVICE_POLLING 1442102052Ssobomax if (ifp->if_flags & IFF_POLLING) 144394883Sluigi goto done; 144494883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 144594883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 144694883Sluigi rl_poll(ifp, 0, 1); 144794883Sluigi goto done; 144894883Sluigi } 144994883Sluigi#endif /* DEVICE_POLLING */ 145040516Swpaul 145140516Swpaul for (;;) { 145240516Swpaul 145340516Swpaul status = CSR_READ_2(sc, RL_ISR); 1454100957Sjhb /* If the card has gone away the read returns 0xffff. */ 1455100957Sjhb if (status == 0xffff) 1456100957Sjhb break; 145740516Swpaul if (status) 145840516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 145940516Swpaul 146040516Swpaul if ((status & RL_INTRS) == 0) 146140516Swpaul break; 146240516Swpaul 146340516Swpaul if (status & RL_ISR_RX_OK) 146440516Swpaul rl_rxeof(sc); 146540516Swpaul 146640516Swpaul if (status & RL_ISR_RX_ERR) 146740516Swpaul rl_rxeof(sc); 146840516Swpaul 146945633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 147040516Swpaul rl_txeof(sc); 147140516Swpaul 147240516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 147340516Swpaul rl_reset(sc); 147440516Swpaul rl_init(sc); 147540516Swpaul } 147640516Swpaul 147740516Swpaul } 147840516Swpaul 147952426Swpaul if (ifp->if_snd.ifq_head != NULL) 148040516Swpaul rl_start(ifp); 148140516Swpaul 148294883Sluigi#ifdef DEVICE_POLLING 148394883Sluigidone: 148494883Sluigi#endif 148567087Swpaul RL_UNLOCK(sc); 148667087Swpaul 148740516Swpaul return; 148840516Swpaul} 148940516Swpaul 149040516Swpaul/* 149140516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 149240516Swpaul * pointers to the fragment pointers. 149340516Swpaul */ 1494102335Salfredstatic int 1495102335Salfredrl_encap(sc, m_head) 149640516Swpaul struct rl_softc *sc; 149740516Swpaul struct mbuf *m_head; 149840516Swpaul{ 149941243Swpaul struct mbuf *m_new = NULL; 150040516Swpaul 150140516Swpaul /* 150245633Swpaul * The RealTek is brain damaged and wants longword-aligned 150345633Swpaul * TX buffers, plus we can only have one fragment buffer 150445633Swpaul * per packet. We have to copy pretty much all the time. 150540516Swpaul */ 150640516Swpaul 150741243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 150887846Sluigi if (m_new == NULL) 150941243Swpaul return(1); 151041243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 151141243Swpaul MCLGET(m_new, M_DONTWAIT); 151241243Swpaul if (!(m_new->m_flags & M_EXT)) { 151341243Swpaul m_freem(m_new); 151440516Swpaul return(1); 151540516Swpaul } 151640516Swpaul } 151752426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 151841243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 151941243Swpaul m_freem(m_head); 152041243Swpaul m_head = m_new; 152140516Swpaul 152240516Swpaul /* Pad frames to at least 60 bytes. */ 152341243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 152455058Swpaul /* 152555058Swpaul * Make security concious people happy: zero out the 152655058Swpaul * bytes in the pad area, since we don't know what 152755058Swpaul * this mbuf cluster buffer's previous user might 152855058Swpaul * have left in it. 152955058Swpaul */ 153055058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 153155058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 153240516Swpaul m_head->m_pkthdr.len += 153352426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 153441243Swpaul m_head->m_len = m_head->m_pkthdr.len; 153541243Swpaul } 153640516Swpaul 153745633Swpaul RL_CUR_TXMBUF(sc) = m_head; 153840516Swpaul 153940516Swpaul return(0); 154040516Swpaul} 154140516Swpaul 154240516Swpaul/* 154340516Swpaul * Main transmit routine. 154440516Swpaul */ 154540516Swpaul 1546102335Salfredstatic void 1547102335Salfredrl_start(ifp) 154840516Swpaul struct ifnet *ifp; 154940516Swpaul{ 155040516Swpaul struct rl_softc *sc; 155140516Swpaul struct mbuf *m_head = NULL; 155240516Swpaul 155340516Swpaul sc = ifp->if_softc; 155467087Swpaul RL_LOCK(sc); 155540516Swpaul 155645633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 155740516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 155840516Swpaul if (m_head == NULL) 155940516Swpaul break; 156040516Swpaul 156158801Swpaul if (rl_encap(sc, m_head)) { 156258801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 156358801Swpaul ifp->if_flags |= IFF_OACTIVE; 156458801Swpaul break; 156558801Swpaul } 156640516Swpaul 156740516Swpaul /* 156840516Swpaul * If there's a BPF listener, bounce a copy of this frame 156940516Swpaul * to him. 157040516Swpaul */ 1571106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 157251583Swpaul 157340516Swpaul /* 157440516Swpaul * Transmit the frame. 157540516Swpaul */ 157681713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 157781713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 157881713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 157981713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 158081713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 158181713Swpaul BUS_DMASYNC_PREREAD); 158245633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 158352426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 158452426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 158545633Swpaul 158645633Swpaul RL_INC(sc->rl_cdata.cur_tx); 158740516Swpaul } 158840516Swpaul 158940516Swpaul /* 159045633Swpaul * We broke out of the loop because all our TX slots are 159145633Swpaul * full. Mark the NIC as busy until it drains some of the 159245633Swpaul * packets from the queue. 159345633Swpaul */ 159445633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 159545633Swpaul ifp->if_flags |= IFF_OACTIVE; 159645633Swpaul 159745633Swpaul /* 159840516Swpaul * Set a timeout in case the chip goes out to lunch. 159940516Swpaul */ 160040516Swpaul ifp->if_timer = 5; 160167087Swpaul RL_UNLOCK(sc); 160240516Swpaul 160340516Swpaul return; 160440516Swpaul} 160540516Swpaul 1606102335Salfredstatic void 1607102335Salfredrl_init(xsc) 160840516Swpaul void *xsc; 160940516Swpaul{ 161040516Swpaul struct rl_softc *sc = xsc; 161140516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 161250703Swpaul struct mii_data *mii; 161367087Swpaul int i; 161440516Swpaul u_int32_t rxcfg = 0; 161540516Swpaul 161667087Swpaul RL_LOCK(sc); 161750703Swpaul mii = device_get_softc(sc->rl_miibus); 161840516Swpaul 161940516Swpaul /* 162040516Swpaul * Cancel pending I/O and free all RX/TX buffers. 162140516Swpaul */ 162240516Swpaul rl_stop(sc); 162340516Swpaul 162440516Swpaul /* Init our MAC address */ 162540516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 162640516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 162740516Swpaul } 162840516Swpaul 162940516Swpaul /* Init the RX buffer pointer register. */ 163081713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 163181713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 163281713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 163381713Swpaul BUS_DMASYNC_PREWRITE); 163440516Swpaul 163540516Swpaul /* Init TX descriptors. */ 163640516Swpaul rl_list_tx_init(sc); 163740516Swpaul 163840516Swpaul /* 163940516Swpaul * Enable transmit and receive. 164040516Swpaul */ 164140516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 164240516Swpaul 164340516Swpaul /* 164445633Swpaul * Set the initial TX and RX configuration. 164540516Swpaul */ 164645633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 164740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 164840516Swpaul 164940516Swpaul /* Set the individual bit to receive frames for this host only. */ 165040516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 165140516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 165240516Swpaul 165340516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 165440516Swpaul if (ifp->if_flags & IFF_PROMISC) { 165540516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 165640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165740516Swpaul } else { 165840516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 165940516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 166040516Swpaul } 166140516Swpaul 166240516Swpaul /* 166340516Swpaul * Set capture broadcast bit to capture broadcast frames. 166440516Swpaul */ 166540516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 166640516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 166740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 166840516Swpaul } else { 166940516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 167040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 167140516Swpaul } 167240516Swpaul 167340516Swpaul /* 167440516Swpaul * Program the multicast filter, if necessary. 167540516Swpaul */ 167640516Swpaul rl_setmulti(sc); 167740516Swpaul 167894883Sluigi#ifdef DEVICE_POLLING 167940516Swpaul /* 168094883Sluigi * Disable interrupts if we are polling. 168194883Sluigi */ 1682102052Ssobomax if (ifp->if_flags & IFF_POLLING) 168394883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 168494883Sluigi else /* otherwise ... */ 168594883Sluigi#endif /* DEVICE_POLLING */ 168694883Sluigi /* 168740516Swpaul * Enable interrupts. 168840516Swpaul */ 168940516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 169040516Swpaul 169152426Swpaul /* Set initial TX threshold */ 169252426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 169352426Swpaul 169440516Swpaul /* Start RX/TX process. */ 169540516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 169640516Swpaul 169740516Swpaul /* Enable receiver and transmitter. */ 169840516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 169940516Swpaul 170050703Swpaul mii_mediachg(mii); 170140516Swpaul 170240516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 170340516Swpaul 170440516Swpaul ifp->if_flags |= IFF_RUNNING; 170540516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 170640516Swpaul 170750703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 170867087Swpaul RL_UNLOCK(sc); 170950703Swpaul 171040516Swpaul return; 171140516Swpaul} 171240516Swpaul 171340516Swpaul/* 171440516Swpaul * Set media options. 171540516Swpaul */ 1716102335Salfredstatic int 1717102335Salfredrl_ifmedia_upd(ifp) 171840516Swpaul struct ifnet *ifp; 171940516Swpaul{ 172040516Swpaul struct rl_softc *sc; 172150703Swpaul struct mii_data *mii; 172240516Swpaul 172340516Swpaul sc = ifp->if_softc; 172450703Swpaul mii = device_get_softc(sc->rl_miibus); 172550703Swpaul mii_mediachg(mii); 172640516Swpaul 172740516Swpaul return(0); 172840516Swpaul} 172940516Swpaul 173040516Swpaul/* 173140516Swpaul * Report current media status. 173240516Swpaul */ 1733102335Salfredstatic void 1734102335Salfredrl_ifmedia_sts(ifp, ifmr) 173540516Swpaul struct ifnet *ifp; 173640516Swpaul struct ifmediareq *ifmr; 173740516Swpaul{ 173840516Swpaul struct rl_softc *sc; 173950703Swpaul struct mii_data *mii; 174040516Swpaul 174140516Swpaul sc = ifp->if_softc; 174250703Swpaul mii = device_get_softc(sc->rl_miibus); 174340516Swpaul 174450703Swpaul mii_pollstat(mii); 174550703Swpaul ifmr->ifm_active = mii->mii_media_active; 174650703Swpaul ifmr->ifm_status = mii->mii_media_status; 174740516Swpaul 174840516Swpaul return; 174940516Swpaul} 175040516Swpaul 1751102335Salfredstatic int 1752102335Salfredrl_ioctl(ifp, command, data) 175340516Swpaul struct ifnet *ifp; 175440516Swpaul u_long command; 175540516Swpaul caddr_t data; 175640516Swpaul{ 175740516Swpaul struct rl_softc *sc = ifp->if_softc; 175840516Swpaul struct ifreq *ifr = (struct ifreq *) data; 175950703Swpaul struct mii_data *mii; 176067087Swpaul int error = 0; 176140516Swpaul 176267087Swpaul RL_LOCK(sc); 176340516Swpaul 176440516Swpaul switch(command) { 176540516Swpaul case SIOCSIFFLAGS: 176640516Swpaul if (ifp->if_flags & IFF_UP) { 176740516Swpaul rl_init(sc); 176840516Swpaul } else { 176940516Swpaul if (ifp->if_flags & IFF_RUNNING) 177040516Swpaul rl_stop(sc); 177140516Swpaul } 177240516Swpaul error = 0; 177340516Swpaul break; 177440516Swpaul case SIOCADDMULTI: 177540516Swpaul case SIOCDELMULTI: 177640516Swpaul rl_setmulti(sc); 177740516Swpaul error = 0; 177840516Swpaul break; 177940516Swpaul case SIOCGIFMEDIA: 178040516Swpaul case SIOCSIFMEDIA: 178150703Swpaul mii = device_get_softc(sc->rl_miibus); 178250703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 178340516Swpaul break; 178440516Swpaul default: 1785106936Ssam error = ether_ioctl(ifp, command, data); 178640516Swpaul break; 178740516Swpaul } 178840516Swpaul 178967087Swpaul RL_UNLOCK(sc); 179040516Swpaul 179140516Swpaul return(error); 179240516Swpaul} 179340516Swpaul 1794102335Salfredstatic void 1795102335Salfredrl_watchdog(ifp) 179640516Swpaul struct ifnet *ifp; 179740516Swpaul{ 179840516Swpaul struct rl_softc *sc; 179940516Swpaul 180040516Swpaul sc = ifp->if_softc; 180167087Swpaul RL_LOCK(sc); 180240516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 180340516Swpaul ifp->if_oerrors++; 180450703Swpaul 180540516Swpaul rl_txeof(sc); 180640516Swpaul rl_rxeof(sc); 180740516Swpaul rl_init(sc); 180867087Swpaul RL_UNLOCK(sc); 180940516Swpaul 181040516Swpaul return; 181140516Swpaul} 181240516Swpaul 181340516Swpaul/* 181440516Swpaul * Stop the adapter and free any mbufs allocated to the 181540516Swpaul * RX and TX lists. 181640516Swpaul */ 1817102335Salfredstatic void 1818102335Salfredrl_stop(sc) 181940516Swpaul struct rl_softc *sc; 182040516Swpaul{ 182140516Swpaul register int i; 182240516Swpaul struct ifnet *ifp; 182340516Swpaul 182467087Swpaul RL_LOCK(sc); 182540516Swpaul ifp = &sc->arpcom.ac_if; 182640516Swpaul ifp->if_timer = 0; 182740516Swpaul 182850703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 182994883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 183094883Sluigi#ifdef DEVICE_POLLING 183194883Sluigi ether_poll_deregister(ifp); 183294883Sluigi#endif /* DEVICE_POLLING */ 183350703Swpaul 183440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 183540516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 183681713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 183740516Swpaul 183840516Swpaul /* 183940516Swpaul * Free the TX list buffers. 184040516Swpaul */ 184140516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 184245633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 184381713Swpaul bus_dmamap_unload(sc->rl_tag, 184481713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 184581713Swpaul bus_dmamap_destroy(sc->rl_tag, 184681713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 184745633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 184845633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 184945633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 185040516Swpaul } 185140516Swpaul } 185240516Swpaul 185367087Swpaul RL_UNLOCK(sc); 185440516Swpaul return; 185540516Swpaul} 185640516Swpaul 185740516Swpaul/* 185886822Siwasaki * Device suspend routine. Stop the interface and save some PCI 185986822Siwasaki * settings in case the BIOS doesn't restore them properly on 186086822Siwasaki * resume. 186186822Siwasaki */ 1862102335Salfredstatic int 1863102335Salfredrl_suspend(dev) 186486822Siwasaki device_t dev; 186586822Siwasaki{ 186686822Siwasaki register int i; 186786822Siwasaki struct rl_softc *sc; 186886822Siwasaki 186986822Siwasaki sc = device_get_softc(dev); 187086822Siwasaki 187186822Siwasaki rl_stop(sc); 187286822Siwasaki 187386822Siwasaki for (i = 0; i < 5; i++) 187486822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 187586822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 187686822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 187786822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 187886822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 187986822Siwasaki 188086822Siwasaki sc->suspended = 1; 188186822Siwasaki 188286822Siwasaki return (0); 188386822Siwasaki} 188486822Siwasaki 188586822Siwasaki/* 188686822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 188786822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 188886822Siwasaki * appropriate. 188986822Siwasaki */ 1890102335Salfredstatic int 1891102335Salfredrl_resume(dev) 189286822Siwasaki device_t dev; 189386822Siwasaki{ 189486822Siwasaki register int i; 189586822Siwasaki struct rl_softc *sc; 189686822Siwasaki struct ifnet *ifp; 189786822Siwasaki 189886822Siwasaki sc = device_get_softc(dev); 189986822Siwasaki ifp = &sc->arpcom.ac_if; 190086822Siwasaki 190186822Siwasaki /* better way to do this? */ 190286822Siwasaki for (i = 0; i < 5; i++) 190386822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 190486822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 190586822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 190686822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 190786822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 190886822Siwasaki 190986822Siwasaki /* reenable busmastering */ 191086822Siwasaki pci_enable_busmaster(dev); 191186822Siwasaki pci_enable_io(dev, RL_RES); 191286822Siwasaki 191386822Siwasaki /* reinitialize interface if necessary */ 191486822Siwasaki if (ifp->if_flags & IFF_UP) 191586822Siwasaki rl_init(sc); 191686822Siwasaki 191786822Siwasaki sc->suspended = 0; 191886822Siwasaki 191986822Siwasaki return (0); 192086822Siwasaki} 192186822Siwasaki 192286822Siwasaki/* 192340516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 192440516Swpaul * get confused by errant DMAs when rebooting. 192540516Swpaul */ 1926102335Salfredstatic void 1927102335Salfredrl_shutdown(dev) 192850703Swpaul device_t dev; 192940516Swpaul{ 193050703Swpaul struct rl_softc *sc; 193140516Swpaul 193250703Swpaul sc = device_get_softc(dev); 193350703Swpaul 193440516Swpaul rl_stop(sc); 193540516Swpaul 193640516Swpaul return; 193740516Swpaul} 1938