rc.c revision 9822
18471Sache/* 28471Sache * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 38471Sache * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 48471Sache * All rights reserved. 58471Sache * 68471Sache * Redistribution and use in source and binary forms, with or without 78471Sache * modification, are permitted provided that the following conditions 88471Sache * are met: 98471Sache * 1. Redistributions of source code must retain the above copyright 108471Sache * notice, this list of conditions and the following disclaimer. 118471Sache * 2. Redistributions in binary form must reproduce the above copyright 128471Sache * notice, this list of conditions and the following disclaimer in the 138471Sache * documentation and/or other materials provided with the distribution. 148471Sache * 158471Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 168471Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 178471Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 188471Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 198471Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 208471Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 218471Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 228471Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 238471Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 248471Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 258471Sache * SUCH DAMAGE. 268471Sache */ 278471Sache 288471Sache/* 298471Sache * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 308471Sache * 318471Sache */ 328471Sache 338471Sache#include "rc.h" 348471Sache#if NRC > 0 358471Sache 369232Sache/*#define RCDEBUG*/ 378471Sache 388471Sache#include <sys/param.h> 398471Sache#include <sys/systm.h> 408471Sache#include <sys/ioctl.h> 418471Sache#include <sys/tty.h> 428471Sache#include <sys/proc.h> 438471Sache#include <sys/user.h> 448471Sache#include <sys/conf.h> 458471Sache#include <sys/dkstat.h> 468471Sache#include <sys/file.h> 478471Sache#include <sys/uio.h> 488471Sache#include <sys/kernel.h> 498471Sache#include <sys/syslog.h> 508471Sache#include <sys/devconf.h> 518471Sache 528471Sache#include <machine/clock.h> 538471Sache 548471Sache#include <i386/isa/isa.h> 558471Sache#include <i386/isa/isa_device.h> 568471Sache#include <i386/isa/sioreg.h> 578471Sache 588471Sache#include <i386/isa/ic/cd180.h> 598471Sache#include <i386/isa/rcreg.h> 608471Sache 618471Sache/* Prototypes */ 628471Sacheint rcprobe __P((struct isa_device *)); 638471Sacheint rcattach __P((struct isa_device *)); 648471Sache 658471Sacheint rcopen __P((dev_t, int, int, struct proc *)); 668471Sacheint rcclose __P((dev_t, int, int, struct proc *)); 678471Sacheint rcread __P((dev_t, struct uio *, int)); 688471Sacheint rcwrite __P((dev_t, struct uio *, int)); 698471Sachevoid rcintr __P((int)); 708471Sachevoid rcpoll __P((void)); 718471Sachevoid rcstop __P((struct tty *, int)); 728471Sacheint rcioctl __P((dev_t, int, caddr_t, int, struct proc *)); 738471Sache 748471Sache#define rcin(port) RC_IN (nec, port) 758471Sache#define rcout(port,v) RC_OUT (nec, port, v) 768471Sache 779232Sache#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 789232Sache#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 798471Sache 809232Sache#define RC_IBUFSIZE 256 819232Sache#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 829232Sache#define RC_OBUFSIZE 512 838471Sache#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 848471Sache#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 858471Sache#define LOTS_OF_EVENTS 64 868471Sache 878471Sache#define RC_FAKEID 0x10 888471Sache 899232Sache#define RC_PROBED 1 909232Sache#define RC_ATTACHED 2 919232Sache 928471Sache#define GET_UNIT(dev) (minor(dev) & 0x3F) 938471Sache#define CALLOUT(dev) (minor(dev) & 0x80) 948471Sache 958471Sache/* For isa routines */ 968471Sachestruct isa_driver rcdriver = { 978471Sache rcprobe, rcattach, "rc" 988471Sache}; 998471Sache 1008471Sache/* Per-board structure */ 1018471Sachestatic struct rc_softc { 1029232Sache u_int rcb_probed; /* 1 - probed, 2 - attached */ 1038471Sache u_int rcb_addr; /* Base I/O addr */ 1048471Sache u_int rcb_unit; /* unit # */ 1058471Sache u_char rcb_dtr; /* DTR status */ 1068471Sache struct rc_chans *rcb_baserc; /* base rc ptr */ 1078471Sache} rc_softc[NRC]; 1088471Sache 1098471Sache/* Per-channel structure */ 1108471Sachestatic struct rc_chans { 1118471Sache struct rc_softc *rc_rcb; /* back ptr */ 1128471Sache u_short rc_flags; /* Misc. flags */ 1138471Sache int rc_chan; /* Channel # */ 1148471Sache u_char rc_ier; /* intr. enable reg */ 1158471Sache u_char rc_msvr; /* modem sig. status */ 1168471Sache u_char rc_cor2; /* options reg */ 1178471Sache u_char rc_pendcmd; /* special cmd pending */ 1188471Sache u_int rc_dtrwait; /* dtr timeout */ 1198471Sache u_int rc_dcdwaits; /* how many waits DCD in open */ 1208471Sache u_char rc_hotchar; /* end packed optimize */ 1218471Sache struct tty *rc_tp; /* tty struct */ 1228471Sache u_char *rc_iptr; /* Chars input buffer */ 1238471Sache u_char *rc_hiwat; /* hi-water mark */ 1248471Sache u_char *rc_bufend; /* end of buffer */ 1258471Sache u_char *rc_optr; /* ptr in output buf */ 1268471Sache u_char *rc_obufend; /* end of output buf */ 1278471Sache u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 1288471Sache u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 1298471Sache} rc_chans[NRC * CD180_NCHAN]; 1308471Sache 1318471Sachestatic int rc_scheduled_event = 0; 1328471Sache 1338471Sache/* for pstat -t */ 1348471Sachestruct tty rc_tty[NRC * CD180_NCHAN]; 1358471Sacheint nrc_tty = NRC * CD180_NCHAN; 1368471Sache 1378471Sache/* Flags */ 1389232Sache#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 1399232Sache#define RC_ACTOUT 0x0002 /* Dial-out port active */ 1409232Sache#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 1419232Sache#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 1429232Sache#define RC_DORXFER 0x0010 /* RXFER event planned */ 1439232Sache#define RC_DOXXFER 0x0020 /* XXFER event planned */ 1449232Sache#define RC_MODCHG 0x0040 /* Modem status changed */ 1459232Sache#define RC_OSUSP 0x0080 /* Output suspended */ 1469232Sache#define RC_OSBUSY 0x0100 /* start() routine in progress */ 1479232Sache#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 1489232Sache#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 1499232Sache#define RC_SEND_RDY 0x0800 /* ready to send */ 1508471Sache 1518471Sachestatic struct speedtab rc_speedtab[] = { 1528471Sache 0, 0, 1538471Sache 50, RC_BRD(50), 1548471Sache 75, RC_BRD(75), 1558471Sache 110, RC_BRD(110), 1568471Sache 134, RC_BRD(134), 1578471Sache 150, RC_BRD(150), 1588471Sache 200, RC_BRD(200), 1598471Sache 300, RC_BRD(300), 1608471Sache 600, RC_BRD(600), 1618471Sache 1200, RC_BRD(1200), 1628471Sache 1800, RC_BRD(1800), 1638471Sache 2400, RC_BRD(2400), 1648471Sache 4800, RC_BRD(4800), 1658471Sache 9600, RC_BRD(9600), 1668471Sache 19200, RC_BRD(19200), 1678471Sache 38400, RC_BRD(38400), 1688471Sache 57600, RC_BRD(57600), 1698471Sache /* real max value is 76800 with 9.8304 MHz clock */ 1708471Sache -1, -1 1718471Sache}; 1728471Sache 1738471Sache/* Table for translation of RCSR status bits to internal form */ 1748471Sachestatic int rc_rcsrt[16] = { 1758471Sache 0, TTY_OE, TTY_FE, 1768471Sache TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 1778471Sache TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 1788471Sache TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 1798471Sache TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 1808471Sache TTY_BI|TTY_PE|TTY_FE|TTY_OE 1818471Sache}; 1828471Sache 1838471Sache/* Static prototypes */ 1849232Sachestatic void rc_hwreset __P((int, int, unsigned int)); 1858471Sachestatic int rc_test __P((int, int)); 1868471Sachestatic void rc_discard_output __P((struct rc_chans *)); 1878471Sachestatic void rc_hardclose __P((struct rc_chans *)); 1888471Sachestatic int rc_modctl __P((struct rc_chans *, int, int)); 1898471Sachestatic void rc_start __P((struct tty *)); 1908471Sachestatic int rc_param __P((struct tty *, struct termios *)); 1918471Sachestatic void rc_registerdev __P((struct isa_device *id)); 1929232Sachestatic void rc_reinit __P((struct rc_softc *)); 1939232Sache#ifdef RCDEBUG 1949232Sachestatic void printrcflags(); 1959232Sache#endif 1968471Sachestatic timeout_t rc_dtrwakeup; 1978471Sachestatic timeout_t rc_wakeup; 1988471Sachestatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 1999232Sachestatic void rc_wait0 __P((int nec, int unit, int chan, int line)); 2008471Sache 2018471Sache/**********************************************/ 2028471Sache 2038471Sache/* Quick device probing */ 2048471Sacheint rcprobe(dvp) 2058471Sache struct isa_device *dvp; 2068471Sache{ 2078471Sache int irq = ffs(dvp->id_irq) - 1; 2088471Sache register int nec = dvp->id_iobase; 2098471Sache 2108471Sache if (dvp->id_unit > NRC) 2118471Sache return 0; 2128471Sache if (!RC_VALIDADDR(nec)) { 2138471Sache printf("rc%d: illegal base address %x\n", nec); 2148471Sache return 0; 2158471Sache } 2168471Sache if (!RC_VALIDIRQ(irq)) { 2178471Sache printf("rc%d: illegal IRQ value %d\n", irq); 2188471Sache return 0; 2198471Sache } 2208471Sache rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 2218471Sache rcout(CD180_PPRH, 0x11); 2228471Sache if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 2238471Sache return 0; 2248471Sache /* Now, test the board more thoroughly, with diagnostic */ 2258471Sache if (rc_test(nec, dvp->id_unit)) 2268471Sache return 0; 2279232Sache rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 2289232Sache 2299232Sache return 0xF; 2308471Sache} 2318471Sache 2328471Sachestatic struct kern_devconf kdc_rc[NRC] = { { 2338471Sache 0, 0, 0, /* filled in by dev_attach */ 2348471Sache "rc", 0, { MDDT_ISA, 0, "tty" }, 2358471Sache isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 2368471Sache &kdc_isa0, /* parent */ 2378471Sache 0, /* parentdata */ 2388471Sache DC_UNCONFIGURED, /* state */ 2398471Sache "RISCom/8 multiport card", 2408471Sache DC_CLS_SERIAL /* class */ 2418471Sache} }; 2428471Sache 2438471Sachestatic void 2448471Sacherc_registerdev(id) 2458471Sache struct isa_device *id; 2468471Sache{ 2478471Sache int unit; 2488471Sache 2498471Sache unit = id->id_unit; 2508471Sache if (unit != 0) 2518471Sache kdc_rc[unit] = kdc_rc[0]; 2528471Sache kdc_rc[unit].kdc_unit = unit; 2538471Sache kdc_rc[unit].kdc_isa = id; 2548471Sache kdc_rc[unit].kdc_state = DC_UNKNOWN; 2558471Sache dev_attach(&kdc_rc[unit]); 2568471Sache} 2578471Sache 2588471Sacheint rcattach(dvp) 2598471Sache struct isa_device *dvp; 2608471Sache{ 2618471Sache register int i, chan, nec = dvp->id_iobase; 2628471Sache struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 2638471Sache struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 2648471Sache static int rc_wakeup_started = 0; 2659232Sache struct tty *tp; 2668471Sache 2678471Sache /* Thorooughly test the device */ 2689232Sache if (rcb->rcb_probed != RC_PROBED) 2698471Sache return 0; 2708471Sache rcb->rcb_addr = nec; 2718471Sache rcb->rcb_dtr = 0; 2728471Sache rcb->rcb_baserc = rc; 2738471Sache /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 2748471Sache printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 2758471Sache CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 2768471Sache 2778471Sache rc_registerdev(dvp); 2788471Sache 2798471Sache for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 2808471Sache rc->rc_rcb = rcb; 2818471Sache rc->rc_chan = chan; 2828471Sache rc->rc_iptr = rc->rc_ibuf; 2838471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 2848471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 2858471Sache rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 2868471Sache rc->rc_cor2 = rc->rc_pendcmd = 0; 2878471Sache rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 2888471Sache rc->rc_dtrwait = 3 * hz; 2898471Sache rc->rc_dcdwaits= 0; 2908471Sache rc->rc_hotchar = 0; 2919232Sache tp = rc->rc_tp = &rc_tty[chan]; 2929232Sache ttychars(tp); 2939232Sache tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 2949232Sache tp->t_cflag = TTYDEF_CFLAG; 2959232Sache tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 2968471Sache } 2979232Sache rcb->rcb_probed = RC_ATTACHED; 2988471Sache if (!rc_wakeup_started) { 2998471Sache rc_wakeup((void *)NULL); 3008471Sache rc_wakeup_started = 0; 3018471Sache } 3028471Sache return 1; 3038471Sache} 3048471Sache 3058471Sache/* RC interrupt handling */ 3068471Sachevoid rcintr(unit) 3078471Sache int unit; 3088471Sache{ 3098471Sache register struct rc_softc *rcb = &rc_softc[unit]; 3108471Sache register struct rc_chans *rc; 3119232Sache register int nec, resid; 3129232Sache register u_char val, iack, bsr, ucnt, *optr; 3139232Sache int good_data, t_state; 3148471Sache 3159232Sache if (rcb->rcb_probed != RC_ATTACHED) { 3169232Sache printf("rc%d: bogus interrupt\n", unit); 3179232Sache return; 3189232Sache } 3198471Sache nec = rcb->rcb_addr; 3208471Sache 3218471Sache bsr = ~(rcin(RC_BSR)); 3228471Sache 3239232Sache if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 3249232Sache printf("rc%d: extra interrupt\n", unit); 3259232Sache rcout(CD180_EOIR, 0); 3269232Sache return; 3279232Sache } 3289232Sache 3299232Sache while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 3309232Sache#ifdef RCDEBUG_DETAILED 3319232Sache printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 3329232Sache (bsr & RC_BSR_TOUT)?"TOUT ":"", 3339232Sache (bsr & RC_BSR_RXINT)?"RXINT ":"", 3349232Sache (bsr & RC_BSR_TXINT)?"TXINT ":"", 3359232Sache (bsr & RC_BSR_MOINT)?"MOINT":""); 3368471Sache#endif 3379232Sache if (bsr & RC_BSR_TOUT) { 3389232Sache printf("rc%d: hardware failure, reset board\n", unit); 3399232Sache rcout(RC_CTOUT, 0); 3409232Sache rc_reinit(rcb); 3419232Sache return; 3428471Sache } 3439232Sache if (bsr & RC_BSR_RXINT) { 3449232Sache iack = rcin(RC_PILR_RX); 3459232Sache good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 3469232Sache if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 3479232Sache printf("rc%d: fake rxint: %02x\n", unit, iack); 3489232Sache goto more_intrs; 3499232Sache } 3509232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 3519232Sache t_state = rc->rc_tp->t_state; 3529232Sache /* Do RTS flow control stuff */ 3539232Sache if ( (rc->rc_flags & RC_RTSFLOW) 3549232Sache || !(t_state & TS_ISOPEN) 3559232Sache ) { 3569232Sache if ( ( !(t_state & TS_ISOPEN) 3579232Sache || (t_state & TS_TBLOCK) 3589232Sache ) 3599232Sache && (rc->rc_msvr & MSVR_RTS) 3609232Sache ) 3619232Sache rcout(CD180_MSVR, 3629232Sache rc->rc_msvr &= ~MSVR_RTS); 3639232Sache else if (!(rc->rc_msvr & MSVR_RTS)) 3649232Sache rcout(CD180_MSVR, 3659232Sache rc->rc_msvr |= MSVR_RTS); 3669232Sache } 3679232Sache ucnt = rcin(CD180_RDCR) & 0xF; 3689232Sache resid = 0; 3698471Sache 3709232Sache if (t_state & TS_ISOPEN) { 3719232Sache /* check for input buffer overflow */ 3729232Sache if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 3739232Sache resid = ucnt; 3749232Sache ucnt = rc->rc_bufend - rc->rc_iptr; 3759232Sache resid -= ucnt; 3769232Sache if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 3779232Sache rc->rc_flags |= RC_WAS_BUFOVFL; 3789232Sache rc_scheduled_event++; 3799232Sache } 3808471Sache } 3819232Sache optr = rc->rc_iptr; 3829232Sache /* check foor good data */ 3839232Sache if (good_data) { 3849232Sache while (ucnt-- > 0) { 3859232Sache val = rcin(CD180_RDR); 3869232Sache optr[0] = val; 3879232Sache optr[INPUT_FLAGS_SHIFT] = 0; 3889232Sache optr++; 3898471Sache rc_scheduled_event++; 3909232Sache if (val != 0 && val == rc->rc_hotchar) 3918471Sache setsofttty(); 3928471Sache } 3939232Sache } else { 3949232Sache /* Store also status data */ 3959232Sache while (ucnt-- > 0) { 3969232Sache iack = rcin(CD180_RCSR); 3979232Sache if (iack & RCSR_Timeout) 3989232Sache break; 3999232Sache if ( (iack & RCSR_OE) 4009232Sache && !(rc->rc_flags & RC_WAS_SILOVFL)) { 4019232Sache rc->rc_flags |= RC_WAS_SILOVFL; 4029232Sache rc_scheduled_event++; 4039232Sache } 4049232Sache val = rcin(CD180_RDR); 4059232Sache /* 4069232Sache Don't store PE if IGNPAR and BREAK if IGNBRK, 4079232Sache this hack allows "raw" tty optimization 4089232Sache works even if IGN* is set. 4099232Sache */ 4109232Sache if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 4119232Sache || (!(iack & (RCSR_PE|RCSR_FE)) 4129232Sache || !(rc->rc_tp->t_iflag & IGNPAR)) 4139232Sache && (!(iack & RCSR_Break) 4149232Sache || !(rc->rc_tp->t_iflag & IGNBRK))) { 4159232Sache if ( (iack & (RCSR_PE|RCSR_FE)) 4169232Sache && (t_state & TS_CAN_BYPASS_L_RINT) 4179232Sache && ((iack & RCSR_FE) 4189232Sache || (iack & RCSR_PE) 4199232Sache && (rc->rc_tp->t_iflag & INPCK))) 4209232Sache val = 0; 4219232Sache else if (val != 0 && val == rc->rc_hotchar) 4229232Sache setsofttty(); 4239232Sache optr[0] = val; 4249232Sache optr[INPUT_FLAGS_SHIFT] = iack; 4259232Sache optr++; 4269232Sache rc_scheduled_event++; 4279232Sache } 4289232Sache } 4298471Sache } 4309232Sache rc->rc_iptr = optr; 4319232Sache rc->rc_flags |= RC_DORXFER; 4329232Sache } else 4339232Sache resid = ucnt; 4349232Sache /* Clear FIFO if necessary */ 4359232Sache while (resid-- > 0) { 4369232Sache if (!good_data) 4379232Sache iack = rcin(CD180_RCSR); 4389232Sache else 4399232Sache iack = 0; 4409232Sache if (iack & RCSR_Timeout) 4419232Sache break; 4429232Sache (void) rcin(CD180_RDR); 4438471Sache } 4449232Sache goto more_intrs; 4458471Sache } 4469232Sache if (bsr & RC_BSR_MOINT) { 4479232Sache iack = rcin(RC_PILR_MODEM); 4489232Sache if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 4499232Sache printf("rc%d: fake moint: %02x\n", unit, iack); 4509232Sache goto more_intrs; 4519232Sache } 4529232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4539232Sache iack = rcin(CD180_MCR); 4549232Sache rc->rc_msvr = rcin(CD180_MSVR); 4559232Sache rcout(CD180_MCR, 0); 4568471Sache#ifdef RCDEBUG 4579232Sache printrcflags(rc, "moint"); 4588471Sache#endif 4599232Sache if (rc->rc_flags & RC_CTSFLOW) { 4609232Sache if (rc->rc_msvr & MSVR_CTS) 4619232Sache rc->rc_flags |= RC_SEND_RDY; 4629232Sache else 4639232Sache rc->rc_flags &= ~RC_SEND_RDY; 4649232Sache } else 4658471Sache rc->rc_flags |= RC_SEND_RDY; 4669232Sache if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 4679232Sache rc_scheduled_event += LOTS_OF_EVENTS; 4689232Sache rc->rc_flags |= RC_MODCHG; 4699232Sache setsofttty(); 4709232Sache } 4719232Sache goto more_intrs; 4728471Sache } 4739232Sache if (bsr & RC_BSR_TXINT) { 4749232Sache iack = rcin(RC_PILR_TX); 4759232Sache if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 4769232Sache printf("rc%d: fake txint: %02x\n", unit, iack); 4779232Sache goto more_intrs; 4789232Sache } 4799232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4809232Sache if ( (rc->rc_flags & RC_OSUSP) 4819232Sache || !(rc->rc_flags & RC_SEND_RDY) 4829232Sache ) 4839232Sache goto more_intrs; 4849232Sache /* Handle breaks and other stuff */ 4859232Sache if (rc->rc_pendcmd) { 4869232Sache rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 4879232Sache rcout(CD180_TDR, CD180_C_ESC); 4889232Sache rcout(CD180_TDR, rc->rc_pendcmd); 4899232Sache rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 4909232Sache rc->rc_pendcmd = 0; 4919232Sache goto more_intrs; 4929232Sache } 4939232Sache optr = rc->rc_optr; 4949232Sache resid = rc->rc_obufend - optr; 4959232Sache if (resid > CD180_NFIFO) 4969232Sache resid = CD180_NFIFO; 4979232Sache while (resid-- > 0) 4989232Sache rcout(CD180_TDR, *optr++); 4999232Sache rc->rc_optr = optr; 5008471Sache 5019232Sache /* output completed? */ 5029232Sache if (optr >= rc->rc_obufend) { 5039232Sache rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 5048471Sache#ifdef RCDEBUG 5059232Sache printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 5068471Sache#endif 5079232Sache if (!(rc->rc_flags & RC_DOXXFER)) { 5089232Sache rc_scheduled_event += LOTS_OF_EVENTS; 5099232Sache rc->rc_flags |= RC_DOXXFER; 5109232Sache setsofttty(); 5119232Sache } 5129232Sache } 5138471Sache } 5149232Sache more_intrs: 5159232Sache rcout(CD180_EOIR, 0); /* end of interrupt */ 5169232Sache rcout(RC_CTOUT, 0); 5179232Sache bsr = ~(rcin(RC_BSR)); 5188471Sache } 5198471Sache} 5208471Sache 5218471Sache/* Feed characters to output buffer */ 5228471Sachestatic void rc_start(tp) 5238471Sacheregister struct tty *tp; 5248471Sache{ 5258471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 5268471Sache register int nec = rc->rc_rcb->rcb_addr, s; 5278471Sache 5288471Sache if (rc->rc_flags & RC_OSBUSY) 5298471Sache return; 5308471Sache s = spltty(); 5318471Sache rc->rc_flags |= RC_OSBUSY; 5328471Sache disable_intr(); 5338471Sache if (tp->t_state & TS_TTSTOP) 5348471Sache rc->rc_flags |= RC_OSUSP; 5358471Sache else 5368471Sache rc->rc_flags &= ~RC_OSUSP; 5378471Sache /* Do RTS flow control stuff */ 5389232Sache if ( (rc->rc_flags & RC_RTSFLOW) 5399232Sache && (tp->t_state & TS_TBLOCK) 5409232Sache && (rc->rc_msvr & MSVR_RTS) 5419232Sache ) { 5429232Sache rcout(CD180_CAR, rc->rc_chan); 5439232Sache rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 5449232Sache } else if (!(rc->rc_msvr & MSVR_RTS)) { 5459232Sache rcout(CD180_CAR, rc->rc_chan); 5469232Sache rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 5478471Sache } 5488471Sache enable_intr(); 5498471Sache if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 5508471Sache goto out; 5518471Sache#ifdef RCDEBUG 5528471Sache printrcflags(rc, "rcstart"); 5538471Sache#endif 5549626Sbde ttwwakeup(tp); 5558471Sache#ifdef RCDEBUG 5569232Sache printf("rcstart: outq = %d obuf = %d\n", 5578471Sache tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 5588471Sache#endif 5599232Sache if (tp->t_state & TS_BUSY) 5608471Sache goto out; /* output still in progress ... */ 5618471Sache 5628471Sache if (tp->t_outq.c_cc > 0) { 5638471Sache u_int ocnt; 5648471Sache 5658471Sache tp->t_state |= TS_BUSY; 5668471Sache ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 5678471Sache disable_intr(); 5688471Sache rc->rc_optr = rc->rc_obuf; 5699232Sache rc->rc_obufend = rc->rc_optr + ocnt; 5708471Sache enable_intr(); 5719232Sache if (!(rc->rc_ier & IER_TxRdy)) { 5728471Sache#ifdef RCDEBUG 5739232Sache printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 5748471Sache#endif 5758471Sache rcout(CD180_CAR, rc->rc_chan); 5769232Sache rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 5778471Sache } 5788471Sache } 5798471Sacheout: 5808471Sache rc->rc_flags &= ~RC_OSBUSY; 5818471Sache (void) splx(s); 5828471Sache} 5838471Sache 5848471Sache/* Handle delayed events. */ 5858471Sachevoid rcpoll() 5868471Sache{ 5878471Sache register struct rc_chans *rc; 5888471Sache register struct rc_softc *rcb; 5898471Sache register u_char *tptr, *eptr; 5908471Sache register int s; 5918471Sache register struct tty *tp; 5928471Sache register int chan, icnt, c, nec, unit; 5938471Sache 5948471Sache if (rc_scheduled_event == 0) 5958471Sache return; 5968471Sacherepeat: 5978471Sache for (unit = 0; unit < NRC; unit++) { 5988471Sache rcb = &rc_softc[unit]; 5998471Sache rc = rcb->rcb_baserc; 6008471Sache nec = rc->rc_rcb->rcb_addr; 6018471Sache for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 6028471Sache tp = rc->rc_tp; 6038471Sache#ifdef RCDEBUG 6048471Sache if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 6058471Sache RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 6068471Sache printrcflags(rc, "rcevent"); 6078471Sache#endif 6088471Sache if (rc->rc_flags & RC_WAS_BUFOVFL) { 6099232Sache disable_intr(); 6108471Sache rc->rc_flags &= ~RC_WAS_BUFOVFL; 6118471Sache rc_scheduled_event--; 6129232Sache enable_intr(); 6138471Sache printf("rc%d/%d: interrupt-level buffer overflow\n", 6148471Sache unit, chan); 6158471Sache } 6168471Sache if (rc->rc_flags & RC_WAS_SILOVFL) { 6179232Sache disable_intr(); 6188471Sache rc->rc_flags &= ~RC_WAS_SILOVFL; 6198471Sache rc_scheduled_event--; 6209232Sache enable_intr(); 6218471Sache printf("rc%d/%d: silo overflow\n", 6228471Sache unit, chan); 6238471Sache } 6248471Sache if (rc->rc_flags & RC_MODCHG) { 6259232Sache disable_intr(); 6268471Sache rc->rc_flags &= ~RC_MODCHG; 6278471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 6289232Sache enable_intr(); 6299232Sache (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 6308471Sache } 6318471Sache if (rc->rc_flags & RC_DORXFER) { 6329232Sache disable_intr(); 6338471Sache rc->rc_flags &= ~RC_DORXFER; 6348471Sache eptr = rc->rc_iptr; 6358471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 6368471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6378471Sache else 6388471Sache tptr = rc->rc_ibuf; 6398471Sache icnt = eptr - tptr; 6408471Sache if (icnt > 0) { 6418471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 6428471Sache rc->rc_iptr = rc->rc_ibuf; 6438471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 6448471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 6458471Sache } else { 6468471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6478471Sache rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 6488471Sache rc->rc_hiwat = 6498471Sache &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 6508471Sache } 6519232Sache if ( (rc->rc_flags & RC_RTSFLOW) 6529232Sache && (tp->t_state & TS_ISOPEN) 6539232Sache && !(tp->t_state & TS_TBLOCK) 6548471Sache && !(rc->rc_msvr & MSVR_RTS) 6559232Sache ) { 6568471Sache rcout(CD180_CAR, chan); 6578471Sache rcout(CD180_MSVR, 6588471Sache rc->rc_msvr |= MSVR_RTS); 6598471Sache } 6608471Sache rc_scheduled_event -= icnt; 6618471Sache } 6628471Sache enable_intr(); 6638471Sache 6649232Sache if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 6658471Sache goto done1; 6668471Sache 6678471Sache if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 6688471Sache && !(tp->t_state & TS_LOCAL)) { 6699822Sbde if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 6709822Sbde && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 6719822Sbde && !(tp->t_state & TS_TBLOCK)) 6729822Sbde ttyblock(tp); 6738471Sache tk_nin += icnt; 6748471Sache tk_rawcc += icnt; 6758471Sache tp->t_rawcc += icnt; 6768471Sache if (b_to_q(tptr, icnt, &tp->t_rawq)) 6778471Sache printf("rc%d/%d: tty-level buffer overflow\n", 6788471Sache unit, chan); 6798471Sache ttwakeup(tp); 6808471Sache if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 6818471Sache || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 6828471Sache tp->t_state &= ~TS_TTSTOP; 6838471Sache tp->t_lflag &= ~FLUSHO; 6849754Sbde rc_start(tp); 6858471Sache } 6868471Sache } else { 6878471Sache for (; tptr < eptr; tptr++) 6888471Sache (*linesw[tp->t_line].l_rint) 6898471Sache (tptr[0] | 6908471Sache rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 6918471Sache } 6928471Sachedone1: 6938471Sache } 6948471Sache if (rc->rc_flags & RC_DOXXFER) { 6959232Sache disable_intr(); 6969232Sache rc_scheduled_event -= LOTS_OF_EVENTS; 6979232Sache rc->rc_flags &= ~RC_DOXXFER; 6989232Sache rc->rc_tp->t_state &= ~TS_BUSY; 6999232Sache enable_intr(); 7008471Sache (*linesw[tp->t_line].l_start)(tp); 7018471Sache } 7028471Sache } 7038471Sache if (rc_scheduled_event == 0) 7048471Sache break; 7058471Sache } 7068471Sache if (rc_scheduled_event >= LOTS_OF_EVENTS) 7078471Sache goto repeat; 7088471Sache} 7098471Sache 7108471Sachevoid rcstop(tp, rw) 7118471Sache register struct tty *tp; 7128471Sache int rw; 7138471Sache{ 7148471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 7158471Sache u_char *tptr, *eptr; 7168471Sache 7178471Sache#ifdef RCDEBUG 7189232Sache printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 7198471Sache (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 7208471Sache#endif 7218471Sache if (rw & FWRITE) 7228471Sache rc_discard_output(rc); 7238471Sache disable_intr(); 7248471Sache if (rw & FREAD) { 7259232Sache rc->rc_flags &= ~RC_DORXFER; 7268471Sache eptr = rc->rc_iptr; 7278471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 7288471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7298471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7308471Sache } else { 7318471Sache tptr = rc->rc_ibuf; 7328471Sache rc->rc_iptr = rc->rc_ibuf; 7338471Sache } 7348471Sache rc_scheduled_event -= eptr - tptr; 7358471Sache } 7368471Sache if (tp->t_state & TS_TTSTOP) 7378471Sache rc->rc_flags |= RC_OSUSP; 7388471Sache else 7398471Sache rc->rc_flags &= ~RC_OSUSP; 7408471Sache enable_intr(); 7418471Sache} 7428471Sache 7438471Sacheint rcopen(dev, flag, mode, p) 7448471Sache dev_t dev; 7458471Sache int flag, mode; 7468471Sache struct proc *p; 7478471Sache{ 7488471Sache register struct rc_chans *rc; 7498471Sache register struct tty *tp; 7508471Sache int unit, nec, s, error = 0; 7518471Sache 7528471Sache unit = GET_UNIT(dev); 7538471Sache if (unit >= NRC * CD180_NCHAN) 7548471Sache return ENXIO; 7559232Sache if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 7569232Sache return ENXIO; 7578471Sache rc = &rc_chans[unit]; 7589232Sache tp = rc->rc_tp; 7598471Sache nec = rc->rc_rcb->rcb_addr; 7608471Sache#ifdef RCDEBUG 7619232Sache printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 7628471Sache#endif 7638471Sache s = spltty(); 7648471Sache 7658471Sacheagain: 7668471Sache while (rc->rc_flags & RC_DTR_OFF) { 7679232Sache error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 7688471Sache if (error != 0) 7698471Sache goto out; 7708471Sache } 7718471Sache if (tp->t_state & TS_ISOPEN) { 7728471Sache if (CALLOUT(dev)) { 7738471Sache if (!(rc->rc_flags & RC_ACTOUT)) { 7748471Sache error = EBUSY; 7758471Sache goto out; 7768471Sache } 7778471Sache } else { 7788471Sache if (rc->rc_flags & RC_ACTOUT) { 7798471Sache if (flag & O_NONBLOCK) { 7808471Sache error = EBUSY; 7818471Sache goto out; 7828471Sache } 7838471Sache if (error = tsleep(&rc->rc_rcb, 7848471Sache TTIPRI|PCATCH, "rcbi", 0)) 7858471Sache goto out; 7868471Sache goto again; 7878471Sache } 7888471Sache } 7898471Sache if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 7908471Sache error = EBUSY; 7918471Sache goto out; 7928471Sache } 7938471Sache } else { 7948471Sache tp->t_oproc = rc_start; 7958471Sache tp->t_param = rc_param; 7968471Sache tp->t_dev = dev; 7978471Sache 7988471Sache if (CALLOUT(dev)) 7998471Sache tp->t_cflag |= CLOCAL; 8008471Sache else 8018471Sache tp->t_cflag &= ~CLOCAL; 8028471Sache 8038471Sache error = rc_param(tp, &tp->t_termios); 8048471Sache if (error) 8058471Sache goto out; 8069232Sache (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 8078471Sache 8088471Sache ttsetwater(tp); 8098471Sache 8108471Sache if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 8118471Sache (*linesw[tp->t_line].l_modem)(tp, 1); 8128471Sache } 8138471Sache if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 8148471Sache && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 8158471Sache rc->rc_dcdwaits++; 8169639Sbde error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 8178471Sache rc->rc_dcdwaits--; 8188471Sache if (error != 0) 8198471Sache goto out; 8208471Sache goto again; 8218471Sache } 8228471Sache error = (*linesw[tp->t_line].l_open)(dev, tp); 8238471Sache if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 8248471Sache rc->rc_flags |= RC_ACTOUT; 8258471Sacheout: 8268471Sache (void) splx(s); 8278471Sache 8288471Sache if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 8298471Sache rc_hardclose(rc); 8308471Sache 8318471Sache return error; 8328471Sache} 8338471Sache 8348471Sacheint rcclose(dev, flag, mode, p) 8358471Sache dev_t dev; 8368471Sache int flag, mode; 8378471Sache struct proc *p; 8388471Sache{ 8398471Sache register struct rc_chans *rc; 8408471Sache register struct tty *tp; 8418471Sache int s, unit = GET_UNIT(dev); 8428471Sache 8438471Sache if (unit >= NRC * CD180_NCHAN) 8448471Sache return ENXIO; 8458471Sache rc = &rc_chans[unit]; 8468471Sache tp = rc->rc_tp; 8479232Sache#ifdef RCDEBUG 8489232Sache printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 8499232Sache#endif 8508471Sache s = spltty(); 8518471Sache (*linesw[tp->t_line].l_close)(tp, flag); 8528471Sache rcstop(tp, FREAD | FWRITE); 8538471Sache rc_hardclose(rc); 8548471Sache ttyclose(tp); 8558471Sache splx(s); 8568471Sache return 0; 8578471Sache} 8588471Sache 8598471Sachestatic void rc_hardclose(rc) 8608471Sacheregister struct rc_chans *rc; 8618471Sache{ 8628471Sache register int s, nec = rc->rc_rcb->rcb_addr; 8638471Sache register struct tty *tp = rc->rc_tp; 8648471Sache 8658471Sache s = spltty(); 8668471Sache rcout(CD180_CAR, rc->rc_chan); 8678471Sache 8689232Sache /* Disable rx/tx intrs */ 8698471Sache rcout(CD180_IER, rc->rc_ier = 0); 8709232Sache if ( (tp->t_cflag & HUPCL) 8718471Sache || !(rc->rc_flags & RC_ACTOUT) 8728471Sache && !(rc->rc_msvr & MSVR_CD) 8738471Sache && !(tp->t_cflag & CLOCAL) 8749232Sache || !(tp->t_state & TS_ISOPEN) 8759232Sache ) { 8769232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 8779232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 8788471Sache (void) rc_modctl(rc, TIOCM_RTS, DMSET); 8798471Sache if (rc->rc_dtrwait) { 8808471Sache timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 8818471Sache rc->rc_flags |= RC_DTR_OFF; 8828471Sache } 8838471Sache } 8848471Sache rc->rc_flags &= ~RC_ACTOUT; 8858471Sache wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 8869639Sbde wakeup(TSA_CARR_ON(tp)); 8878471Sache (void) splx(s); 8888471Sache} 8898471Sache 8908471Sache/* Read from line */ 8918471Sacheint rcread(dev, uio, flag) 8928471Sache dev_t dev; 8938471Sache struct uio *uio; 8948471Sache int flag; 8958471Sache{ 8968471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 8979232Sache 8988471Sache return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 8998471Sache} 9008471Sache 9018471Sache/* Write to line */ 9028471Sacheint rcwrite(dev, uio, flag) 9038471Sache dev_t dev; 9048471Sache struct uio *uio; 9058471Sache int flag; 9068471Sache{ 9078471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 9089232Sache 9098471Sache return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 9108471Sache} 9118471Sache 9128471Sache/* Reset the bastard */ 9139232Sachestatic void rc_hwreset(unit, nec, chipid) 9149232Sache register int unit, nec; 9158471Sache unsigned int chipid; 9168471Sache{ 9179232Sache CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 9188471Sache DELAY(20000); 9199232Sache WAITFORCCR(unit, -1); 9209232Sache 9219232Sache rcout(RC_CTOUT, 0); /* Clear timeout */ 9228471Sache rcout(CD180_GIVR, chipid); 9238471Sache rcout(CD180_GICR, 0); 9248471Sache 9258471Sache /* Set Prescaler Registers (1 msec) */ 9269232Sache rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 9279232Sache rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 9288471Sache 9298471Sache /* Initialize Priority Interrupt Level Registers */ 9308471Sache rcout(CD180_PILR1, RC_PILR_MODEM); 9318471Sache rcout(CD180_PILR2, RC_PILR_TX); 9328471Sache rcout(CD180_PILR3, RC_PILR_RX); 9338471Sache 9348471Sache /* Reset DTR */ 9359232Sache rcout(RC_DTREG, ~0); 9368471Sache} 9378471Sache 9388471Sache/* Set channel parameters */ 9398471Sachestatic int rc_param(tp, ts) 9408471Sache register struct tty *tp; 9418471Sache struct termios *ts; 9428471Sache{ 9439232Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 9448471Sache register int nec = rc->rc_rcb->rcb_addr; 9459232Sache int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 9468471Sache 9478471Sache odivs = ttspeedtab(ts->c_ospeed, rc_speedtab); 9488471Sache if (ts->c_ispeed == 0) 9498471Sache ts->c_ispeed = ts->c_ospeed; 9508471Sache idivs = ttspeedtab(ts->c_ispeed, rc_speedtab); 9518471Sache if (idivs < 0 || odivs < 0) 9528471Sache return (EINVAL); 9538471Sache 9548471Sache s = spltty(); 9558471Sache 9569232Sache /* Select channel */ 9579232Sache rcout(CD180_CAR, rc->rc_chan); 9589232Sache 9598471Sache /* If speed == 0, hangup line */ 9609232Sache if (ts->c_ospeed == 0) { 9619232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 9629232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 9639232Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 9649232Sache } 9658471Sache 9668471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 9678471Sache cflag = ts->c_cflag; 9688471Sache iflag = ts->c_iflag; 9698471Sache lflag = ts->c_lflag; 9708471Sache 9718471Sache if (idivs > 0) { 9728471Sache rcout(CD180_RBPRL, idivs & 0xFF); 9738471Sache rcout(CD180_RBPRH, idivs >> 8); 9748471Sache } 9758471Sache if (odivs > 0) { 9768471Sache rcout(CD180_TBPRL, odivs & 0xFF); 9778471Sache rcout(CD180_TBPRH, odivs >> 8); 9788471Sache } 9798471Sache 9808471Sache /* set timeout value */ 9819232Sache if (ts->c_ispeed > 0) { 9829232Sache int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 9838471Sache 9849232Sache if ( !(lflag & ICANON) 9859232Sache && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 9869232Sache && ts->c_cc[VTIME] * 10 > itm) 9879232Sache itm = ts->c_cc[VTIME] * 10; 9889232Sache 9899232Sache rcout(CD180_RTPR, itm <= 255 ? itm : 255); 9909232Sache } 9919232Sache 9928471Sache switch (cflag & CSIZE) { 9938471Sache case CS5: val = COR1_5BITS; break; 9948471Sache case CS6: val = COR1_6BITS; break; 9958471Sache case CS7: val = COR1_7BITS; break; 9968471Sache default: 9978471Sache case CS8: val = COR1_8BITS; break; 9988471Sache } 9998471Sache if (cflag & PARENB) { 10008471Sache val |= COR1_NORMPAR; 10018471Sache if (cflag & PARODD) 10028471Sache val |= COR1_ODDP; 10039232Sache if (!(cflag & INPCK)) 10049232Sache val |= COR1_Ignore; 10058471Sache } else 10069232Sache val |= COR1_Ignore; 10078471Sache if (cflag & CSTOPB) 10088471Sache val |= COR1_2SB; 10098471Sache rcout(CD180_COR1, val); 10108471Sache 10118471Sache /* Set FIFO threshold */ 10129232Sache val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 10139232Sache inpflow = 0; 10149232Sache if ( (iflag & IXOFF) 10159232Sache && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 10169232Sache && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 10179232Sache || (iflag & IXANY) 10189232Sache ) 10199232Sache ) 10209232Sache ) { 10219232Sache inpflow = 1; 10229232Sache val |= COR3_SCDE|COR3_FCT; 10239232Sache } 10249232Sache rcout(CD180_COR3, val); 10258471Sache 10268471Sache /* Initialize on-chip automatic flow control */ 10278471Sache val = 0; 10289232Sache rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 10298471Sache if (cflag & CCTS_OFLOW) { 10308471Sache rc->rc_flags |= RC_CTSFLOW; 10319232Sache val |= COR2_CtsAE; 10329232Sache } else 10339232Sache rc->rc_flags |= RC_SEND_RDY; 10349232Sache if (tp->t_state & TS_TTSTOP) 10359232Sache rc->rc_flags |= RC_OSUSP; 10368471Sache else 10379232Sache rc->rc_flags &= ~RC_OSUSP; 10388471Sache if (cflag & CRTS_IFLOW) 10398471Sache rc->rc_flags |= RC_RTSFLOW; 10409232Sache else 10419232Sache rc->rc_flags &= ~RC_RTSFLOW; 10428471Sache 10439232Sache if (inpflow) { 10449232Sache if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 10459232Sache rcout(CD180_SCHR1, ts->c_cc[VSTART]); 10469232Sache rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 10479232Sache val |= COR2_TxIBE; 10489232Sache if (iflag & IXANY) 10499232Sache val |= COR2_IXM; 10508471Sache } 10518471Sache 10529232Sache rcout(CD180_COR2, rc->rc_cor2 = val); 10538471Sache 10549232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10559232Sache CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 10569232Sache 10578471Sache disc_optim(tp, ts, rc); 10588471Sache 10598471Sache /* modem ctl */ 10609232Sache val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 10619232Sache if (cflag & CCTS_OFLOW) 10629232Sache val |= MCOR1_CTSzd; 10639232Sache rcout(CD180_MCOR1, val); 10648471Sache 10659232Sache val = cflag & CLOCAL ? 0 : MCOR2_CDod; 10669232Sache if (cflag & CCTS_OFLOW) 10679232Sache val |= MCOR2_CTSod; 10689232Sache rcout(CD180_MCOR2, val); 10699232Sache 10708471Sache /* enable i/o and interrupts */ 10719232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10729232Sache CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 10739232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 10748471Sache 10759232Sache rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 10769232Sache if (cflag & CCTS_OFLOW) 10779232Sache rc->rc_ier |= IER_CTS; 10789232Sache if (cflag & CREAD) 10799232Sache rc->rc_ier |= IER_RxData; 10809232Sache if (tp->t_state & TS_BUSY) 10819232Sache rc->rc_ier |= IER_TxRdy; 10829232Sache if (ts->c_ospeed != 0) 10839232Sache rc_modctl(rc, TIOCM_DTR, DMBIS); 10849232Sache if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 10859232Sache rc->rc_flags |= RC_SEND_RDY; 10869232Sache rcout(CD180_IER, rc->rc_ier); 10878471Sache (void) splx(s); 10888471Sache return 0; 10898471Sache} 10908471Sache 10919232Sache/* Re-initialize board after bogus interrupts */ 10929232Sachestatic void rc_reinit(rcb) 10939232Sachestruct rc_softc *rcb; 10949232Sache{ 10959232Sache register struct rc_chans *rc, *rce; 10969232Sache register int i, nec; 10979232Sache 10989232Sache nec = rcb->rcb_addr; 10999232Sache rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 11009232Sache rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 11019232Sache rce = rc + CD180_NCHAN; 11029232Sache for (; rc < rce; rc++) 11039232Sache (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 11049232Sache} 11059232Sache 11068471Sacheint rcioctl(dev, cmd, data, flag, p) 11078471Sachedev_t dev; 11088471Sacheint cmd, flag; 11098471Sachecaddr_t data; 11108471Sachestruct proc *p; 11118471Sache{ 11128471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 11138471Sache register int s, error; 11148471Sache struct tty *tp = rc->rc_tp; 11158471Sache 11168471Sache error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 11178471Sache if (error >= 0) 11188471Sache return (error); 11198471Sache error = ttioctl(tp, cmd, data, flag); 11208471Sache if (error >= 0) 11218471Sache return (error); 11228471Sache s = spltty(); 11238471Sache 11248471Sache switch (cmd) { 11258471Sache case TIOCSBRK: 11268471Sache rc->rc_pendcmd = CD180_C_SBRK; 11278471Sache break; 11288471Sache 11298471Sache case TIOCCBRK: 11308471Sache rc->rc_pendcmd = CD180_C_EBRK; 11318471Sache break; 11328471Sache 11338471Sache case TIOCSDTR: 11349232Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 11358471Sache break; 11368471Sache 11378471Sache case TIOCCDTR: 11388471Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 11398471Sache break; 11408471Sache 11418471Sache case TIOCMGET: 11428471Sache *(int *) data = rc_modctl(rc, 0, DMGET); 11438471Sache break; 11448471Sache 11458471Sache case TIOCMSET: 11468471Sache (void) rc_modctl(rc, *(int *) data, DMSET); 11478471Sache break; 11488471Sache 11498471Sache case TIOCMBIC: 11508471Sache (void) rc_modctl(rc, *(int *) data, DMBIC); 11518471Sache break; 11528471Sache 11538471Sache case TIOCMBIS: 11548471Sache (void) rc_modctl(rc, *(int *) data, DMBIS); 11558471Sache break; 11568471Sache 11578471Sache case TIOCMSDTRWAIT: 11588471Sache error = suser(p->p_ucred, &p->p_acflag); 11598471Sache if (error != 0) { 11608471Sache splx(s); 11618471Sache return (error); 11628471Sache } 11638471Sache rc->rc_dtrwait = *(int *)data * hz / 100; 11648471Sache break; 11658471Sache 11668471Sache case TIOCMGDTRWAIT: 11678471Sache *(int *)data = rc->rc_dtrwait * 100 / hz; 11688471Sache break; 11698471Sache 11708471Sache default: 11718471Sache (void) splx(s); 11728471Sache return ENOTTY; 11738471Sache } 11748471Sache (void) splx(s); 11758471Sache return 0; 11768471Sache} 11778471Sache 11788471Sache 11798471Sache/* Modem control routines */ 11808471Sache 11818471Sachestatic int rc_modctl(rc, bits, cmd) 11828471Sacheregister struct rc_chans *rc; 11838471Sacheint bits, cmd; 11848471Sache{ 11858471Sache register int nec = rc->rc_rcb->rcb_addr; 11869232Sache u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 11878471Sache 11888471Sache rcout(CD180_CAR, rc->rc_chan); 11898471Sache 11908471Sache switch (cmd) { 11918471Sache case DMSET: 11929232Sache rcout(RC_DTREG, (bits & TIOCM_DTR) ? 11939232Sache ~(*dtr |= 1 << rc->rc_chan) : 11949232Sache ~(*dtr &= ~(1 << rc->rc_chan))); 11959232Sache msvr = rcin(CD180_MSVR); 11969232Sache if (bits & TIOCM_RTS) 11979232Sache msvr |= MSVR_RTS; 11989232Sache else 11999232Sache msvr &= ~MSVR_RTS; 12009232Sache if (bits & TIOCM_DTR) 12019232Sache msvr |= MSVR_DTR; 12029232Sache else 12039232Sache msvr &= ~MSVR_DTR; 12049232Sache rcout(CD180_MSVR, msvr); 12059232Sache break; 12068471Sache 12078471Sache case DMBIS: 12089232Sache if (bits & TIOCM_DTR) 12099232Sache rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 12109232Sache msvr = rcin(CD180_MSVR); 12118471Sache if (bits & TIOCM_RTS) 12129232Sache msvr |= MSVR_RTS; 12138471Sache if (bits & TIOCM_DTR) 12149232Sache msvr |= MSVR_DTR; 12159232Sache rcout(CD180_MSVR, msvr); 12168471Sache break; 12178471Sache 12188471Sache case DMGET: 12198471Sache bits = TIOCM_LE; 12209232Sache msvr = rc->rc_msvr = rcin(CD180_MSVR); 12218471Sache 12228471Sache if (msvr & MSVR_RTS) 12238471Sache bits |= TIOCM_RTS; 12248471Sache if (msvr & MSVR_CTS) 12258471Sache bits |= TIOCM_CTS; 12268471Sache if (msvr & MSVR_DSR) 12278471Sache bits |= TIOCM_DSR; 12288471Sache if (msvr & MSVR_DTR) 12298471Sache bits |= TIOCM_DTR; 12309232Sache if (msvr & MSVR_CD) 12319232Sache bits |= TIOCM_CD; 12329232Sache if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 12339232Sache bits |= TIOCM_RI; 12348471Sache return bits; 12358471Sache 12368471Sache case DMBIC: 12378471Sache if (bits & TIOCM_DTR) 12389232Sache rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 12399232Sache msvr = rcin(CD180_MSVR); 12408471Sache if (bits & TIOCM_RTS) 12419232Sache msvr &= ~MSVR_RTS; 12429232Sache if (bits & TIOCM_DTR) 12439232Sache msvr &= ~MSVR_DTR; 12449232Sache rcout(CD180_MSVR, msvr); 12458471Sache break; 12468471Sache } 12479232Sache rc->rc_msvr = rcin(CD180_MSVR); 12488471Sache return 0; 12498471Sache} 12508471Sache 12518471Sache/* Test the board. */ 12528471Sacheint rc_test(nec, unit) 12538471Sache register int nec; 12548471Sache int unit; 12558471Sache{ 12568471Sache int chan = 0, nopt = 0; 12578471Sache int i = 0, rcnt, old_level; 12588471Sache unsigned int iack, chipid; 12598471Sache unsigned short divs; 12608471Sache static u_char ctest[] = "\377\125\252\045\244\0\377"; 12618471Sache#define CTLEN 8 12628471Sache#define ERR(s) { \ 12638471Sache printf("rc%d: ", unit); printf s ; printf("\n"); \ 12648471Sache (void) splx(old_level); return 1; } 12658471Sache 12668471Sache struct rtest { 12678471Sache u_char txbuf[CD180_NFIFO]; /* TX buffer */ 12688471Sache u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 12698471Sache int rxptr; /* RX pointer */ 12708471Sache int txptr; /* TX pointer */ 12718471Sache } tchans[CD180_NCHAN]; 12728471Sache 12739232Sache old_level = spltty(); 12748471Sache 12758471Sache chipid = RC_FAKEID; 12768471Sache 12778471Sache /* First, reset board to inital state */ 12789232Sache rc_hwreset(unit, nec, chipid); 12798471Sache 12809232Sache divs = RC_BRD(19200); 12819232Sache 12828471Sache /* Initialize channels */ 12838471Sache for (chan = 0; chan < CD180_NCHAN; chan++) { 12848471Sache 12858471Sache /* Select and reset channel */ 12868471Sache rcout(CD180_CAR, chan); 12879232Sache CCRCMD(unit, chan, CCR_ResetChan); 12889232Sache WAITFORCCR(unit, chan); 12898471Sache 12908471Sache /* Set speed */ 12918471Sache rcout(CD180_RBPRL, divs & 0xFF); 12928471Sache rcout(CD180_RBPRH, divs >> 8); 12938471Sache rcout(CD180_TBPRL, divs & 0xFF); 12948471Sache rcout(CD180_TBPRH, divs >> 8); 12958471Sache 12968471Sache /* set timeout value */ 12978471Sache rcout(CD180_RTPR, 0); 12988471Sache 12998471Sache /* Establish local loopback */ 13008471Sache rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 13018471Sache rcout(CD180_COR2, COR2_LLM); 13028471Sache rcout(CD180_COR3, CD180_NFIFO); 13039232Sache CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 13049232Sache CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 13059232Sache WAITFORCCR(unit, chan); 13068471Sache rcout(CD180_MSVR, MSVR_RTS); 13078471Sache 13088471Sache /* Fill TXBUF with test data */ 13098471Sache for (i = 0; i < CD180_NFIFO; i++) { 13108471Sache tchans[chan].txbuf[i] = ctest[i]; 13118471Sache tchans[chan].rxbuf[i] = 0; 13128471Sache } 13138471Sache tchans[chan].txptr = tchans[chan].rxptr = 0; 13148471Sache 13158471Sache /* Now, start transmit */ 13169232Sache rcout(CD180_IER, IER_TxMpty|IER_RxData); 13178471Sache } 13188471Sache /* Pseudo-interrupt poll stuff */ 13198471Sache for (rcnt = 10000; rcnt-- > 0; rcnt--) { 13209232Sache i = ~(rcin(RC_BSR)); 13218471Sache if (i & RC_BSR_TOUT) 13228471Sache ERR(("BSR timeout bit set\n")) 13239232Sache else if (i & RC_BSR_TXINT) { 13248471Sache iack = rcin(RC_PILR_TX); 13258471Sache if (iack != (GIVR_IT_TDI | chipid)) 13268471Sache ERR(("Bad TX intr ack (%02x != %02x)\n", 13278471Sache iack, GIVR_IT_TDI | chipid)); 13289232Sache chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13298471Sache /* If no more data to transmit, disable TX intr */ 13308471Sache if (tchans[chan].txptr >= CD180_NFIFO) { 13318471Sache iack = rcin(CD180_IER); 13329232Sache rcout(CD180_IER, iack & ~IER_TxMpty); 13338471Sache } else { 13348471Sache for (iack = tchans[chan].txptr; 13358471Sache iack < CD180_NFIFO; iack++) 13368471Sache rcout(CD180_TDR, 13378471Sache tchans[chan].txbuf[iack]); 13388471Sache tchans[chan].txptr = iack; 13398471Sache } 13409232Sache rcout(CD180_EOIR, 0); 13419232Sache } else if (i & RC_BSR_RXINT) { 13429232Sache u_char ucnt; 13438471Sache 13448471Sache iack = rcin(RC_PILR_RX); 13458471Sache if (iack != (GIVR_IT_RGDI | chipid) && 13468471Sache iack != (GIVR_IT_REI | chipid)) 13478471Sache ERR(("Bad RX intr ack (%02x != %02x)\n", 13488471Sache iack, GIVR_IT_RGDI | chipid)) 13499232Sache chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13508471Sache ucnt = rcin(CD180_RDCR) & 0xF; 13518471Sache while (ucnt-- > 0) { 13528471Sache iack = rcin(CD180_RCSR); 13539232Sache if (iack & RCSR_Timeout) 13548471Sache break; 13558471Sache if (iack & 0xF) 13568471Sache ERR(("Bad char chan %d (RCSR = %02X)\n", 13578471Sache chan, iack)) 13588471Sache if (tchans[chan].rxptr > CD180_NFIFO) 13598471Sache ERR(("Got extra chars chan %d\n", 13608471Sache chan)) 13618471Sache tchans[chan].rxbuf[tchans[chan].rxptr++] = 13628471Sache rcin(CD180_RDR); 13638471Sache } 13648471Sache rcout(CD180_EOIR, 0); 13658471Sache } 13669232Sache rcout(RC_CTOUT, 0); 13678471Sache for (iack = chan = 0; chan < CD180_NCHAN; chan++) 13688471Sache if (tchans[chan].rxptr >= CD180_NFIFO) 13698471Sache iack++; 13708471Sache if (iack == CD180_NCHAN) 13718471Sache break; 13728471Sache } 13739232Sache for (chan = 0; chan < CD180_NCHAN; chan++) { 13749232Sache /* Select and reset channel */ 13759232Sache rcout(CD180_CAR, chan); 13769232Sache CCRCMD(unit, chan, CCR_ResetChan); 13779232Sache } 13789232Sache 13798471Sache if (!rcnt) 13808471Sache ERR(("looses characters during local loopback\n")) 13818471Sache /* Now, check data */ 13828471Sache for (chan = 0; chan < CD180_NCHAN; chan++) 13838471Sache for (i = 0; i < CD180_NFIFO; i++) 13848471Sache if (ctest[i] != tchans[chan].rxbuf[i]) 13858471Sache ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 13868471Sache chan, i, ctest[i], tchans[chan].rxbuf[i])) 13878471Sache (void) splx(old_level); 13888471Sache return 0; 13898471Sache} 13908471Sache 13918471Sache#ifdef RCDEBUG 13929232Sachestatic void printrcflags(rc, comment) 13938471Sachestruct rc_chans *rc; 13948471Sachechar *comment; 13958471Sache{ 13968471Sache u_short f = rc->rc_flags; 13979232Sache register int nec = rc->rc_rcb->rcb_addr; 13988471Sache 13999232Sache printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 14008471Sache rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 14018471Sache (f & RC_DTR_OFF)?"DTR_OFF " :"", 14029232Sache (f & RC_ACTOUT) ?"ACTOUT " :"", 14039232Sache (f & RC_RTSFLOW)?"RTSFLOW " :"", 14049232Sache (f & RC_CTSFLOW)?"CTSFLOW " :"", 14059232Sache (f & RC_DORXFER)?"DORXFER " :"", 14069232Sache (f & RC_DOXXFER)?"DOXXFER " :"", 14079232Sache (f & RC_MODCHG) ?"MODCHG " :"", 14089232Sache (f & RC_OSUSP) ?"OSUSP " :"", 14099232Sache (f & RC_OSBUSY) ?"OSBUSY " :"", 14109232Sache (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 14119232Sache (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 14129232Sache (f & RC_SEND_RDY) ?"SEND_RDY":""); 14139232Sache 14149232Sache rcout(CD180_CAR, rc->rc_chan); 14159232Sache 14169232Sache printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 14179232Sache rc->rc_rcb->rcb_unit, rc->rc_chan, 14189232Sache rcin(CD180_MSVR), 14199232Sache rcin(CD180_IER), 14209232Sache rcin(CD180_CCSR)); 14218471Sache} 14228471Sache#endif /* RCDEBUG */ 14238471Sache 14248471Sachestruct tty * 14258471Sachercdevtotty(dev) 14268471Sache dev_t dev; 14278471Sache{ 14288471Sache int unit; 14298471Sache 14308471Sache unit = GET_UNIT(dev); 14318471Sache if (unit >= NRC * CD180_NCHAN) 14328471Sache return NULL; 14338471Sache return (&rc_tty[unit]); 14348471Sache} 14358471Sache 14368471Sachestatic void 14378471Sacherc_dtrwakeup(chan) 14388471Sache void *chan; 14398471Sache{ 14408471Sache struct rc_chans *rc; 14418471Sache 14428471Sache rc = (struct rc_chans *)chan; 14438471Sache rc->rc_flags &= ~RC_DTR_OFF; 14448471Sache wakeup(&rc->rc_dtrwait); 14458471Sache} 14468471Sache 14478471Sachestatic void 14488471Sacherc_discard_output(rc) 14498471Sache struct rc_chans *rc; 14508471Sache{ 14518471Sache disable_intr(); 14528471Sache if (rc->rc_flags & RC_DOXXFER) { 14538471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 14548471Sache rc->rc_flags &= ~RC_DOXXFER; 14558471Sache } 14568471Sache rc->rc_optr = rc->rc_obufend; 14579232Sache rc->rc_tp->t_state &= ~TS_BUSY; 14588471Sache enable_intr(); 14599754Sbde ttwwakeup(rc->rc_tp); 14608471Sache} 14618471Sache 14628471Sachestatic void 14638471Sacherc_wakeup(chan) 14648471Sache void *chan; 14658471Sache{ 14668471Sache int unit; 14678471Sache 14688471Sache timeout(rc_wakeup, (caddr_t)NULL, 1); 14698471Sache 14708471Sache if (rc_scheduled_event != 0) { 14718471Sache int s; 14728471Sache 14738471Sache s = splsofttty(); 14748471Sache rcpoll(); 14758471Sache splx(s); 14768471Sache } 14778471Sache} 14788471Sache 14798471Sachestatic void 14808471Sachedisc_optim(tp, t, rc) 14818471Sache struct tty *tp; 14828471Sache struct termios *t; 14838471Sache struct rc_chans *rc; 14848471Sache{ 14858471Sache 14869757Sbde if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 14878471Sache && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 14889757Sbde && (!(t->c_iflag & PARMRK) 14899757Sbde || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 14909757Sbde && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 14918471Sache && linesw[tp->t_line].l_rint == ttyinput) 14928471Sache tp->t_state |= TS_CAN_BYPASS_L_RINT; 14938471Sache else 14948471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 14958471Sache if (tp->t_line == SLIPDISC) 14968471Sache rc->rc_hotchar = 0xc0; 14978471Sache else if (tp->t_line == PPPDISC) 14988471Sache rc->rc_hotchar = 0x7e; 14998471Sache else 15008471Sache rc->rc_hotchar = 0; 15018471Sache} 15029232Sache 15039232Sachestatic void 15049232Sacherc_wait0(nec, unit, chan, line) 15059232Sache int nec, unit, chan, line; 15069232Sache{ 15079232Sache int rcnt; 15089232Sache 15099232Sache for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--) 15109232Sache DELAY(15); 15119232Sache if (rcnt == 0) 15129232Sache printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 15139232Sache unit, chan, line); 15149232Sache} 15158471Sache#endif /* NRC */ 1516