rc.c revision 9822
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/user.h> 44#include <sys/conf.h> 45#include <sys/dkstat.h> 46#include <sys/file.h> 47#include <sys/uio.h> 48#include <sys/kernel.h> 49#include <sys/syslog.h> 50#include <sys/devconf.h> 51 52#include <machine/clock.h> 53 54#include <i386/isa/isa.h> 55#include <i386/isa/isa_device.h> 56#include <i386/isa/sioreg.h> 57 58#include <i386/isa/ic/cd180.h> 59#include <i386/isa/rcreg.h> 60 61/* Prototypes */ 62int rcprobe __P((struct isa_device *)); 63int rcattach __P((struct isa_device *)); 64 65int rcopen __P((dev_t, int, int, struct proc *)); 66int rcclose __P((dev_t, int, int, struct proc *)); 67int rcread __P((dev_t, struct uio *, int)); 68int rcwrite __P((dev_t, struct uio *, int)); 69void rcintr __P((int)); 70void rcpoll __P((void)); 71void rcstop __P((struct tty *, int)); 72int rcioctl __P((dev_t, int, caddr_t, int, struct proc *)); 73 74#define rcin(port) RC_IN (nec, port) 75#define rcout(port,v) RC_OUT (nec, port, v) 76 77#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 78#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 79 80#define RC_IBUFSIZE 256 81#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 82#define RC_OBUFSIZE 512 83#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 84#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 85#define LOTS_OF_EVENTS 64 86 87#define RC_FAKEID 0x10 88 89#define RC_PROBED 1 90#define RC_ATTACHED 2 91 92#define GET_UNIT(dev) (minor(dev) & 0x3F) 93#define CALLOUT(dev) (minor(dev) & 0x80) 94 95/* For isa routines */ 96struct isa_driver rcdriver = { 97 rcprobe, rcattach, "rc" 98}; 99 100/* Per-board structure */ 101static struct rc_softc { 102 u_int rcb_probed; /* 1 - probed, 2 - attached */ 103 u_int rcb_addr; /* Base I/O addr */ 104 u_int rcb_unit; /* unit # */ 105 u_char rcb_dtr; /* DTR status */ 106 struct rc_chans *rcb_baserc; /* base rc ptr */ 107} rc_softc[NRC]; 108 109/* Per-channel structure */ 110static struct rc_chans { 111 struct rc_softc *rc_rcb; /* back ptr */ 112 u_short rc_flags; /* Misc. flags */ 113 int rc_chan; /* Channel # */ 114 u_char rc_ier; /* intr. enable reg */ 115 u_char rc_msvr; /* modem sig. status */ 116 u_char rc_cor2; /* options reg */ 117 u_char rc_pendcmd; /* special cmd pending */ 118 u_int rc_dtrwait; /* dtr timeout */ 119 u_int rc_dcdwaits; /* how many waits DCD in open */ 120 u_char rc_hotchar; /* end packed optimize */ 121 struct tty *rc_tp; /* tty struct */ 122 u_char *rc_iptr; /* Chars input buffer */ 123 u_char *rc_hiwat; /* hi-water mark */ 124 u_char *rc_bufend; /* end of buffer */ 125 u_char *rc_optr; /* ptr in output buf */ 126 u_char *rc_obufend; /* end of output buf */ 127 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 128 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 129} rc_chans[NRC * CD180_NCHAN]; 130 131static int rc_scheduled_event = 0; 132 133/* for pstat -t */ 134struct tty rc_tty[NRC * CD180_NCHAN]; 135int nrc_tty = NRC * CD180_NCHAN; 136 137/* Flags */ 138#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 139#define RC_ACTOUT 0x0002 /* Dial-out port active */ 140#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 141#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 142#define RC_DORXFER 0x0010 /* RXFER event planned */ 143#define RC_DOXXFER 0x0020 /* XXFER event planned */ 144#define RC_MODCHG 0x0040 /* Modem status changed */ 145#define RC_OSUSP 0x0080 /* Output suspended */ 146#define RC_OSBUSY 0x0100 /* start() routine in progress */ 147#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 148#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 149#define RC_SEND_RDY 0x0800 /* ready to send */ 150 151static struct speedtab rc_speedtab[] = { 152 0, 0, 153 50, RC_BRD(50), 154 75, RC_BRD(75), 155 110, RC_BRD(110), 156 134, RC_BRD(134), 157 150, RC_BRD(150), 158 200, RC_BRD(200), 159 300, RC_BRD(300), 160 600, RC_BRD(600), 161 1200, RC_BRD(1200), 162 1800, RC_BRD(1800), 163 2400, RC_BRD(2400), 164 4800, RC_BRD(4800), 165 9600, RC_BRD(9600), 166 19200, RC_BRD(19200), 167 38400, RC_BRD(38400), 168 57600, RC_BRD(57600), 169 /* real max value is 76800 with 9.8304 MHz clock */ 170 -1, -1 171}; 172 173/* Table for translation of RCSR status bits to internal form */ 174static int rc_rcsrt[16] = { 175 0, TTY_OE, TTY_FE, 176 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 177 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 178 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 179 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 180 TTY_BI|TTY_PE|TTY_FE|TTY_OE 181}; 182 183/* Static prototypes */ 184static void rc_hwreset __P((int, int, unsigned int)); 185static int rc_test __P((int, int)); 186static void rc_discard_output __P((struct rc_chans *)); 187static void rc_hardclose __P((struct rc_chans *)); 188static int rc_modctl __P((struct rc_chans *, int, int)); 189static void rc_start __P((struct tty *)); 190static int rc_param __P((struct tty *, struct termios *)); 191static void rc_registerdev __P((struct isa_device *id)); 192static void rc_reinit __P((struct rc_softc *)); 193#ifdef RCDEBUG 194static void printrcflags(); 195#endif 196static timeout_t rc_dtrwakeup; 197static timeout_t rc_wakeup; 198static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 199static void rc_wait0 __P((int nec, int unit, int chan, int line)); 200 201/**********************************************/ 202 203/* Quick device probing */ 204int rcprobe(dvp) 205 struct isa_device *dvp; 206{ 207 int irq = ffs(dvp->id_irq) - 1; 208 register int nec = dvp->id_iobase; 209 210 if (dvp->id_unit > NRC) 211 return 0; 212 if (!RC_VALIDADDR(nec)) { 213 printf("rc%d: illegal base address %x\n", nec); 214 return 0; 215 } 216 if (!RC_VALIDIRQ(irq)) { 217 printf("rc%d: illegal IRQ value %d\n", irq); 218 return 0; 219 } 220 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 221 rcout(CD180_PPRH, 0x11); 222 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 223 return 0; 224 /* Now, test the board more thoroughly, with diagnostic */ 225 if (rc_test(nec, dvp->id_unit)) 226 return 0; 227 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 228 229 return 0xF; 230} 231 232static struct kern_devconf kdc_rc[NRC] = { { 233 0, 0, 0, /* filled in by dev_attach */ 234 "rc", 0, { MDDT_ISA, 0, "tty" }, 235 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 236 &kdc_isa0, /* parent */ 237 0, /* parentdata */ 238 DC_UNCONFIGURED, /* state */ 239 "RISCom/8 multiport card", 240 DC_CLS_SERIAL /* class */ 241} }; 242 243static void 244rc_registerdev(id) 245 struct isa_device *id; 246{ 247 int unit; 248 249 unit = id->id_unit; 250 if (unit != 0) 251 kdc_rc[unit] = kdc_rc[0]; 252 kdc_rc[unit].kdc_unit = unit; 253 kdc_rc[unit].kdc_isa = id; 254 kdc_rc[unit].kdc_state = DC_UNKNOWN; 255 dev_attach(&kdc_rc[unit]); 256} 257 258int rcattach(dvp) 259 struct isa_device *dvp; 260{ 261 register int i, chan, nec = dvp->id_iobase; 262 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 263 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 264 static int rc_wakeup_started = 0; 265 struct tty *tp; 266 267 /* Thorooughly test the device */ 268 if (rcb->rcb_probed != RC_PROBED) 269 return 0; 270 rcb->rcb_addr = nec; 271 rcb->rcb_dtr = 0; 272 rcb->rcb_baserc = rc; 273 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 274 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 275 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 276 277 rc_registerdev(dvp); 278 279 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 280 rc->rc_rcb = rcb; 281 rc->rc_chan = chan; 282 rc->rc_iptr = rc->rc_ibuf; 283 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 284 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 285 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 286 rc->rc_cor2 = rc->rc_pendcmd = 0; 287 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 288 rc->rc_dtrwait = 3 * hz; 289 rc->rc_dcdwaits= 0; 290 rc->rc_hotchar = 0; 291 tp = rc->rc_tp = &rc_tty[chan]; 292 ttychars(tp); 293 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 294 tp->t_cflag = TTYDEF_CFLAG; 295 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 296 } 297 rcb->rcb_probed = RC_ATTACHED; 298 if (!rc_wakeup_started) { 299 rc_wakeup((void *)NULL); 300 rc_wakeup_started = 0; 301 } 302 return 1; 303} 304 305/* RC interrupt handling */ 306void rcintr(unit) 307 int unit; 308{ 309 register struct rc_softc *rcb = &rc_softc[unit]; 310 register struct rc_chans *rc; 311 register int nec, resid; 312 register u_char val, iack, bsr, ucnt, *optr; 313 int good_data, t_state; 314 315 if (rcb->rcb_probed != RC_ATTACHED) { 316 printf("rc%d: bogus interrupt\n", unit); 317 return; 318 } 319 nec = rcb->rcb_addr; 320 321 bsr = ~(rcin(RC_BSR)); 322 323 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 324 printf("rc%d: extra interrupt\n", unit); 325 rcout(CD180_EOIR, 0); 326 return; 327 } 328 329 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 330#ifdef RCDEBUG_DETAILED 331 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 332 (bsr & RC_BSR_TOUT)?"TOUT ":"", 333 (bsr & RC_BSR_RXINT)?"RXINT ":"", 334 (bsr & RC_BSR_TXINT)?"TXINT ":"", 335 (bsr & RC_BSR_MOINT)?"MOINT":""); 336#endif 337 if (bsr & RC_BSR_TOUT) { 338 printf("rc%d: hardware failure, reset board\n", unit); 339 rcout(RC_CTOUT, 0); 340 rc_reinit(rcb); 341 return; 342 } 343 if (bsr & RC_BSR_RXINT) { 344 iack = rcin(RC_PILR_RX); 345 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 346 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 347 printf("rc%d: fake rxint: %02x\n", unit, iack); 348 goto more_intrs; 349 } 350 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 351 t_state = rc->rc_tp->t_state; 352 /* Do RTS flow control stuff */ 353 if ( (rc->rc_flags & RC_RTSFLOW) 354 || !(t_state & TS_ISOPEN) 355 ) { 356 if ( ( !(t_state & TS_ISOPEN) 357 || (t_state & TS_TBLOCK) 358 ) 359 && (rc->rc_msvr & MSVR_RTS) 360 ) 361 rcout(CD180_MSVR, 362 rc->rc_msvr &= ~MSVR_RTS); 363 else if (!(rc->rc_msvr & MSVR_RTS)) 364 rcout(CD180_MSVR, 365 rc->rc_msvr |= MSVR_RTS); 366 } 367 ucnt = rcin(CD180_RDCR) & 0xF; 368 resid = 0; 369 370 if (t_state & TS_ISOPEN) { 371 /* check for input buffer overflow */ 372 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 373 resid = ucnt; 374 ucnt = rc->rc_bufend - rc->rc_iptr; 375 resid -= ucnt; 376 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 377 rc->rc_flags |= RC_WAS_BUFOVFL; 378 rc_scheduled_event++; 379 } 380 } 381 optr = rc->rc_iptr; 382 /* check foor good data */ 383 if (good_data) { 384 while (ucnt-- > 0) { 385 val = rcin(CD180_RDR); 386 optr[0] = val; 387 optr[INPUT_FLAGS_SHIFT] = 0; 388 optr++; 389 rc_scheduled_event++; 390 if (val != 0 && val == rc->rc_hotchar) 391 setsofttty(); 392 } 393 } else { 394 /* Store also status data */ 395 while (ucnt-- > 0) { 396 iack = rcin(CD180_RCSR); 397 if (iack & RCSR_Timeout) 398 break; 399 if ( (iack & RCSR_OE) 400 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 401 rc->rc_flags |= RC_WAS_SILOVFL; 402 rc_scheduled_event++; 403 } 404 val = rcin(CD180_RDR); 405 /* 406 Don't store PE if IGNPAR and BREAK if IGNBRK, 407 this hack allows "raw" tty optimization 408 works even if IGN* is set. 409 */ 410 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 411 || (!(iack & (RCSR_PE|RCSR_FE)) 412 || !(rc->rc_tp->t_iflag & IGNPAR)) 413 && (!(iack & RCSR_Break) 414 || !(rc->rc_tp->t_iflag & IGNBRK))) { 415 if ( (iack & (RCSR_PE|RCSR_FE)) 416 && (t_state & TS_CAN_BYPASS_L_RINT) 417 && ((iack & RCSR_FE) 418 || (iack & RCSR_PE) 419 && (rc->rc_tp->t_iflag & INPCK))) 420 val = 0; 421 else if (val != 0 && val == rc->rc_hotchar) 422 setsofttty(); 423 optr[0] = val; 424 optr[INPUT_FLAGS_SHIFT] = iack; 425 optr++; 426 rc_scheduled_event++; 427 } 428 } 429 } 430 rc->rc_iptr = optr; 431 rc->rc_flags |= RC_DORXFER; 432 } else 433 resid = ucnt; 434 /* Clear FIFO if necessary */ 435 while (resid-- > 0) { 436 if (!good_data) 437 iack = rcin(CD180_RCSR); 438 else 439 iack = 0; 440 if (iack & RCSR_Timeout) 441 break; 442 (void) rcin(CD180_RDR); 443 } 444 goto more_intrs; 445 } 446 if (bsr & RC_BSR_MOINT) { 447 iack = rcin(RC_PILR_MODEM); 448 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 449 printf("rc%d: fake moint: %02x\n", unit, iack); 450 goto more_intrs; 451 } 452 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 453 iack = rcin(CD180_MCR); 454 rc->rc_msvr = rcin(CD180_MSVR); 455 rcout(CD180_MCR, 0); 456#ifdef RCDEBUG 457 printrcflags(rc, "moint"); 458#endif 459 if (rc->rc_flags & RC_CTSFLOW) { 460 if (rc->rc_msvr & MSVR_CTS) 461 rc->rc_flags |= RC_SEND_RDY; 462 else 463 rc->rc_flags &= ~RC_SEND_RDY; 464 } else 465 rc->rc_flags |= RC_SEND_RDY; 466 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 467 rc_scheduled_event += LOTS_OF_EVENTS; 468 rc->rc_flags |= RC_MODCHG; 469 setsofttty(); 470 } 471 goto more_intrs; 472 } 473 if (bsr & RC_BSR_TXINT) { 474 iack = rcin(RC_PILR_TX); 475 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 476 printf("rc%d: fake txint: %02x\n", unit, iack); 477 goto more_intrs; 478 } 479 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 480 if ( (rc->rc_flags & RC_OSUSP) 481 || !(rc->rc_flags & RC_SEND_RDY) 482 ) 483 goto more_intrs; 484 /* Handle breaks and other stuff */ 485 if (rc->rc_pendcmd) { 486 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 487 rcout(CD180_TDR, CD180_C_ESC); 488 rcout(CD180_TDR, rc->rc_pendcmd); 489 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 490 rc->rc_pendcmd = 0; 491 goto more_intrs; 492 } 493 optr = rc->rc_optr; 494 resid = rc->rc_obufend - optr; 495 if (resid > CD180_NFIFO) 496 resid = CD180_NFIFO; 497 while (resid-- > 0) 498 rcout(CD180_TDR, *optr++); 499 rc->rc_optr = optr; 500 501 /* output completed? */ 502 if (optr >= rc->rc_obufend) { 503 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 504#ifdef RCDEBUG 505 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 506#endif 507 if (!(rc->rc_flags & RC_DOXXFER)) { 508 rc_scheduled_event += LOTS_OF_EVENTS; 509 rc->rc_flags |= RC_DOXXFER; 510 setsofttty(); 511 } 512 } 513 } 514 more_intrs: 515 rcout(CD180_EOIR, 0); /* end of interrupt */ 516 rcout(RC_CTOUT, 0); 517 bsr = ~(rcin(RC_BSR)); 518 } 519} 520 521/* Feed characters to output buffer */ 522static void rc_start(tp) 523register struct tty *tp; 524{ 525 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 526 register int nec = rc->rc_rcb->rcb_addr, s; 527 528 if (rc->rc_flags & RC_OSBUSY) 529 return; 530 s = spltty(); 531 rc->rc_flags |= RC_OSBUSY; 532 disable_intr(); 533 if (tp->t_state & TS_TTSTOP) 534 rc->rc_flags |= RC_OSUSP; 535 else 536 rc->rc_flags &= ~RC_OSUSP; 537 /* Do RTS flow control stuff */ 538 if ( (rc->rc_flags & RC_RTSFLOW) 539 && (tp->t_state & TS_TBLOCK) 540 && (rc->rc_msvr & MSVR_RTS) 541 ) { 542 rcout(CD180_CAR, rc->rc_chan); 543 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 544 } else if (!(rc->rc_msvr & MSVR_RTS)) { 545 rcout(CD180_CAR, rc->rc_chan); 546 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 547 } 548 enable_intr(); 549 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 550 goto out; 551#ifdef RCDEBUG 552 printrcflags(rc, "rcstart"); 553#endif 554 ttwwakeup(tp); 555#ifdef RCDEBUG 556 printf("rcstart: outq = %d obuf = %d\n", 557 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 558#endif 559 if (tp->t_state & TS_BUSY) 560 goto out; /* output still in progress ... */ 561 562 if (tp->t_outq.c_cc > 0) { 563 u_int ocnt; 564 565 tp->t_state |= TS_BUSY; 566 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 567 disable_intr(); 568 rc->rc_optr = rc->rc_obuf; 569 rc->rc_obufend = rc->rc_optr + ocnt; 570 enable_intr(); 571 if (!(rc->rc_ier & IER_TxRdy)) { 572#ifdef RCDEBUG 573 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 574#endif 575 rcout(CD180_CAR, rc->rc_chan); 576 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 577 } 578 } 579out: 580 rc->rc_flags &= ~RC_OSBUSY; 581 (void) splx(s); 582} 583 584/* Handle delayed events. */ 585void rcpoll() 586{ 587 register struct rc_chans *rc; 588 register struct rc_softc *rcb; 589 register u_char *tptr, *eptr; 590 register int s; 591 register struct tty *tp; 592 register int chan, icnt, c, nec, unit; 593 594 if (rc_scheduled_event == 0) 595 return; 596repeat: 597 for (unit = 0; unit < NRC; unit++) { 598 rcb = &rc_softc[unit]; 599 rc = rcb->rcb_baserc; 600 nec = rc->rc_rcb->rcb_addr; 601 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 602 tp = rc->rc_tp; 603#ifdef RCDEBUG 604 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 605 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 606 printrcflags(rc, "rcevent"); 607#endif 608 if (rc->rc_flags & RC_WAS_BUFOVFL) { 609 disable_intr(); 610 rc->rc_flags &= ~RC_WAS_BUFOVFL; 611 rc_scheduled_event--; 612 enable_intr(); 613 printf("rc%d/%d: interrupt-level buffer overflow\n", 614 unit, chan); 615 } 616 if (rc->rc_flags & RC_WAS_SILOVFL) { 617 disable_intr(); 618 rc->rc_flags &= ~RC_WAS_SILOVFL; 619 rc_scheduled_event--; 620 enable_intr(); 621 printf("rc%d/%d: silo overflow\n", 622 unit, chan); 623 } 624 if (rc->rc_flags & RC_MODCHG) { 625 disable_intr(); 626 rc->rc_flags &= ~RC_MODCHG; 627 rc_scheduled_event -= LOTS_OF_EVENTS; 628 enable_intr(); 629 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 630 } 631 if (rc->rc_flags & RC_DORXFER) { 632 disable_intr(); 633 rc->rc_flags &= ~RC_DORXFER; 634 eptr = rc->rc_iptr; 635 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 636 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 637 else 638 tptr = rc->rc_ibuf; 639 icnt = eptr - tptr; 640 if (icnt > 0) { 641 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 642 rc->rc_iptr = rc->rc_ibuf; 643 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 644 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 645 } else { 646 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 647 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 648 rc->rc_hiwat = 649 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 650 } 651 if ( (rc->rc_flags & RC_RTSFLOW) 652 && (tp->t_state & TS_ISOPEN) 653 && !(tp->t_state & TS_TBLOCK) 654 && !(rc->rc_msvr & MSVR_RTS) 655 ) { 656 rcout(CD180_CAR, chan); 657 rcout(CD180_MSVR, 658 rc->rc_msvr |= MSVR_RTS); 659 } 660 rc_scheduled_event -= icnt; 661 } 662 enable_intr(); 663 664 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 665 goto done1; 666 667 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 668 && !(tp->t_state & TS_LOCAL)) { 669 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 670 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 671 && !(tp->t_state & TS_TBLOCK)) 672 ttyblock(tp); 673 tk_nin += icnt; 674 tk_rawcc += icnt; 675 tp->t_rawcc += icnt; 676 if (b_to_q(tptr, icnt, &tp->t_rawq)) 677 printf("rc%d/%d: tty-level buffer overflow\n", 678 unit, chan); 679 ttwakeup(tp); 680 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 681 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 682 tp->t_state &= ~TS_TTSTOP; 683 tp->t_lflag &= ~FLUSHO; 684 rc_start(tp); 685 } 686 } else { 687 for (; tptr < eptr; tptr++) 688 (*linesw[tp->t_line].l_rint) 689 (tptr[0] | 690 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 691 } 692done1: 693 } 694 if (rc->rc_flags & RC_DOXXFER) { 695 disable_intr(); 696 rc_scheduled_event -= LOTS_OF_EVENTS; 697 rc->rc_flags &= ~RC_DOXXFER; 698 rc->rc_tp->t_state &= ~TS_BUSY; 699 enable_intr(); 700 (*linesw[tp->t_line].l_start)(tp); 701 } 702 } 703 if (rc_scheduled_event == 0) 704 break; 705 } 706 if (rc_scheduled_event >= LOTS_OF_EVENTS) 707 goto repeat; 708} 709 710void rcstop(tp, rw) 711 register struct tty *tp; 712 int rw; 713{ 714 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 715 u_char *tptr, *eptr; 716 717#ifdef RCDEBUG 718 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 719 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 720#endif 721 if (rw & FWRITE) 722 rc_discard_output(rc); 723 disable_intr(); 724 if (rw & FREAD) { 725 rc->rc_flags &= ~RC_DORXFER; 726 eptr = rc->rc_iptr; 727 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 728 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 729 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 730 } else { 731 tptr = rc->rc_ibuf; 732 rc->rc_iptr = rc->rc_ibuf; 733 } 734 rc_scheduled_event -= eptr - tptr; 735 } 736 if (tp->t_state & TS_TTSTOP) 737 rc->rc_flags |= RC_OSUSP; 738 else 739 rc->rc_flags &= ~RC_OSUSP; 740 enable_intr(); 741} 742 743int rcopen(dev, flag, mode, p) 744 dev_t dev; 745 int flag, mode; 746 struct proc *p; 747{ 748 register struct rc_chans *rc; 749 register struct tty *tp; 750 int unit, nec, s, error = 0; 751 752 unit = GET_UNIT(dev); 753 if (unit >= NRC * CD180_NCHAN) 754 return ENXIO; 755 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 756 return ENXIO; 757 rc = &rc_chans[unit]; 758 tp = rc->rc_tp; 759 nec = rc->rc_rcb->rcb_addr; 760#ifdef RCDEBUG 761 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 762#endif 763 s = spltty(); 764 765again: 766 while (rc->rc_flags & RC_DTR_OFF) { 767 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 768 if (error != 0) 769 goto out; 770 } 771 if (tp->t_state & TS_ISOPEN) { 772 if (CALLOUT(dev)) { 773 if (!(rc->rc_flags & RC_ACTOUT)) { 774 error = EBUSY; 775 goto out; 776 } 777 } else { 778 if (rc->rc_flags & RC_ACTOUT) { 779 if (flag & O_NONBLOCK) { 780 error = EBUSY; 781 goto out; 782 } 783 if (error = tsleep(&rc->rc_rcb, 784 TTIPRI|PCATCH, "rcbi", 0)) 785 goto out; 786 goto again; 787 } 788 } 789 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 790 error = EBUSY; 791 goto out; 792 } 793 } else { 794 tp->t_oproc = rc_start; 795 tp->t_param = rc_param; 796 tp->t_dev = dev; 797 798 if (CALLOUT(dev)) 799 tp->t_cflag |= CLOCAL; 800 else 801 tp->t_cflag &= ~CLOCAL; 802 803 error = rc_param(tp, &tp->t_termios); 804 if (error) 805 goto out; 806 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 807 808 ttsetwater(tp); 809 810 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 811 (*linesw[tp->t_line].l_modem)(tp, 1); 812 } 813 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 814 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 815 rc->rc_dcdwaits++; 816 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 817 rc->rc_dcdwaits--; 818 if (error != 0) 819 goto out; 820 goto again; 821 } 822 error = (*linesw[tp->t_line].l_open)(dev, tp); 823 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 824 rc->rc_flags |= RC_ACTOUT; 825out: 826 (void) splx(s); 827 828 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 829 rc_hardclose(rc); 830 831 return error; 832} 833 834int rcclose(dev, flag, mode, p) 835 dev_t dev; 836 int flag, mode; 837 struct proc *p; 838{ 839 register struct rc_chans *rc; 840 register struct tty *tp; 841 int s, unit = GET_UNIT(dev); 842 843 if (unit >= NRC * CD180_NCHAN) 844 return ENXIO; 845 rc = &rc_chans[unit]; 846 tp = rc->rc_tp; 847#ifdef RCDEBUG 848 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 849#endif 850 s = spltty(); 851 (*linesw[tp->t_line].l_close)(tp, flag); 852 rcstop(tp, FREAD | FWRITE); 853 rc_hardclose(rc); 854 ttyclose(tp); 855 splx(s); 856 return 0; 857} 858 859static void rc_hardclose(rc) 860register struct rc_chans *rc; 861{ 862 register int s, nec = rc->rc_rcb->rcb_addr; 863 register struct tty *tp = rc->rc_tp; 864 865 s = spltty(); 866 rcout(CD180_CAR, rc->rc_chan); 867 868 /* Disable rx/tx intrs */ 869 rcout(CD180_IER, rc->rc_ier = 0); 870 if ( (tp->t_cflag & HUPCL) 871 || !(rc->rc_flags & RC_ACTOUT) 872 && !(rc->rc_msvr & MSVR_CD) 873 && !(tp->t_cflag & CLOCAL) 874 || !(tp->t_state & TS_ISOPEN) 875 ) { 876 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 877 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 878 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 879 if (rc->rc_dtrwait) { 880 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 881 rc->rc_flags |= RC_DTR_OFF; 882 } 883 } 884 rc->rc_flags &= ~RC_ACTOUT; 885 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 886 wakeup(TSA_CARR_ON(tp)); 887 (void) splx(s); 888} 889 890/* Read from line */ 891int rcread(dev, uio, flag) 892 dev_t dev; 893 struct uio *uio; 894 int flag; 895{ 896 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 897 898 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 899} 900 901/* Write to line */ 902int rcwrite(dev, uio, flag) 903 dev_t dev; 904 struct uio *uio; 905 int flag; 906{ 907 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 908 909 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 910} 911 912/* Reset the bastard */ 913static void rc_hwreset(unit, nec, chipid) 914 register int unit, nec; 915 unsigned int chipid; 916{ 917 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 918 DELAY(20000); 919 WAITFORCCR(unit, -1); 920 921 rcout(RC_CTOUT, 0); /* Clear timeout */ 922 rcout(CD180_GIVR, chipid); 923 rcout(CD180_GICR, 0); 924 925 /* Set Prescaler Registers (1 msec) */ 926 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 927 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 928 929 /* Initialize Priority Interrupt Level Registers */ 930 rcout(CD180_PILR1, RC_PILR_MODEM); 931 rcout(CD180_PILR2, RC_PILR_TX); 932 rcout(CD180_PILR3, RC_PILR_RX); 933 934 /* Reset DTR */ 935 rcout(RC_DTREG, ~0); 936} 937 938/* Set channel parameters */ 939static int rc_param(tp, ts) 940 register struct tty *tp; 941 struct termios *ts; 942{ 943 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 944 register int nec = rc->rc_rcb->rcb_addr; 945 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 946 947 odivs = ttspeedtab(ts->c_ospeed, rc_speedtab); 948 if (ts->c_ispeed == 0) 949 ts->c_ispeed = ts->c_ospeed; 950 idivs = ttspeedtab(ts->c_ispeed, rc_speedtab); 951 if (idivs < 0 || odivs < 0) 952 return (EINVAL); 953 954 s = spltty(); 955 956 /* Select channel */ 957 rcout(CD180_CAR, rc->rc_chan); 958 959 /* If speed == 0, hangup line */ 960 if (ts->c_ospeed == 0) { 961 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 962 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 963 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 964 } 965 966 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 967 cflag = ts->c_cflag; 968 iflag = ts->c_iflag; 969 lflag = ts->c_lflag; 970 971 if (idivs > 0) { 972 rcout(CD180_RBPRL, idivs & 0xFF); 973 rcout(CD180_RBPRH, idivs >> 8); 974 } 975 if (odivs > 0) { 976 rcout(CD180_TBPRL, odivs & 0xFF); 977 rcout(CD180_TBPRH, odivs >> 8); 978 } 979 980 /* set timeout value */ 981 if (ts->c_ispeed > 0) { 982 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 983 984 if ( !(lflag & ICANON) 985 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 986 && ts->c_cc[VTIME] * 10 > itm) 987 itm = ts->c_cc[VTIME] * 10; 988 989 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 990 } 991 992 switch (cflag & CSIZE) { 993 case CS5: val = COR1_5BITS; break; 994 case CS6: val = COR1_6BITS; break; 995 case CS7: val = COR1_7BITS; break; 996 default: 997 case CS8: val = COR1_8BITS; break; 998 } 999 if (cflag & PARENB) { 1000 val |= COR1_NORMPAR; 1001 if (cflag & PARODD) 1002 val |= COR1_ODDP; 1003 if (!(cflag & INPCK)) 1004 val |= COR1_Ignore; 1005 } else 1006 val |= COR1_Ignore; 1007 if (cflag & CSTOPB) 1008 val |= COR1_2SB; 1009 rcout(CD180_COR1, val); 1010 1011 /* Set FIFO threshold */ 1012 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1013 inpflow = 0; 1014 if ( (iflag & IXOFF) 1015 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1016 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1017 || (iflag & IXANY) 1018 ) 1019 ) 1020 ) { 1021 inpflow = 1; 1022 val |= COR3_SCDE|COR3_FCT; 1023 } 1024 rcout(CD180_COR3, val); 1025 1026 /* Initialize on-chip automatic flow control */ 1027 val = 0; 1028 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1029 if (cflag & CCTS_OFLOW) { 1030 rc->rc_flags |= RC_CTSFLOW; 1031 val |= COR2_CtsAE; 1032 } else 1033 rc->rc_flags |= RC_SEND_RDY; 1034 if (tp->t_state & TS_TTSTOP) 1035 rc->rc_flags |= RC_OSUSP; 1036 else 1037 rc->rc_flags &= ~RC_OSUSP; 1038 if (cflag & CRTS_IFLOW) 1039 rc->rc_flags |= RC_RTSFLOW; 1040 else 1041 rc->rc_flags &= ~RC_RTSFLOW; 1042 1043 if (inpflow) { 1044 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1045 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1046 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1047 val |= COR2_TxIBE; 1048 if (iflag & IXANY) 1049 val |= COR2_IXM; 1050 } 1051 1052 rcout(CD180_COR2, rc->rc_cor2 = val); 1053 1054 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1055 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1056 1057 disc_optim(tp, ts, rc); 1058 1059 /* modem ctl */ 1060 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1061 if (cflag & CCTS_OFLOW) 1062 val |= MCOR1_CTSzd; 1063 rcout(CD180_MCOR1, val); 1064 1065 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1066 if (cflag & CCTS_OFLOW) 1067 val |= MCOR2_CTSod; 1068 rcout(CD180_MCOR2, val); 1069 1070 /* enable i/o and interrupts */ 1071 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1072 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1073 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1074 1075 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1076 if (cflag & CCTS_OFLOW) 1077 rc->rc_ier |= IER_CTS; 1078 if (cflag & CREAD) 1079 rc->rc_ier |= IER_RxData; 1080 if (tp->t_state & TS_BUSY) 1081 rc->rc_ier |= IER_TxRdy; 1082 if (ts->c_ospeed != 0) 1083 rc_modctl(rc, TIOCM_DTR, DMBIS); 1084 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1085 rc->rc_flags |= RC_SEND_RDY; 1086 rcout(CD180_IER, rc->rc_ier); 1087 (void) splx(s); 1088 return 0; 1089} 1090 1091/* Re-initialize board after bogus interrupts */ 1092static void rc_reinit(rcb) 1093struct rc_softc *rcb; 1094{ 1095 register struct rc_chans *rc, *rce; 1096 register int i, nec; 1097 1098 nec = rcb->rcb_addr; 1099 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1100 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1101 rce = rc + CD180_NCHAN; 1102 for (; rc < rce; rc++) 1103 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1104} 1105 1106int rcioctl(dev, cmd, data, flag, p) 1107dev_t dev; 1108int cmd, flag; 1109caddr_t data; 1110struct proc *p; 1111{ 1112 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1113 register int s, error; 1114 struct tty *tp = rc->rc_tp; 1115 1116 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1117 if (error >= 0) 1118 return (error); 1119 error = ttioctl(tp, cmd, data, flag); 1120 if (error >= 0) 1121 return (error); 1122 s = spltty(); 1123 1124 switch (cmd) { 1125 case TIOCSBRK: 1126 rc->rc_pendcmd = CD180_C_SBRK; 1127 break; 1128 1129 case TIOCCBRK: 1130 rc->rc_pendcmd = CD180_C_EBRK; 1131 break; 1132 1133 case TIOCSDTR: 1134 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1135 break; 1136 1137 case TIOCCDTR: 1138 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1139 break; 1140 1141 case TIOCMGET: 1142 *(int *) data = rc_modctl(rc, 0, DMGET); 1143 break; 1144 1145 case TIOCMSET: 1146 (void) rc_modctl(rc, *(int *) data, DMSET); 1147 break; 1148 1149 case TIOCMBIC: 1150 (void) rc_modctl(rc, *(int *) data, DMBIC); 1151 break; 1152 1153 case TIOCMBIS: 1154 (void) rc_modctl(rc, *(int *) data, DMBIS); 1155 break; 1156 1157 case TIOCMSDTRWAIT: 1158 error = suser(p->p_ucred, &p->p_acflag); 1159 if (error != 0) { 1160 splx(s); 1161 return (error); 1162 } 1163 rc->rc_dtrwait = *(int *)data * hz / 100; 1164 break; 1165 1166 case TIOCMGDTRWAIT: 1167 *(int *)data = rc->rc_dtrwait * 100 / hz; 1168 break; 1169 1170 default: 1171 (void) splx(s); 1172 return ENOTTY; 1173 } 1174 (void) splx(s); 1175 return 0; 1176} 1177 1178 1179/* Modem control routines */ 1180 1181static int rc_modctl(rc, bits, cmd) 1182register struct rc_chans *rc; 1183int bits, cmd; 1184{ 1185 register int nec = rc->rc_rcb->rcb_addr; 1186 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1187 1188 rcout(CD180_CAR, rc->rc_chan); 1189 1190 switch (cmd) { 1191 case DMSET: 1192 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1193 ~(*dtr |= 1 << rc->rc_chan) : 1194 ~(*dtr &= ~(1 << rc->rc_chan))); 1195 msvr = rcin(CD180_MSVR); 1196 if (bits & TIOCM_RTS) 1197 msvr |= MSVR_RTS; 1198 else 1199 msvr &= ~MSVR_RTS; 1200 if (bits & TIOCM_DTR) 1201 msvr |= MSVR_DTR; 1202 else 1203 msvr &= ~MSVR_DTR; 1204 rcout(CD180_MSVR, msvr); 1205 break; 1206 1207 case DMBIS: 1208 if (bits & TIOCM_DTR) 1209 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1210 msvr = rcin(CD180_MSVR); 1211 if (bits & TIOCM_RTS) 1212 msvr |= MSVR_RTS; 1213 if (bits & TIOCM_DTR) 1214 msvr |= MSVR_DTR; 1215 rcout(CD180_MSVR, msvr); 1216 break; 1217 1218 case DMGET: 1219 bits = TIOCM_LE; 1220 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1221 1222 if (msvr & MSVR_RTS) 1223 bits |= TIOCM_RTS; 1224 if (msvr & MSVR_CTS) 1225 bits |= TIOCM_CTS; 1226 if (msvr & MSVR_DSR) 1227 bits |= TIOCM_DSR; 1228 if (msvr & MSVR_DTR) 1229 bits |= TIOCM_DTR; 1230 if (msvr & MSVR_CD) 1231 bits |= TIOCM_CD; 1232 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1233 bits |= TIOCM_RI; 1234 return bits; 1235 1236 case DMBIC: 1237 if (bits & TIOCM_DTR) 1238 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1239 msvr = rcin(CD180_MSVR); 1240 if (bits & TIOCM_RTS) 1241 msvr &= ~MSVR_RTS; 1242 if (bits & TIOCM_DTR) 1243 msvr &= ~MSVR_DTR; 1244 rcout(CD180_MSVR, msvr); 1245 break; 1246 } 1247 rc->rc_msvr = rcin(CD180_MSVR); 1248 return 0; 1249} 1250 1251/* Test the board. */ 1252int rc_test(nec, unit) 1253 register int nec; 1254 int unit; 1255{ 1256 int chan = 0, nopt = 0; 1257 int i = 0, rcnt, old_level; 1258 unsigned int iack, chipid; 1259 unsigned short divs; 1260 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1261#define CTLEN 8 1262#define ERR(s) { \ 1263 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1264 (void) splx(old_level); return 1; } 1265 1266 struct rtest { 1267 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1268 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1269 int rxptr; /* RX pointer */ 1270 int txptr; /* TX pointer */ 1271 } tchans[CD180_NCHAN]; 1272 1273 old_level = spltty(); 1274 1275 chipid = RC_FAKEID; 1276 1277 /* First, reset board to inital state */ 1278 rc_hwreset(unit, nec, chipid); 1279 1280 divs = RC_BRD(19200); 1281 1282 /* Initialize channels */ 1283 for (chan = 0; chan < CD180_NCHAN; chan++) { 1284 1285 /* Select and reset channel */ 1286 rcout(CD180_CAR, chan); 1287 CCRCMD(unit, chan, CCR_ResetChan); 1288 WAITFORCCR(unit, chan); 1289 1290 /* Set speed */ 1291 rcout(CD180_RBPRL, divs & 0xFF); 1292 rcout(CD180_RBPRH, divs >> 8); 1293 rcout(CD180_TBPRL, divs & 0xFF); 1294 rcout(CD180_TBPRH, divs >> 8); 1295 1296 /* set timeout value */ 1297 rcout(CD180_RTPR, 0); 1298 1299 /* Establish local loopback */ 1300 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1301 rcout(CD180_COR2, COR2_LLM); 1302 rcout(CD180_COR3, CD180_NFIFO); 1303 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1304 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1305 WAITFORCCR(unit, chan); 1306 rcout(CD180_MSVR, MSVR_RTS); 1307 1308 /* Fill TXBUF with test data */ 1309 for (i = 0; i < CD180_NFIFO; i++) { 1310 tchans[chan].txbuf[i] = ctest[i]; 1311 tchans[chan].rxbuf[i] = 0; 1312 } 1313 tchans[chan].txptr = tchans[chan].rxptr = 0; 1314 1315 /* Now, start transmit */ 1316 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1317 } 1318 /* Pseudo-interrupt poll stuff */ 1319 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1320 i = ~(rcin(RC_BSR)); 1321 if (i & RC_BSR_TOUT) 1322 ERR(("BSR timeout bit set\n")) 1323 else if (i & RC_BSR_TXINT) { 1324 iack = rcin(RC_PILR_TX); 1325 if (iack != (GIVR_IT_TDI | chipid)) 1326 ERR(("Bad TX intr ack (%02x != %02x)\n", 1327 iack, GIVR_IT_TDI | chipid)); 1328 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1329 /* If no more data to transmit, disable TX intr */ 1330 if (tchans[chan].txptr >= CD180_NFIFO) { 1331 iack = rcin(CD180_IER); 1332 rcout(CD180_IER, iack & ~IER_TxMpty); 1333 } else { 1334 for (iack = tchans[chan].txptr; 1335 iack < CD180_NFIFO; iack++) 1336 rcout(CD180_TDR, 1337 tchans[chan].txbuf[iack]); 1338 tchans[chan].txptr = iack; 1339 } 1340 rcout(CD180_EOIR, 0); 1341 } else if (i & RC_BSR_RXINT) { 1342 u_char ucnt; 1343 1344 iack = rcin(RC_PILR_RX); 1345 if (iack != (GIVR_IT_RGDI | chipid) && 1346 iack != (GIVR_IT_REI | chipid)) 1347 ERR(("Bad RX intr ack (%02x != %02x)\n", 1348 iack, GIVR_IT_RGDI | chipid)) 1349 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1350 ucnt = rcin(CD180_RDCR) & 0xF; 1351 while (ucnt-- > 0) { 1352 iack = rcin(CD180_RCSR); 1353 if (iack & RCSR_Timeout) 1354 break; 1355 if (iack & 0xF) 1356 ERR(("Bad char chan %d (RCSR = %02X)\n", 1357 chan, iack)) 1358 if (tchans[chan].rxptr > CD180_NFIFO) 1359 ERR(("Got extra chars chan %d\n", 1360 chan)) 1361 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1362 rcin(CD180_RDR); 1363 } 1364 rcout(CD180_EOIR, 0); 1365 } 1366 rcout(RC_CTOUT, 0); 1367 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1368 if (tchans[chan].rxptr >= CD180_NFIFO) 1369 iack++; 1370 if (iack == CD180_NCHAN) 1371 break; 1372 } 1373 for (chan = 0; chan < CD180_NCHAN; chan++) { 1374 /* Select and reset channel */ 1375 rcout(CD180_CAR, chan); 1376 CCRCMD(unit, chan, CCR_ResetChan); 1377 } 1378 1379 if (!rcnt) 1380 ERR(("looses characters during local loopback\n")) 1381 /* Now, check data */ 1382 for (chan = 0; chan < CD180_NCHAN; chan++) 1383 for (i = 0; i < CD180_NFIFO; i++) 1384 if (ctest[i] != tchans[chan].rxbuf[i]) 1385 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1386 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1387 (void) splx(old_level); 1388 return 0; 1389} 1390 1391#ifdef RCDEBUG 1392static void printrcflags(rc, comment) 1393struct rc_chans *rc; 1394char *comment; 1395{ 1396 u_short f = rc->rc_flags; 1397 register int nec = rc->rc_rcb->rcb_addr; 1398 1399 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1400 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1401 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1402 (f & RC_ACTOUT) ?"ACTOUT " :"", 1403 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1404 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1405 (f & RC_DORXFER)?"DORXFER " :"", 1406 (f & RC_DOXXFER)?"DOXXFER " :"", 1407 (f & RC_MODCHG) ?"MODCHG " :"", 1408 (f & RC_OSUSP) ?"OSUSP " :"", 1409 (f & RC_OSBUSY) ?"OSBUSY " :"", 1410 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1411 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1412 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1413 1414 rcout(CD180_CAR, rc->rc_chan); 1415 1416 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1417 rc->rc_rcb->rcb_unit, rc->rc_chan, 1418 rcin(CD180_MSVR), 1419 rcin(CD180_IER), 1420 rcin(CD180_CCSR)); 1421} 1422#endif /* RCDEBUG */ 1423 1424struct tty * 1425rcdevtotty(dev) 1426 dev_t dev; 1427{ 1428 int unit; 1429 1430 unit = GET_UNIT(dev); 1431 if (unit >= NRC * CD180_NCHAN) 1432 return NULL; 1433 return (&rc_tty[unit]); 1434} 1435 1436static void 1437rc_dtrwakeup(chan) 1438 void *chan; 1439{ 1440 struct rc_chans *rc; 1441 1442 rc = (struct rc_chans *)chan; 1443 rc->rc_flags &= ~RC_DTR_OFF; 1444 wakeup(&rc->rc_dtrwait); 1445} 1446 1447static void 1448rc_discard_output(rc) 1449 struct rc_chans *rc; 1450{ 1451 disable_intr(); 1452 if (rc->rc_flags & RC_DOXXFER) { 1453 rc_scheduled_event -= LOTS_OF_EVENTS; 1454 rc->rc_flags &= ~RC_DOXXFER; 1455 } 1456 rc->rc_optr = rc->rc_obufend; 1457 rc->rc_tp->t_state &= ~TS_BUSY; 1458 enable_intr(); 1459 ttwwakeup(rc->rc_tp); 1460} 1461 1462static void 1463rc_wakeup(chan) 1464 void *chan; 1465{ 1466 int unit; 1467 1468 timeout(rc_wakeup, (caddr_t)NULL, 1); 1469 1470 if (rc_scheduled_event != 0) { 1471 int s; 1472 1473 s = splsofttty(); 1474 rcpoll(); 1475 splx(s); 1476 } 1477} 1478 1479static void 1480disc_optim(tp, t, rc) 1481 struct tty *tp; 1482 struct termios *t; 1483 struct rc_chans *rc; 1484{ 1485 1486 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1487 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1488 && (!(t->c_iflag & PARMRK) 1489 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1490 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1491 && linesw[tp->t_line].l_rint == ttyinput) 1492 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1493 else 1494 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1495 if (tp->t_line == SLIPDISC) 1496 rc->rc_hotchar = 0xc0; 1497 else if (tp->t_line == PPPDISC) 1498 rc->rc_hotchar = 0x7e; 1499 else 1500 rc->rc_hotchar = 0; 1501} 1502 1503static void 1504rc_wait0(nec, unit, chan, line) 1505 int nec, unit, chan, line; 1506{ 1507 int rcnt; 1508 1509 for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--) 1510 DELAY(15); 1511 if (rcnt == 0) 1512 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1513 unit, chan, line); 1514} 1515#endif /* NRC */ 1516