rc.c revision 27125
18471Sache/* 28471Sache * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 38471Sache * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 48471Sache * All rights reserved. 58471Sache * 68471Sache * Redistribution and use in source and binary forms, with or without 78471Sache * modification, are permitted provided that the following conditions 88471Sache * are met: 98471Sache * 1. Redistributions of source code must retain the above copyright 108471Sache * notice, this list of conditions and the following disclaimer. 118471Sache * 2. Redistributions in binary form must reproduce the above copyright 128471Sache * notice, this list of conditions and the following disclaimer in the 138471Sache * documentation and/or other materials provided with the distribution. 148471Sache * 158471Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 168471Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 178471Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 188471Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 198471Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 208471Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 218471Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 228471Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 238471Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 248471Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 258471Sache * SUCH DAMAGE. 268471Sache */ 278471Sache 288471Sache/* 298471Sache * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 308471Sache * 318471Sache */ 328471Sache 3319123Spst#include "opt_comconsole.h" 348471Sache#include "rc.h" 3519123Spst 368471Sache#if NRC > 0 378471Sache 389232Sache/*#define RCDEBUG*/ 398471Sache 408471Sache#include <sys/param.h> 418471Sache#include <sys/systm.h> 428471Sache#include <sys/tty.h> 438471Sache#include <sys/proc.h> 448471Sache#include <sys/conf.h> 458471Sache#include <sys/dkstat.h> 4624131Sbde#include <sys/fcntl.h> 478471Sache#include <sys/uio.h> 488471Sache#include <sys/kernel.h> 498471Sache#include <sys/syslog.h> 5012675Sjulian#ifdef DEVFS 5112675Sjulian#include <sys/devfsext.h> 5212675Sjulian#endif /*DEVFS*/ 538471Sache 548471Sache#include <machine/clock.h> 558471Sache 568471Sache#include <i386/isa/isa_device.h> 578471Sache#include <i386/isa/sioreg.h> 588471Sache 598471Sache#include <i386/isa/ic/cd180.h> 608471Sache#include <i386/isa/rcreg.h> 618471Sache 6212502Sjulian 638471Sache/* Prototypes */ 6412724Sphkstatic int rcprobe __P((struct isa_device *)); 6512724Sphkstatic int rcattach __P((struct isa_device *)); 668471Sache 6712071Sbde/*- 6812071Sbde * This space intentionally left blank to stop __LINE__ from screwing up 6912071Sbde * regression tests :-(. 7012071Sbde * 7112071Sbde * 7212080Sbde * 7312071Sbde */ 748471Sachevoid rcpoll __P((void)); 758471Sache 768471Sache#define rcin(port) RC_IN (nec, port) 778471Sache#define rcout(port,v) RC_OUT (nec, port, v) 788471Sache 799232Sache#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 809232Sache#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 818471Sache 829232Sache#define RC_IBUFSIZE 256 839232Sache#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 849232Sache#define RC_OBUFSIZE 512 858471Sache#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 868471Sache#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 878471Sache#define LOTS_OF_EVENTS 64 888471Sache 898471Sache#define RC_FAKEID 0x10 908471Sache 919232Sache#define RC_PROBED 1 929232Sache#define RC_ATTACHED 2 939232Sache 948471Sache#define GET_UNIT(dev) (minor(dev) & 0x3F) 958471Sache#define CALLOUT(dev) (minor(dev) & 0x80) 968471Sache 978471Sache/* For isa routines */ 988471Sachestruct isa_driver rcdriver = { 998471Sache rcprobe, rcattach, "rc" 1008471Sache}; 1018471Sache 10212675Sjulianstatic d_open_t rcopen; 10312675Sjulianstatic d_close_t rcclose; 10412675Sjulianstatic d_read_t rcread; 10512675Sjulianstatic d_write_t rcwrite; 10612675Sjulianstatic d_ioctl_t rcioctl; 10712675Sjulianstatic d_stop_t rcstop; 10812731Sbdestatic d_devtotty_t rcdevtotty; 10912675Sjulian 11012675Sjulian#define CDEV_MAJOR 63 11112678Sphkstatic struct cdevsw rc_cdevsw = 11212675Sjulian { rcopen, rcclose, rcread, rcwrite, /*63*/ 11312743Sbde rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 11412675Sjulian ttselect, nommap, NULL, "rc", NULL, -1 }; 11512675Sjulian 1168471Sache/* Per-board structure */ 1178471Sachestatic struct rc_softc { 1189232Sache u_int rcb_probed; /* 1 - probed, 2 - attached */ 1198471Sache u_int rcb_addr; /* Base I/O addr */ 1208471Sache u_int rcb_unit; /* unit # */ 1218471Sache u_char rcb_dtr; /* DTR status */ 1228471Sache struct rc_chans *rcb_baserc; /* base rc ptr */ 1238471Sache} rc_softc[NRC]; 1248471Sache 1258471Sache/* Per-channel structure */ 1268471Sachestatic struct rc_chans { 1278471Sache struct rc_softc *rc_rcb; /* back ptr */ 1288471Sache u_short rc_flags; /* Misc. flags */ 1298471Sache int rc_chan; /* Channel # */ 1308471Sache u_char rc_ier; /* intr. enable reg */ 1318471Sache u_char rc_msvr; /* modem sig. status */ 1328471Sache u_char rc_cor2; /* options reg */ 1338471Sache u_char rc_pendcmd; /* special cmd pending */ 1348471Sache u_int rc_dtrwait; /* dtr timeout */ 1358471Sache u_int rc_dcdwaits; /* how many waits DCD in open */ 1368471Sache u_char rc_hotchar; /* end packed optimize */ 1378471Sache struct tty *rc_tp; /* tty struct */ 1388471Sache u_char *rc_iptr; /* Chars input buffer */ 1398471Sache u_char *rc_hiwat; /* hi-water mark */ 1408471Sache u_char *rc_bufend; /* end of buffer */ 1418471Sache u_char *rc_optr; /* ptr in output buf */ 1428471Sache u_char *rc_obufend; /* end of output buf */ 1438471Sache u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 1448471Sache u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 14512675Sjulian#ifdef DEVFS 14612675Sjulian void *devfs_token; 14712675Sjulian#endif 1488471Sache} rc_chans[NRC * CD180_NCHAN]; 1498471Sache 1508471Sachestatic int rc_scheduled_event = 0; 1518471Sache 1528471Sache/* for pstat -t */ 15312724Sphkstatic struct tty rc_tty[NRC * CD180_NCHAN]; 15416322Sgpalmerstatic const int nrc_tty = NRC * CD180_NCHAN; 1558471Sache 1568471Sache/* Flags */ 1579232Sache#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 1589232Sache#define RC_ACTOUT 0x0002 /* Dial-out port active */ 1599232Sache#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 1609232Sache#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 1619232Sache#define RC_DORXFER 0x0010 /* RXFER event planned */ 1629232Sache#define RC_DOXXFER 0x0020 /* XXFER event planned */ 1639232Sache#define RC_MODCHG 0x0040 /* Modem status changed */ 1649232Sache#define RC_OSUSP 0x0080 /* Output suspended */ 1659232Sache#define RC_OSBUSY 0x0100 /* start() routine in progress */ 1669232Sache#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 1679232Sache#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 1689232Sache#define RC_SEND_RDY 0x0800 /* ready to send */ 1698471Sache 1708471Sache/* Table for translation of RCSR status bits to internal form */ 1718471Sachestatic int rc_rcsrt[16] = { 1728471Sache 0, TTY_OE, TTY_FE, 1738471Sache TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 1748471Sache TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 1758471Sache TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 1768471Sache TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 1778471Sache TTY_BI|TTY_PE|TTY_FE|TTY_OE 1788471Sache}; 1798471Sache 1808471Sache/* Static prototypes */ 1819232Sachestatic void rc_hwreset __P((int, int, unsigned int)); 1828471Sachestatic int rc_test __P((int, int)); 1838471Sachestatic void rc_discard_output __P((struct rc_chans *)); 1848471Sachestatic void rc_hardclose __P((struct rc_chans *)); 1858471Sachestatic int rc_modctl __P((struct rc_chans *, int, int)); 1868471Sachestatic void rc_start __P((struct tty *)); 1878471Sachestatic int rc_param __P((struct tty *, struct termios *)); 1889232Sachestatic void rc_reinit __P((struct rc_softc *)); 1899232Sache#ifdef RCDEBUG 1909232Sachestatic void printrcflags(); 1919232Sache#endif 1928471Sachestatic timeout_t rc_dtrwakeup; 1938471Sachestatic timeout_t rc_wakeup; 1948471Sachestatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 1959232Sachestatic void rc_wait0 __P((int nec, int unit, int chan, int line)); 1968471Sache 1978471Sache/**********************************************/ 1988471Sache 1998471Sache/* Quick device probing */ 20012724Sphkstatic int 20112724Sphkrcprobe(dvp) 2028471Sache struct isa_device *dvp; 2038471Sache{ 2048471Sache int irq = ffs(dvp->id_irq) - 1; 2058471Sache register int nec = dvp->id_iobase; 2068471Sache 2078471Sache if (dvp->id_unit > NRC) 2088471Sache return 0; 2098471Sache if (!RC_VALIDADDR(nec)) { 2108471Sache printf("rc%d: illegal base address %x\n", nec); 2118471Sache return 0; 2128471Sache } 2138471Sache if (!RC_VALIDIRQ(irq)) { 2148471Sache printf("rc%d: illegal IRQ value %d\n", irq); 2158471Sache return 0; 2168471Sache } 2178471Sache rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 2188471Sache rcout(CD180_PPRH, 0x11); 2198471Sache if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 2208471Sache return 0; 2218471Sache /* Now, test the board more thoroughly, with diagnostic */ 2228471Sache if (rc_test(nec, dvp->id_unit)) 2238471Sache return 0; 2249232Sache rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 2259232Sache 2269232Sache return 0xF; 2278471Sache} 2288471Sache 22912724Sphkstatic int 23012724Sphkrcattach(dvp) 2318471Sache struct isa_device *dvp; 2328471Sache{ 23316322Sgpalmer register int chan, nec = dvp->id_iobase; 2348471Sache struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 2358471Sache struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 2368471Sache static int rc_wakeup_started = 0; 2379232Sache struct tty *tp; 2388471Sache 2398471Sache /* Thorooughly test the device */ 2409232Sache if (rcb->rcb_probed != RC_PROBED) 2418471Sache return 0; 2428471Sache rcb->rcb_addr = nec; 2438471Sache rcb->rcb_dtr = 0; 2448471Sache rcb->rcb_baserc = rc; 2458471Sache /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 2468471Sache printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 2478471Sache CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 2488471Sache 2498471Sache for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 2508471Sache rc->rc_rcb = rcb; 2518471Sache rc->rc_chan = chan; 2528471Sache rc->rc_iptr = rc->rc_ibuf; 2538471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 2548471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 2558471Sache rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 2568471Sache rc->rc_cor2 = rc->rc_pendcmd = 0; 2578471Sache rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 2588471Sache rc->rc_dtrwait = 3 * hz; 2598471Sache rc->rc_dcdwaits= 0; 2608471Sache rc->rc_hotchar = 0; 2619232Sache tp = rc->rc_tp = &rc_tty[chan]; 2629232Sache ttychars(tp); 2639232Sache tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 2649232Sache tp->t_cflag = TTYDEF_CFLAG; 2659232Sache tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 26612675Sjulian#ifdef DEVFS 26712675Sjulian/* FIX THIS to reflect real devices */ 26814873Sscrappy rc->devfs_token = 26914873Sscrappy devfs_add_devswf(&rc_cdevsw, 27014873Sscrappy (dvp->id_unit * CD180_NCHAN) + chan, 27114873Sscrappy DV_CHR, 0, 0, 0600, "rc%d.%d", 27214873Sscrappy dvp->id_unit, chan); 27312675Sjulian#endif 2748471Sache } 2759232Sache rcb->rcb_probed = RC_ATTACHED; 2768471Sache if (!rc_wakeup_started) { 2778471Sache rc_wakeup((void *)NULL); 2788471Sache rc_wakeup_started = 0; 2798471Sache } 2808471Sache return 1; 2818471Sache} 2828471Sache 2838471Sache/* RC interrupt handling */ 2848471Sachevoid rcintr(unit) 2858471Sache int unit; 2868471Sache{ 2878471Sache register struct rc_softc *rcb = &rc_softc[unit]; 2888471Sache register struct rc_chans *rc; 2899232Sache register int nec, resid; 2909232Sache register u_char val, iack, bsr, ucnt, *optr; 2919232Sache int good_data, t_state; 2928471Sache 2939232Sache if (rcb->rcb_probed != RC_ATTACHED) { 2949232Sache printf("rc%d: bogus interrupt\n", unit); 2959232Sache return; 2969232Sache } 2978471Sache nec = rcb->rcb_addr; 2988471Sache 2998471Sache bsr = ~(rcin(RC_BSR)); 3008471Sache 3019232Sache if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 3029232Sache printf("rc%d: extra interrupt\n", unit); 3039232Sache rcout(CD180_EOIR, 0); 3049232Sache return; 3059232Sache } 3069232Sache 3079232Sache while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 3089232Sache#ifdef RCDEBUG_DETAILED 3099232Sache printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 3109232Sache (bsr & RC_BSR_TOUT)?"TOUT ":"", 3119232Sache (bsr & RC_BSR_RXINT)?"RXINT ":"", 3129232Sache (bsr & RC_BSR_TXINT)?"TXINT ":"", 3139232Sache (bsr & RC_BSR_MOINT)?"MOINT":""); 3148471Sache#endif 3159232Sache if (bsr & RC_BSR_TOUT) { 3169232Sache printf("rc%d: hardware failure, reset board\n", unit); 3179232Sache rcout(RC_CTOUT, 0); 3189232Sache rc_reinit(rcb); 3199232Sache return; 3208471Sache } 3219232Sache if (bsr & RC_BSR_RXINT) { 3229232Sache iack = rcin(RC_PILR_RX); 3239232Sache good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 3249232Sache if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 3259232Sache printf("rc%d: fake rxint: %02x\n", unit, iack); 3269232Sache goto more_intrs; 3279232Sache } 3289232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 3299232Sache t_state = rc->rc_tp->t_state; 3309232Sache /* Do RTS flow control stuff */ 3319232Sache if ( (rc->rc_flags & RC_RTSFLOW) 3329232Sache || !(t_state & TS_ISOPEN) 3339232Sache ) { 3349232Sache if ( ( !(t_state & TS_ISOPEN) 3359232Sache || (t_state & TS_TBLOCK) 3369232Sache ) 3379232Sache && (rc->rc_msvr & MSVR_RTS) 3389232Sache ) 3399232Sache rcout(CD180_MSVR, 3409232Sache rc->rc_msvr &= ~MSVR_RTS); 3419232Sache else if (!(rc->rc_msvr & MSVR_RTS)) 3429232Sache rcout(CD180_MSVR, 3439232Sache rc->rc_msvr |= MSVR_RTS); 3449232Sache } 3459232Sache ucnt = rcin(CD180_RDCR) & 0xF; 3469232Sache resid = 0; 3478471Sache 3489232Sache if (t_state & TS_ISOPEN) { 3499232Sache /* check for input buffer overflow */ 3509232Sache if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 3519232Sache resid = ucnt; 3529232Sache ucnt = rc->rc_bufend - rc->rc_iptr; 3539232Sache resid -= ucnt; 3549232Sache if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 3559232Sache rc->rc_flags |= RC_WAS_BUFOVFL; 3569232Sache rc_scheduled_event++; 3579232Sache } 3588471Sache } 3599232Sache optr = rc->rc_iptr; 3609232Sache /* check foor good data */ 3619232Sache if (good_data) { 3629232Sache while (ucnt-- > 0) { 3639232Sache val = rcin(CD180_RDR); 3649232Sache optr[0] = val; 3659232Sache optr[INPUT_FLAGS_SHIFT] = 0; 3669232Sache optr++; 3678471Sache rc_scheduled_event++; 3689232Sache if (val != 0 && val == rc->rc_hotchar) 3698471Sache setsofttty(); 3708471Sache } 3719232Sache } else { 3729232Sache /* Store also status data */ 3739232Sache while (ucnt-- > 0) { 3749232Sache iack = rcin(CD180_RCSR); 3759232Sache if (iack & RCSR_Timeout) 3769232Sache break; 3779232Sache if ( (iack & RCSR_OE) 3789232Sache && !(rc->rc_flags & RC_WAS_SILOVFL)) { 3799232Sache rc->rc_flags |= RC_WAS_SILOVFL; 3809232Sache rc_scheduled_event++; 3819232Sache } 3829232Sache val = rcin(CD180_RDR); 3839232Sache /* 3849232Sache Don't store PE if IGNPAR and BREAK if IGNBRK, 3859232Sache this hack allows "raw" tty optimization 3869232Sache works even if IGN* is set. 3879232Sache */ 3889232Sache if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 3899232Sache || (!(iack & (RCSR_PE|RCSR_FE)) 3909232Sache || !(rc->rc_tp->t_iflag & IGNPAR)) 3919232Sache && (!(iack & RCSR_Break) 3929232Sache || !(rc->rc_tp->t_iflag & IGNBRK))) { 3939232Sache if ( (iack & (RCSR_PE|RCSR_FE)) 3949232Sache && (t_state & TS_CAN_BYPASS_L_RINT) 3959232Sache && ((iack & RCSR_FE) 3969232Sache || (iack & RCSR_PE) 3979232Sache && (rc->rc_tp->t_iflag & INPCK))) 3989232Sache val = 0; 3999232Sache else if (val != 0 && val == rc->rc_hotchar) 4009232Sache setsofttty(); 4019232Sache optr[0] = val; 4029232Sache optr[INPUT_FLAGS_SHIFT] = iack; 4039232Sache optr++; 4049232Sache rc_scheduled_event++; 4059232Sache } 4069232Sache } 4078471Sache } 4089232Sache rc->rc_iptr = optr; 4099232Sache rc->rc_flags |= RC_DORXFER; 4109232Sache } else 4119232Sache resid = ucnt; 4129232Sache /* Clear FIFO if necessary */ 4139232Sache while (resid-- > 0) { 4149232Sache if (!good_data) 4159232Sache iack = rcin(CD180_RCSR); 4169232Sache else 4179232Sache iack = 0; 4189232Sache if (iack & RCSR_Timeout) 4199232Sache break; 4209232Sache (void) rcin(CD180_RDR); 4218471Sache } 4229232Sache goto more_intrs; 4238471Sache } 4249232Sache if (bsr & RC_BSR_MOINT) { 4259232Sache iack = rcin(RC_PILR_MODEM); 4269232Sache if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 4279232Sache printf("rc%d: fake moint: %02x\n", unit, iack); 4289232Sache goto more_intrs; 4299232Sache } 4309232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4319232Sache iack = rcin(CD180_MCR); 4329232Sache rc->rc_msvr = rcin(CD180_MSVR); 4339232Sache rcout(CD180_MCR, 0); 4348471Sache#ifdef RCDEBUG 4359232Sache printrcflags(rc, "moint"); 4368471Sache#endif 4379232Sache if (rc->rc_flags & RC_CTSFLOW) { 4389232Sache if (rc->rc_msvr & MSVR_CTS) 4399232Sache rc->rc_flags |= RC_SEND_RDY; 4409232Sache else 4419232Sache rc->rc_flags &= ~RC_SEND_RDY; 4429232Sache } else 4438471Sache rc->rc_flags |= RC_SEND_RDY; 4449232Sache if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 4459232Sache rc_scheduled_event += LOTS_OF_EVENTS; 4469232Sache rc->rc_flags |= RC_MODCHG; 4479232Sache setsofttty(); 4489232Sache } 4499232Sache goto more_intrs; 4508471Sache } 4519232Sache if (bsr & RC_BSR_TXINT) { 4529232Sache iack = rcin(RC_PILR_TX); 4539232Sache if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 4549232Sache printf("rc%d: fake txint: %02x\n", unit, iack); 4559232Sache goto more_intrs; 4569232Sache } 4579232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4589232Sache if ( (rc->rc_flags & RC_OSUSP) 4599232Sache || !(rc->rc_flags & RC_SEND_RDY) 4609232Sache ) 4619232Sache goto more_intrs; 4629232Sache /* Handle breaks and other stuff */ 4639232Sache if (rc->rc_pendcmd) { 4649232Sache rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 4659232Sache rcout(CD180_TDR, CD180_C_ESC); 4669232Sache rcout(CD180_TDR, rc->rc_pendcmd); 4679232Sache rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 4689232Sache rc->rc_pendcmd = 0; 4699232Sache goto more_intrs; 4709232Sache } 4719232Sache optr = rc->rc_optr; 4729232Sache resid = rc->rc_obufend - optr; 4739232Sache if (resid > CD180_NFIFO) 4749232Sache resid = CD180_NFIFO; 4759232Sache while (resid-- > 0) 4769232Sache rcout(CD180_TDR, *optr++); 4779232Sache rc->rc_optr = optr; 4788471Sache 4799232Sache /* output completed? */ 4809232Sache if (optr >= rc->rc_obufend) { 4819232Sache rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 4828471Sache#ifdef RCDEBUG 4839232Sache printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 4848471Sache#endif 4859232Sache if (!(rc->rc_flags & RC_DOXXFER)) { 4869232Sache rc_scheduled_event += LOTS_OF_EVENTS; 4879232Sache rc->rc_flags |= RC_DOXXFER; 4889232Sache setsofttty(); 4899232Sache } 4909232Sache } 4918471Sache } 4929232Sache more_intrs: 4939232Sache rcout(CD180_EOIR, 0); /* end of interrupt */ 4949232Sache rcout(RC_CTOUT, 0); 4959232Sache bsr = ~(rcin(RC_BSR)); 4968471Sache } 4978471Sache} 4988471Sache 4998471Sache/* Feed characters to output buffer */ 5008471Sachestatic void rc_start(tp) 5018471Sacheregister struct tty *tp; 5028471Sache{ 5038471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 5048471Sache register int nec = rc->rc_rcb->rcb_addr, s; 5058471Sache 5068471Sache if (rc->rc_flags & RC_OSBUSY) 5078471Sache return; 5088471Sache s = spltty(); 5098471Sache rc->rc_flags |= RC_OSBUSY; 5108471Sache disable_intr(); 5118471Sache if (tp->t_state & TS_TTSTOP) 5128471Sache rc->rc_flags |= RC_OSUSP; 5138471Sache else 5148471Sache rc->rc_flags &= ~RC_OSUSP; 5158471Sache /* Do RTS flow control stuff */ 5169232Sache if ( (rc->rc_flags & RC_RTSFLOW) 5179232Sache && (tp->t_state & TS_TBLOCK) 5189232Sache && (rc->rc_msvr & MSVR_RTS) 5199232Sache ) { 5209232Sache rcout(CD180_CAR, rc->rc_chan); 5219232Sache rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 5229232Sache } else if (!(rc->rc_msvr & MSVR_RTS)) { 5239232Sache rcout(CD180_CAR, rc->rc_chan); 5249232Sache rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 5258471Sache } 5268471Sache enable_intr(); 5278471Sache if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 5288471Sache goto out; 5298471Sache#ifdef RCDEBUG 5308471Sache printrcflags(rc, "rcstart"); 5318471Sache#endif 5329626Sbde ttwwakeup(tp); 5338471Sache#ifdef RCDEBUG 5349232Sache printf("rcstart: outq = %d obuf = %d\n", 5358471Sache tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 5368471Sache#endif 5379232Sache if (tp->t_state & TS_BUSY) 5388471Sache goto out; /* output still in progress ... */ 5398471Sache 5408471Sache if (tp->t_outq.c_cc > 0) { 5418471Sache u_int ocnt; 5428471Sache 5438471Sache tp->t_state |= TS_BUSY; 5448471Sache ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 5458471Sache disable_intr(); 5468471Sache rc->rc_optr = rc->rc_obuf; 5479232Sache rc->rc_obufend = rc->rc_optr + ocnt; 5488471Sache enable_intr(); 5499232Sache if (!(rc->rc_ier & IER_TxRdy)) { 5508471Sache#ifdef RCDEBUG 5519232Sache printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 5528471Sache#endif 5538471Sache rcout(CD180_CAR, rc->rc_chan); 5549232Sache rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 5558471Sache } 5568471Sache } 5578471Sacheout: 5588471Sache rc->rc_flags &= ~RC_OSBUSY; 5598471Sache (void) splx(s); 5608471Sache} 5618471Sache 5628471Sache/* Handle delayed events. */ 5638471Sachevoid rcpoll() 5648471Sache{ 5658471Sache register struct rc_chans *rc; 5668471Sache register struct rc_softc *rcb; 5678471Sache register u_char *tptr, *eptr; 5688471Sache register struct tty *tp; 56916322Sgpalmer register int chan, icnt, nec, unit; 5708471Sache 5718471Sache if (rc_scheduled_event == 0) 5728471Sache return; 5738471Sacherepeat: 5748471Sache for (unit = 0; unit < NRC; unit++) { 5758471Sache rcb = &rc_softc[unit]; 5768471Sache rc = rcb->rcb_baserc; 5778471Sache nec = rc->rc_rcb->rcb_addr; 5788471Sache for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 5798471Sache tp = rc->rc_tp; 5808471Sache#ifdef RCDEBUG 5818471Sache if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 5828471Sache RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 5838471Sache printrcflags(rc, "rcevent"); 5848471Sache#endif 5858471Sache if (rc->rc_flags & RC_WAS_BUFOVFL) { 5869232Sache disable_intr(); 5878471Sache rc->rc_flags &= ~RC_WAS_BUFOVFL; 5888471Sache rc_scheduled_event--; 5899232Sache enable_intr(); 5908471Sache printf("rc%d/%d: interrupt-level buffer overflow\n", 5918471Sache unit, chan); 5928471Sache } 5938471Sache if (rc->rc_flags & RC_WAS_SILOVFL) { 5949232Sache disable_intr(); 5958471Sache rc->rc_flags &= ~RC_WAS_SILOVFL; 5968471Sache rc_scheduled_event--; 5979232Sache enable_intr(); 5988471Sache printf("rc%d/%d: silo overflow\n", 5998471Sache unit, chan); 6008471Sache } 6018471Sache if (rc->rc_flags & RC_MODCHG) { 6029232Sache disable_intr(); 6038471Sache rc->rc_flags &= ~RC_MODCHG; 6048471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 6059232Sache enable_intr(); 6069232Sache (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 6078471Sache } 6088471Sache if (rc->rc_flags & RC_DORXFER) { 6099232Sache disable_intr(); 6108471Sache rc->rc_flags &= ~RC_DORXFER; 6118471Sache eptr = rc->rc_iptr; 6128471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 6138471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6148471Sache else 6158471Sache tptr = rc->rc_ibuf; 6168471Sache icnt = eptr - tptr; 6178471Sache if (icnt > 0) { 6188471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 6198471Sache rc->rc_iptr = rc->rc_ibuf; 6208471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 6218471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 6228471Sache } else { 6238471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6248471Sache rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 6258471Sache rc->rc_hiwat = 6268471Sache &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 6278471Sache } 6289232Sache if ( (rc->rc_flags & RC_RTSFLOW) 6299232Sache && (tp->t_state & TS_ISOPEN) 6309232Sache && !(tp->t_state & TS_TBLOCK) 6318471Sache && !(rc->rc_msvr & MSVR_RTS) 6329232Sache ) { 6338471Sache rcout(CD180_CAR, chan); 6348471Sache rcout(CD180_MSVR, 6358471Sache rc->rc_msvr |= MSVR_RTS); 6368471Sache } 6378471Sache rc_scheduled_event -= icnt; 6388471Sache } 6398471Sache enable_intr(); 6408471Sache 6419232Sache if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 6428471Sache goto done1; 6438471Sache 6448471Sache if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 6458471Sache && !(tp->t_state & TS_LOCAL)) { 6469822Sbde if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 6479822Sbde && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 6489822Sbde && !(tp->t_state & TS_TBLOCK)) 6499822Sbde ttyblock(tp); 6508471Sache tk_nin += icnt; 6518471Sache tk_rawcc += icnt; 6528471Sache tp->t_rawcc += icnt; 6538471Sache if (b_to_q(tptr, icnt, &tp->t_rawq)) 6548471Sache printf("rc%d/%d: tty-level buffer overflow\n", 6558471Sache unit, chan); 6568471Sache ttwakeup(tp); 6578471Sache if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 6588471Sache || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 6598471Sache tp->t_state &= ~TS_TTSTOP; 6608471Sache tp->t_lflag &= ~FLUSHO; 6619754Sbde rc_start(tp); 6628471Sache } 6638471Sache } else { 6648471Sache for (; tptr < eptr; tptr++) 6658471Sache (*linesw[tp->t_line].l_rint) 6668471Sache (tptr[0] | 6678471Sache rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 6688471Sache } 66927125Sbdedone1: ; 6708471Sache } 6718471Sache if (rc->rc_flags & RC_DOXXFER) { 6729232Sache disable_intr(); 6739232Sache rc_scheduled_event -= LOTS_OF_EVENTS; 6749232Sache rc->rc_flags &= ~RC_DOXXFER; 6759232Sache rc->rc_tp->t_state &= ~TS_BUSY; 6769232Sache enable_intr(); 6778471Sache (*linesw[tp->t_line].l_start)(tp); 6788471Sache } 6798471Sache } 6808471Sache if (rc_scheduled_event == 0) 6818471Sache break; 6828471Sache } 6838471Sache if (rc_scheduled_event >= LOTS_OF_EVENTS) 6848471Sache goto repeat; 6858471Sache} 6868471Sache 68712675Sjulianstatic void 68812675Sjulianrcstop(tp, rw) 6898471Sache register struct tty *tp; 6908471Sache int rw; 6918471Sache{ 6928471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 6938471Sache u_char *tptr, *eptr; 6948471Sache 6958471Sache#ifdef RCDEBUG 6969232Sache printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 6978471Sache (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 6988471Sache#endif 6998471Sache if (rw & FWRITE) 7008471Sache rc_discard_output(rc); 7018471Sache disable_intr(); 7028471Sache if (rw & FREAD) { 7039232Sache rc->rc_flags &= ~RC_DORXFER; 7048471Sache eptr = rc->rc_iptr; 7058471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 7068471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7078471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7088471Sache } else { 7098471Sache tptr = rc->rc_ibuf; 7108471Sache rc->rc_iptr = rc->rc_ibuf; 7118471Sache } 7128471Sache rc_scheduled_event -= eptr - tptr; 7138471Sache } 7148471Sache if (tp->t_state & TS_TTSTOP) 7158471Sache rc->rc_flags |= RC_OSUSP; 7168471Sache else 7178471Sache rc->rc_flags &= ~RC_OSUSP; 7188471Sache enable_intr(); 7198471Sache} 7208471Sache 72112675Sjulianstatic int 72212675Sjulianrcopen(dev, flag, mode, p) 7238471Sache dev_t dev; 7248471Sache int flag, mode; 7258471Sache struct proc *p; 7268471Sache{ 7278471Sache register struct rc_chans *rc; 7288471Sache register struct tty *tp; 7298471Sache int unit, nec, s, error = 0; 7308471Sache 7318471Sache unit = GET_UNIT(dev); 7328471Sache if (unit >= NRC * CD180_NCHAN) 7338471Sache return ENXIO; 7349232Sache if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 7359232Sache return ENXIO; 7368471Sache rc = &rc_chans[unit]; 7379232Sache tp = rc->rc_tp; 7388471Sache nec = rc->rc_rcb->rcb_addr; 7398471Sache#ifdef RCDEBUG 7409232Sache printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 7418471Sache#endif 7428471Sache s = spltty(); 7438471Sache 7448471Sacheagain: 7458471Sache while (rc->rc_flags & RC_DTR_OFF) { 7469232Sache error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 7478471Sache if (error != 0) 7488471Sache goto out; 7498471Sache } 7508471Sache if (tp->t_state & TS_ISOPEN) { 7518471Sache if (CALLOUT(dev)) { 7528471Sache if (!(rc->rc_flags & RC_ACTOUT)) { 7538471Sache error = EBUSY; 7548471Sache goto out; 7558471Sache } 7568471Sache } else { 7578471Sache if (rc->rc_flags & RC_ACTOUT) { 7588471Sache if (flag & O_NONBLOCK) { 7598471Sache error = EBUSY; 7608471Sache goto out; 7618471Sache } 7628471Sache if (error = tsleep(&rc->rc_rcb, 7638471Sache TTIPRI|PCATCH, "rcbi", 0)) 7648471Sache goto out; 7658471Sache goto again; 7668471Sache } 7678471Sache } 7688471Sache if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 7698471Sache error = EBUSY; 7708471Sache goto out; 7718471Sache } 7728471Sache } else { 7738471Sache tp->t_oproc = rc_start; 7748471Sache tp->t_param = rc_param; 7758471Sache tp->t_dev = dev; 7768471Sache 7778471Sache if (CALLOUT(dev)) 7788471Sache tp->t_cflag |= CLOCAL; 7798471Sache else 7808471Sache tp->t_cflag &= ~CLOCAL; 7818471Sache 7828471Sache error = rc_param(tp, &tp->t_termios); 7838471Sache if (error) 7848471Sache goto out; 7859232Sache (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 7868471Sache 7878471Sache ttsetwater(tp); 7888471Sache 7898471Sache if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 7908471Sache (*linesw[tp->t_line].l_modem)(tp, 1); 7918471Sache } 7928471Sache if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 7938471Sache && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 7948471Sache rc->rc_dcdwaits++; 7959639Sbde error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 7968471Sache rc->rc_dcdwaits--; 7978471Sache if (error != 0) 7988471Sache goto out; 7998471Sache goto again; 8008471Sache } 8018471Sache error = (*linesw[tp->t_line].l_open)(dev, tp); 80213074Sache disc_optim(tp, &tp->t_termios, rc); 8038471Sache if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 8048471Sache rc->rc_flags |= RC_ACTOUT; 8058471Sacheout: 8068471Sache (void) splx(s); 8078471Sache 8088471Sache if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 8098471Sache rc_hardclose(rc); 8108471Sache 8118471Sache return error; 8128471Sache} 8138471Sache 81412675Sjulianstatic int 81512675Sjulianrcclose(dev, flag, mode, p) 8168471Sache dev_t dev; 8178471Sache int flag, mode; 8188471Sache struct proc *p; 8198471Sache{ 8208471Sache register struct rc_chans *rc; 8218471Sache register struct tty *tp; 8228471Sache int s, unit = GET_UNIT(dev); 8238471Sache 8248471Sache if (unit >= NRC * CD180_NCHAN) 8258471Sache return ENXIO; 8268471Sache rc = &rc_chans[unit]; 8278471Sache tp = rc->rc_tp; 8289232Sache#ifdef RCDEBUG 8299232Sache printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 8309232Sache#endif 8318471Sache s = spltty(); 8328471Sache (*linesw[tp->t_line].l_close)(tp, flag); 83313074Sache disc_optim(tp, &tp->t_termios, rc); 8348471Sache rcstop(tp, FREAD | FWRITE); 8358471Sache rc_hardclose(rc); 8368471Sache ttyclose(tp); 8378471Sache splx(s); 8388471Sache return 0; 8398471Sache} 8408471Sache 8418471Sachestatic void rc_hardclose(rc) 8428471Sacheregister struct rc_chans *rc; 8438471Sache{ 8448471Sache register int s, nec = rc->rc_rcb->rcb_addr; 8458471Sache register struct tty *tp = rc->rc_tp; 8468471Sache 8478471Sache s = spltty(); 8488471Sache rcout(CD180_CAR, rc->rc_chan); 8498471Sache 8509232Sache /* Disable rx/tx intrs */ 8518471Sache rcout(CD180_IER, rc->rc_ier = 0); 8529232Sache if ( (tp->t_cflag & HUPCL) 8538471Sache || !(rc->rc_flags & RC_ACTOUT) 8548471Sache && !(rc->rc_msvr & MSVR_CD) 8558471Sache && !(tp->t_cflag & CLOCAL) 8569232Sache || !(tp->t_state & TS_ISOPEN) 8579232Sache ) { 8589232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 8599232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 8608471Sache (void) rc_modctl(rc, TIOCM_RTS, DMSET); 8618471Sache if (rc->rc_dtrwait) { 8628471Sache timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 8638471Sache rc->rc_flags |= RC_DTR_OFF; 8648471Sache } 8658471Sache } 8668471Sache rc->rc_flags &= ~RC_ACTOUT; 8678471Sache wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 8689639Sbde wakeup(TSA_CARR_ON(tp)); 8698471Sache (void) splx(s); 8708471Sache} 8718471Sache 8728471Sache/* Read from line */ 87312675Sjulianstatic int 87412675Sjulianrcread(dev, uio, flag) 8758471Sache dev_t dev; 8768471Sache struct uio *uio; 8778471Sache int flag; 8788471Sache{ 8798471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 8809232Sache 8818471Sache return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 8828471Sache} 8838471Sache 8848471Sache/* Write to line */ 88512675Sjulianstatic int 88612675Sjulianrcwrite(dev, uio, flag) 8878471Sache dev_t dev; 8888471Sache struct uio *uio; 8898471Sache int flag; 8908471Sache{ 8918471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 8929232Sache 8938471Sache return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 8948471Sache} 8958471Sache 8968471Sache/* Reset the bastard */ 8979232Sachestatic void rc_hwreset(unit, nec, chipid) 8989232Sache register int unit, nec; 8998471Sache unsigned int chipid; 9008471Sache{ 9019232Sache CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 9028471Sache DELAY(20000); 9039232Sache WAITFORCCR(unit, -1); 9049232Sache 9059232Sache rcout(RC_CTOUT, 0); /* Clear timeout */ 9068471Sache rcout(CD180_GIVR, chipid); 9078471Sache rcout(CD180_GICR, 0); 9088471Sache 9098471Sache /* Set Prescaler Registers (1 msec) */ 9109232Sache rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 9119232Sache rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 9128471Sache 9138471Sache /* Initialize Priority Interrupt Level Registers */ 9148471Sache rcout(CD180_PILR1, RC_PILR_MODEM); 9158471Sache rcout(CD180_PILR2, RC_PILR_TX); 9168471Sache rcout(CD180_PILR3, RC_PILR_RX); 9178471Sache 9188471Sache /* Reset DTR */ 9199232Sache rcout(RC_DTREG, ~0); 9208471Sache} 9218471Sache 9228471Sache/* Set channel parameters */ 9238471Sachestatic int rc_param(tp, ts) 9248471Sache register struct tty *tp; 9258471Sache struct termios *ts; 9268471Sache{ 9279232Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 9288471Sache register int nec = rc->rc_rcb->rcb_addr; 9299232Sache int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 9308471Sache 9319855Sache if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 9329855Sache || ts->c_ispeed < 0 || ts->c_ispeed > 76800 9339855Sache ) 9349855Sache return (EINVAL); 9358471Sache if (ts->c_ispeed == 0) 9368471Sache ts->c_ispeed = ts->c_ospeed; 9379855Sache odivs = RC_BRD(ts->c_ospeed); 9389855Sache idivs = RC_BRD(ts->c_ispeed); 9398471Sache 9408471Sache s = spltty(); 9418471Sache 9429232Sache /* Select channel */ 9439232Sache rcout(CD180_CAR, rc->rc_chan); 9449232Sache 9458471Sache /* If speed == 0, hangup line */ 9469232Sache if (ts->c_ospeed == 0) { 9479232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 9489232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 9499232Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 9509232Sache } 9518471Sache 9528471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 9538471Sache cflag = ts->c_cflag; 9548471Sache iflag = ts->c_iflag; 9558471Sache lflag = ts->c_lflag; 9568471Sache 9578471Sache if (idivs > 0) { 9588471Sache rcout(CD180_RBPRL, idivs & 0xFF); 9598471Sache rcout(CD180_RBPRH, idivs >> 8); 9608471Sache } 9618471Sache if (odivs > 0) { 9628471Sache rcout(CD180_TBPRL, odivs & 0xFF); 9638471Sache rcout(CD180_TBPRH, odivs >> 8); 9648471Sache } 9658471Sache 9668471Sache /* set timeout value */ 9679232Sache if (ts->c_ispeed > 0) { 9689232Sache int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 9698471Sache 9709232Sache if ( !(lflag & ICANON) 9719232Sache && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 9729232Sache && ts->c_cc[VTIME] * 10 > itm) 9739232Sache itm = ts->c_cc[VTIME] * 10; 9749232Sache 9759232Sache rcout(CD180_RTPR, itm <= 255 ? itm : 255); 9769232Sache } 9779232Sache 9788471Sache switch (cflag & CSIZE) { 9798471Sache case CS5: val = COR1_5BITS; break; 9808471Sache case CS6: val = COR1_6BITS; break; 9818471Sache case CS7: val = COR1_7BITS; break; 9828471Sache default: 9838471Sache case CS8: val = COR1_8BITS; break; 9848471Sache } 9858471Sache if (cflag & PARENB) { 9868471Sache val |= COR1_NORMPAR; 9878471Sache if (cflag & PARODD) 9888471Sache val |= COR1_ODDP; 9899232Sache if (!(cflag & INPCK)) 9909232Sache val |= COR1_Ignore; 9918471Sache } else 9929232Sache val |= COR1_Ignore; 9938471Sache if (cflag & CSTOPB) 9948471Sache val |= COR1_2SB; 9958471Sache rcout(CD180_COR1, val); 9968471Sache 9978471Sache /* Set FIFO threshold */ 9989232Sache val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 9999232Sache inpflow = 0; 10009232Sache if ( (iflag & IXOFF) 10019232Sache && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 10029232Sache && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 10039232Sache || (iflag & IXANY) 10049232Sache ) 10059232Sache ) 10069232Sache ) { 10079232Sache inpflow = 1; 10089232Sache val |= COR3_SCDE|COR3_FCT; 10099232Sache } 10109232Sache rcout(CD180_COR3, val); 10118471Sache 10128471Sache /* Initialize on-chip automatic flow control */ 10138471Sache val = 0; 10149232Sache rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 10158471Sache if (cflag & CCTS_OFLOW) { 10168471Sache rc->rc_flags |= RC_CTSFLOW; 10179232Sache val |= COR2_CtsAE; 10189232Sache } else 10199232Sache rc->rc_flags |= RC_SEND_RDY; 10209232Sache if (tp->t_state & TS_TTSTOP) 10219232Sache rc->rc_flags |= RC_OSUSP; 10228471Sache else 10239232Sache rc->rc_flags &= ~RC_OSUSP; 10248471Sache if (cflag & CRTS_IFLOW) 10258471Sache rc->rc_flags |= RC_RTSFLOW; 10269232Sache else 10279232Sache rc->rc_flags &= ~RC_RTSFLOW; 10288471Sache 10299232Sache if (inpflow) { 10309232Sache if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 10319232Sache rcout(CD180_SCHR1, ts->c_cc[VSTART]); 10329232Sache rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 10339232Sache val |= COR2_TxIBE; 10349232Sache if (iflag & IXANY) 10359232Sache val |= COR2_IXM; 10368471Sache } 10378471Sache 10389232Sache rcout(CD180_COR2, rc->rc_cor2 = val); 10398471Sache 10409232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10419232Sache CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 10429232Sache 10438471Sache disc_optim(tp, ts, rc); 10448471Sache 10458471Sache /* modem ctl */ 10469232Sache val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 10479232Sache if (cflag & CCTS_OFLOW) 10489232Sache val |= MCOR1_CTSzd; 10499232Sache rcout(CD180_MCOR1, val); 10508471Sache 10519232Sache val = cflag & CLOCAL ? 0 : MCOR2_CDod; 10529232Sache if (cflag & CCTS_OFLOW) 10539232Sache val |= MCOR2_CTSod; 10549232Sache rcout(CD180_MCOR2, val); 10559232Sache 10568471Sache /* enable i/o and interrupts */ 10579232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10589232Sache CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 10599232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 10608471Sache 10619232Sache rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 10629232Sache if (cflag & CCTS_OFLOW) 10639232Sache rc->rc_ier |= IER_CTS; 10649232Sache if (cflag & CREAD) 10659232Sache rc->rc_ier |= IER_RxData; 10669232Sache if (tp->t_state & TS_BUSY) 10679232Sache rc->rc_ier |= IER_TxRdy; 10689232Sache if (ts->c_ospeed != 0) 10699232Sache rc_modctl(rc, TIOCM_DTR, DMBIS); 10709232Sache if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 10719232Sache rc->rc_flags |= RC_SEND_RDY; 10729232Sache rcout(CD180_IER, rc->rc_ier); 10738471Sache (void) splx(s); 10748471Sache return 0; 10758471Sache} 10768471Sache 10779232Sache/* Re-initialize board after bogus interrupts */ 10789232Sachestatic void rc_reinit(rcb) 10799232Sachestruct rc_softc *rcb; 10809232Sache{ 10819232Sache register struct rc_chans *rc, *rce; 108216322Sgpalmer register int nec; 10839232Sache 10849232Sache nec = rcb->rcb_addr; 10859232Sache rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 10869232Sache rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 10879232Sache rce = rc + CD180_NCHAN; 10889232Sache for (; rc < rce; rc++) 10899232Sache (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 10909232Sache} 10919232Sache 109212675Sjulianstatic int 109312675Sjulianrcioctl(dev, cmd, data, flag, p) 10948471Sachedev_t dev; 10958471Sacheint cmd, flag; 10968471Sachecaddr_t data; 10978471Sachestruct proc *p; 10988471Sache{ 10998471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 11008471Sache register int s, error; 11018471Sache struct tty *tp = rc->rc_tp; 11028471Sache 11038471Sache error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 11048471Sache if (error >= 0) 11058471Sache return (error); 11068471Sache error = ttioctl(tp, cmd, data, flag); 110713074Sache disc_optim(tp, &tp->t_termios, rc); 11088471Sache if (error >= 0) 11098471Sache return (error); 11108471Sache s = spltty(); 11118471Sache 11128471Sache switch (cmd) { 11138471Sache case TIOCSBRK: 11148471Sache rc->rc_pendcmd = CD180_C_SBRK; 11158471Sache break; 11168471Sache 11178471Sache case TIOCCBRK: 11188471Sache rc->rc_pendcmd = CD180_C_EBRK; 11198471Sache break; 11208471Sache 11218471Sache case TIOCSDTR: 11229232Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 11238471Sache break; 11248471Sache 11258471Sache case TIOCCDTR: 11268471Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 11278471Sache break; 11288471Sache 11298471Sache case TIOCMGET: 11308471Sache *(int *) data = rc_modctl(rc, 0, DMGET); 11318471Sache break; 11328471Sache 11338471Sache case TIOCMSET: 11348471Sache (void) rc_modctl(rc, *(int *) data, DMSET); 11358471Sache break; 11368471Sache 11378471Sache case TIOCMBIC: 11388471Sache (void) rc_modctl(rc, *(int *) data, DMBIC); 11398471Sache break; 11408471Sache 11418471Sache case TIOCMBIS: 11428471Sache (void) rc_modctl(rc, *(int *) data, DMBIS); 11438471Sache break; 11448471Sache 11458471Sache case TIOCMSDTRWAIT: 11468471Sache error = suser(p->p_ucred, &p->p_acflag); 11478471Sache if (error != 0) { 11488471Sache splx(s); 11498471Sache return (error); 11508471Sache } 11518471Sache rc->rc_dtrwait = *(int *)data * hz / 100; 11528471Sache break; 11538471Sache 11548471Sache case TIOCMGDTRWAIT: 11558471Sache *(int *)data = rc->rc_dtrwait * 100 / hz; 11568471Sache break; 11578471Sache 11588471Sache default: 11598471Sache (void) splx(s); 11608471Sache return ENOTTY; 11618471Sache } 11628471Sache (void) splx(s); 11638471Sache return 0; 11648471Sache} 11658471Sache 11668471Sache 11678471Sache/* Modem control routines */ 11688471Sache 11698471Sachestatic int rc_modctl(rc, bits, cmd) 11708471Sacheregister struct rc_chans *rc; 11718471Sacheint bits, cmd; 11728471Sache{ 11738471Sache register int nec = rc->rc_rcb->rcb_addr; 11749232Sache u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 11758471Sache 11768471Sache rcout(CD180_CAR, rc->rc_chan); 11778471Sache 11788471Sache switch (cmd) { 11798471Sache case DMSET: 11809232Sache rcout(RC_DTREG, (bits & TIOCM_DTR) ? 11819232Sache ~(*dtr |= 1 << rc->rc_chan) : 11829232Sache ~(*dtr &= ~(1 << rc->rc_chan))); 11839232Sache msvr = rcin(CD180_MSVR); 11849232Sache if (bits & TIOCM_RTS) 11859232Sache msvr |= MSVR_RTS; 11869232Sache else 11879232Sache msvr &= ~MSVR_RTS; 11889232Sache if (bits & TIOCM_DTR) 11899232Sache msvr |= MSVR_DTR; 11909232Sache else 11919232Sache msvr &= ~MSVR_DTR; 11929232Sache rcout(CD180_MSVR, msvr); 11939232Sache break; 11948471Sache 11958471Sache case DMBIS: 11969232Sache if (bits & TIOCM_DTR) 11979232Sache rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 11989232Sache msvr = rcin(CD180_MSVR); 11998471Sache if (bits & TIOCM_RTS) 12009232Sache msvr |= MSVR_RTS; 12018471Sache if (bits & TIOCM_DTR) 12029232Sache msvr |= MSVR_DTR; 12039232Sache rcout(CD180_MSVR, msvr); 12048471Sache break; 12058471Sache 12068471Sache case DMGET: 12078471Sache bits = TIOCM_LE; 12089232Sache msvr = rc->rc_msvr = rcin(CD180_MSVR); 12098471Sache 12108471Sache if (msvr & MSVR_RTS) 12118471Sache bits |= TIOCM_RTS; 12128471Sache if (msvr & MSVR_CTS) 12138471Sache bits |= TIOCM_CTS; 12148471Sache if (msvr & MSVR_DSR) 12158471Sache bits |= TIOCM_DSR; 12168471Sache if (msvr & MSVR_DTR) 12178471Sache bits |= TIOCM_DTR; 12189232Sache if (msvr & MSVR_CD) 12199232Sache bits |= TIOCM_CD; 12209232Sache if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 12219232Sache bits |= TIOCM_RI; 12228471Sache return bits; 12238471Sache 12248471Sache case DMBIC: 12258471Sache if (bits & TIOCM_DTR) 12269232Sache rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 12279232Sache msvr = rcin(CD180_MSVR); 12288471Sache if (bits & TIOCM_RTS) 12299232Sache msvr &= ~MSVR_RTS; 12309232Sache if (bits & TIOCM_DTR) 12319232Sache msvr &= ~MSVR_DTR; 12329232Sache rcout(CD180_MSVR, msvr); 12338471Sache break; 12348471Sache } 12359232Sache rc->rc_msvr = rcin(CD180_MSVR); 12368471Sache return 0; 12378471Sache} 12388471Sache 12398471Sache/* Test the board. */ 12408471Sacheint rc_test(nec, unit) 12418471Sache register int nec; 12428471Sache int unit; 12438471Sache{ 124416322Sgpalmer int chan = 0; 12458471Sache int i = 0, rcnt, old_level; 12468471Sache unsigned int iack, chipid; 12478471Sache unsigned short divs; 12488471Sache static u_char ctest[] = "\377\125\252\045\244\0\377"; 12498471Sache#define CTLEN 8 12508471Sache#define ERR(s) { \ 12518471Sache printf("rc%d: ", unit); printf s ; printf("\n"); \ 12528471Sache (void) splx(old_level); return 1; } 12538471Sache 12548471Sache struct rtest { 12558471Sache u_char txbuf[CD180_NFIFO]; /* TX buffer */ 12568471Sache u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 12578471Sache int rxptr; /* RX pointer */ 12588471Sache int txptr; /* TX pointer */ 12598471Sache } tchans[CD180_NCHAN]; 12608471Sache 12619232Sache old_level = spltty(); 12628471Sache 12638471Sache chipid = RC_FAKEID; 12648471Sache 12658471Sache /* First, reset board to inital state */ 12669232Sache rc_hwreset(unit, nec, chipid); 12678471Sache 12689232Sache divs = RC_BRD(19200); 12699232Sache 12708471Sache /* Initialize channels */ 12718471Sache for (chan = 0; chan < CD180_NCHAN; chan++) { 12728471Sache 12738471Sache /* Select and reset channel */ 12748471Sache rcout(CD180_CAR, chan); 12759232Sache CCRCMD(unit, chan, CCR_ResetChan); 12769232Sache WAITFORCCR(unit, chan); 12778471Sache 12788471Sache /* Set speed */ 12798471Sache rcout(CD180_RBPRL, divs & 0xFF); 12808471Sache rcout(CD180_RBPRH, divs >> 8); 12818471Sache rcout(CD180_TBPRL, divs & 0xFF); 12828471Sache rcout(CD180_TBPRH, divs >> 8); 12838471Sache 12848471Sache /* set timeout value */ 12858471Sache rcout(CD180_RTPR, 0); 12868471Sache 12878471Sache /* Establish local loopback */ 12888471Sache rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 12898471Sache rcout(CD180_COR2, COR2_LLM); 12908471Sache rcout(CD180_COR3, CD180_NFIFO); 12919232Sache CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 12929232Sache CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 12939232Sache WAITFORCCR(unit, chan); 12948471Sache rcout(CD180_MSVR, MSVR_RTS); 12958471Sache 12968471Sache /* Fill TXBUF with test data */ 12978471Sache for (i = 0; i < CD180_NFIFO; i++) { 12988471Sache tchans[chan].txbuf[i] = ctest[i]; 12998471Sache tchans[chan].rxbuf[i] = 0; 13008471Sache } 13018471Sache tchans[chan].txptr = tchans[chan].rxptr = 0; 13028471Sache 13038471Sache /* Now, start transmit */ 13049232Sache rcout(CD180_IER, IER_TxMpty|IER_RxData); 13058471Sache } 13068471Sache /* Pseudo-interrupt poll stuff */ 13078471Sache for (rcnt = 10000; rcnt-- > 0; rcnt--) { 13089232Sache i = ~(rcin(RC_BSR)); 13098471Sache if (i & RC_BSR_TOUT) 13108471Sache ERR(("BSR timeout bit set\n")) 13119232Sache else if (i & RC_BSR_TXINT) { 13128471Sache iack = rcin(RC_PILR_TX); 13138471Sache if (iack != (GIVR_IT_TDI | chipid)) 13148471Sache ERR(("Bad TX intr ack (%02x != %02x)\n", 13158471Sache iack, GIVR_IT_TDI | chipid)); 13169232Sache chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13178471Sache /* If no more data to transmit, disable TX intr */ 13188471Sache if (tchans[chan].txptr >= CD180_NFIFO) { 13198471Sache iack = rcin(CD180_IER); 13209232Sache rcout(CD180_IER, iack & ~IER_TxMpty); 13218471Sache } else { 13228471Sache for (iack = tchans[chan].txptr; 13238471Sache iack < CD180_NFIFO; iack++) 13248471Sache rcout(CD180_TDR, 13258471Sache tchans[chan].txbuf[iack]); 13268471Sache tchans[chan].txptr = iack; 13278471Sache } 13289232Sache rcout(CD180_EOIR, 0); 13299232Sache } else if (i & RC_BSR_RXINT) { 13309232Sache u_char ucnt; 13318471Sache 13328471Sache iack = rcin(RC_PILR_RX); 13338471Sache if (iack != (GIVR_IT_RGDI | chipid) && 13348471Sache iack != (GIVR_IT_REI | chipid)) 13358471Sache ERR(("Bad RX intr ack (%02x != %02x)\n", 13368471Sache iack, GIVR_IT_RGDI | chipid)) 13379232Sache chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13388471Sache ucnt = rcin(CD180_RDCR) & 0xF; 13398471Sache while (ucnt-- > 0) { 13408471Sache iack = rcin(CD180_RCSR); 13419232Sache if (iack & RCSR_Timeout) 13428471Sache break; 13438471Sache if (iack & 0xF) 13448471Sache ERR(("Bad char chan %d (RCSR = %02X)\n", 13458471Sache chan, iack)) 13468471Sache if (tchans[chan].rxptr > CD180_NFIFO) 13478471Sache ERR(("Got extra chars chan %d\n", 13488471Sache chan)) 13498471Sache tchans[chan].rxbuf[tchans[chan].rxptr++] = 13508471Sache rcin(CD180_RDR); 13518471Sache } 13528471Sache rcout(CD180_EOIR, 0); 13538471Sache } 13549232Sache rcout(RC_CTOUT, 0); 13558471Sache for (iack = chan = 0; chan < CD180_NCHAN; chan++) 13568471Sache if (tchans[chan].rxptr >= CD180_NFIFO) 13578471Sache iack++; 13588471Sache if (iack == CD180_NCHAN) 13598471Sache break; 13608471Sache } 13619232Sache for (chan = 0; chan < CD180_NCHAN; chan++) { 13629232Sache /* Select and reset channel */ 13639232Sache rcout(CD180_CAR, chan); 13649232Sache CCRCMD(unit, chan, CCR_ResetChan); 13659232Sache } 13669232Sache 13678471Sache if (!rcnt) 13688471Sache ERR(("looses characters during local loopback\n")) 13698471Sache /* Now, check data */ 13708471Sache for (chan = 0; chan < CD180_NCHAN; chan++) 13718471Sache for (i = 0; i < CD180_NFIFO; i++) 13728471Sache if (ctest[i] != tchans[chan].rxbuf[i]) 13738471Sache ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 13748471Sache chan, i, ctest[i], tchans[chan].rxbuf[i])) 13758471Sache (void) splx(old_level); 13768471Sache return 0; 13778471Sache} 13788471Sache 13798471Sache#ifdef RCDEBUG 13809232Sachestatic void printrcflags(rc, comment) 13818471Sachestruct rc_chans *rc; 13828471Sachechar *comment; 13838471Sache{ 13848471Sache u_short f = rc->rc_flags; 13859232Sache register int nec = rc->rc_rcb->rcb_addr; 13868471Sache 13879232Sache printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 13888471Sache rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 13898471Sache (f & RC_DTR_OFF)?"DTR_OFF " :"", 13909232Sache (f & RC_ACTOUT) ?"ACTOUT " :"", 13919232Sache (f & RC_RTSFLOW)?"RTSFLOW " :"", 13929232Sache (f & RC_CTSFLOW)?"CTSFLOW " :"", 13939232Sache (f & RC_DORXFER)?"DORXFER " :"", 13949232Sache (f & RC_DOXXFER)?"DOXXFER " :"", 13959232Sache (f & RC_MODCHG) ?"MODCHG " :"", 13969232Sache (f & RC_OSUSP) ?"OSUSP " :"", 13979232Sache (f & RC_OSBUSY) ?"OSBUSY " :"", 13989232Sache (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 13999232Sache (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 14009232Sache (f & RC_SEND_RDY) ?"SEND_RDY":""); 14019232Sache 14029232Sache rcout(CD180_CAR, rc->rc_chan); 14039232Sache 14049232Sache printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 14059232Sache rc->rc_rcb->rcb_unit, rc->rc_chan, 14069232Sache rcin(CD180_MSVR), 14079232Sache rcin(CD180_IER), 14089232Sache rcin(CD180_CCSR)); 14098471Sache} 14108471Sache#endif /* RCDEBUG */ 14118471Sache 141212675Sjulianstatic struct tty * 14138471Sachercdevtotty(dev) 14148471Sache dev_t dev; 14158471Sache{ 14168471Sache int unit; 14178471Sache 14188471Sache unit = GET_UNIT(dev); 14198471Sache if (unit >= NRC * CD180_NCHAN) 14208471Sache return NULL; 14218471Sache return (&rc_tty[unit]); 14228471Sache} 14238471Sache 14248471Sachestatic void 14258471Sacherc_dtrwakeup(chan) 14268471Sache void *chan; 14278471Sache{ 14288471Sache struct rc_chans *rc; 14298471Sache 14308471Sache rc = (struct rc_chans *)chan; 14318471Sache rc->rc_flags &= ~RC_DTR_OFF; 14328471Sache wakeup(&rc->rc_dtrwait); 14338471Sache} 14348471Sache 14358471Sachestatic void 14368471Sacherc_discard_output(rc) 14378471Sache struct rc_chans *rc; 14388471Sache{ 14398471Sache disable_intr(); 14408471Sache if (rc->rc_flags & RC_DOXXFER) { 14418471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 14428471Sache rc->rc_flags &= ~RC_DOXXFER; 14438471Sache } 14448471Sache rc->rc_optr = rc->rc_obufend; 14459232Sache rc->rc_tp->t_state &= ~TS_BUSY; 14468471Sache enable_intr(); 14479754Sbde ttwwakeup(rc->rc_tp); 14488471Sache} 14498471Sache 14508471Sachestatic void 14518471Sacherc_wakeup(chan) 14528471Sache void *chan; 14538471Sache{ 14548471Sache timeout(rc_wakeup, (caddr_t)NULL, 1); 14558471Sache 14568471Sache if (rc_scheduled_event != 0) { 14578471Sache int s; 14588471Sache 14598471Sache s = splsofttty(); 14608471Sache rcpoll(); 14618471Sache splx(s); 14628471Sache } 14638471Sache} 14648471Sache 14658471Sachestatic void 14668471Sachedisc_optim(tp, t, rc) 14678471Sache struct tty *tp; 14688471Sache struct termios *t; 14698471Sache struct rc_chans *rc; 14708471Sache{ 14718471Sache 14729757Sbde if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 14738471Sache && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 14749757Sbde && (!(t->c_iflag & PARMRK) 14759757Sbde || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 14769757Sbde && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 14778471Sache && linesw[tp->t_line].l_rint == ttyinput) 14788471Sache tp->t_state |= TS_CAN_BYPASS_L_RINT; 14798471Sache else 14808471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 14818471Sache if (tp->t_line == SLIPDISC) 14828471Sache rc->rc_hotchar = 0xc0; 14838471Sache else if (tp->t_line == PPPDISC) 14848471Sache rc->rc_hotchar = 0x7e; 14858471Sache else 14868471Sache rc->rc_hotchar = 0; 14878471Sache} 14889232Sache 14899232Sachestatic void 14909232Sacherc_wait0(nec, unit, chan, line) 14919232Sache int nec, unit, chan, line; 14929232Sache{ 14939232Sache int rcnt; 14949232Sache 149514441Srgrimes for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 149614441Srgrimes DELAY(30); 14979232Sache if (rcnt == 0) 14989232Sache printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 14999232Sache unit, chan, line); 15009232Sache} 150112502Sjulian 150212502Sjulianstatic rc_devsw_installed = 0; 150312502Sjulian 150412517Sjulianstatic void rc_drvinit(void *unused) 150512502Sjulian{ 150612517Sjulian dev_t dev; 150712517Sjulian 150812502Sjulian if( ! rc_devsw_installed ) { 150912675Sjulian dev = makedev(CDEV_MAJOR, 0); 151012675Sjulian cdevsw_add(&dev,&rc_cdevsw, NULL); 151112502Sjulian rc_devsw_installed = 1; 151212517Sjulian } 151312502Sjulian} 151412517Sjulian 151512517SjulianSYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 151612517Sjulian 151712517Sjulian 15188471Sache#endif /* NRC */ 1519