rc.c revision 27125
11558Srgrimes/* 21558Srgrimes * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 31558Srgrimes * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 41558Srgrimes * All rights reserved. 51558Srgrimes * 61558Srgrimes * Redistribution and use in source and binary forms, with or without 71558Srgrimes * modification, are permitted provided that the following conditions 81558Srgrimes * are met: 91558Srgrimes * 1. Redistributions of source code must retain the above copyright 101558Srgrimes * notice, this list of conditions and the following disclaimer. 111558Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 121558Srgrimes * notice, this list of conditions and the following disclaimer in the 131558Srgrimes * documentation and/or other materials provided with the distribution. 141558Srgrimes * 151558Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 161558Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 171558Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 181558Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 191558Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 201558Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 211558Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 221558Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 231558Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 241558Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 251558Srgrimes * SUCH DAMAGE. 261558Srgrimes */ 271558Srgrimes 281558Srgrimes/* 291558Srgrimes * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 301558Srgrimes * 311558Srgrimes */ 321558Srgrimes 331558Srgrimes#include "opt_comconsole.h" 341558Srgrimes#include "rc.h" 3536997Scharnier 361558Srgrimes#if NRC > 0 3736997Scharnier 3836997Scharnier/*#define RCDEBUG*/ 3950476Speter 401558Srgrimes#include <sys/param.h> 411558Srgrimes#include <sys/systm.h> 421558Srgrimes#include <sys/tty.h> 431558Srgrimes#include <sys/proc.h> 441558Srgrimes#include <sys/conf.h> 451558Srgrimes#include <sys/dkstat.h> 461558Srgrimes#include <sys/fcntl.h> 471558Srgrimes#include <sys/uio.h> 481558Srgrimes#include <sys/kernel.h> 491558Srgrimes#include <sys/syslog.h> 501558Srgrimes#ifdef DEVFS 511558Srgrimes#include <sys/devfsext.h> 521558Srgrimes#endif /*DEVFS*/ 531558Srgrimes 541558Srgrimes#include <machine/clock.h> 551558Srgrimes 561558Srgrimes#include <i386/isa/isa_device.h> 571558Srgrimes#include <i386/isa/sioreg.h> 581558Srgrimes 591558Srgrimes#include <i386/isa/ic/cd180.h> 601558Srgrimes#include <i386/isa/rcreg.h> 611558Srgrimes 621558Srgrimes 631558Srgrimes/* Prototypes */ 641558Srgrimesstatic int rcprobe __P((struct isa_device *)); 651558Srgrimesstatic int rcattach __P((struct isa_device *)); 661558Srgrimes 671558Srgrimes/*- 681558Srgrimes * This space intentionally left blank to stop __LINE__ from screwing up 691558Srgrimes * regression tests :-(. 701558Srgrimes * 711558Srgrimes * 721558Srgrimes * 731558Srgrimes */ 741558Srgrimesvoid rcpoll __P((void)); 751558Srgrimes 761558Srgrimes#define rcin(port) RC_IN (nec, port) 771558Srgrimes#define rcout(port,v) RC_OUT (nec, port, v) 781558Srgrimes 791558Srgrimes#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 801558Srgrimes#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 811558Srgrimes 821558Srgrimes#define RC_IBUFSIZE 256 831558Srgrimes#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 841558Srgrimes#define RC_OBUFSIZE 512 851558Srgrimes#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 861558Srgrimes#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 871558Srgrimes#define LOTS_OF_EVENTS 64 881558Srgrimes 891558Srgrimes#define RC_FAKEID 0x10 901558Srgrimes 911558Srgrimes#define RC_PROBED 1 921558Srgrimes#define RC_ATTACHED 2 931558Srgrimes 941558Srgrimes#define GET_UNIT(dev) (minor(dev) & 0x3F) 951558Srgrimes#define CALLOUT(dev) (minor(dev) & 0x80) 961558Srgrimes 971558Srgrimes/* For isa routines */ 981558Srgrimesstruct isa_driver rcdriver = { 991558Srgrimes rcprobe, rcattach, "rc" 1001558Srgrimes}; 1011558Srgrimes 1021558Srgrimesstatic d_open_t rcopen; 1031558Srgrimesstatic d_close_t rcclose; 1041558Srgrimesstatic d_read_t rcread; 1051558Srgrimesstatic d_write_t rcwrite; 1061558Srgrimesstatic d_ioctl_t rcioctl; 1071558Srgrimesstatic d_stop_t rcstop; 1081558Srgrimesstatic d_devtotty_t rcdevtotty; 1091558Srgrimes 1101558Srgrimes#define CDEV_MAJOR 63 1111558Srgrimesstatic struct cdevsw rc_cdevsw = 1121558Srgrimes { rcopen, rcclose, rcread, rcwrite, /*63*/ 1131558Srgrimes rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 1141558Srgrimes ttselect, nommap, NULL, "rc", NULL, -1 }; 1151558Srgrimes 1161558Srgrimes/* Per-board structure */ 1171558Srgrimesstatic struct rc_softc { 1181558Srgrimes u_int rcb_probed; /* 1 - probed, 2 - attached */ 1191558Srgrimes u_int rcb_addr; /* Base I/O addr */ 1201558Srgrimes u_int rcb_unit; /* unit # */ 1211558Srgrimes u_char rcb_dtr; /* DTR status */ 1221558Srgrimes struct rc_chans *rcb_baserc; /* base rc ptr */ 1231558Srgrimes} rc_softc[NRC]; 1241558Srgrimes 1251558Srgrimes/* Per-channel structure */ 1261558Srgrimesstatic struct rc_chans { 1271558Srgrimes struct rc_softc *rc_rcb; /* back ptr */ 1281558Srgrimes u_short rc_flags; /* Misc. flags */ 1291558Srgrimes int rc_chan; /* Channel # */ 1301558Srgrimes u_char rc_ier; /* intr. enable reg */ 1311558Srgrimes u_char rc_msvr; /* modem sig. status */ 1321558Srgrimes u_char rc_cor2; /* options reg */ 1331558Srgrimes u_char rc_pendcmd; /* special cmd pending */ 1341558Srgrimes u_int rc_dtrwait; /* dtr timeout */ 1351558Srgrimes u_int rc_dcdwaits; /* how many waits DCD in open */ 1361558Srgrimes u_char rc_hotchar; /* end packed optimize */ 1371558Srgrimes struct tty *rc_tp; /* tty struct */ 1381558Srgrimes u_char *rc_iptr; /* Chars input buffer */ 1391558Srgrimes u_char *rc_hiwat; /* hi-water mark */ 1401558Srgrimes u_char *rc_bufend; /* end of buffer */ 1411558Srgrimes u_char *rc_optr; /* ptr in output buf */ 1421558Srgrimes u_char *rc_obufend; /* end of output buf */ 1431558Srgrimes u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 1441558Srgrimes u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 1451558Srgrimes#ifdef DEVFS 1461558Srgrimes void *devfs_token; 1471558Srgrimes#endif 1481558Srgrimes} rc_chans[NRC * CD180_NCHAN]; 1491558Srgrimes 1501558Srgrimesstatic int rc_scheduled_event = 0; 1511558Srgrimes 1521558Srgrimes/* for pstat -t */ 1531558Srgrimesstatic struct tty rc_tty[NRC * CD180_NCHAN]; 1541558Srgrimesstatic const int nrc_tty = NRC * CD180_NCHAN; 1551558Srgrimes 1561558Srgrimes/* Flags */ 1571558Srgrimes#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 1581558Srgrimes#define RC_ACTOUT 0x0002 /* Dial-out port active */ 1591558Srgrimes#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 1601558Srgrimes#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 1611558Srgrimes#define RC_DORXFER 0x0010 /* RXFER event planned */ 1621558Srgrimes#define RC_DOXXFER 0x0020 /* XXFER event planned */ 1631558Srgrimes#define RC_MODCHG 0x0040 /* Modem status changed */ 1641558Srgrimes#define RC_OSUSP 0x0080 /* Output suspended */ 1651558Srgrimes#define RC_OSBUSY 0x0100 /* start() routine in progress */ 1661558Srgrimes#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 1671558Srgrimes#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 1681558Srgrimes#define RC_SEND_RDY 0x0800 /* ready to send */ 1698871Srgrimes 1701558Srgrimes/* Table for translation of RCSR status bits to internal form */ 1711558Srgrimesstatic int rc_rcsrt[16] = { 1721558Srgrimes 0, TTY_OE, TTY_FE, 1731558Srgrimes TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 1741558Srgrimes TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 1751558Srgrimes TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 1761558Srgrimes TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 1771558Srgrimes TTY_BI|TTY_PE|TTY_FE|TTY_OE 1781558Srgrimes}; 1791558Srgrimes 1801558Srgrimes/* Static prototypes */ 1811558Srgrimesstatic void rc_hwreset __P((int, int, unsigned int)); 1821558Srgrimesstatic int rc_test __P((int, int)); 1831558Srgrimesstatic void rc_discard_output __P((struct rc_chans *)); 1841558Srgrimesstatic void rc_hardclose __P((struct rc_chans *)); 1851558Srgrimesstatic int rc_modctl __P((struct rc_chans *, int, int)); 1861558Srgrimesstatic void rc_start __P((struct tty *)); 1871558Srgrimesstatic int rc_param __P((struct tty *, struct termios *)); 1881558Srgrimesstatic void rc_reinit __P((struct rc_softc *)); 1891558Srgrimes#ifdef RCDEBUG 1901558Srgrimesstatic void printrcflags(); 1911558Srgrimes#endif 1921558Srgrimesstatic timeout_t rc_dtrwakeup; 1931558Srgrimesstatic timeout_t rc_wakeup; 1941558Srgrimesstatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 1951558Srgrimesstatic void rc_wait0 __P((int nec, int unit, int chan, int line)); 1961558Srgrimes 1971558Srgrimes/**********************************************/ 1981558Srgrimes 1991558Srgrimes/* Quick device probing */ 2001558Srgrimesstatic int 2011558Srgrimesrcprobe(dvp) 2021558Srgrimes struct isa_device *dvp; 2031558Srgrimes{ 2041558Srgrimes int irq = ffs(dvp->id_irq) - 1; 2051558Srgrimes register int nec = dvp->id_iobase; 2061558Srgrimes 2071558Srgrimes if (dvp->id_unit > NRC) 2081558Srgrimes return 0; 2091558Srgrimes if (!RC_VALIDADDR(nec)) { 2101558Srgrimes printf("rc%d: illegal base address %x\n", nec); 2111558Srgrimes return 0; 2121558Srgrimes } 2131558Srgrimes if (!RC_VALIDIRQ(irq)) { 2141558Srgrimes printf("rc%d: illegal IRQ value %d\n", irq); 2151558Srgrimes return 0; 2161558Srgrimes } 2171558Srgrimes rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 2181558Srgrimes rcout(CD180_PPRH, 0x11); 2191558Srgrimes if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 2201558Srgrimes return 0; 2211558Srgrimes /* Now, test the board more thoroughly, with diagnostic */ 2221558Srgrimes if (rc_test(nec, dvp->id_unit)) 2231558Srgrimes return 0; 2241558Srgrimes rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 2251558Srgrimes 2261558Srgrimes return 0xF; 2271558Srgrimes} 2281558Srgrimes 2291558Srgrimesstatic int 2301558Srgrimesrcattach(dvp) 2311558Srgrimes struct isa_device *dvp; 2321558Srgrimes{ 2331558Srgrimes register int chan, nec = dvp->id_iobase; 2341558Srgrimes struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 2351558Srgrimes struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 2361558Srgrimes static int rc_wakeup_started = 0; 2371558Srgrimes struct tty *tp; 2381558Srgrimes 2391558Srgrimes /* Thorooughly test the device */ 2401558Srgrimes if (rcb->rcb_probed != RC_PROBED) 2411558Srgrimes return 0; 2421558Srgrimes rcb->rcb_addr = nec; 2431558Srgrimes rcb->rcb_dtr = 0; 2441558Srgrimes rcb->rcb_baserc = rc; 2451558Srgrimes /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 2461558Srgrimes printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 2471558Srgrimes CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 2481558Srgrimes 2491558Srgrimes for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 25021409Simp rc->rc_rcb = rcb; 2511558Srgrimes rc->rc_chan = chan; 2521558Srgrimes rc->rc_iptr = rc->rc_ibuf; 2531558Srgrimes rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 2541558Srgrimes rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 2551558Srgrimes rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 25621409Simp rc->rc_cor2 = rc->rc_pendcmd = 0; 2571558Srgrimes rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 2581558Srgrimes rc->rc_dtrwait = 3 * hz; 2591558Srgrimes rc->rc_dcdwaits= 0; 2601558Srgrimes rc->rc_hotchar = 0; 2611558Srgrimes tp = rc->rc_tp = &rc_tty[chan]; 2621558Srgrimes ttychars(tp); 2631558Srgrimes tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 2641558Srgrimes tp->t_cflag = TTYDEF_CFLAG; 2651558Srgrimes tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 2661558Srgrimes#ifdef DEVFS 2671558Srgrimes/* FIX THIS to reflect real devices */ 2681558Srgrimes rc->devfs_token = 2691558Srgrimes devfs_add_devswf(&rc_cdevsw, 2701558Srgrimes (dvp->id_unit * CD180_NCHAN) + chan, 2711558Srgrimes DV_CHR, 0, 0, 0600, "rc%d.%d", 2721558Srgrimes dvp->id_unit, chan); 2731558Srgrimes#endif 2741558Srgrimes } 2751558Srgrimes rcb->rcb_probed = RC_ATTACHED; 2761558Srgrimes if (!rc_wakeup_started) { 2771558Srgrimes rc_wakeup((void *)NULL); 2781558Srgrimes rc_wakeup_started = 0; 2791558Srgrimes } 2801558Srgrimes return 1; 2811558Srgrimes} 2821558Srgrimes 2831558Srgrimes/* RC interrupt handling */ 2841558Srgrimesvoid rcintr(unit) 2851558Srgrimes int unit; 2861558Srgrimes{ 2871558Srgrimes register struct rc_softc *rcb = &rc_softc[unit]; 2881558Srgrimes register struct rc_chans *rc; 2891558Srgrimes register int nec, resid; 2901558Srgrimes register u_char val, iack, bsr, ucnt, *optr; 2911558Srgrimes int good_data, t_state; 2921558Srgrimes 2931558Srgrimes if (rcb->rcb_probed != RC_ATTACHED) { 2941558Srgrimes printf("rc%d: bogus interrupt\n", unit); 2951558Srgrimes return; 2961558Srgrimes } 2971558Srgrimes nec = rcb->rcb_addr; 2988871Srgrimes 2991558Srgrimes bsr = ~(rcin(RC_BSR)); 3001558Srgrimes 3011558Srgrimes if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 3021558Srgrimes printf("rc%d: extra interrupt\n", unit); 3031558Srgrimes rcout(CD180_EOIR, 0); 3041558Srgrimes return; 3051558Srgrimes } 3061558Srgrimes 3071558Srgrimes while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 3081558Srgrimes#ifdef RCDEBUG_DETAILED 3091558Srgrimes printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 3101558Srgrimes (bsr & RC_BSR_TOUT)?"TOUT ":"", 3111558Srgrimes (bsr & RC_BSR_RXINT)?"RXINT ":"", 3121558Srgrimes (bsr & RC_BSR_TXINT)?"TXINT ":"", 3131558Srgrimes (bsr & RC_BSR_MOINT)?"MOINT":""); 3141558Srgrimes#endif 3151558Srgrimes if (bsr & RC_BSR_TOUT) { 3161558Srgrimes printf("rc%d: hardware failure, reset board\n", unit); 3171558Srgrimes rcout(RC_CTOUT, 0); 3181558Srgrimes rc_reinit(rcb); 3191558Srgrimes return; 3201558Srgrimes } 3211558Srgrimes if (bsr & RC_BSR_RXINT) { 3221558Srgrimes iack = rcin(RC_PILR_RX); 3231558Srgrimes good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 3241558Srgrimes if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 3251558Srgrimes printf("rc%d: fake rxint: %02x\n", unit, iack); 3261558Srgrimes goto more_intrs; 3271558Srgrimes } 3281558Srgrimes rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 3291558Srgrimes t_state = rc->rc_tp->t_state; 3301558Srgrimes /* Do RTS flow control stuff */ 3311558Srgrimes if ( (rc->rc_flags & RC_RTSFLOW) 3321558Srgrimes || !(t_state & TS_ISOPEN) 3331558Srgrimes ) { 3341558Srgrimes if ( ( !(t_state & TS_ISOPEN) 3351558Srgrimes || (t_state & TS_TBLOCK) 3361558Srgrimes ) 3371558Srgrimes && (rc->rc_msvr & MSVR_RTS) 3381558Srgrimes ) 3391558Srgrimes rcout(CD180_MSVR, 3401558Srgrimes rc->rc_msvr &= ~MSVR_RTS); 3411558Srgrimes else if (!(rc->rc_msvr & MSVR_RTS)) 3421558Srgrimes rcout(CD180_MSVR, 3431558Srgrimes rc->rc_msvr |= MSVR_RTS); 3441558Srgrimes } 3451558Srgrimes ucnt = rcin(CD180_RDCR) & 0xF; 3461558Srgrimes resid = 0; 3471558Srgrimes 3481558Srgrimes if (t_state & TS_ISOPEN) { 3491558Srgrimes /* check for input buffer overflow */ 3501558Srgrimes if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 3511558Srgrimes resid = ucnt; 3521558Srgrimes ucnt = rc->rc_bufend - rc->rc_iptr; 3531558Srgrimes resid -= ucnt; 3541558Srgrimes if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 3551558Srgrimes rc->rc_flags |= RC_WAS_BUFOVFL; 3561558Srgrimes rc_scheduled_event++; 3571558Srgrimes } 3581558Srgrimes } 3591558Srgrimes optr = rc->rc_iptr; 3601558Srgrimes /* check foor good data */ 3611558Srgrimes if (good_data) { 3621558Srgrimes while (ucnt-- > 0) { 3631558Srgrimes val = rcin(CD180_RDR); 3641558Srgrimes optr[0] = val; 3651558Srgrimes optr[INPUT_FLAGS_SHIFT] = 0; 3661558Srgrimes optr++; 3671558Srgrimes rc_scheduled_event++; 3681558Srgrimes if (val != 0 && val == rc->rc_hotchar) 3691558Srgrimes setsofttty(); 3701558Srgrimes } 3711558Srgrimes } else { 3721558Srgrimes /* Store also status data */ 3731558Srgrimes while (ucnt-- > 0) { 3741558Srgrimes iack = rcin(CD180_RCSR); 3751558Srgrimes if (iack & RCSR_Timeout) 3761558Srgrimes break; 3771558Srgrimes if ( (iack & RCSR_OE) 3781558Srgrimes && !(rc->rc_flags & RC_WAS_SILOVFL)) { 3791558Srgrimes rc->rc_flags |= RC_WAS_SILOVFL; 3801558Srgrimes rc_scheduled_event++; 3811558Srgrimes } 3821558Srgrimes val = rcin(CD180_RDR); 3831558Srgrimes /* 3841558Srgrimes Don't store PE if IGNPAR and BREAK if IGNBRK, 3851558Srgrimes this hack allows "raw" tty optimization 3861558Srgrimes works even if IGN* is set. 3871558Srgrimes */ 3881558Srgrimes if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 3891558Srgrimes || (!(iack & (RCSR_PE|RCSR_FE)) 3901558Srgrimes || !(rc->rc_tp->t_iflag & IGNPAR)) 3911558Srgrimes && (!(iack & RCSR_Break) 3921558Srgrimes || !(rc->rc_tp->t_iflag & IGNBRK))) { 3931558Srgrimes if ( (iack & (RCSR_PE|RCSR_FE)) 3941558Srgrimes && (t_state & TS_CAN_BYPASS_L_RINT) 3951558Srgrimes && ((iack & RCSR_FE) 3961558Srgrimes || (iack & RCSR_PE) 3971558Srgrimes && (rc->rc_tp->t_iflag & INPCK))) 3981558Srgrimes val = 0; 3991558Srgrimes else if (val != 0 && val == rc->rc_hotchar) 4001558Srgrimes setsofttty(); 4011558Srgrimes optr[0] = val; 4021558Srgrimes optr[INPUT_FLAGS_SHIFT] = iack; 4031558Srgrimes optr++; 4041558Srgrimes rc_scheduled_event++; 4051558Srgrimes } 4061558Srgrimes } 4071558Srgrimes } 4081558Srgrimes rc->rc_iptr = optr; 4091558Srgrimes rc->rc_flags |= RC_DORXFER; 4101558Srgrimes } else 4111558Srgrimes resid = ucnt; 4121558Srgrimes /* Clear FIFO if necessary */ 4131558Srgrimes while (resid-- > 0) { 4141558Srgrimes if (!good_data) 4151558Srgrimes iack = rcin(CD180_RCSR); 4161558Srgrimes else 4171558Srgrimes iack = 0; 4181558Srgrimes if (iack & RCSR_Timeout) 4191558Srgrimes break; 4201558Srgrimes (void) rcin(CD180_RDR); 4211558Srgrimes } 4221558Srgrimes goto more_intrs; 4231558Srgrimes } 4241558Srgrimes if (bsr & RC_BSR_MOINT) { 4251558Srgrimes iack = rcin(RC_PILR_MODEM); 4261558Srgrimes if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 4271558Srgrimes printf("rc%d: fake moint: %02x\n", unit, iack); 4281558Srgrimes goto more_intrs; 4291558Srgrimes } 4301558Srgrimes rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4311558Srgrimes iack = rcin(CD180_MCR); 4321558Srgrimes rc->rc_msvr = rcin(CD180_MSVR); 4331558Srgrimes rcout(CD180_MCR, 0); 4341558Srgrimes#ifdef RCDEBUG 4351558Srgrimes printrcflags(rc, "moint"); 4361558Srgrimes#endif 4371558Srgrimes if (rc->rc_flags & RC_CTSFLOW) { 4381558Srgrimes if (rc->rc_msvr & MSVR_CTS) 4391558Srgrimes rc->rc_flags |= RC_SEND_RDY; 4401558Srgrimes else 4411558Srgrimes rc->rc_flags &= ~RC_SEND_RDY; 4421558Srgrimes } else 4431558Srgrimes rc->rc_flags |= RC_SEND_RDY; 4441558Srgrimes if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 4451558Srgrimes rc_scheduled_event += LOTS_OF_EVENTS; 4461558Srgrimes rc->rc_flags |= RC_MODCHG; 4471558Srgrimes setsofttty(); 4481558Srgrimes } 4491558Srgrimes goto more_intrs; 4501558Srgrimes } 4511558Srgrimes if (bsr & RC_BSR_TXINT) { 4521558Srgrimes iack = rcin(RC_PILR_TX); 4531558Srgrimes if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 4541558Srgrimes printf("rc%d: fake txint: %02x\n", unit, iack); 4551558Srgrimes goto more_intrs; 4561558Srgrimes } 4571558Srgrimes rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4581558Srgrimes if ( (rc->rc_flags & RC_OSUSP) 4591558Srgrimes || !(rc->rc_flags & RC_SEND_RDY) 4601558Srgrimes ) 4611558Srgrimes goto more_intrs; 4621558Srgrimes /* Handle breaks and other stuff */ 4631558Srgrimes if (rc->rc_pendcmd) { 4641558Srgrimes rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 4651558Srgrimes rcout(CD180_TDR, CD180_C_ESC); 4661558Srgrimes rcout(CD180_TDR, rc->rc_pendcmd); 4671558Srgrimes rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 4681558Srgrimes rc->rc_pendcmd = 0; 4691558Srgrimes goto more_intrs; 4701558Srgrimes } 4711558Srgrimes optr = rc->rc_optr; 4721558Srgrimes resid = rc->rc_obufend - optr; 4731558Srgrimes if (resid > CD180_NFIFO) 4741558Srgrimes resid = CD180_NFIFO; 4751558Srgrimes while (resid-- > 0) 4761558Srgrimes rcout(CD180_TDR, *optr++); 4771558Srgrimes rc->rc_optr = optr; 4781558Srgrimes 4791558Srgrimes /* output completed? */ 4801558Srgrimes if (optr >= rc->rc_obufend) { 4811558Srgrimes rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 4821558Srgrimes#ifdef RCDEBUG 4831558Srgrimes printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 4841558Srgrimes#endif 4851558Srgrimes if (!(rc->rc_flags & RC_DOXXFER)) { 4861558Srgrimes rc_scheduled_event += LOTS_OF_EVENTS; 48748447Sjkh rc->rc_flags |= RC_DOXXFER; 48848447Sjkh setsofttty(); 4891558Srgrimes } 4901558Srgrimes } 4911558Srgrimes } 4921558Srgrimes more_intrs: 4931558Srgrimes rcout(CD180_EOIR, 0); /* end of interrupt */ 4941558Srgrimes rcout(RC_CTOUT, 0); 4951558Srgrimes bsr = ~(rcin(RC_BSR)); 4961558Srgrimes } 4971558Srgrimes} 4981558Srgrimes 4991558Srgrimes/* Feed characters to output buffer */ 5001558Srgrimesstatic void rc_start(tp) 5011558Srgrimesregister struct tty *tp; 5021558Srgrimes{ 5031558Srgrimes register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 50448447Sjkh register int nec = rc->rc_rcb->rcb_addr, s; 5051558Srgrimes 5061558Srgrimes if (rc->rc_flags & RC_OSBUSY) 5071558Srgrimes return; 50848447Sjkh s = spltty(); 50948447Sjkh rc->rc_flags |= RC_OSBUSY; 51048447Sjkh disable_intr(); 51148447Sjkh if (tp->t_state & TS_TTSTOP) 51248447Sjkh rc->rc_flags |= RC_OSUSP; 51348447Sjkh else 51448447Sjkh rc->rc_flags &= ~RC_OSUSP; 5151558Srgrimes /* Do RTS flow control stuff */ 5161558Srgrimes if ( (rc->rc_flags & RC_RTSFLOW) 5171558Srgrimes && (tp->t_state & TS_TBLOCK) 5181558Srgrimes && (rc->rc_msvr & MSVR_RTS) 5191558Srgrimes ) { 5201558Srgrimes rcout(CD180_CAR, rc->rc_chan); 5211558Srgrimes rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 5221558Srgrimes } else if (!(rc->rc_msvr & MSVR_RTS)) { 5231558Srgrimes rcout(CD180_CAR, rc->rc_chan); 5241558Srgrimes rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 5251558Srgrimes } 5261558Srgrimes enable_intr(); 5271558Srgrimes if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 5281558Srgrimes goto out; 5291558Srgrimes#ifdef RCDEBUG 5301558Srgrimes printrcflags(rc, "rcstart"); 5311558Srgrimes#endif 5321558Srgrimes ttwwakeup(tp); 5331558Srgrimes#ifdef RCDEBUG 5341558Srgrimes printf("rcstart: outq = %d obuf = %d\n", 5351558Srgrimes tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 5361558Srgrimes#endif 5371558Srgrimes if (tp->t_state & TS_BUSY) 5381558Srgrimes goto out; /* output still in progress ... */ 539 540 if (tp->t_outq.c_cc > 0) { 541 u_int ocnt; 542 543 tp->t_state |= TS_BUSY; 544 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 545 disable_intr(); 546 rc->rc_optr = rc->rc_obuf; 547 rc->rc_obufend = rc->rc_optr + ocnt; 548 enable_intr(); 549 if (!(rc->rc_ier & IER_TxRdy)) { 550#ifdef RCDEBUG 551 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 552#endif 553 rcout(CD180_CAR, rc->rc_chan); 554 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 555 } 556 } 557out: 558 rc->rc_flags &= ~RC_OSBUSY; 559 (void) splx(s); 560} 561 562/* Handle delayed events. */ 563void rcpoll() 564{ 565 register struct rc_chans *rc; 566 register struct rc_softc *rcb; 567 register u_char *tptr, *eptr; 568 register struct tty *tp; 569 register int chan, icnt, nec, unit; 570 571 if (rc_scheduled_event == 0) 572 return; 573repeat: 574 for (unit = 0; unit < NRC; unit++) { 575 rcb = &rc_softc[unit]; 576 rc = rcb->rcb_baserc; 577 nec = rc->rc_rcb->rcb_addr; 578 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 579 tp = rc->rc_tp; 580#ifdef RCDEBUG 581 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 582 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 583 printrcflags(rc, "rcevent"); 584#endif 585 if (rc->rc_flags & RC_WAS_BUFOVFL) { 586 disable_intr(); 587 rc->rc_flags &= ~RC_WAS_BUFOVFL; 588 rc_scheduled_event--; 589 enable_intr(); 590 printf("rc%d/%d: interrupt-level buffer overflow\n", 591 unit, chan); 592 } 593 if (rc->rc_flags & RC_WAS_SILOVFL) { 594 disable_intr(); 595 rc->rc_flags &= ~RC_WAS_SILOVFL; 596 rc_scheduled_event--; 597 enable_intr(); 598 printf("rc%d/%d: silo overflow\n", 599 unit, chan); 600 } 601 if (rc->rc_flags & RC_MODCHG) { 602 disable_intr(); 603 rc->rc_flags &= ~RC_MODCHG; 604 rc_scheduled_event -= LOTS_OF_EVENTS; 605 enable_intr(); 606 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 607 } 608 if (rc->rc_flags & RC_DORXFER) { 609 disable_intr(); 610 rc->rc_flags &= ~RC_DORXFER; 611 eptr = rc->rc_iptr; 612 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 613 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 614 else 615 tptr = rc->rc_ibuf; 616 icnt = eptr - tptr; 617 if (icnt > 0) { 618 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 619 rc->rc_iptr = rc->rc_ibuf; 620 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 621 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 622 } else { 623 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 624 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 625 rc->rc_hiwat = 626 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 627 } 628 if ( (rc->rc_flags & RC_RTSFLOW) 629 && (tp->t_state & TS_ISOPEN) 630 && !(tp->t_state & TS_TBLOCK) 631 && !(rc->rc_msvr & MSVR_RTS) 632 ) { 633 rcout(CD180_CAR, chan); 634 rcout(CD180_MSVR, 635 rc->rc_msvr |= MSVR_RTS); 636 } 637 rc_scheduled_event -= icnt; 638 } 639 enable_intr(); 640 641 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 642 goto done1; 643 644 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 645 && !(tp->t_state & TS_LOCAL)) { 646 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 647 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 648 && !(tp->t_state & TS_TBLOCK)) 649 ttyblock(tp); 650 tk_nin += icnt; 651 tk_rawcc += icnt; 652 tp->t_rawcc += icnt; 653 if (b_to_q(tptr, icnt, &tp->t_rawq)) 654 printf("rc%d/%d: tty-level buffer overflow\n", 655 unit, chan); 656 ttwakeup(tp); 657 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 658 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 659 tp->t_state &= ~TS_TTSTOP; 660 tp->t_lflag &= ~FLUSHO; 661 rc_start(tp); 662 } 663 } else { 664 for (; tptr < eptr; tptr++) 665 (*linesw[tp->t_line].l_rint) 666 (tptr[0] | 667 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 668 } 669done1: ; 670 } 671 if (rc->rc_flags & RC_DOXXFER) { 672 disable_intr(); 673 rc_scheduled_event -= LOTS_OF_EVENTS; 674 rc->rc_flags &= ~RC_DOXXFER; 675 rc->rc_tp->t_state &= ~TS_BUSY; 676 enable_intr(); 677 (*linesw[tp->t_line].l_start)(tp); 678 } 679 } 680 if (rc_scheduled_event == 0) 681 break; 682 } 683 if (rc_scheduled_event >= LOTS_OF_EVENTS) 684 goto repeat; 685} 686 687static void 688rcstop(tp, rw) 689 register struct tty *tp; 690 int rw; 691{ 692 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 693 u_char *tptr, *eptr; 694 695#ifdef RCDEBUG 696 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 697 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 698#endif 699 if (rw & FWRITE) 700 rc_discard_output(rc); 701 disable_intr(); 702 if (rw & FREAD) { 703 rc->rc_flags &= ~RC_DORXFER; 704 eptr = rc->rc_iptr; 705 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 706 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 707 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 708 } else { 709 tptr = rc->rc_ibuf; 710 rc->rc_iptr = rc->rc_ibuf; 711 } 712 rc_scheduled_event -= eptr - tptr; 713 } 714 if (tp->t_state & TS_TTSTOP) 715 rc->rc_flags |= RC_OSUSP; 716 else 717 rc->rc_flags &= ~RC_OSUSP; 718 enable_intr(); 719} 720 721static int 722rcopen(dev, flag, mode, p) 723 dev_t dev; 724 int flag, mode; 725 struct proc *p; 726{ 727 register struct rc_chans *rc; 728 register struct tty *tp; 729 int unit, nec, s, error = 0; 730 731 unit = GET_UNIT(dev); 732 if (unit >= NRC * CD180_NCHAN) 733 return ENXIO; 734 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 735 return ENXIO; 736 rc = &rc_chans[unit]; 737 tp = rc->rc_tp; 738 nec = rc->rc_rcb->rcb_addr; 739#ifdef RCDEBUG 740 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 741#endif 742 s = spltty(); 743 744again: 745 while (rc->rc_flags & RC_DTR_OFF) { 746 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 747 if (error != 0) 748 goto out; 749 } 750 if (tp->t_state & TS_ISOPEN) { 751 if (CALLOUT(dev)) { 752 if (!(rc->rc_flags & RC_ACTOUT)) { 753 error = EBUSY; 754 goto out; 755 } 756 } else { 757 if (rc->rc_flags & RC_ACTOUT) { 758 if (flag & O_NONBLOCK) { 759 error = EBUSY; 760 goto out; 761 } 762 if (error = tsleep(&rc->rc_rcb, 763 TTIPRI|PCATCH, "rcbi", 0)) 764 goto out; 765 goto again; 766 } 767 } 768 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 769 error = EBUSY; 770 goto out; 771 } 772 } else { 773 tp->t_oproc = rc_start; 774 tp->t_param = rc_param; 775 tp->t_dev = dev; 776 777 if (CALLOUT(dev)) 778 tp->t_cflag |= CLOCAL; 779 else 780 tp->t_cflag &= ~CLOCAL; 781 782 error = rc_param(tp, &tp->t_termios); 783 if (error) 784 goto out; 785 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 786 787 ttsetwater(tp); 788 789 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 790 (*linesw[tp->t_line].l_modem)(tp, 1); 791 } 792 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 793 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 794 rc->rc_dcdwaits++; 795 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 796 rc->rc_dcdwaits--; 797 if (error != 0) 798 goto out; 799 goto again; 800 } 801 error = (*linesw[tp->t_line].l_open)(dev, tp); 802 disc_optim(tp, &tp->t_termios, rc); 803 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 804 rc->rc_flags |= RC_ACTOUT; 805out: 806 (void) splx(s); 807 808 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 809 rc_hardclose(rc); 810 811 return error; 812} 813 814static int 815rcclose(dev, flag, mode, p) 816 dev_t dev; 817 int flag, mode; 818 struct proc *p; 819{ 820 register struct rc_chans *rc; 821 register struct tty *tp; 822 int s, unit = GET_UNIT(dev); 823 824 if (unit >= NRC * CD180_NCHAN) 825 return ENXIO; 826 rc = &rc_chans[unit]; 827 tp = rc->rc_tp; 828#ifdef RCDEBUG 829 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 830#endif 831 s = spltty(); 832 (*linesw[tp->t_line].l_close)(tp, flag); 833 disc_optim(tp, &tp->t_termios, rc); 834 rcstop(tp, FREAD | FWRITE); 835 rc_hardclose(rc); 836 ttyclose(tp); 837 splx(s); 838 return 0; 839} 840 841static void rc_hardclose(rc) 842register struct rc_chans *rc; 843{ 844 register int s, nec = rc->rc_rcb->rcb_addr; 845 register struct tty *tp = rc->rc_tp; 846 847 s = spltty(); 848 rcout(CD180_CAR, rc->rc_chan); 849 850 /* Disable rx/tx intrs */ 851 rcout(CD180_IER, rc->rc_ier = 0); 852 if ( (tp->t_cflag & HUPCL) 853 || !(rc->rc_flags & RC_ACTOUT) 854 && !(rc->rc_msvr & MSVR_CD) 855 && !(tp->t_cflag & CLOCAL) 856 || !(tp->t_state & TS_ISOPEN) 857 ) { 858 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 859 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 860 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 861 if (rc->rc_dtrwait) { 862 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 863 rc->rc_flags |= RC_DTR_OFF; 864 } 865 } 866 rc->rc_flags &= ~RC_ACTOUT; 867 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 868 wakeup(TSA_CARR_ON(tp)); 869 (void) splx(s); 870} 871 872/* Read from line */ 873static int 874rcread(dev, uio, flag) 875 dev_t dev; 876 struct uio *uio; 877 int flag; 878{ 879 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 880 881 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 882} 883 884/* Write to line */ 885static int 886rcwrite(dev, uio, flag) 887 dev_t dev; 888 struct uio *uio; 889 int flag; 890{ 891 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 892 893 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 894} 895 896/* Reset the bastard */ 897static void rc_hwreset(unit, nec, chipid) 898 register int unit, nec; 899 unsigned int chipid; 900{ 901 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 902 DELAY(20000); 903 WAITFORCCR(unit, -1); 904 905 rcout(RC_CTOUT, 0); /* Clear timeout */ 906 rcout(CD180_GIVR, chipid); 907 rcout(CD180_GICR, 0); 908 909 /* Set Prescaler Registers (1 msec) */ 910 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 911 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 912 913 /* Initialize Priority Interrupt Level Registers */ 914 rcout(CD180_PILR1, RC_PILR_MODEM); 915 rcout(CD180_PILR2, RC_PILR_TX); 916 rcout(CD180_PILR3, RC_PILR_RX); 917 918 /* Reset DTR */ 919 rcout(RC_DTREG, ~0); 920} 921 922/* Set channel parameters */ 923static int rc_param(tp, ts) 924 register struct tty *tp; 925 struct termios *ts; 926{ 927 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 928 register int nec = rc->rc_rcb->rcb_addr; 929 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 930 931 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 932 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 933 ) 934 return (EINVAL); 935 if (ts->c_ispeed == 0) 936 ts->c_ispeed = ts->c_ospeed; 937 odivs = RC_BRD(ts->c_ospeed); 938 idivs = RC_BRD(ts->c_ispeed); 939 940 s = spltty(); 941 942 /* Select channel */ 943 rcout(CD180_CAR, rc->rc_chan); 944 945 /* If speed == 0, hangup line */ 946 if (ts->c_ospeed == 0) { 947 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 948 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 949 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 950 } 951 952 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 953 cflag = ts->c_cflag; 954 iflag = ts->c_iflag; 955 lflag = ts->c_lflag; 956 957 if (idivs > 0) { 958 rcout(CD180_RBPRL, idivs & 0xFF); 959 rcout(CD180_RBPRH, idivs >> 8); 960 } 961 if (odivs > 0) { 962 rcout(CD180_TBPRL, odivs & 0xFF); 963 rcout(CD180_TBPRH, odivs >> 8); 964 } 965 966 /* set timeout value */ 967 if (ts->c_ispeed > 0) { 968 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 969 970 if ( !(lflag & ICANON) 971 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 972 && ts->c_cc[VTIME] * 10 > itm) 973 itm = ts->c_cc[VTIME] * 10; 974 975 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 976 } 977 978 switch (cflag & CSIZE) { 979 case CS5: val = COR1_5BITS; break; 980 case CS6: val = COR1_6BITS; break; 981 case CS7: val = COR1_7BITS; break; 982 default: 983 case CS8: val = COR1_8BITS; break; 984 } 985 if (cflag & PARENB) { 986 val |= COR1_NORMPAR; 987 if (cflag & PARODD) 988 val |= COR1_ODDP; 989 if (!(cflag & INPCK)) 990 val |= COR1_Ignore; 991 } else 992 val |= COR1_Ignore; 993 if (cflag & CSTOPB) 994 val |= COR1_2SB; 995 rcout(CD180_COR1, val); 996 997 /* Set FIFO threshold */ 998 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 999 inpflow = 0; 1000 if ( (iflag & IXOFF) 1001 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1002 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1003 || (iflag & IXANY) 1004 ) 1005 ) 1006 ) { 1007 inpflow = 1; 1008 val |= COR3_SCDE|COR3_FCT; 1009 } 1010 rcout(CD180_COR3, val); 1011 1012 /* Initialize on-chip automatic flow control */ 1013 val = 0; 1014 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1015 if (cflag & CCTS_OFLOW) { 1016 rc->rc_flags |= RC_CTSFLOW; 1017 val |= COR2_CtsAE; 1018 } else 1019 rc->rc_flags |= RC_SEND_RDY; 1020 if (tp->t_state & TS_TTSTOP) 1021 rc->rc_flags |= RC_OSUSP; 1022 else 1023 rc->rc_flags &= ~RC_OSUSP; 1024 if (cflag & CRTS_IFLOW) 1025 rc->rc_flags |= RC_RTSFLOW; 1026 else 1027 rc->rc_flags &= ~RC_RTSFLOW; 1028 1029 if (inpflow) { 1030 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1031 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1032 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1033 val |= COR2_TxIBE; 1034 if (iflag & IXANY) 1035 val |= COR2_IXM; 1036 } 1037 1038 rcout(CD180_COR2, rc->rc_cor2 = val); 1039 1040 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1041 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1042 1043 disc_optim(tp, ts, rc); 1044 1045 /* modem ctl */ 1046 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1047 if (cflag & CCTS_OFLOW) 1048 val |= MCOR1_CTSzd; 1049 rcout(CD180_MCOR1, val); 1050 1051 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1052 if (cflag & CCTS_OFLOW) 1053 val |= MCOR2_CTSod; 1054 rcout(CD180_MCOR2, val); 1055 1056 /* enable i/o and interrupts */ 1057 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1058 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1059 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1060 1061 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1062 if (cflag & CCTS_OFLOW) 1063 rc->rc_ier |= IER_CTS; 1064 if (cflag & CREAD) 1065 rc->rc_ier |= IER_RxData; 1066 if (tp->t_state & TS_BUSY) 1067 rc->rc_ier |= IER_TxRdy; 1068 if (ts->c_ospeed != 0) 1069 rc_modctl(rc, TIOCM_DTR, DMBIS); 1070 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1071 rc->rc_flags |= RC_SEND_RDY; 1072 rcout(CD180_IER, rc->rc_ier); 1073 (void) splx(s); 1074 return 0; 1075} 1076 1077/* Re-initialize board after bogus interrupts */ 1078static void rc_reinit(rcb) 1079struct rc_softc *rcb; 1080{ 1081 register struct rc_chans *rc, *rce; 1082 register int nec; 1083 1084 nec = rcb->rcb_addr; 1085 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1086 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1087 rce = rc + CD180_NCHAN; 1088 for (; rc < rce; rc++) 1089 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1090} 1091 1092static int 1093rcioctl(dev, cmd, data, flag, p) 1094dev_t dev; 1095int cmd, flag; 1096caddr_t data; 1097struct proc *p; 1098{ 1099 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1100 register int s, error; 1101 struct tty *tp = rc->rc_tp; 1102 1103 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1104 if (error >= 0) 1105 return (error); 1106 error = ttioctl(tp, cmd, data, flag); 1107 disc_optim(tp, &tp->t_termios, rc); 1108 if (error >= 0) 1109 return (error); 1110 s = spltty(); 1111 1112 switch (cmd) { 1113 case TIOCSBRK: 1114 rc->rc_pendcmd = CD180_C_SBRK; 1115 break; 1116 1117 case TIOCCBRK: 1118 rc->rc_pendcmd = CD180_C_EBRK; 1119 break; 1120 1121 case TIOCSDTR: 1122 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1123 break; 1124 1125 case TIOCCDTR: 1126 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1127 break; 1128 1129 case TIOCMGET: 1130 *(int *) data = rc_modctl(rc, 0, DMGET); 1131 break; 1132 1133 case TIOCMSET: 1134 (void) rc_modctl(rc, *(int *) data, DMSET); 1135 break; 1136 1137 case TIOCMBIC: 1138 (void) rc_modctl(rc, *(int *) data, DMBIC); 1139 break; 1140 1141 case TIOCMBIS: 1142 (void) rc_modctl(rc, *(int *) data, DMBIS); 1143 break; 1144 1145 case TIOCMSDTRWAIT: 1146 error = suser(p->p_ucred, &p->p_acflag); 1147 if (error != 0) { 1148 splx(s); 1149 return (error); 1150 } 1151 rc->rc_dtrwait = *(int *)data * hz / 100; 1152 break; 1153 1154 case TIOCMGDTRWAIT: 1155 *(int *)data = rc->rc_dtrwait * 100 / hz; 1156 break; 1157 1158 default: 1159 (void) splx(s); 1160 return ENOTTY; 1161 } 1162 (void) splx(s); 1163 return 0; 1164} 1165 1166 1167/* Modem control routines */ 1168 1169static int rc_modctl(rc, bits, cmd) 1170register struct rc_chans *rc; 1171int bits, cmd; 1172{ 1173 register int nec = rc->rc_rcb->rcb_addr; 1174 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1175 1176 rcout(CD180_CAR, rc->rc_chan); 1177 1178 switch (cmd) { 1179 case DMSET: 1180 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1181 ~(*dtr |= 1 << rc->rc_chan) : 1182 ~(*dtr &= ~(1 << rc->rc_chan))); 1183 msvr = rcin(CD180_MSVR); 1184 if (bits & TIOCM_RTS) 1185 msvr |= MSVR_RTS; 1186 else 1187 msvr &= ~MSVR_RTS; 1188 if (bits & TIOCM_DTR) 1189 msvr |= MSVR_DTR; 1190 else 1191 msvr &= ~MSVR_DTR; 1192 rcout(CD180_MSVR, msvr); 1193 break; 1194 1195 case DMBIS: 1196 if (bits & TIOCM_DTR) 1197 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1198 msvr = rcin(CD180_MSVR); 1199 if (bits & TIOCM_RTS) 1200 msvr |= MSVR_RTS; 1201 if (bits & TIOCM_DTR) 1202 msvr |= MSVR_DTR; 1203 rcout(CD180_MSVR, msvr); 1204 break; 1205 1206 case DMGET: 1207 bits = TIOCM_LE; 1208 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1209 1210 if (msvr & MSVR_RTS) 1211 bits |= TIOCM_RTS; 1212 if (msvr & MSVR_CTS) 1213 bits |= TIOCM_CTS; 1214 if (msvr & MSVR_DSR) 1215 bits |= TIOCM_DSR; 1216 if (msvr & MSVR_DTR) 1217 bits |= TIOCM_DTR; 1218 if (msvr & MSVR_CD) 1219 bits |= TIOCM_CD; 1220 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1221 bits |= TIOCM_RI; 1222 return bits; 1223 1224 case DMBIC: 1225 if (bits & TIOCM_DTR) 1226 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1227 msvr = rcin(CD180_MSVR); 1228 if (bits & TIOCM_RTS) 1229 msvr &= ~MSVR_RTS; 1230 if (bits & TIOCM_DTR) 1231 msvr &= ~MSVR_DTR; 1232 rcout(CD180_MSVR, msvr); 1233 break; 1234 } 1235 rc->rc_msvr = rcin(CD180_MSVR); 1236 return 0; 1237} 1238 1239/* Test the board. */ 1240int rc_test(nec, unit) 1241 register int nec; 1242 int unit; 1243{ 1244 int chan = 0; 1245 int i = 0, rcnt, old_level; 1246 unsigned int iack, chipid; 1247 unsigned short divs; 1248 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1249#define CTLEN 8 1250#define ERR(s) { \ 1251 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1252 (void) splx(old_level); return 1; } 1253 1254 struct rtest { 1255 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1256 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1257 int rxptr; /* RX pointer */ 1258 int txptr; /* TX pointer */ 1259 } tchans[CD180_NCHAN]; 1260 1261 old_level = spltty(); 1262 1263 chipid = RC_FAKEID; 1264 1265 /* First, reset board to inital state */ 1266 rc_hwreset(unit, nec, chipid); 1267 1268 divs = RC_BRD(19200); 1269 1270 /* Initialize channels */ 1271 for (chan = 0; chan < CD180_NCHAN; chan++) { 1272 1273 /* Select and reset channel */ 1274 rcout(CD180_CAR, chan); 1275 CCRCMD(unit, chan, CCR_ResetChan); 1276 WAITFORCCR(unit, chan); 1277 1278 /* Set speed */ 1279 rcout(CD180_RBPRL, divs & 0xFF); 1280 rcout(CD180_RBPRH, divs >> 8); 1281 rcout(CD180_TBPRL, divs & 0xFF); 1282 rcout(CD180_TBPRH, divs >> 8); 1283 1284 /* set timeout value */ 1285 rcout(CD180_RTPR, 0); 1286 1287 /* Establish local loopback */ 1288 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1289 rcout(CD180_COR2, COR2_LLM); 1290 rcout(CD180_COR3, CD180_NFIFO); 1291 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1292 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1293 WAITFORCCR(unit, chan); 1294 rcout(CD180_MSVR, MSVR_RTS); 1295 1296 /* Fill TXBUF with test data */ 1297 for (i = 0; i < CD180_NFIFO; i++) { 1298 tchans[chan].txbuf[i] = ctest[i]; 1299 tchans[chan].rxbuf[i] = 0; 1300 } 1301 tchans[chan].txptr = tchans[chan].rxptr = 0; 1302 1303 /* Now, start transmit */ 1304 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1305 } 1306 /* Pseudo-interrupt poll stuff */ 1307 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1308 i = ~(rcin(RC_BSR)); 1309 if (i & RC_BSR_TOUT) 1310 ERR(("BSR timeout bit set\n")) 1311 else if (i & RC_BSR_TXINT) { 1312 iack = rcin(RC_PILR_TX); 1313 if (iack != (GIVR_IT_TDI | chipid)) 1314 ERR(("Bad TX intr ack (%02x != %02x)\n", 1315 iack, GIVR_IT_TDI | chipid)); 1316 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1317 /* If no more data to transmit, disable TX intr */ 1318 if (tchans[chan].txptr >= CD180_NFIFO) { 1319 iack = rcin(CD180_IER); 1320 rcout(CD180_IER, iack & ~IER_TxMpty); 1321 } else { 1322 for (iack = tchans[chan].txptr; 1323 iack < CD180_NFIFO; iack++) 1324 rcout(CD180_TDR, 1325 tchans[chan].txbuf[iack]); 1326 tchans[chan].txptr = iack; 1327 } 1328 rcout(CD180_EOIR, 0); 1329 } else if (i & RC_BSR_RXINT) { 1330 u_char ucnt; 1331 1332 iack = rcin(RC_PILR_RX); 1333 if (iack != (GIVR_IT_RGDI | chipid) && 1334 iack != (GIVR_IT_REI | chipid)) 1335 ERR(("Bad RX intr ack (%02x != %02x)\n", 1336 iack, GIVR_IT_RGDI | chipid)) 1337 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1338 ucnt = rcin(CD180_RDCR) & 0xF; 1339 while (ucnt-- > 0) { 1340 iack = rcin(CD180_RCSR); 1341 if (iack & RCSR_Timeout) 1342 break; 1343 if (iack & 0xF) 1344 ERR(("Bad char chan %d (RCSR = %02X)\n", 1345 chan, iack)) 1346 if (tchans[chan].rxptr > CD180_NFIFO) 1347 ERR(("Got extra chars chan %d\n", 1348 chan)) 1349 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1350 rcin(CD180_RDR); 1351 } 1352 rcout(CD180_EOIR, 0); 1353 } 1354 rcout(RC_CTOUT, 0); 1355 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1356 if (tchans[chan].rxptr >= CD180_NFIFO) 1357 iack++; 1358 if (iack == CD180_NCHAN) 1359 break; 1360 } 1361 for (chan = 0; chan < CD180_NCHAN; chan++) { 1362 /* Select and reset channel */ 1363 rcout(CD180_CAR, chan); 1364 CCRCMD(unit, chan, CCR_ResetChan); 1365 } 1366 1367 if (!rcnt) 1368 ERR(("looses characters during local loopback\n")) 1369 /* Now, check data */ 1370 for (chan = 0; chan < CD180_NCHAN; chan++) 1371 for (i = 0; i < CD180_NFIFO; i++) 1372 if (ctest[i] != tchans[chan].rxbuf[i]) 1373 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1374 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1375 (void) splx(old_level); 1376 return 0; 1377} 1378 1379#ifdef RCDEBUG 1380static void printrcflags(rc, comment) 1381struct rc_chans *rc; 1382char *comment; 1383{ 1384 u_short f = rc->rc_flags; 1385 register int nec = rc->rc_rcb->rcb_addr; 1386 1387 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1388 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1389 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1390 (f & RC_ACTOUT) ?"ACTOUT " :"", 1391 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1392 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1393 (f & RC_DORXFER)?"DORXFER " :"", 1394 (f & RC_DOXXFER)?"DOXXFER " :"", 1395 (f & RC_MODCHG) ?"MODCHG " :"", 1396 (f & RC_OSUSP) ?"OSUSP " :"", 1397 (f & RC_OSBUSY) ?"OSBUSY " :"", 1398 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1399 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1400 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1401 1402 rcout(CD180_CAR, rc->rc_chan); 1403 1404 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1405 rc->rc_rcb->rcb_unit, rc->rc_chan, 1406 rcin(CD180_MSVR), 1407 rcin(CD180_IER), 1408 rcin(CD180_CCSR)); 1409} 1410#endif /* RCDEBUG */ 1411 1412static struct tty * 1413rcdevtotty(dev) 1414 dev_t dev; 1415{ 1416 int unit; 1417 1418 unit = GET_UNIT(dev); 1419 if (unit >= NRC * CD180_NCHAN) 1420 return NULL; 1421 return (&rc_tty[unit]); 1422} 1423 1424static void 1425rc_dtrwakeup(chan) 1426 void *chan; 1427{ 1428 struct rc_chans *rc; 1429 1430 rc = (struct rc_chans *)chan; 1431 rc->rc_flags &= ~RC_DTR_OFF; 1432 wakeup(&rc->rc_dtrwait); 1433} 1434 1435static void 1436rc_discard_output(rc) 1437 struct rc_chans *rc; 1438{ 1439 disable_intr(); 1440 if (rc->rc_flags & RC_DOXXFER) { 1441 rc_scheduled_event -= LOTS_OF_EVENTS; 1442 rc->rc_flags &= ~RC_DOXXFER; 1443 } 1444 rc->rc_optr = rc->rc_obufend; 1445 rc->rc_tp->t_state &= ~TS_BUSY; 1446 enable_intr(); 1447 ttwwakeup(rc->rc_tp); 1448} 1449 1450static void 1451rc_wakeup(chan) 1452 void *chan; 1453{ 1454 timeout(rc_wakeup, (caddr_t)NULL, 1); 1455 1456 if (rc_scheduled_event != 0) { 1457 int s; 1458 1459 s = splsofttty(); 1460 rcpoll(); 1461 splx(s); 1462 } 1463} 1464 1465static void 1466disc_optim(tp, t, rc) 1467 struct tty *tp; 1468 struct termios *t; 1469 struct rc_chans *rc; 1470{ 1471 1472 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1473 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1474 && (!(t->c_iflag & PARMRK) 1475 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1476 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1477 && linesw[tp->t_line].l_rint == ttyinput) 1478 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1479 else 1480 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1481 if (tp->t_line == SLIPDISC) 1482 rc->rc_hotchar = 0xc0; 1483 else if (tp->t_line == PPPDISC) 1484 rc->rc_hotchar = 0x7e; 1485 else 1486 rc->rc_hotchar = 0; 1487} 1488 1489static void 1490rc_wait0(nec, unit, chan, line) 1491 int nec, unit, chan, line; 1492{ 1493 int rcnt; 1494 1495 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1496 DELAY(30); 1497 if (rcnt == 0) 1498 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1499 unit, chan, line); 1500} 1501 1502static rc_devsw_installed = 0; 1503 1504static void rc_drvinit(void *unused) 1505{ 1506 dev_t dev; 1507 1508 if( ! rc_devsw_installed ) { 1509 dev = makedev(CDEV_MAJOR, 0); 1510 cdevsw_add(&dev,&rc_cdevsw, NULL); 1511 rc_devsw_installed = 1; 1512 } 1513} 1514 1515SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1516 1517 1518#endif /* NRC */ 1519