rc.c revision 14441
18471Sache/* 28471Sache * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 38471Sache * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 48471Sache * All rights reserved. 58471Sache * 68471Sache * Redistribution and use in source and binary forms, with or without 78471Sache * modification, are permitted provided that the following conditions 88471Sache * are met: 98471Sache * 1. Redistributions of source code must retain the above copyright 108471Sache * notice, this list of conditions and the following disclaimer. 118471Sache * 2. Redistributions in binary form must reproduce the above copyright 128471Sache * notice, this list of conditions and the following disclaimer in the 138471Sache * documentation and/or other materials provided with the distribution. 148471Sache * 158471Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 168471Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 178471Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 188471Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 198471Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 208471Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 218471Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 228471Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 238471Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 248471Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 258471Sache * SUCH DAMAGE. 268471Sache */ 278471Sache 288471Sache/* 298471Sache * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 308471Sache * 318471Sache */ 328471Sache 338471Sache#include "rc.h" 348471Sache#if NRC > 0 358471Sache 369232Sache/*#define RCDEBUG*/ 378471Sache 388471Sache#include <sys/param.h> 398471Sache#include <sys/systm.h> 408471Sache#include <sys/ioctl.h> 418471Sache#include <sys/tty.h> 428471Sache#include <sys/proc.h> 438471Sache#include <sys/conf.h> 448471Sache#include <sys/dkstat.h> 458471Sache#include <sys/file.h> 468471Sache#include <sys/uio.h> 478471Sache#include <sys/kernel.h> 488471Sache#include <sys/syslog.h> 498471Sache#include <sys/devconf.h> 5012675Sjulian#ifdef DEVFS 5112675Sjulian#include <sys/devfsext.h> 5212675Sjulian#endif /*DEVFS*/ 538471Sache 548471Sache#include <machine/clock.h> 558471Sache 568471Sache#include <i386/isa/isa.h> 578471Sache#include <i386/isa/isa_device.h> 588471Sache#include <i386/isa/sioreg.h> 598471Sache 608471Sache#include <i386/isa/ic/cd180.h> 618471Sache#include <i386/isa/rcreg.h> 628471Sache 6312502Sjulian 648471Sache/* Prototypes */ 6512724Sphkstatic int rcprobe __P((struct isa_device *)); 6612724Sphkstatic int rcattach __P((struct isa_device *)); 678471Sache 6812071Sbde/*- 6912071Sbde * This space intentionally left blank to stop __LINE__ from screwing up 7012071Sbde * regression tests :-(. 7112071Sbde * 7212071Sbde * 7312080Sbde * 7412071Sbde */ 758471Sachevoid rcpoll __P((void)); 768471Sache 778471Sache#define rcin(port) RC_IN (nec, port) 788471Sache#define rcout(port,v) RC_OUT (nec, port, v) 798471Sache 809232Sache#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 819232Sache#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 828471Sache 839232Sache#define RC_IBUFSIZE 256 849232Sache#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 859232Sache#define RC_OBUFSIZE 512 868471Sache#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 878471Sache#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 888471Sache#define LOTS_OF_EVENTS 64 898471Sache 908471Sache#define RC_FAKEID 0x10 918471Sache 929232Sache#define RC_PROBED 1 939232Sache#define RC_ATTACHED 2 949232Sache 958471Sache#define GET_UNIT(dev) (minor(dev) & 0x3F) 968471Sache#define CALLOUT(dev) (minor(dev) & 0x80) 978471Sache 988471Sache/* For isa routines */ 998471Sachestruct isa_driver rcdriver = { 1008471Sache rcprobe, rcattach, "rc" 1018471Sache}; 1028471Sache 10312675Sjulianstatic d_open_t rcopen; 10412675Sjulianstatic d_close_t rcclose; 10512675Sjulianstatic d_read_t rcread; 10612675Sjulianstatic d_write_t rcwrite; 10712675Sjulianstatic d_ioctl_t rcioctl; 10812675Sjulianstatic d_stop_t rcstop; 10912731Sbdestatic d_devtotty_t rcdevtotty; 11012675Sjulian 11112675Sjulian#define CDEV_MAJOR 63 11212678Sphkstatic struct cdevsw rc_cdevsw = 11312675Sjulian { rcopen, rcclose, rcread, rcwrite, /*63*/ 11412743Sbde rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 11512675Sjulian ttselect, nommap, NULL, "rc", NULL, -1 }; 11612675Sjulian 1178471Sache/* Per-board structure */ 1188471Sachestatic struct rc_softc { 1199232Sache u_int rcb_probed; /* 1 - probed, 2 - attached */ 1208471Sache u_int rcb_addr; /* Base I/O addr */ 1218471Sache u_int rcb_unit; /* unit # */ 1228471Sache u_char rcb_dtr; /* DTR status */ 1238471Sache struct rc_chans *rcb_baserc; /* base rc ptr */ 1248471Sache} rc_softc[NRC]; 1258471Sache 1268471Sache/* Per-channel structure */ 1278471Sachestatic struct rc_chans { 1288471Sache struct rc_softc *rc_rcb; /* back ptr */ 1298471Sache u_short rc_flags; /* Misc. flags */ 1308471Sache int rc_chan; /* Channel # */ 1318471Sache u_char rc_ier; /* intr. enable reg */ 1328471Sache u_char rc_msvr; /* modem sig. status */ 1338471Sache u_char rc_cor2; /* options reg */ 1348471Sache u_char rc_pendcmd; /* special cmd pending */ 1358471Sache u_int rc_dtrwait; /* dtr timeout */ 1368471Sache u_int rc_dcdwaits; /* how many waits DCD in open */ 1378471Sache u_char rc_hotchar; /* end packed optimize */ 1388471Sache struct tty *rc_tp; /* tty struct */ 1398471Sache u_char *rc_iptr; /* Chars input buffer */ 1408471Sache u_char *rc_hiwat; /* hi-water mark */ 1418471Sache u_char *rc_bufend; /* end of buffer */ 1428471Sache u_char *rc_optr; /* ptr in output buf */ 1438471Sache u_char *rc_obufend; /* end of output buf */ 1448471Sache u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 1458471Sache u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 14612675Sjulian#ifdef DEVFS 14712675Sjulian void *devfs_token; 14812675Sjulian#endif 1498471Sache} rc_chans[NRC * CD180_NCHAN]; 1508471Sache 1518471Sachestatic int rc_scheduled_event = 0; 1528471Sache 1538471Sache/* for pstat -t */ 15412724Sphkstatic struct tty rc_tty[NRC * CD180_NCHAN]; 15512724Sphkstatic int nrc_tty = NRC * CD180_NCHAN; 1568471Sache 1578471Sache/* Flags */ 1589232Sache#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 1599232Sache#define RC_ACTOUT 0x0002 /* Dial-out port active */ 1609232Sache#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 1619232Sache#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 1629232Sache#define RC_DORXFER 0x0010 /* RXFER event planned */ 1639232Sache#define RC_DOXXFER 0x0020 /* XXFER event planned */ 1649232Sache#define RC_MODCHG 0x0040 /* Modem status changed */ 1659232Sache#define RC_OSUSP 0x0080 /* Output suspended */ 1669232Sache#define RC_OSBUSY 0x0100 /* start() routine in progress */ 1679232Sache#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 1689232Sache#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 1699232Sache#define RC_SEND_RDY 0x0800 /* ready to send */ 1708471Sache 1718471Sache/* Table for translation of RCSR status bits to internal form */ 1728471Sachestatic int rc_rcsrt[16] = { 1738471Sache 0, TTY_OE, TTY_FE, 1748471Sache TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 1758471Sache TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 1768471Sache TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 1778471Sache TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 1788471Sache TTY_BI|TTY_PE|TTY_FE|TTY_OE 1798471Sache}; 1808471Sache 1818471Sache/* Static prototypes */ 1829232Sachestatic void rc_hwreset __P((int, int, unsigned int)); 1838471Sachestatic int rc_test __P((int, int)); 1848471Sachestatic void rc_discard_output __P((struct rc_chans *)); 1858471Sachestatic void rc_hardclose __P((struct rc_chans *)); 1868471Sachestatic int rc_modctl __P((struct rc_chans *, int, int)); 1878471Sachestatic void rc_start __P((struct tty *)); 1888471Sachestatic int rc_param __P((struct tty *, struct termios *)); 1898471Sachestatic void rc_registerdev __P((struct isa_device *id)); 1909232Sachestatic void rc_reinit __P((struct rc_softc *)); 1919232Sache#ifdef RCDEBUG 1929232Sachestatic void printrcflags(); 1939232Sache#endif 1948471Sachestatic timeout_t rc_dtrwakeup; 1958471Sachestatic timeout_t rc_wakeup; 1968471Sachestatic void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 1979232Sachestatic void rc_wait0 __P((int nec, int unit, int chan, int line)); 1988471Sache 1998471Sache/**********************************************/ 2008471Sache 2018471Sache/* Quick device probing */ 20212724Sphkstatic int 20312724Sphkrcprobe(dvp) 2048471Sache struct isa_device *dvp; 2058471Sache{ 2068471Sache int irq = ffs(dvp->id_irq) - 1; 2078471Sache register int nec = dvp->id_iobase; 2088471Sache 2098471Sache if (dvp->id_unit > NRC) 2108471Sache return 0; 2118471Sache if (!RC_VALIDADDR(nec)) { 2128471Sache printf("rc%d: illegal base address %x\n", nec); 2138471Sache return 0; 2148471Sache } 2158471Sache if (!RC_VALIDIRQ(irq)) { 2168471Sache printf("rc%d: illegal IRQ value %d\n", irq); 2178471Sache return 0; 2188471Sache } 2198471Sache rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 2208471Sache rcout(CD180_PPRH, 0x11); 2218471Sache if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 2228471Sache return 0; 2238471Sache /* Now, test the board more thoroughly, with diagnostic */ 2248471Sache if (rc_test(nec, dvp->id_unit)) 2258471Sache return 0; 2269232Sache rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 2279232Sache 2289232Sache return 0xF; 2298471Sache} 2308471Sache 2318471Sachestatic struct kern_devconf kdc_rc[NRC] = { { 2328471Sache 0, 0, 0, /* filled in by dev_attach */ 2338471Sache "rc", 0, { MDDT_ISA, 0, "tty" }, 2348471Sache isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 2358471Sache &kdc_isa0, /* parent */ 2368471Sache 0, /* parentdata */ 2378471Sache DC_UNCONFIGURED, /* state */ 2388471Sache "RISCom/8 multiport card", 2398471Sache DC_CLS_SERIAL /* class */ 2408471Sache} }; 2418471Sache 2428471Sachestatic void 2438471Sacherc_registerdev(id) 2448471Sache struct isa_device *id; 2458471Sache{ 2468471Sache int unit; 2478471Sache 2488471Sache unit = id->id_unit; 2498471Sache if (unit != 0) 2508471Sache kdc_rc[unit] = kdc_rc[0]; 2518471Sache kdc_rc[unit].kdc_unit = unit; 2528471Sache kdc_rc[unit].kdc_isa = id; 2538471Sache kdc_rc[unit].kdc_state = DC_UNKNOWN; 2548471Sache dev_attach(&kdc_rc[unit]); 2558471Sache} 2568471Sache 25712724Sphkstatic int 25812724Sphkrcattach(dvp) 2598471Sache struct isa_device *dvp; 2608471Sache{ 2618471Sache register int i, chan, nec = dvp->id_iobase; 2628471Sache struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 2638471Sache struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 2648471Sache static int rc_wakeup_started = 0; 2659232Sache struct tty *tp; 26612675Sjulian char name[32]; 2678471Sache 2688471Sache /* Thorooughly test the device */ 2699232Sache if (rcb->rcb_probed != RC_PROBED) 2708471Sache return 0; 2718471Sache rcb->rcb_addr = nec; 2728471Sache rcb->rcb_dtr = 0; 2738471Sache rcb->rcb_baserc = rc; 2748471Sache /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 2758471Sache printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 2768471Sache CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 2778471Sache 2788471Sache rc_registerdev(dvp); 2798471Sache 2808471Sache for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 2818471Sache rc->rc_rcb = rcb; 2828471Sache rc->rc_chan = chan; 2838471Sache rc->rc_iptr = rc->rc_ibuf; 2848471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 2858471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 2868471Sache rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 2878471Sache rc->rc_cor2 = rc->rc_pendcmd = 0; 2888471Sache rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 2898471Sache rc->rc_dtrwait = 3 * hz; 2908471Sache rc->rc_dcdwaits= 0; 2918471Sache rc->rc_hotchar = 0; 2929232Sache tp = rc->rc_tp = &rc_tty[chan]; 2939232Sache ttychars(tp); 2949232Sache tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 2959232Sache tp->t_cflag = TTYDEF_CFLAG; 2969232Sache tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 29712675Sjulian#ifdef DEVFS 29812675Sjulian/* FIX THIS to reflect real devices */ 29912675Sjulian sprintf(name,"rc%d.%d",dvp->id_unit,chan); 30012675Sjulian rc->devfs_token = devfs_add_devsw( "/", name, 30112675Sjulian &rc_cdevsw,(dvp->id_unit * CD180_NCHAN) + chan , 30212675Sjulian DV_CHR, 0, 0, 0600); 30312675Sjulian#endif 3048471Sache } 3059232Sache rcb->rcb_probed = RC_ATTACHED; 3068471Sache if (!rc_wakeup_started) { 3078471Sache rc_wakeup((void *)NULL); 3088471Sache rc_wakeup_started = 0; 3098471Sache } 3108471Sache return 1; 3118471Sache} 3128471Sache 3138471Sache/* RC interrupt handling */ 3148471Sachevoid rcintr(unit) 3158471Sache int unit; 3168471Sache{ 3178471Sache register struct rc_softc *rcb = &rc_softc[unit]; 3188471Sache register struct rc_chans *rc; 3199232Sache register int nec, resid; 3209232Sache register u_char val, iack, bsr, ucnt, *optr; 3219232Sache int good_data, t_state; 3228471Sache 3239232Sache if (rcb->rcb_probed != RC_ATTACHED) { 3249232Sache printf("rc%d: bogus interrupt\n", unit); 3259232Sache return; 3269232Sache } 3278471Sache nec = rcb->rcb_addr; 3288471Sache 3298471Sache bsr = ~(rcin(RC_BSR)); 3308471Sache 3319232Sache if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 3329232Sache printf("rc%d: extra interrupt\n", unit); 3339232Sache rcout(CD180_EOIR, 0); 3349232Sache return; 3359232Sache } 3369232Sache 3379232Sache while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 3389232Sache#ifdef RCDEBUG_DETAILED 3399232Sache printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 3409232Sache (bsr & RC_BSR_TOUT)?"TOUT ":"", 3419232Sache (bsr & RC_BSR_RXINT)?"RXINT ":"", 3429232Sache (bsr & RC_BSR_TXINT)?"TXINT ":"", 3439232Sache (bsr & RC_BSR_MOINT)?"MOINT":""); 3448471Sache#endif 3459232Sache if (bsr & RC_BSR_TOUT) { 3469232Sache printf("rc%d: hardware failure, reset board\n", unit); 3479232Sache rcout(RC_CTOUT, 0); 3489232Sache rc_reinit(rcb); 3499232Sache return; 3508471Sache } 3519232Sache if (bsr & RC_BSR_RXINT) { 3529232Sache iack = rcin(RC_PILR_RX); 3539232Sache good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 3549232Sache if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 3559232Sache printf("rc%d: fake rxint: %02x\n", unit, iack); 3569232Sache goto more_intrs; 3579232Sache } 3589232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 3599232Sache t_state = rc->rc_tp->t_state; 3609232Sache /* Do RTS flow control stuff */ 3619232Sache if ( (rc->rc_flags & RC_RTSFLOW) 3629232Sache || !(t_state & TS_ISOPEN) 3639232Sache ) { 3649232Sache if ( ( !(t_state & TS_ISOPEN) 3659232Sache || (t_state & TS_TBLOCK) 3669232Sache ) 3679232Sache && (rc->rc_msvr & MSVR_RTS) 3689232Sache ) 3699232Sache rcout(CD180_MSVR, 3709232Sache rc->rc_msvr &= ~MSVR_RTS); 3719232Sache else if (!(rc->rc_msvr & MSVR_RTS)) 3729232Sache rcout(CD180_MSVR, 3739232Sache rc->rc_msvr |= MSVR_RTS); 3749232Sache } 3759232Sache ucnt = rcin(CD180_RDCR) & 0xF; 3769232Sache resid = 0; 3778471Sache 3789232Sache if (t_state & TS_ISOPEN) { 3799232Sache /* check for input buffer overflow */ 3809232Sache if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 3819232Sache resid = ucnt; 3829232Sache ucnt = rc->rc_bufend - rc->rc_iptr; 3839232Sache resid -= ucnt; 3849232Sache if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 3859232Sache rc->rc_flags |= RC_WAS_BUFOVFL; 3869232Sache rc_scheduled_event++; 3879232Sache } 3888471Sache } 3899232Sache optr = rc->rc_iptr; 3909232Sache /* check foor good data */ 3919232Sache if (good_data) { 3929232Sache while (ucnt-- > 0) { 3939232Sache val = rcin(CD180_RDR); 3949232Sache optr[0] = val; 3959232Sache optr[INPUT_FLAGS_SHIFT] = 0; 3969232Sache optr++; 3978471Sache rc_scheduled_event++; 3989232Sache if (val != 0 && val == rc->rc_hotchar) 3998471Sache setsofttty(); 4008471Sache } 4019232Sache } else { 4029232Sache /* Store also status data */ 4039232Sache while (ucnt-- > 0) { 4049232Sache iack = rcin(CD180_RCSR); 4059232Sache if (iack & RCSR_Timeout) 4069232Sache break; 4079232Sache if ( (iack & RCSR_OE) 4089232Sache && !(rc->rc_flags & RC_WAS_SILOVFL)) { 4099232Sache rc->rc_flags |= RC_WAS_SILOVFL; 4109232Sache rc_scheduled_event++; 4119232Sache } 4129232Sache val = rcin(CD180_RDR); 4139232Sache /* 4149232Sache Don't store PE if IGNPAR and BREAK if IGNBRK, 4159232Sache this hack allows "raw" tty optimization 4169232Sache works even if IGN* is set. 4179232Sache */ 4189232Sache if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 4199232Sache || (!(iack & (RCSR_PE|RCSR_FE)) 4209232Sache || !(rc->rc_tp->t_iflag & IGNPAR)) 4219232Sache && (!(iack & RCSR_Break) 4229232Sache || !(rc->rc_tp->t_iflag & IGNBRK))) { 4239232Sache if ( (iack & (RCSR_PE|RCSR_FE)) 4249232Sache && (t_state & TS_CAN_BYPASS_L_RINT) 4259232Sache && ((iack & RCSR_FE) 4269232Sache || (iack & RCSR_PE) 4279232Sache && (rc->rc_tp->t_iflag & INPCK))) 4289232Sache val = 0; 4299232Sache else if (val != 0 && val == rc->rc_hotchar) 4309232Sache setsofttty(); 4319232Sache optr[0] = val; 4329232Sache optr[INPUT_FLAGS_SHIFT] = iack; 4339232Sache optr++; 4349232Sache rc_scheduled_event++; 4359232Sache } 4369232Sache } 4378471Sache } 4389232Sache rc->rc_iptr = optr; 4399232Sache rc->rc_flags |= RC_DORXFER; 4409232Sache } else 4419232Sache resid = ucnt; 4429232Sache /* Clear FIFO if necessary */ 4439232Sache while (resid-- > 0) { 4449232Sache if (!good_data) 4459232Sache iack = rcin(CD180_RCSR); 4469232Sache else 4479232Sache iack = 0; 4489232Sache if (iack & RCSR_Timeout) 4499232Sache break; 4509232Sache (void) rcin(CD180_RDR); 4518471Sache } 4529232Sache goto more_intrs; 4538471Sache } 4549232Sache if (bsr & RC_BSR_MOINT) { 4559232Sache iack = rcin(RC_PILR_MODEM); 4569232Sache if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 4579232Sache printf("rc%d: fake moint: %02x\n", unit, iack); 4589232Sache goto more_intrs; 4599232Sache } 4609232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4619232Sache iack = rcin(CD180_MCR); 4629232Sache rc->rc_msvr = rcin(CD180_MSVR); 4639232Sache rcout(CD180_MCR, 0); 4648471Sache#ifdef RCDEBUG 4659232Sache printrcflags(rc, "moint"); 4668471Sache#endif 4679232Sache if (rc->rc_flags & RC_CTSFLOW) { 4689232Sache if (rc->rc_msvr & MSVR_CTS) 4699232Sache rc->rc_flags |= RC_SEND_RDY; 4709232Sache else 4719232Sache rc->rc_flags &= ~RC_SEND_RDY; 4729232Sache } else 4738471Sache rc->rc_flags |= RC_SEND_RDY; 4749232Sache if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 4759232Sache rc_scheduled_event += LOTS_OF_EVENTS; 4769232Sache rc->rc_flags |= RC_MODCHG; 4779232Sache setsofttty(); 4789232Sache } 4799232Sache goto more_intrs; 4808471Sache } 4819232Sache if (bsr & RC_BSR_TXINT) { 4829232Sache iack = rcin(RC_PILR_TX); 4839232Sache if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 4849232Sache printf("rc%d: fake txint: %02x\n", unit, iack); 4859232Sache goto more_intrs; 4869232Sache } 4879232Sache rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 4889232Sache if ( (rc->rc_flags & RC_OSUSP) 4899232Sache || !(rc->rc_flags & RC_SEND_RDY) 4909232Sache ) 4919232Sache goto more_intrs; 4929232Sache /* Handle breaks and other stuff */ 4939232Sache if (rc->rc_pendcmd) { 4949232Sache rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 4959232Sache rcout(CD180_TDR, CD180_C_ESC); 4969232Sache rcout(CD180_TDR, rc->rc_pendcmd); 4979232Sache rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 4989232Sache rc->rc_pendcmd = 0; 4999232Sache goto more_intrs; 5009232Sache } 5019232Sache optr = rc->rc_optr; 5029232Sache resid = rc->rc_obufend - optr; 5039232Sache if (resid > CD180_NFIFO) 5049232Sache resid = CD180_NFIFO; 5059232Sache while (resid-- > 0) 5069232Sache rcout(CD180_TDR, *optr++); 5079232Sache rc->rc_optr = optr; 5088471Sache 5099232Sache /* output completed? */ 5109232Sache if (optr >= rc->rc_obufend) { 5119232Sache rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 5128471Sache#ifdef RCDEBUG 5139232Sache printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 5148471Sache#endif 5159232Sache if (!(rc->rc_flags & RC_DOXXFER)) { 5169232Sache rc_scheduled_event += LOTS_OF_EVENTS; 5179232Sache rc->rc_flags |= RC_DOXXFER; 5189232Sache setsofttty(); 5199232Sache } 5209232Sache } 5218471Sache } 5229232Sache more_intrs: 5239232Sache rcout(CD180_EOIR, 0); /* end of interrupt */ 5249232Sache rcout(RC_CTOUT, 0); 5259232Sache bsr = ~(rcin(RC_BSR)); 5268471Sache } 5278471Sache} 5288471Sache 5298471Sache/* Feed characters to output buffer */ 5308471Sachestatic void rc_start(tp) 5318471Sacheregister struct tty *tp; 5328471Sache{ 5338471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 5348471Sache register int nec = rc->rc_rcb->rcb_addr, s; 5358471Sache 5368471Sache if (rc->rc_flags & RC_OSBUSY) 5378471Sache return; 5388471Sache s = spltty(); 5398471Sache rc->rc_flags |= RC_OSBUSY; 5408471Sache disable_intr(); 5418471Sache if (tp->t_state & TS_TTSTOP) 5428471Sache rc->rc_flags |= RC_OSUSP; 5438471Sache else 5448471Sache rc->rc_flags &= ~RC_OSUSP; 5458471Sache /* Do RTS flow control stuff */ 5469232Sache if ( (rc->rc_flags & RC_RTSFLOW) 5479232Sache && (tp->t_state & TS_TBLOCK) 5489232Sache && (rc->rc_msvr & MSVR_RTS) 5499232Sache ) { 5509232Sache rcout(CD180_CAR, rc->rc_chan); 5519232Sache rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 5529232Sache } else if (!(rc->rc_msvr & MSVR_RTS)) { 5539232Sache rcout(CD180_CAR, rc->rc_chan); 5549232Sache rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 5558471Sache } 5568471Sache enable_intr(); 5578471Sache if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 5588471Sache goto out; 5598471Sache#ifdef RCDEBUG 5608471Sache printrcflags(rc, "rcstart"); 5618471Sache#endif 5629626Sbde ttwwakeup(tp); 5638471Sache#ifdef RCDEBUG 5649232Sache printf("rcstart: outq = %d obuf = %d\n", 5658471Sache tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 5668471Sache#endif 5679232Sache if (tp->t_state & TS_BUSY) 5688471Sache goto out; /* output still in progress ... */ 5698471Sache 5708471Sache if (tp->t_outq.c_cc > 0) { 5718471Sache u_int ocnt; 5728471Sache 5738471Sache tp->t_state |= TS_BUSY; 5748471Sache ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 5758471Sache disable_intr(); 5768471Sache rc->rc_optr = rc->rc_obuf; 5779232Sache rc->rc_obufend = rc->rc_optr + ocnt; 5788471Sache enable_intr(); 5799232Sache if (!(rc->rc_ier & IER_TxRdy)) { 5808471Sache#ifdef RCDEBUG 5819232Sache printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 5828471Sache#endif 5838471Sache rcout(CD180_CAR, rc->rc_chan); 5849232Sache rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 5858471Sache } 5868471Sache } 5878471Sacheout: 5888471Sache rc->rc_flags &= ~RC_OSBUSY; 5898471Sache (void) splx(s); 5908471Sache} 5918471Sache 5928471Sache/* Handle delayed events. */ 5938471Sachevoid rcpoll() 5948471Sache{ 5958471Sache register struct rc_chans *rc; 5968471Sache register struct rc_softc *rcb; 5978471Sache register u_char *tptr, *eptr; 5988471Sache register int s; 5998471Sache register struct tty *tp; 6008471Sache register int chan, icnt, c, nec, unit; 6018471Sache 6028471Sache if (rc_scheduled_event == 0) 6038471Sache return; 6048471Sacherepeat: 6058471Sache for (unit = 0; unit < NRC; unit++) { 6068471Sache rcb = &rc_softc[unit]; 6078471Sache rc = rcb->rcb_baserc; 6088471Sache nec = rc->rc_rcb->rcb_addr; 6098471Sache for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 6108471Sache tp = rc->rc_tp; 6118471Sache#ifdef RCDEBUG 6128471Sache if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 6138471Sache RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 6148471Sache printrcflags(rc, "rcevent"); 6158471Sache#endif 6168471Sache if (rc->rc_flags & RC_WAS_BUFOVFL) { 6179232Sache disable_intr(); 6188471Sache rc->rc_flags &= ~RC_WAS_BUFOVFL; 6198471Sache rc_scheduled_event--; 6209232Sache enable_intr(); 6218471Sache printf("rc%d/%d: interrupt-level buffer overflow\n", 6228471Sache unit, chan); 6238471Sache } 6248471Sache if (rc->rc_flags & RC_WAS_SILOVFL) { 6259232Sache disable_intr(); 6268471Sache rc->rc_flags &= ~RC_WAS_SILOVFL; 6278471Sache rc_scheduled_event--; 6289232Sache enable_intr(); 6298471Sache printf("rc%d/%d: silo overflow\n", 6308471Sache unit, chan); 6318471Sache } 6328471Sache if (rc->rc_flags & RC_MODCHG) { 6339232Sache disable_intr(); 6348471Sache rc->rc_flags &= ~RC_MODCHG; 6358471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 6369232Sache enable_intr(); 6379232Sache (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 6388471Sache } 6398471Sache if (rc->rc_flags & RC_DORXFER) { 6409232Sache disable_intr(); 6418471Sache rc->rc_flags &= ~RC_DORXFER; 6428471Sache eptr = rc->rc_iptr; 6438471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 6448471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6458471Sache else 6468471Sache tptr = rc->rc_ibuf; 6478471Sache icnt = eptr - tptr; 6488471Sache if (icnt > 0) { 6498471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 6508471Sache rc->rc_iptr = rc->rc_ibuf; 6518471Sache rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 6528471Sache rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 6538471Sache } else { 6548471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 6558471Sache rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 6568471Sache rc->rc_hiwat = 6578471Sache &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 6588471Sache } 6599232Sache if ( (rc->rc_flags & RC_RTSFLOW) 6609232Sache && (tp->t_state & TS_ISOPEN) 6619232Sache && !(tp->t_state & TS_TBLOCK) 6628471Sache && !(rc->rc_msvr & MSVR_RTS) 6639232Sache ) { 6648471Sache rcout(CD180_CAR, chan); 6658471Sache rcout(CD180_MSVR, 6668471Sache rc->rc_msvr |= MSVR_RTS); 6678471Sache } 6688471Sache rc_scheduled_event -= icnt; 6698471Sache } 6708471Sache enable_intr(); 6718471Sache 6729232Sache if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 6738471Sache goto done1; 6748471Sache 6758471Sache if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 6768471Sache && !(tp->t_state & TS_LOCAL)) { 6779822Sbde if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 6789822Sbde && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 6799822Sbde && !(tp->t_state & TS_TBLOCK)) 6809822Sbde ttyblock(tp); 6818471Sache tk_nin += icnt; 6828471Sache tk_rawcc += icnt; 6838471Sache tp->t_rawcc += icnt; 6848471Sache if (b_to_q(tptr, icnt, &tp->t_rawq)) 6858471Sache printf("rc%d/%d: tty-level buffer overflow\n", 6868471Sache unit, chan); 6878471Sache ttwakeup(tp); 6888471Sache if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 6898471Sache || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 6908471Sache tp->t_state &= ~TS_TTSTOP; 6918471Sache tp->t_lflag &= ~FLUSHO; 6929754Sbde rc_start(tp); 6938471Sache } 6948471Sache } else { 6958471Sache for (; tptr < eptr; tptr++) 6968471Sache (*linesw[tp->t_line].l_rint) 6978471Sache (tptr[0] | 6988471Sache rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 6998471Sache } 7008471Sachedone1: 7018471Sache } 7028471Sache if (rc->rc_flags & RC_DOXXFER) { 7039232Sache disable_intr(); 7049232Sache rc_scheduled_event -= LOTS_OF_EVENTS; 7059232Sache rc->rc_flags &= ~RC_DOXXFER; 7069232Sache rc->rc_tp->t_state &= ~TS_BUSY; 7079232Sache enable_intr(); 7088471Sache (*linesw[tp->t_line].l_start)(tp); 7098471Sache } 7108471Sache } 7118471Sache if (rc_scheduled_event == 0) 7128471Sache break; 7138471Sache } 7148471Sache if (rc_scheduled_event >= LOTS_OF_EVENTS) 7158471Sache goto repeat; 7168471Sache} 7178471Sache 71812675Sjulianstatic void 71912675Sjulianrcstop(tp, rw) 7208471Sache register struct tty *tp; 7218471Sache int rw; 7228471Sache{ 7238471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 7248471Sache u_char *tptr, *eptr; 7258471Sache 7268471Sache#ifdef RCDEBUG 7279232Sache printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 7288471Sache (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 7298471Sache#endif 7308471Sache if (rw & FWRITE) 7318471Sache rc_discard_output(rc); 7328471Sache disable_intr(); 7338471Sache if (rw & FREAD) { 7349232Sache rc->rc_flags &= ~RC_DORXFER; 7358471Sache eptr = rc->rc_iptr; 7368471Sache if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 7378471Sache tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7388471Sache rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 7398471Sache } else { 7408471Sache tptr = rc->rc_ibuf; 7418471Sache rc->rc_iptr = rc->rc_ibuf; 7428471Sache } 7438471Sache rc_scheduled_event -= eptr - tptr; 7448471Sache } 7458471Sache if (tp->t_state & TS_TTSTOP) 7468471Sache rc->rc_flags |= RC_OSUSP; 7478471Sache else 7488471Sache rc->rc_flags &= ~RC_OSUSP; 7498471Sache enable_intr(); 7508471Sache} 7518471Sache 75212675Sjulianstatic int 75312675Sjulianrcopen(dev, flag, mode, p) 7548471Sache dev_t dev; 7558471Sache int flag, mode; 7568471Sache struct proc *p; 7578471Sache{ 7588471Sache register struct rc_chans *rc; 7598471Sache register struct tty *tp; 7608471Sache int unit, nec, s, error = 0; 7618471Sache 7628471Sache unit = GET_UNIT(dev); 7638471Sache if (unit >= NRC * CD180_NCHAN) 7648471Sache return ENXIO; 7659232Sache if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 7669232Sache return ENXIO; 7678471Sache rc = &rc_chans[unit]; 7689232Sache tp = rc->rc_tp; 7698471Sache nec = rc->rc_rcb->rcb_addr; 7708471Sache#ifdef RCDEBUG 7719232Sache printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 7728471Sache#endif 7738471Sache s = spltty(); 7748471Sache 7758471Sacheagain: 7768471Sache while (rc->rc_flags & RC_DTR_OFF) { 7779232Sache error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 7788471Sache if (error != 0) 7798471Sache goto out; 7808471Sache } 7818471Sache if (tp->t_state & TS_ISOPEN) { 7828471Sache if (CALLOUT(dev)) { 7838471Sache if (!(rc->rc_flags & RC_ACTOUT)) { 7848471Sache error = EBUSY; 7858471Sache goto out; 7868471Sache } 7878471Sache } else { 7888471Sache if (rc->rc_flags & RC_ACTOUT) { 7898471Sache if (flag & O_NONBLOCK) { 7908471Sache error = EBUSY; 7918471Sache goto out; 7928471Sache } 7938471Sache if (error = tsleep(&rc->rc_rcb, 7948471Sache TTIPRI|PCATCH, "rcbi", 0)) 7958471Sache goto out; 7968471Sache goto again; 7978471Sache } 7988471Sache } 7998471Sache if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 8008471Sache error = EBUSY; 8018471Sache goto out; 8028471Sache } 8038471Sache } else { 8048471Sache tp->t_oproc = rc_start; 8058471Sache tp->t_param = rc_param; 8068471Sache tp->t_dev = dev; 8078471Sache 8088471Sache if (CALLOUT(dev)) 8098471Sache tp->t_cflag |= CLOCAL; 8108471Sache else 8118471Sache tp->t_cflag &= ~CLOCAL; 8128471Sache 8138471Sache error = rc_param(tp, &tp->t_termios); 8148471Sache if (error) 8158471Sache goto out; 8169232Sache (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 8178471Sache 8188471Sache ttsetwater(tp); 8198471Sache 8208471Sache if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 8218471Sache (*linesw[tp->t_line].l_modem)(tp, 1); 8228471Sache } 8238471Sache if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 8248471Sache && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 8258471Sache rc->rc_dcdwaits++; 8269639Sbde error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 8278471Sache rc->rc_dcdwaits--; 8288471Sache if (error != 0) 8298471Sache goto out; 8308471Sache goto again; 8318471Sache } 8328471Sache error = (*linesw[tp->t_line].l_open)(dev, tp); 83313074Sache disc_optim(tp, &tp->t_termios, rc); 8348471Sache if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 8358471Sache rc->rc_flags |= RC_ACTOUT; 8368471Sacheout: 8378471Sache (void) splx(s); 8388471Sache 8398471Sache if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 8408471Sache rc_hardclose(rc); 8418471Sache 8428471Sache return error; 8438471Sache} 8448471Sache 84512675Sjulianstatic int 84612675Sjulianrcclose(dev, flag, mode, p) 8478471Sache dev_t dev; 8488471Sache int flag, mode; 8498471Sache struct proc *p; 8508471Sache{ 8518471Sache register struct rc_chans *rc; 8528471Sache register struct tty *tp; 8538471Sache int s, unit = GET_UNIT(dev); 8548471Sache 8558471Sache if (unit >= NRC * CD180_NCHAN) 8568471Sache return ENXIO; 8578471Sache rc = &rc_chans[unit]; 8588471Sache tp = rc->rc_tp; 8599232Sache#ifdef RCDEBUG 8609232Sache printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 8619232Sache#endif 8628471Sache s = spltty(); 8638471Sache (*linesw[tp->t_line].l_close)(tp, flag); 86413074Sache disc_optim(tp, &tp->t_termios, rc); 8658471Sache rcstop(tp, FREAD | FWRITE); 8668471Sache rc_hardclose(rc); 8678471Sache ttyclose(tp); 8688471Sache splx(s); 8698471Sache return 0; 8708471Sache} 8718471Sache 8728471Sachestatic void rc_hardclose(rc) 8738471Sacheregister struct rc_chans *rc; 8748471Sache{ 8758471Sache register int s, nec = rc->rc_rcb->rcb_addr; 8768471Sache register struct tty *tp = rc->rc_tp; 8778471Sache 8788471Sache s = spltty(); 8798471Sache rcout(CD180_CAR, rc->rc_chan); 8808471Sache 8819232Sache /* Disable rx/tx intrs */ 8828471Sache rcout(CD180_IER, rc->rc_ier = 0); 8839232Sache if ( (tp->t_cflag & HUPCL) 8848471Sache || !(rc->rc_flags & RC_ACTOUT) 8858471Sache && !(rc->rc_msvr & MSVR_CD) 8868471Sache && !(tp->t_cflag & CLOCAL) 8879232Sache || !(tp->t_state & TS_ISOPEN) 8889232Sache ) { 8899232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 8909232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 8918471Sache (void) rc_modctl(rc, TIOCM_RTS, DMSET); 8928471Sache if (rc->rc_dtrwait) { 8938471Sache timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 8948471Sache rc->rc_flags |= RC_DTR_OFF; 8958471Sache } 8968471Sache } 8978471Sache rc->rc_flags &= ~RC_ACTOUT; 8988471Sache wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 8999639Sbde wakeup(TSA_CARR_ON(tp)); 9008471Sache (void) splx(s); 9018471Sache} 9028471Sache 9038471Sache/* Read from line */ 90412675Sjulianstatic int 90512675Sjulianrcread(dev, uio, flag) 9068471Sache dev_t dev; 9078471Sache struct uio *uio; 9088471Sache int flag; 9098471Sache{ 9108471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 9119232Sache 9128471Sache return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 9138471Sache} 9148471Sache 9158471Sache/* Write to line */ 91612675Sjulianstatic int 91712675Sjulianrcwrite(dev, uio, flag) 9188471Sache dev_t dev; 9198471Sache struct uio *uio; 9208471Sache int flag; 9218471Sache{ 9228471Sache struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 9239232Sache 9248471Sache return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 9258471Sache} 9268471Sache 9278471Sache/* Reset the bastard */ 9289232Sachestatic void rc_hwreset(unit, nec, chipid) 9299232Sache register int unit, nec; 9308471Sache unsigned int chipid; 9318471Sache{ 9329232Sache CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 9338471Sache DELAY(20000); 9349232Sache WAITFORCCR(unit, -1); 9359232Sache 9369232Sache rcout(RC_CTOUT, 0); /* Clear timeout */ 9378471Sache rcout(CD180_GIVR, chipid); 9388471Sache rcout(CD180_GICR, 0); 9398471Sache 9408471Sache /* Set Prescaler Registers (1 msec) */ 9419232Sache rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 9429232Sache rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 9438471Sache 9448471Sache /* Initialize Priority Interrupt Level Registers */ 9458471Sache rcout(CD180_PILR1, RC_PILR_MODEM); 9468471Sache rcout(CD180_PILR2, RC_PILR_TX); 9478471Sache rcout(CD180_PILR3, RC_PILR_RX); 9488471Sache 9498471Sache /* Reset DTR */ 9509232Sache rcout(RC_DTREG, ~0); 9518471Sache} 9528471Sache 9538471Sache/* Set channel parameters */ 9548471Sachestatic int rc_param(tp, ts) 9558471Sache register struct tty *tp; 9568471Sache struct termios *ts; 9578471Sache{ 9589232Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 9598471Sache register int nec = rc->rc_rcb->rcb_addr; 9609232Sache int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 9618471Sache 9629855Sache if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 9639855Sache || ts->c_ispeed < 0 || ts->c_ispeed > 76800 9649855Sache ) 9659855Sache return (EINVAL); 9668471Sache if (ts->c_ispeed == 0) 9678471Sache ts->c_ispeed = ts->c_ospeed; 9689855Sache odivs = RC_BRD(ts->c_ospeed); 9699855Sache idivs = RC_BRD(ts->c_ispeed); 9708471Sache 9718471Sache s = spltty(); 9728471Sache 9739232Sache /* Select channel */ 9749232Sache rcout(CD180_CAR, rc->rc_chan); 9759232Sache 9768471Sache /* If speed == 0, hangup line */ 9779232Sache if (ts->c_ospeed == 0) { 9789232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 9799232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 9809232Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 9819232Sache } 9828471Sache 9838471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 9848471Sache cflag = ts->c_cflag; 9858471Sache iflag = ts->c_iflag; 9868471Sache lflag = ts->c_lflag; 9878471Sache 9888471Sache if (idivs > 0) { 9898471Sache rcout(CD180_RBPRL, idivs & 0xFF); 9908471Sache rcout(CD180_RBPRH, idivs >> 8); 9918471Sache } 9928471Sache if (odivs > 0) { 9938471Sache rcout(CD180_TBPRL, odivs & 0xFF); 9948471Sache rcout(CD180_TBPRH, odivs >> 8); 9958471Sache } 9968471Sache 9978471Sache /* set timeout value */ 9989232Sache if (ts->c_ispeed > 0) { 9999232Sache int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 10008471Sache 10019232Sache if ( !(lflag & ICANON) 10029232Sache && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 10039232Sache && ts->c_cc[VTIME] * 10 > itm) 10049232Sache itm = ts->c_cc[VTIME] * 10; 10059232Sache 10069232Sache rcout(CD180_RTPR, itm <= 255 ? itm : 255); 10079232Sache } 10089232Sache 10098471Sache switch (cflag & CSIZE) { 10108471Sache case CS5: val = COR1_5BITS; break; 10118471Sache case CS6: val = COR1_6BITS; break; 10128471Sache case CS7: val = COR1_7BITS; break; 10138471Sache default: 10148471Sache case CS8: val = COR1_8BITS; break; 10158471Sache } 10168471Sache if (cflag & PARENB) { 10178471Sache val |= COR1_NORMPAR; 10188471Sache if (cflag & PARODD) 10198471Sache val |= COR1_ODDP; 10209232Sache if (!(cflag & INPCK)) 10219232Sache val |= COR1_Ignore; 10228471Sache } else 10239232Sache val |= COR1_Ignore; 10248471Sache if (cflag & CSTOPB) 10258471Sache val |= COR1_2SB; 10268471Sache rcout(CD180_COR1, val); 10278471Sache 10288471Sache /* Set FIFO threshold */ 10299232Sache val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 10309232Sache inpflow = 0; 10319232Sache if ( (iflag & IXOFF) 10329232Sache && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 10339232Sache && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 10349232Sache || (iflag & IXANY) 10359232Sache ) 10369232Sache ) 10379232Sache ) { 10389232Sache inpflow = 1; 10399232Sache val |= COR3_SCDE|COR3_FCT; 10409232Sache } 10419232Sache rcout(CD180_COR3, val); 10428471Sache 10438471Sache /* Initialize on-chip automatic flow control */ 10448471Sache val = 0; 10459232Sache rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 10468471Sache if (cflag & CCTS_OFLOW) { 10478471Sache rc->rc_flags |= RC_CTSFLOW; 10489232Sache val |= COR2_CtsAE; 10499232Sache } else 10509232Sache rc->rc_flags |= RC_SEND_RDY; 10519232Sache if (tp->t_state & TS_TTSTOP) 10529232Sache rc->rc_flags |= RC_OSUSP; 10538471Sache else 10549232Sache rc->rc_flags &= ~RC_OSUSP; 10558471Sache if (cflag & CRTS_IFLOW) 10568471Sache rc->rc_flags |= RC_RTSFLOW; 10579232Sache else 10589232Sache rc->rc_flags &= ~RC_RTSFLOW; 10598471Sache 10609232Sache if (inpflow) { 10619232Sache if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 10629232Sache rcout(CD180_SCHR1, ts->c_cc[VSTART]); 10639232Sache rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 10649232Sache val |= COR2_TxIBE; 10659232Sache if (iflag & IXANY) 10669232Sache val |= COR2_IXM; 10678471Sache } 10688471Sache 10699232Sache rcout(CD180_COR2, rc->rc_cor2 = val); 10708471Sache 10719232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10729232Sache CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 10739232Sache 10748471Sache disc_optim(tp, ts, rc); 10758471Sache 10768471Sache /* modem ctl */ 10779232Sache val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 10789232Sache if (cflag & CCTS_OFLOW) 10799232Sache val |= MCOR1_CTSzd; 10809232Sache rcout(CD180_MCOR1, val); 10818471Sache 10829232Sache val = cflag & CLOCAL ? 0 : MCOR2_CDod; 10839232Sache if (cflag & CCTS_OFLOW) 10849232Sache val |= MCOR2_CTSod; 10859232Sache rcout(CD180_MCOR2, val); 10869232Sache 10878471Sache /* enable i/o and interrupts */ 10889232Sache CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 10899232Sache CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 10909232Sache WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 10918471Sache 10929232Sache rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 10939232Sache if (cflag & CCTS_OFLOW) 10949232Sache rc->rc_ier |= IER_CTS; 10959232Sache if (cflag & CREAD) 10969232Sache rc->rc_ier |= IER_RxData; 10979232Sache if (tp->t_state & TS_BUSY) 10989232Sache rc->rc_ier |= IER_TxRdy; 10999232Sache if (ts->c_ospeed != 0) 11009232Sache rc_modctl(rc, TIOCM_DTR, DMBIS); 11019232Sache if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 11029232Sache rc->rc_flags |= RC_SEND_RDY; 11039232Sache rcout(CD180_IER, rc->rc_ier); 11048471Sache (void) splx(s); 11058471Sache return 0; 11068471Sache} 11078471Sache 11089232Sache/* Re-initialize board after bogus interrupts */ 11099232Sachestatic void rc_reinit(rcb) 11109232Sachestruct rc_softc *rcb; 11119232Sache{ 11129232Sache register struct rc_chans *rc, *rce; 11139232Sache register int i, nec; 11149232Sache 11159232Sache nec = rcb->rcb_addr; 11169232Sache rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 11179232Sache rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 11189232Sache rce = rc + CD180_NCHAN; 11199232Sache for (; rc < rce; rc++) 11209232Sache (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 11219232Sache} 11229232Sache 112312675Sjulianstatic int 112412675Sjulianrcioctl(dev, cmd, data, flag, p) 11258471Sachedev_t dev; 11268471Sacheint cmd, flag; 11278471Sachecaddr_t data; 11288471Sachestruct proc *p; 11298471Sache{ 11308471Sache register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 11318471Sache register int s, error; 11328471Sache struct tty *tp = rc->rc_tp; 11338471Sache 11348471Sache error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 11358471Sache if (error >= 0) 11368471Sache return (error); 11378471Sache error = ttioctl(tp, cmd, data, flag); 113813074Sache disc_optim(tp, &tp->t_termios, rc); 11398471Sache if (error >= 0) 11408471Sache return (error); 11418471Sache s = spltty(); 11428471Sache 11438471Sache switch (cmd) { 11448471Sache case TIOCSBRK: 11458471Sache rc->rc_pendcmd = CD180_C_SBRK; 11468471Sache break; 11478471Sache 11488471Sache case TIOCCBRK: 11498471Sache rc->rc_pendcmd = CD180_C_EBRK; 11508471Sache break; 11518471Sache 11528471Sache case TIOCSDTR: 11539232Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 11548471Sache break; 11558471Sache 11568471Sache case TIOCCDTR: 11578471Sache (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 11588471Sache break; 11598471Sache 11608471Sache case TIOCMGET: 11618471Sache *(int *) data = rc_modctl(rc, 0, DMGET); 11628471Sache break; 11638471Sache 11648471Sache case TIOCMSET: 11658471Sache (void) rc_modctl(rc, *(int *) data, DMSET); 11668471Sache break; 11678471Sache 11688471Sache case TIOCMBIC: 11698471Sache (void) rc_modctl(rc, *(int *) data, DMBIC); 11708471Sache break; 11718471Sache 11728471Sache case TIOCMBIS: 11738471Sache (void) rc_modctl(rc, *(int *) data, DMBIS); 11748471Sache break; 11758471Sache 11768471Sache case TIOCMSDTRWAIT: 11778471Sache error = suser(p->p_ucred, &p->p_acflag); 11788471Sache if (error != 0) { 11798471Sache splx(s); 11808471Sache return (error); 11818471Sache } 11828471Sache rc->rc_dtrwait = *(int *)data * hz / 100; 11838471Sache break; 11848471Sache 11858471Sache case TIOCMGDTRWAIT: 11868471Sache *(int *)data = rc->rc_dtrwait * 100 / hz; 11878471Sache break; 11888471Sache 11898471Sache default: 11908471Sache (void) splx(s); 11918471Sache return ENOTTY; 11928471Sache } 11938471Sache (void) splx(s); 11948471Sache return 0; 11958471Sache} 11968471Sache 11978471Sache 11988471Sache/* Modem control routines */ 11998471Sache 12008471Sachestatic int rc_modctl(rc, bits, cmd) 12018471Sacheregister struct rc_chans *rc; 12028471Sacheint bits, cmd; 12038471Sache{ 12048471Sache register int nec = rc->rc_rcb->rcb_addr; 12059232Sache u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 12068471Sache 12078471Sache rcout(CD180_CAR, rc->rc_chan); 12088471Sache 12098471Sache switch (cmd) { 12108471Sache case DMSET: 12119232Sache rcout(RC_DTREG, (bits & TIOCM_DTR) ? 12129232Sache ~(*dtr |= 1 << rc->rc_chan) : 12139232Sache ~(*dtr &= ~(1 << rc->rc_chan))); 12149232Sache msvr = rcin(CD180_MSVR); 12159232Sache if (bits & TIOCM_RTS) 12169232Sache msvr |= MSVR_RTS; 12179232Sache else 12189232Sache msvr &= ~MSVR_RTS; 12199232Sache if (bits & TIOCM_DTR) 12209232Sache msvr |= MSVR_DTR; 12219232Sache else 12229232Sache msvr &= ~MSVR_DTR; 12239232Sache rcout(CD180_MSVR, msvr); 12249232Sache break; 12258471Sache 12268471Sache case DMBIS: 12279232Sache if (bits & TIOCM_DTR) 12289232Sache rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 12299232Sache msvr = rcin(CD180_MSVR); 12308471Sache if (bits & TIOCM_RTS) 12319232Sache msvr |= MSVR_RTS; 12328471Sache if (bits & TIOCM_DTR) 12339232Sache msvr |= MSVR_DTR; 12349232Sache rcout(CD180_MSVR, msvr); 12358471Sache break; 12368471Sache 12378471Sache case DMGET: 12388471Sache bits = TIOCM_LE; 12399232Sache msvr = rc->rc_msvr = rcin(CD180_MSVR); 12408471Sache 12418471Sache if (msvr & MSVR_RTS) 12428471Sache bits |= TIOCM_RTS; 12438471Sache if (msvr & MSVR_CTS) 12448471Sache bits |= TIOCM_CTS; 12458471Sache if (msvr & MSVR_DSR) 12468471Sache bits |= TIOCM_DSR; 12478471Sache if (msvr & MSVR_DTR) 12488471Sache bits |= TIOCM_DTR; 12499232Sache if (msvr & MSVR_CD) 12509232Sache bits |= TIOCM_CD; 12519232Sache if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 12529232Sache bits |= TIOCM_RI; 12538471Sache return bits; 12548471Sache 12558471Sache case DMBIC: 12568471Sache if (bits & TIOCM_DTR) 12579232Sache rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 12589232Sache msvr = rcin(CD180_MSVR); 12598471Sache if (bits & TIOCM_RTS) 12609232Sache msvr &= ~MSVR_RTS; 12619232Sache if (bits & TIOCM_DTR) 12629232Sache msvr &= ~MSVR_DTR; 12639232Sache rcout(CD180_MSVR, msvr); 12648471Sache break; 12658471Sache } 12669232Sache rc->rc_msvr = rcin(CD180_MSVR); 12678471Sache return 0; 12688471Sache} 12698471Sache 12708471Sache/* Test the board. */ 12718471Sacheint rc_test(nec, unit) 12728471Sache register int nec; 12738471Sache int unit; 12748471Sache{ 12758471Sache int chan = 0, nopt = 0; 12768471Sache int i = 0, rcnt, old_level; 12778471Sache unsigned int iack, chipid; 12788471Sache unsigned short divs; 12798471Sache static u_char ctest[] = "\377\125\252\045\244\0\377"; 12808471Sache#define CTLEN 8 12818471Sache#define ERR(s) { \ 12828471Sache printf("rc%d: ", unit); printf s ; printf("\n"); \ 12838471Sache (void) splx(old_level); return 1; } 12848471Sache 12858471Sache struct rtest { 12868471Sache u_char txbuf[CD180_NFIFO]; /* TX buffer */ 12878471Sache u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 12888471Sache int rxptr; /* RX pointer */ 12898471Sache int txptr; /* TX pointer */ 12908471Sache } tchans[CD180_NCHAN]; 12918471Sache 12929232Sache old_level = spltty(); 12938471Sache 12948471Sache chipid = RC_FAKEID; 12958471Sache 12968471Sache /* First, reset board to inital state */ 12979232Sache rc_hwreset(unit, nec, chipid); 12988471Sache 12999232Sache divs = RC_BRD(19200); 13009232Sache 13018471Sache /* Initialize channels */ 13028471Sache for (chan = 0; chan < CD180_NCHAN; chan++) { 13038471Sache 13048471Sache /* Select and reset channel */ 13058471Sache rcout(CD180_CAR, chan); 13069232Sache CCRCMD(unit, chan, CCR_ResetChan); 13079232Sache WAITFORCCR(unit, chan); 13088471Sache 13098471Sache /* Set speed */ 13108471Sache rcout(CD180_RBPRL, divs & 0xFF); 13118471Sache rcout(CD180_RBPRH, divs >> 8); 13128471Sache rcout(CD180_TBPRL, divs & 0xFF); 13138471Sache rcout(CD180_TBPRH, divs >> 8); 13148471Sache 13158471Sache /* set timeout value */ 13168471Sache rcout(CD180_RTPR, 0); 13178471Sache 13188471Sache /* Establish local loopback */ 13198471Sache rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 13208471Sache rcout(CD180_COR2, COR2_LLM); 13218471Sache rcout(CD180_COR3, CD180_NFIFO); 13229232Sache CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 13239232Sache CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 13249232Sache WAITFORCCR(unit, chan); 13258471Sache rcout(CD180_MSVR, MSVR_RTS); 13268471Sache 13278471Sache /* Fill TXBUF with test data */ 13288471Sache for (i = 0; i < CD180_NFIFO; i++) { 13298471Sache tchans[chan].txbuf[i] = ctest[i]; 13308471Sache tchans[chan].rxbuf[i] = 0; 13318471Sache } 13328471Sache tchans[chan].txptr = tchans[chan].rxptr = 0; 13338471Sache 13348471Sache /* Now, start transmit */ 13359232Sache rcout(CD180_IER, IER_TxMpty|IER_RxData); 13368471Sache } 13378471Sache /* Pseudo-interrupt poll stuff */ 13388471Sache for (rcnt = 10000; rcnt-- > 0; rcnt--) { 13399232Sache i = ~(rcin(RC_BSR)); 13408471Sache if (i & RC_BSR_TOUT) 13418471Sache ERR(("BSR timeout bit set\n")) 13429232Sache else if (i & RC_BSR_TXINT) { 13438471Sache iack = rcin(RC_PILR_TX); 13448471Sache if (iack != (GIVR_IT_TDI | chipid)) 13458471Sache ERR(("Bad TX intr ack (%02x != %02x)\n", 13468471Sache iack, GIVR_IT_TDI | chipid)); 13479232Sache chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13488471Sache /* If no more data to transmit, disable TX intr */ 13498471Sache if (tchans[chan].txptr >= CD180_NFIFO) { 13508471Sache iack = rcin(CD180_IER); 13519232Sache rcout(CD180_IER, iack & ~IER_TxMpty); 13528471Sache } else { 13538471Sache for (iack = tchans[chan].txptr; 13548471Sache iack < CD180_NFIFO; iack++) 13558471Sache rcout(CD180_TDR, 13568471Sache tchans[chan].txbuf[iack]); 13578471Sache tchans[chan].txptr = iack; 13588471Sache } 13599232Sache rcout(CD180_EOIR, 0); 13609232Sache } else if (i & RC_BSR_RXINT) { 13619232Sache u_char ucnt; 13628471Sache 13638471Sache iack = rcin(RC_PILR_RX); 13648471Sache if (iack != (GIVR_IT_RGDI | chipid) && 13658471Sache iack != (GIVR_IT_REI | chipid)) 13668471Sache ERR(("Bad RX intr ack (%02x != %02x)\n", 13678471Sache iack, GIVR_IT_RGDI | chipid)) 13689232Sache chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 13698471Sache ucnt = rcin(CD180_RDCR) & 0xF; 13708471Sache while (ucnt-- > 0) { 13718471Sache iack = rcin(CD180_RCSR); 13729232Sache if (iack & RCSR_Timeout) 13738471Sache break; 13748471Sache if (iack & 0xF) 13758471Sache ERR(("Bad char chan %d (RCSR = %02X)\n", 13768471Sache chan, iack)) 13778471Sache if (tchans[chan].rxptr > CD180_NFIFO) 13788471Sache ERR(("Got extra chars chan %d\n", 13798471Sache chan)) 13808471Sache tchans[chan].rxbuf[tchans[chan].rxptr++] = 13818471Sache rcin(CD180_RDR); 13828471Sache } 13838471Sache rcout(CD180_EOIR, 0); 13848471Sache } 13859232Sache rcout(RC_CTOUT, 0); 13868471Sache for (iack = chan = 0; chan < CD180_NCHAN; chan++) 13878471Sache if (tchans[chan].rxptr >= CD180_NFIFO) 13888471Sache iack++; 13898471Sache if (iack == CD180_NCHAN) 13908471Sache break; 13918471Sache } 13929232Sache for (chan = 0; chan < CD180_NCHAN; chan++) { 13939232Sache /* Select and reset channel */ 13949232Sache rcout(CD180_CAR, chan); 13959232Sache CCRCMD(unit, chan, CCR_ResetChan); 13969232Sache } 13979232Sache 13988471Sache if (!rcnt) 13998471Sache ERR(("looses characters during local loopback\n")) 14008471Sache /* Now, check data */ 14018471Sache for (chan = 0; chan < CD180_NCHAN; chan++) 14028471Sache for (i = 0; i < CD180_NFIFO; i++) 14038471Sache if (ctest[i] != tchans[chan].rxbuf[i]) 14048471Sache ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 14058471Sache chan, i, ctest[i], tchans[chan].rxbuf[i])) 14068471Sache (void) splx(old_level); 14078471Sache return 0; 14088471Sache} 14098471Sache 14108471Sache#ifdef RCDEBUG 14119232Sachestatic void printrcflags(rc, comment) 14128471Sachestruct rc_chans *rc; 14138471Sachechar *comment; 14148471Sache{ 14158471Sache u_short f = rc->rc_flags; 14169232Sache register int nec = rc->rc_rcb->rcb_addr; 14178471Sache 14189232Sache printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 14198471Sache rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 14208471Sache (f & RC_DTR_OFF)?"DTR_OFF " :"", 14219232Sache (f & RC_ACTOUT) ?"ACTOUT " :"", 14229232Sache (f & RC_RTSFLOW)?"RTSFLOW " :"", 14239232Sache (f & RC_CTSFLOW)?"CTSFLOW " :"", 14249232Sache (f & RC_DORXFER)?"DORXFER " :"", 14259232Sache (f & RC_DOXXFER)?"DOXXFER " :"", 14269232Sache (f & RC_MODCHG) ?"MODCHG " :"", 14279232Sache (f & RC_OSUSP) ?"OSUSP " :"", 14289232Sache (f & RC_OSBUSY) ?"OSBUSY " :"", 14299232Sache (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 14309232Sache (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 14319232Sache (f & RC_SEND_RDY) ?"SEND_RDY":""); 14329232Sache 14339232Sache rcout(CD180_CAR, rc->rc_chan); 14349232Sache 14359232Sache printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 14369232Sache rc->rc_rcb->rcb_unit, rc->rc_chan, 14379232Sache rcin(CD180_MSVR), 14389232Sache rcin(CD180_IER), 14399232Sache rcin(CD180_CCSR)); 14408471Sache} 14418471Sache#endif /* RCDEBUG */ 14428471Sache 144312675Sjulianstatic struct tty * 14448471Sachercdevtotty(dev) 14458471Sache dev_t dev; 14468471Sache{ 14478471Sache int unit; 14488471Sache 14498471Sache unit = GET_UNIT(dev); 14508471Sache if (unit >= NRC * CD180_NCHAN) 14518471Sache return NULL; 14528471Sache return (&rc_tty[unit]); 14538471Sache} 14548471Sache 14558471Sachestatic void 14568471Sacherc_dtrwakeup(chan) 14578471Sache void *chan; 14588471Sache{ 14598471Sache struct rc_chans *rc; 14608471Sache 14618471Sache rc = (struct rc_chans *)chan; 14628471Sache rc->rc_flags &= ~RC_DTR_OFF; 14638471Sache wakeup(&rc->rc_dtrwait); 14648471Sache} 14658471Sache 14668471Sachestatic void 14678471Sacherc_discard_output(rc) 14688471Sache struct rc_chans *rc; 14698471Sache{ 14708471Sache disable_intr(); 14718471Sache if (rc->rc_flags & RC_DOXXFER) { 14728471Sache rc_scheduled_event -= LOTS_OF_EVENTS; 14738471Sache rc->rc_flags &= ~RC_DOXXFER; 14748471Sache } 14758471Sache rc->rc_optr = rc->rc_obufend; 14769232Sache rc->rc_tp->t_state &= ~TS_BUSY; 14778471Sache enable_intr(); 14789754Sbde ttwwakeup(rc->rc_tp); 14798471Sache} 14808471Sache 14818471Sachestatic void 14828471Sacherc_wakeup(chan) 14838471Sache void *chan; 14848471Sache{ 14858471Sache int unit; 14868471Sache 14878471Sache timeout(rc_wakeup, (caddr_t)NULL, 1); 14888471Sache 14898471Sache if (rc_scheduled_event != 0) { 14908471Sache int s; 14918471Sache 14928471Sache s = splsofttty(); 14938471Sache rcpoll(); 14948471Sache splx(s); 14958471Sache } 14968471Sache} 14978471Sache 14988471Sachestatic void 14998471Sachedisc_optim(tp, t, rc) 15008471Sache struct tty *tp; 15018471Sache struct termios *t; 15028471Sache struct rc_chans *rc; 15038471Sache{ 15048471Sache 15059757Sbde if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 15068471Sache && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 15079757Sbde && (!(t->c_iflag & PARMRK) 15089757Sbde || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 15099757Sbde && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 15108471Sache && linesw[tp->t_line].l_rint == ttyinput) 15118471Sache tp->t_state |= TS_CAN_BYPASS_L_RINT; 15128471Sache else 15138471Sache tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 15148471Sache if (tp->t_line == SLIPDISC) 15158471Sache rc->rc_hotchar = 0xc0; 15168471Sache else if (tp->t_line == PPPDISC) 15178471Sache rc->rc_hotchar = 0x7e; 15188471Sache else 15198471Sache rc->rc_hotchar = 0; 15208471Sache} 15219232Sache 15229232Sachestatic void 15239232Sacherc_wait0(nec, unit, chan, line) 15249232Sache int nec, unit, chan, line; 15259232Sache{ 15269232Sache int rcnt; 15279232Sache 152814441Srgrimes for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 152914441Srgrimes DELAY(30); 15309232Sache if (rcnt == 0) 15319232Sache printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 15329232Sache unit, chan, line); 15339232Sache} 153412502Sjulian 153512502Sjulianstatic rc_devsw_installed = 0; 153612502Sjulian 153712517Sjulianstatic void rc_drvinit(void *unused) 153812502Sjulian{ 153912517Sjulian dev_t dev; 154012517Sjulian 154112502Sjulian if( ! rc_devsw_installed ) { 154212675Sjulian dev = makedev(CDEV_MAJOR, 0); 154312675Sjulian cdevsw_add(&dev,&rc_cdevsw, NULL); 154412502Sjulian rc_devsw_installed = 1; 154512517Sjulian } 154612502Sjulian} 154712517Sjulian 154812517SjulianSYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 154912517Sjulian 155012517Sjulian 15518471Sache#endif /* NRC */ 1552