rc.c revision 14441
1/* 2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. 3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver 30 * 31 */ 32 33#include "rc.h" 34#if NRC > 0 35 36/*#define RCDEBUG*/ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/ioctl.h> 41#include <sys/tty.h> 42#include <sys/proc.h> 43#include <sys/conf.h> 44#include <sys/dkstat.h> 45#include <sys/file.h> 46#include <sys/uio.h> 47#include <sys/kernel.h> 48#include <sys/syslog.h> 49#include <sys/devconf.h> 50#ifdef DEVFS 51#include <sys/devfsext.h> 52#endif /*DEVFS*/ 53 54#include <machine/clock.h> 55 56#include <i386/isa/isa.h> 57#include <i386/isa/isa_device.h> 58#include <i386/isa/sioreg.h> 59 60#include <i386/isa/ic/cd180.h> 61#include <i386/isa/rcreg.h> 62 63 64/* Prototypes */ 65static int rcprobe __P((struct isa_device *)); 66static int rcattach __P((struct isa_device *)); 67 68/*- 69 * This space intentionally left blank to stop __LINE__ from screwing up 70 * regression tests :-(. 71 * 72 * 73 * 74 */ 75void rcpoll __P((void)); 76 77#define rcin(port) RC_IN (nec, port) 78#define rcout(port,v) RC_OUT (nec, port, v) 79 80#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__) 81#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd)) 82 83#define RC_IBUFSIZE 256 84#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE) 85#define RC_OBUFSIZE 512 86#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4) 87#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE) 88#define LOTS_OF_EVENTS 64 89 90#define RC_FAKEID 0x10 91 92#define RC_PROBED 1 93#define RC_ATTACHED 2 94 95#define GET_UNIT(dev) (minor(dev) & 0x3F) 96#define CALLOUT(dev) (minor(dev) & 0x80) 97 98/* For isa routines */ 99struct isa_driver rcdriver = { 100 rcprobe, rcattach, "rc" 101}; 102 103static d_open_t rcopen; 104static d_close_t rcclose; 105static d_read_t rcread; 106static d_write_t rcwrite; 107static d_ioctl_t rcioctl; 108static d_stop_t rcstop; 109static d_devtotty_t rcdevtotty; 110 111#define CDEV_MAJOR 63 112static struct cdevsw rc_cdevsw = 113 { rcopen, rcclose, rcread, rcwrite, /*63*/ 114 rcioctl, rcstop, noreset, rcdevtotty,/* rc */ 115 ttselect, nommap, NULL, "rc", NULL, -1 }; 116 117/* Per-board structure */ 118static struct rc_softc { 119 u_int rcb_probed; /* 1 - probed, 2 - attached */ 120 u_int rcb_addr; /* Base I/O addr */ 121 u_int rcb_unit; /* unit # */ 122 u_char rcb_dtr; /* DTR status */ 123 struct rc_chans *rcb_baserc; /* base rc ptr */ 124} rc_softc[NRC]; 125 126/* Per-channel structure */ 127static struct rc_chans { 128 struct rc_softc *rc_rcb; /* back ptr */ 129 u_short rc_flags; /* Misc. flags */ 130 int rc_chan; /* Channel # */ 131 u_char rc_ier; /* intr. enable reg */ 132 u_char rc_msvr; /* modem sig. status */ 133 u_char rc_cor2; /* options reg */ 134 u_char rc_pendcmd; /* special cmd pending */ 135 u_int rc_dtrwait; /* dtr timeout */ 136 u_int rc_dcdwaits; /* how many waits DCD in open */ 137 u_char rc_hotchar; /* end packed optimize */ 138 struct tty *rc_tp; /* tty struct */ 139 u_char *rc_iptr; /* Chars input buffer */ 140 u_char *rc_hiwat; /* hi-water mark */ 141 u_char *rc_bufend; /* end of buffer */ 142 u_char *rc_optr; /* ptr in output buf */ 143 u_char *rc_obufend; /* end of output buf */ 144 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */ 145 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */ 146#ifdef DEVFS 147 void *devfs_token; 148#endif 149} rc_chans[NRC * CD180_NCHAN]; 150 151static int rc_scheduled_event = 0; 152 153/* for pstat -t */ 154static struct tty rc_tty[NRC * CD180_NCHAN]; 155static int nrc_tty = NRC * CD180_NCHAN; 156 157/* Flags */ 158#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */ 159#define RC_ACTOUT 0x0002 /* Dial-out port active */ 160#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */ 161#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */ 162#define RC_DORXFER 0x0010 /* RXFER event planned */ 163#define RC_DOXXFER 0x0020 /* XXFER event planned */ 164#define RC_MODCHG 0x0040 /* Modem status changed */ 165#define RC_OSUSP 0x0080 /* Output suspended */ 166#define RC_OSBUSY 0x0100 /* start() routine in progress */ 167#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */ 168#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */ 169#define RC_SEND_RDY 0x0800 /* ready to send */ 170 171/* Table for translation of RCSR status bits to internal form */ 172static int rc_rcsrt[16] = { 173 0, TTY_OE, TTY_FE, 174 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE, 175 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI, 176 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE, 177 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE, 178 TTY_BI|TTY_PE|TTY_FE|TTY_OE 179}; 180 181/* Static prototypes */ 182static void rc_hwreset __P((int, int, unsigned int)); 183static int rc_test __P((int, int)); 184static void rc_discard_output __P((struct rc_chans *)); 185static void rc_hardclose __P((struct rc_chans *)); 186static int rc_modctl __P((struct rc_chans *, int, int)); 187static void rc_start __P((struct tty *)); 188static int rc_param __P((struct tty *, struct termios *)); 189static void rc_registerdev __P((struct isa_device *id)); 190static void rc_reinit __P((struct rc_softc *)); 191#ifdef RCDEBUG 192static void printrcflags(); 193#endif 194static timeout_t rc_dtrwakeup; 195static timeout_t rc_wakeup; 196static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *)); 197static void rc_wait0 __P((int nec, int unit, int chan, int line)); 198 199/**********************************************/ 200 201/* Quick device probing */ 202static int 203rcprobe(dvp) 204 struct isa_device *dvp; 205{ 206 int irq = ffs(dvp->id_irq) - 1; 207 register int nec = dvp->id_iobase; 208 209 if (dvp->id_unit > NRC) 210 return 0; 211 if (!RC_VALIDADDR(nec)) { 212 printf("rc%d: illegal base address %x\n", nec); 213 return 0; 214 } 215 if (!RC_VALIDIRQ(irq)) { 216 printf("rc%d: illegal IRQ value %d\n", irq); 217 return 0; 218 } 219 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */ 220 rcout(CD180_PPRH, 0x11); 221 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) 222 return 0; 223 /* Now, test the board more thoroughly, with diagnostic */ 224 if (rc_test(nec, dvp->id_unit)) 225 return 0; 226 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED; 227 228 return 0xF; 229} 230 231static struct kern_devconf kdc_rc[NRC] = { { 232 0, 0, 0, /* filled in by dev_attach */ 233 "rc", 0, { MDDT_ISA, 0, "tty" }, 234 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN, 235 &kdc_isa0, /* parent */ 236 0, /* parentdata */ 237 DC_UNCONFIGURED, /* state */ 238 "RISCom/8 multiport card", 239 DC_CLS_SERIAL /* class */ 240} }; 241 242static void 243rc_registerdev(id) 244 struct isa_device *id; 245{ 246 int unit; 247 248 unit = id->id_unit; 249 if (unit != 0) 250 kdc_rc[unit] = kdc_rc[0]; 251 kdc_rc[unit].kdc_unit = unit; 252 kdc_rc[unit].kdc_isa = id; 253 kdc_rc[unit].kdc_state = DC_UNKNOWN; 254 dev_attach(&kdc_rc[unit]); 255} 256 257static int 258rcattach(dvp) 259 struct isa_device *dvp; 260{ 261 register int i, chan, nec = dvp->id_iobase; 262 struct rc_softc *rcb = &rc_softc[dvp->id_unit]; 263 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN]; 264 static int rc_wakeup_started = 0; 265 struct tty *tp; 266 char name[32]; 267 268 /* Thorooughly test the device */ 269 if (rcb->rcb_probed != RC_PROBED) 270 return 0; 271 rcb->rcb_addr = nec; 272 rcb->rcb_dtr = 0; 273 rcb->rcb_baserc = rc; 274 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/ 275 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit, 276 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A'); 277 278 rc_registerdev(dvp); 279 280 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) { 281 rc->rc_rcb = rcb; 282 rc->rc_chan = chan; 283 rc->rc_iptr = rc->rc_ibuf; 284 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 285 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 286 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0; 287 rc->rc_cor2 = rc->rc_pendcmd = 0; 288 rc->rc_optr = rc->rc_obufend = rc->rc_obuf; 289 rc->rc_dtrwait = 3 * hz; 290 rc->rc_dcdwaits= 0; 291 rc->rc_hotchar = 0; 292 tp = rc->rc_tp = &rc_tty[chan]; 293 ttychars(tp); 294 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0; 295 tp->t_cflag = TTYDEF_CFLAG; 296 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 297#ifdef DEVFS 298/* FIX THIS to reflect real devices */ 299 sprintf(name,"rc%d.%d",dvp->id_unit,chan); 300 rc->devfs_token = devfs_add_devsw( "/", name, 301 &rc_cdevsw,(dvp->id_unit * CD180_NCHAN) + chan , 302 DV_CHR, 0, 0, 0600); 303#endif 304 } 305 rcb->rcb_probed = RC_ATTACHED; 306 if (!rc_wakeup_started) { 307 rc_wakeup((void *)NULL); 308 rc_wakeup_started = 0; 309 } 310 return 1; 311} 312 313/* RC interrupt handling */ 314void rcintr(unit) 315 int unit; 316{ 317 register struct rc_softc *rcb = &rc_softc[unit]; 318 register struct rc_chans *rc; 319 register int nec, resid; 320 register u_char val, iack, bsr, ucnt, *optr; 321 int good_data, t_state; 322 323 if (rcb->rcb_probed != RC_ATTACHED) { 324 printf("rc%d: bogus interrupt\n", unit); 325 return; 326 } 327 nec = rcb->rcb_addr; 328 329 bsr = ~(rcin(RC_BSR)); 330 331 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) { 332 printf("rc%d: extra interrupt\n", unit); 333 rcout(CD180_EOIR, 0); 334 return; 335 } 336 337 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) { 338#ifdef RCDEBUG_DETAILED 339 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr, 340 (bsr & RC_BSR_TOUT)?"TOUT ":"", 341 (bsr & RC_BSR_RXINT)?"RXINT ":"", 342 (bsr & RC_BSR_TXINT)?"TXINT ":"", 343 (bsr & RC_BSR_MOINT)?"MOINT":""); 344#endif 345 if (bsr & RC_BSR_TOUT) { 346 printf("rc%d: hardware failure, reset board\n", unit); 347 rcout(RC_CTOUT, 0); 348 rc_reinit(rcb); 349 return; 350 } 351 if (bsr & RC_BSR_RXINT) { 352 iack = rcin(RC_PILR_RX); 353 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID)); 354 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) { 355 printf("rc%d: fake rxint: %02x\n", unit, iack); 356 goto more_intrs; 357 } 358 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 359 t_state = rc->rc_tp->t_state; 360 /* Do RTS flow control stuff */ 361 if ( (rc->rc_flags & RC_RTSFLOW) 362 || !(t_state & TS_ISOPEN) 363 ) { 364 if ( ( !(t_state & TS_ISOPEN) 365 || (t_state & TS_TBLOCK) 366 ) 367 && (rc->rc_msvr & MSVR_RTS) 368 ) 369 rcout(CD180_MSVR, 370 rc->rc_msvr &= ~MSVR_RTS); 371 else if (!(rc->rc_msvr & MSVR_RTS)) 372 rcout(CD180_MSVR, 373 rc->rc_msvr |= MSVR_RTS); 374 } 375 ucnt = rcin(CD180_RDCR) & 0xF; 376 resid = 0; 377 378 if (t_state & TS_ISOPEN) { 379 /* check for input buffer overflow */ 380 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) { 381 resid = ucnt; 382 ucnt = rc->rc_bufend - rc->rc_iptr; 383 resid -= ucnt; 384 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) { 385 rc->rc_flags |= RC_WAS_BUFOVFL; 386 rc_scheduled_event++; 387 } 388 } 389 optr = rc->rc_iptr; 390 /* check foor good data */ 391 if (good_data) { 392 while (ucnt-- > 0) { 393 val = rcin(CD180_RDR); 394 optr[0] = val; 395 optr[INPUT_FLAGS_SHIFT] = 0; 396 optr++; 397 rc_scheduled_event++; 398 if (val != 0 && val == rc->rc_hotchar) 399 setsofttty(); 400 } 401 } else { 402 /* Store also status data */ 403 while (ucnt-- > 0) { 404 iack = rcin(CD180_RCSR); 405 if (iack & RCSR_Timeout) 406 break; 407 if ( (iack & RCSR_OE) 408 && !(rc->rc_flags & RC_WAS_SILOVFL)) { 409 rc->rc_flags |= RC_WAS_SILOVFL; 410 rc_scheduled_event++; 411 } 412 val = rcin(CD180_RDR); 413 /* 414 Don't store PE if IGNPAR and BREAK if IGNBRK, 415 this hack allows "raw" tty optimization 416 works even if IGN* is set. 417 */ 418 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break)) 419 || (!(iack & (RCSR_PE|RCSR_FE)) 420 || !(rc->rc_tp->t_iflag & IGNPAR)) 421 && (!(iack & RCSR_Break) 422 || !(rc->rc_tp->t_iflag & IGNBRK))) { 423 if ( (iack & (RCSR_PE|RCSR_FE)) 424 && (t_state & TS_CAN_BYPASS_L_RINT) 425 && ((iack & RCSR_FE) 426 || (iack & RCSR_PE) 427 && (rc->rc_tp->t_iflag & INPCK))) 428 val = 0; 429 else if (val != 0 && val == rc->rc_hotchar) 430 setsofttty(); 431 optr[0] = val; 432 optr[INPUT_FLAGS_SHIFT] = iack; 433 optr++; 434 rc_scheduled_event++; 435 } 436 } 437 } 438 rc->rc_iptr = optr; 439 rc->rc_flags |= RC_DORXFER; 440 } else 441 resid = ucnt; 442 /* Clear FIFO if necessary */ 443 while (resid-- > 0) { 444 if (!good_data) 445 iack = rcin(CD180_RCSR); 446 else 447 iack = 0; 448 if (iack & RCSR_Timeout) 449 break; 450 (void) rcin(CD180_RDR); 451 } 452 goto more_intrs; 453 } 454 if (bsr & RC_BSR_MOINT) { 455 iack = rcin(RC_PILR_MODEM); 456 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) { 457 printf("rc%d: fake moint: %02x\n", unit, iack); 458 goto more_intrs; 459 } 460 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 461 iack = rcin(CD180_MCR); 462 rc->rc_msvr = rcin(CD180_MSVR); 463 rcout(CD180_MCR, 0); 464#ifdef RCDEBUG 465 printrcflags(rc, "moint"); 466#endif 467 if (rc->rc_flags & RC_CTSFLOW) { 468 if (rc->rc_msvr & MSVR_CTS) 469 rc->rc_flags |= RC_SEND_RDY; 470 else 471 rc->rc_flags &= ~RC_SEND_RDY; 472 } else 473 rc->rc_flags |= RC_SEND_RDY; 474 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) { 475 rc_scheduled_event += LOTS_OF_EVENTS; 476 rc->rc_flags |= RC_MODCHG; 477 setsofttty(); 478 } 479 goto more_intrs; 480 } 481 if (bsr & RC_BSR_TXINT) { 482 iack = rcin(RC_PILR_TX); 483 if (iack != (GIVR_IT_TDI | RC_FAKEID)) { 484 printf("rc%d: fake txint: %02x\n", unit, iack); 485 goto more_intrs; 486 } 487 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH); 488 if ( (rc->rc_flags & RC_OSUSP) 489 || !(rc->rc_flags & RC_SEND_RDY) 490 ) 491 goto more_intrs; 492 /* Handle breaks and other stuff */ 493 if (rc->rc_pendcmd) { 494 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC); 495 rcout(CD180_TDR, CD180_C_ESC); 496 rcout(CD180_TDR, rc->rc_pendcmd); 497 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC); 498 rc->rc_pendcmd = 0; 499 goto more_intrs; 500 } 501 optr = rc->rc_optr; 502 resid = rc->rc_obufend - optr; 503 if (resid > CD180_NFIFO) 504 resid = CD180_NFIFO; 505 while (resid-- > 0) 506 rcout(CD180_TDR, *optr++); 507 rc->rc_optr = optr; 508 509 /* output completed? */ 510 if (optr >= rc->rc_obufend) { 511 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy); 512#ifdef RCDEBUG 513 printf("rc%d/%d: output completed\n", unit, rc->rc_chan); 514#endif 515 if (!(rc->rc_flags & RC_DOXXFER)) { 516 rc_scheduled_event += LOTS_OF_EVENTS; 517 rc->rc_flags |= RC_DOXXFER; 518 setsofttty(); 519 } 520 } 521 } 522 more_intrs: 523 rcout(CD180_EOIR, 0); /* end of interrupt */ 524 rcout(RC_CTOUT, 0); 525 bsr = ~(rcin(RC_BSR)); 526 } 527} 528 529/* Feed characters to output buffer */ 530static void rc_start(tp) 531register struct tty *tp; 532{ 533 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 534 register int nec = rc->rc_rcb->rcb_addr, s; 535 536 if (rc->rc_flags & RC_OSBUSY) 537 return; 538 s = spltty(); 539 rc->rc_flags |= RC_OSBUSY; 540 disable_intr(); 541 if (tp->t_state & TS_TTSTOP) 542 rc->rc_flags |= RC_OSUSP; 543 else 544 rc->rc_flags &= ~RC_OSUSP; 545 /* Do RTS flow control stuff */ 546 if ( (rc->rc_flags & RC_RTSFLOW) 547 && (tp->t_state & TS_TBLOCK) 548 && (rc->rc_msvr & MSVR_RTS) 549 ) { 550 rcout(CD180_CAR, rc->rc_chan); 551 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS); 552 } else if (!(rc->rc_msvr & MSVR_RTS)) { 553 rcout(CD180_CAR, rc->rc_chan); 554 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS); 555 } 556 enable_intr(); 557 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP)) 558 goto out; 559#ifdef RCDEBUG 560 printrcflags(rc, "rcstart"); 561#endif 562 ttwwakeup(tp); 563#ifdef RCDEBUG 564 printf("rcstart: outq = %d obuf = %d\n", 565 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr); 566#endif 567 if (tp->t_state & TS_BUSY) 568 goto out; /* output still in progress ... */ 569 570 if (tp->t_outq.c_cc > 0) { 571 u_int ocnt; 572 573 tp->t_state |= TS_BUSY; 574 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf); 575 disable_intr(); 576 rc->rc_optr = rc->rc_obuf; 577 rc->rc_obufend = rc->rc_optr + ocnt; 578 enable_intr(); 579 if (!(rc->rc_ier & IER_TxRdy)) { 580#ifdef RCDEBUG 581 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan); 582#endif 583 rcout(CD180_CAR, rc->rc_chan); 584 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy); 585 } 586 } 587out: 588 rc->rc_flags &= ~RC_OSBUSY; 589 (void) splx(s); 590} 591 592/* Handle delayed events. */ 593void rcpoll() 594{ 595 register struct rc_chans *rc; 596 register struct rc_softc *rcb; 597 register u_char *tptr, *eptr; 598 register int s; 599 register struct tty *tp; 600 register int chan, icnt, c, nec, unit; 601 602 if (rc_scheduled_event == 0) 603 return; 604repeat: 605 for (unit = 0; unit < NRC; unit++) { 606 rcb = &rc_softc[unit]; 607 rc = rcb->rcb_baserc; 608 nec = rc->rc_rcb->rcb_addr; 609 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) { 610 tp = rc->rc_tp; 611#ifdef RCDEBUG 612 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG| 613 RC_WAS_BUFOVFL|RC_WAS_SILOVFL)) 614 printrcflags(rc, "rcevent"); 615#endif 616 if (rc->rc_flags & RC_WAS_BUFOVFL) { 617 disable_intr(); 618 rc->rc_flags &= ~RC_WAS_BUFOVFL; 619 rc_scheduled_event--; 620 enable_intr(); 621 printf("rc%d/%d: interrupt-level buffer overflow\n", 622 unit, chan); 623 } 624 if (rc->rc_flags & RC_WAS_SILOVFL) { 625 disable_intr(); 626 rc->rc_flags &= ~RC_WAS_SILOVFL; 627 rc_scheduled_event--; 628 enable_intr(); 629 printf("rc%d/%d: silo overflow\n", 630 unit, chan); 631 } 632 if (rc->rc_flags & RC_MODCHG) { 633 disable_intr(); 634 rc->rc_flags &= ~RC_MODCHG; 635 rc_scheduled_event -= LOTS_OF_EVENTS; 636 enable_intr(); 637 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD)); 638 } 639 if (rc->rc_flags & RC_DORXFER) { 640 disable_intr(); 641 rc->rc_flags &= ~RC_DORXFER; 642 eptr = rc->rc_iptr; 643 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) 644 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 645 else 646 tptr = rc->rc_ibuf; 647 icnt = eptr - tptr; 648 if (icnt > 0) { 649 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 650 rc->rc_iptr = rc->rc_ibuf; 651 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE]; 652 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER]; 653 } else { 654 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 655 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE]; 656 rc->rc_hiwat = 657 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER]; 658 } 659 if ( (rc->rc_flags & RC_RTSFLOW) 660 && (tp->t_state & TS_ISOPEN) 661 && !(tp->t_state & TS_TBLOCK) 662 && !(rc->rc_msvr & MSVR_RTS) 663 ) { 664 rcout(CD180_CAR, chan); 665 rcout(CD180_MSVR, 666 rc->rc_msvr |= MSVR_RTS); 667 } 668 rc_scheduled_event -= icnt; 669 } 670 enable_intr(); 671 672 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN)) 673 goto done1; 674 675 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT) 676 && !(tp->t_state & TS_LOCAL)) { 677 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER 678 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF)) 679 && !(tp->t_state & TS_TBLOCK)) 680 ttyblock(tp); 681 tk_nin += icnt; 682 tk_rawcc += icnt; 683 tp->t_rawcc += icnt; 684 if (b_to_q(tptr, icnt, &tp->t_rawq)) 685 printf("rc%d/%d: tty-level buffer overflow\n", 686 unit, chan); 687 ttwakeup(tp); 688 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY) 689 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) { 690 tp->t_state &= ~TS_TTSTOP; 691 tp->t_lflag &= ~FLUSHO; 692 rc_start(tp); 693 } 694 } else { 695 for (; tptr < eptr; tptr++) 696 (*linesw[tp->t_line].l_rint) 697 (tptr[0] | 698 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp); 699 } 700done1: 701 } 702 if (rc->rc_flags & RC_DOXXFER) { 703 disable_intr(); 704 rc_scheduled_event -= LOTS_OF_EVENTS; 705 rc->rc_flags &= ~RC_DOXXFER; 706 rc->rc_tp->t_state &= ~TS_BUSY; 707 enable_intr(); 708 (*linesw[tp->t_line].l_start)(tp); 709 } 710 } 711 if (rc_scheduled_event == 0) 712 break; 713 } 714 if (rc_scheduled_event >= LOTS_OF_EVENTS) 715 goto repeat; 716} 717 718static void 719rcstop(tp, rw) 720 register struct tty *tp; 721 int rw; 722{ 723 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 724 u_char *tptr, *eptr; 725 726#ifdef RCDEBUG 727 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan, 728 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":""); 729#endif 730 if (rw & FWRITE) 731 rc_discard_output(rc); 732 disable_intr(); 733 if (rw & FREAD) { 734 rc->rc_flags &= ~RC_DORXFER; 735 eptr = rc->rc_iptr; 736 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) { 737 tptr = &rc->rc_ibuf[RC_IBUFSIZE]; 738 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE]; 739 } else { 740 tptr = rc->rc_ibuf; 741 rc->rc_iptr = rc->rc_ibuf; 742 } 743 rc_scheduled_event -= eptr - tptr; 744 } 745 if (tp->t_state & TS_TTSTOP) 746 rc->rc_flags |= RC_OSUSP; 747 else 748 rc->rc_flags &= ~RC_OSUSP; 749 enable_intr(); 750} 751 752static int 753rcopen(dev, flag, mode, p) 754 dev_t dev; 755 int flag, mode; 756 struct proc *p; 757{ 758 register struct rc_chans *rc; 759 register struct tty *tp; 760 int unit, nec, s, error = 0; 761 762 unit = GET_UNIT(dev); 763 if (unit >= NRC * CD180_NCHAN) 764 return ENXIO; 765 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) 766 return ENXIO; 767 rc = &rc_chans[unit]; 768 tp = rc->rc_tp; 769 nec = rc->rc_rcb->rcb_addr; 770#ifdef RCDEBUG 771 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 772#endif 773 s = spltty(); 774 775again: 776 while (rc->rc_flags & RC_DTR_OFF) { 777 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0); 778 if (error != 0) 779 goto out; 780 } 781 if (tp->t_state & TS_ISOPEN) { 782 if (CALLOUT(dev)) { 783 if (!(rc->rc_flags & RC_ACTOUT)) { 784 error = EBUSY; 785 goto out; 786 } 787 } else { 788 if (rc->rc_flags & RC_ACTOUT) { 789 if (flag & O_NONBLOCK) { 790 error = EBUSY; 791 goto out; 792 } 793 if (error = tsleep(&rc->rc_rcb, 794 TTIPRI|PCATCH, "rcbi", 0)) 795 goto out; 796 goto again; 797 } 798 } 799 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 800 error = EBUSY; 801 goto out; 802 } 803 } else { 804 tp->t_oproc = rc_start; 805 tp->t_param = rc_param; 806 tp->t_dev = dev; 807 808 if (CALLOUT(dev)) 809 tp->t_cflag |= CLOCAL; 810 else 811 tp->t_cflag &= ~CLOCAL; 812 813 error = rc_param(tp, &tp->t_termios); 814 if (error) 815 goto out; 816 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET); 817 818 ttsetwater(tp); 819 820 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev)) 821 (*linesw[tp->t_line].l_modem)(tp, 1); 822 } 823 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev) 824 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 825 rc->rc_dcdwaits++; 826 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0); 827 rc->rc_dcdwaits--; 828 if (error != 0) 829 goto out; 830 goto again; 831 } 832 error = (*linesw[tp->t_line].l_open)(dev, tp); 833 disc_optim(tp, &tp->t_termios, rc); 834 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev)) 835 rc->rc_flags |= RC_ACTOUT; 836out: 837 (void) splx(s); 838 839 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN)) 840 rc_hardclose(rc); 841 842 return error; 843} 844 845static int 846rcclose(dev, flag, mode, p) 847 dev_t dev; 848 int flag, mode; 849 struct proc *p; 850{ 851 register struct rc_chans *rc; 852 register struct tty *tp; 853 int s, unit = GET_UNIT(dev); 854 855 if (unit >= NRC * CD180_NCHAN) 856 return ENXIO; 857 rc = &rc_chans[unit]; 858 tp = rc->rc_tp; 859#ifdef RCDEBUG 860 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev); 861#endif 862 s = spltty(); 863 (*linesw[tp->t_line].l_close)(tp, flag); 864 disc_optim(tp, &tp->t_termios, rc); 865 rcstop(tp, FREAD | FWRITE); 866 rc_hardclose(rc); 867 ttyclose(tp); 868 splx(s); 869 return 0; 870} 871 872static void rc_hardclose(rc) 873register struct rc_chans *rc; 874{ 875 register int s, nec = rc->rc_rcb->rcb_addr; 876 register struct tty *tp = rc->rc_tp; 877 878 s = spltty(); 879 rcout(CD180_CAR, rc->rc_chan); 880 881 /* Disable rx/tx intrs */ 882 rcout(CD180_IER, rc->rc_ier = 0); 883 if ( (tp->t_cflag & HUPCL) 884 || !(rc->rc_flags & RC_ACTOUT) 885 && !(rc->rc_msvr & MSVR_CD) 886 && !(tp->t_cflag & CLOCAL) 887 || !(tp->t_state & TS_ISOPEN) 888 ) { 889 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 890 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 891 (void) rc_modctl(rc, TIOCM_RTS, DMSET); 892 if (rc->rc_dtrwait) { 893 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait); 894 rc->rc_flags |= RC_DTR_OFF; 895 } 896 } 897 rc->rc_flags &= ~RC_ACTOUT; 898 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */ 899 wakeup(TSA_CARR_ON(tp)); 900 (void) splx(s); 901} 902 903/* Read from line */ 904static int 905rcread(dev, uio, flag) 906 dev_t dev; 907 struct uio *uio; 908 int flag; 909{ 910 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 911 912 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 913} 914 915/* Write to line */ 916static int 917rcwrite(dev, uio, flag) 918 dev_t dev; 919 struct uio *uio; 920 int flag; 921{ 922 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp; 923 924 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 925} 926 927/* Reset the bastard */ 928static void rc_hwreset(unit, nec, chipid) 929 register int unit, nec; 930 unsigned int chipid; 931{ 932 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */ 933 DELAY(20000); 934 WAITFORCCR(unit, -1); 935 936 rcout(RC_CTOUT, 0); /* Clear timeout */ 937 rcout(CD180_GIVR, chipid); 938 rcout(CD180_GICR, 0); 939 940 /* Set Prescaler Registers (1 msec) */ 941 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF); 942 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8); 943 944 /* Initialize Priority Interrupt Level Registers */ 945 rcout(CD180_PILR1, RC_PILR_MODEM); 946 rcout(CD180_PILR2, RC_PILR_TX); 947 rcout(CD180_PILR3, RC_PILR_RX); 948 949 /* Reset DTR */ 950 rcout(RC_DTREG, ~0); 951} 952 953/* Set channel parameters */ 954static int rc_param(tp, ts) 955 register struct tty *tp; 956 struct termios *ts; 957{ 958 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)]; 959 register int nec = rc->rc_rcb->rcb_addr; 960 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow; 961 962 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800 963 || ts->c_ispeed < 0 || ts->c_ispeed > 76800 964 ) 965 return (EINVAL); 966 if (ts->c_ispeed == 0) 967 ts->c_ispeed = ts->c_ospeed; 968 odivs = RC_BRD(ts->c_ospeed); 969 idivs = RC_BRD(ts->c_ispeed); 970 971 s = spltty(); 972 973 /* Select channel */ 974 rcout(CD180_CAR, rc->rc_chan); 975 976 /* If speed == 0, hangup line */ 977 if (ts->c_ospeed == 0) { 978 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan); 979 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 980 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 981 } 982 983 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 984 cflag = ts->c_cflag; 985 iflag = ts->c_iflag; 986 lflag = ts->c_lflag; 987 988 if (idivs > 0) { 989 rcout(CD180_RBPRL, idivs & 0xFF); 990 rcout(CD180_RBPRH, idivs >> 8); 991 } 992 if (odivs > 0) { 993 rcout(CD180_TBPRL, odivs & 0xFF); 994 rcout(CD180_TBPRH, odivs >> 8); 995 } 996 997 /* set timeout value */ 998 if (ts->c_ispeed > 0) { 999 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1; 1000 1001 if ( !(lflag & ICANON) 1002 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0 1003 && ts->c_cc[VTIME] * 10 > itm) 1004 itm = ts->c_cc[VTIME] * 10; 1005 1006 rcout(CD180_RTPR, itm <= 255 ? itm : 255); 1007 } 1008 1009 switch (cflag & CSIZE) { 1010 case CS5: val = COR1_5BITS; break; 1011 case CS6: val = COR1_6BITS; break; 1012 case CS7: val = COR1_7BITS; break; 1013 default: 1014 case CS8: val = COR1_8BITS; break; 1015 } 1016 if (cflag & PARENB) { 1017 val |= COR1_NORMPAR; 1018 if (cflag & PARODD) 1019 val |= COR1_ODDP; 1020 if (!(cflag & INPCK)) 1021 val |= COR1_Ignore; 1022 } else 1023 val |= COR1_Ignore; 1024 if (cflag & CSTOPB) 1025 val |= COR1_2SB; 1026 rcout(CD180_COR1, val); 1027 1028 /* Set FIFO threshold */ 1029 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2; 1030 inpflow = 0; 1031 if ( (iflag & IXOFF) 1032 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE 1033 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE 1034 || (iflag & IXANY) 1035 ) 1036 ) 1037 ) { 1038 inpflow = 1; 1039 val |= COR3_SCDE|COR3_FCT; 1040 } 1041 rcout(CD180_COR3, val); 1042 1043 /* Initialize on-chip automatic flow control */ 1044 val = 0; 1045 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY); 1046 if (cflag & CCTS_OFLOW) { 1047 rc->rc_flags |= RC_CTSFLOW; 1048 val |= COR2_CtsAE; 1049 } else 1050 rc->rc_flags |= RC_SEND_RDY; 1051 if (tp->t_state & TS_TTSTOP) 1052 rc->rc_flags |= RC_OSUSP; 1053 else 1054 rc->rc_flags &= ~RC_OSUSP; 1055 if (cflag & CRTS_IFLOW) 1056 rc->rc_flags |= RC_RTSFLOW; 1057 else 1058 rc->rc_flags &= ~RC_RTSFLOW; 1059 1060 if (inpflow) { 1061 if (ts->c_cc[VSTART] != _POSIX_VDISABLE) 1062 rcout(CD180_SCHR1, ts->c_cc[VSTART]); 1063 rcout(CD180_SCHR2, ts->c_cc[VSTOP]); 1064 val |= COR2_TxIBE; 1065 if (iflag & IXANY) 1066 val |= COR2_IXM; 1067 } 1068 1069 rcout(CD180_COR2, rc->rc_cor2 = val); 1070 1071 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1072 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1073 1074 disc_optim(tp, ts, rc); 1075 1076 /* modem ctl */ 1077 val = cflag & CLOCAL ? 0 : MCOR1_CDzd; 1078 if (cflag & CCTS_OFLOW) 1079 val |= MCOR1_CTSzd; 1080 rcout(CD180_MCOR1, val); 1081 1082 val = cflag & CLOCAL ? 0 : MCOR2_CDod; 1083 if (cflag & CCTS_OFLOW) 1084 val |= MCOR2_CTSod; 1085 rcout(CD180_MCOR2, val); 1086 1087 /* enable i/o and interrupts */ 1088 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, 1089 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS)); 1090 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan); 1091 1092 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD; 1093 if (cflag & CCTS_OFLOW) 1094 rc->rc_ier |= IER_CTS; 1095 if (cflag & CREAD) 1096 rc->rc_ier |= IER_RxData; 1097 if (tp->t_state & TS_BUSY) 1098 rc->rc_ier |= IER_TxRdy; 1099 if (ts->c_ospeed != 0) 1100 rc_modctl(rc, TIOCM_DTR, DMBIS); 1101 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS)) 1102 rc->rc_flags |= RC_SEND_RDY; 1103 rcout(CD180_IER, rc->rc_ier); 1104 (void) splx(s); 1105 return 0; 1106} 1107 1108/* Re-initialize board after bogus interrupts */ 1109static void rc_reinit(rcb) 1110struct rc_softc *rcb; 1111{ 1112 register struct rc_chans *rc, *rce; 1113 register int i, nec; 1114 1115 nec = rcb->rcb_addr; 1116 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID); 1117 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN]; 1118 rce = rc + CD180_NCHAN; 1119 for (; rc < rce; rc++) 1120 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios); 1121} 1122 1123static int 1124rcioctl(dev, cmd, data, flag, p) 1125dev_t dev; 1126int cmd, flag; 1127caddr_t data; 1128struct proc *p; 1129{ 1130 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)]; 1131 register int s, error; 1132 struct tty *tp = rc->rc_tp; 1133 1134 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1135 if (error >= 0) 1136 return (error); 1137 error = ttioctl(tp, cmd, data, flag); 1138 disc_optim(tp, &tp->t_termios, rc); 1139 if (error >= 0) 1140 return (error); 1141 s = spltty(); 1142 1143 switch (cmd) { 1144 case TIOCSBRK: 1145 rc->rc_pendcmd = CD180_C_SBRK; 1146 break; 1147 1148 case TIOCCBRK: 1149 rc->rc_pendcmd = CD180_C_EBRK; 1150 break; 1151 1152 case TIOCSDTR: 1153 (void) rc_modctl(rc, TIOCM_DTR, DMBIS); 1154 break; 1155 1156 case TIOCCDTR: 1157 (void) rc_modctl(rc, TIOCM_DTR, DMBIC); 1158 break; 1159 1160 case TIOCMGET: 1161 *(int *) data = rc_modctl(rc, 0, DMGET); 1162 break; 1163 1164 case TIOCMSET: 1165 (void) rc_modctl(rc, *(int *) data, DMSET); 1166 break; 1167 1168 case TIOCMBIC: 1169 (void) rc_modctl(rc, *(int *) data, DMBIC); 1170 break; 1171 1172 case TIOCMBIS: 1173 (void) rc_modctl(rc, *(int *) data, DMBIS); 1174 break; 1175 1176 case TIOCMSDTRWAIT: 1177 error = suser(p->p_ucred, &p->p_acflag); 1178 if (error != 0) { 1179 splx(s); 1180 return (error); 1181 } 1182 rc->rc_dtrwait = *(int *)data * hz / 100; 1183 break; 1184 1185 case TIOCMGDTRWAIT: 1186 *(int *)data = rc->rc_dtrwait * 100 / hz; 1187 break; 1188 1189 default: 1190 (void) splx(s); 1191 return ENOTTY; 1192 } 1193 (void) splx(s); 1194 return 0; 1195} 1196 1197 1198/* Modem control routines */ 1199 1200static int rc_modctl(rc, bits, cmd) 1201register struct rc_chans *rc; 1202int bits, cmd; 1203{ 1204 register int nec = rc->rc_rcb->rcb_addr; 1205 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr; 1206 1207 rcout(CD180_CAR, rc->rc_chan); 1208 1209 switch (cmd) { 1210 case DMSET: 1211 rcout(RC_DTREG, (bits & TIOCM_DTR) ? 1212 ~(*dtr |= 1 << rc->rc_chan) : 1213 ~(*dtr &= ~(1 << rc->rc_chan))); 1214 msvr = rcin(CD180_MSVR); 1215 if (bits & TIOCM_RTS) 1216 msvr |= MSVR_RTS; 1217 else 1218 msvr &= ~MSVR_RTS; 1219 if (bits & TIOCM_DTR) 1220 msvr |= MSVR_DTR; 1221 else 1222 msvr &= ~MSVR_DTR; 1223 rcout(CD180_MSVR, msvr); 1224 break; 1225 1226 case DMBIS: 1227 if (bits & TIOCM_DTR) 1228 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan)); 1229 msvr = rcin(CD180_MSVR); 1230 if (bits & TIOCM_RTS) 1231 msvr |= MSVR_RTS; 1232 if (bits & TIOCM_DTR) 1233 msvr |= MSVR_DTR; 1234 rcout(CD180_MSVR, msvr); 1235 break; 1236 1237 case DMGET: 1238 bits = TIOCM_LE; 1239 msvr = rc->rc_msvr = rcin(CD180_MSVR); 1240 1241 if (msvr & MSVR_RTS) 1242 bits |= TIOCM_RTS; 1243 if (msvr & MSVR_CTS) 1244 bits |= TIOCM_CTS; 1245 if (msvr & MSVR_DSR) 1246 bits |= TIOCM_DSR; 1247 if (msvr & MSVR_DTR) 1248 bits |= TIOCM_DTR; 1249 if (msvr & MSVR_CD) 1250 bits |= TIOCM_CD; 1251 if (~rcin(RC_RIREG) & (1 << rc->rc_chan)) 1252 bits |= TIOCM_RI; 1253 return bits; 1254 1255 case DMBIC: 1256 if (bits & TIOCM_DTR) 1257 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan))); 1258 msvr = rcin(CD180_MSVR); 1259 if (bits & TIOCM_RTS) 1260 msvr &= ~MSVR_RTS; 1261 if (bits & TIOCM_DTR) 1262 msvr &= ~MSVR_DTR; 1263 rcout(CD180_MSVR, msvr); 1264 break; 1265 } 1266 rc->rc_msvr = rcin(CD180_MSVR); 1267 return 0; 1268} 1269 1270/* Test the board. */ 1271int rc_test(nec, unit) 1272 register int nec; 1273 int unit; 1274{ 1275 int chan = 0, nopt = 0; 1276 int i = 0, rcnt, old_level; 1277 unsigned int iack, chipid; 1278 unsigned short divs; 1279 static u_char ctest[] = "\377\125\252\045\244\0\377"; 1280#define CTLEN 8 1281#define ERR(s) { \ 1282 printf("rc%d: ", unit); printf s ; printf("\n"); \ 1283 (void) splx(old_level); return 1; } 1284 1285 struct rtest { 1286 u_char txbuf[CD180_NFIFO]; /* TX buffer */ 1287 u_char rxbuf[CD180_NFIFO]; /* RX buffer */ 1288 int rxptr; /* RX pointer */ 1289 int txptr; /* TX pointer */ 1290 } tchans[CD180_NCHAN]; 1291 1292 old_level = spltty(); 1293 1294 chipid = RC_FAKEID; 1295 1296 /* First, reset board to inital state */ 1297 rc_hwreset(unit, nec, chipid); 1298 1299 divs = RC_BRD(19200); 1300 1301 /* Initialize channels */ 1302 for (chan = 0; chan < CD180_NCHAN; chan++) { 1303 1304 /* Select and reset channel */ 1305 rcout(CD180_CAR, chan); 1306 CCRCMD(unit, chan, CCR_ResetChan); 1307 WAITFORCCR(unit, chan); 1308 1309 /* Set speed */ 1310 rcout(CD180_RBPRL, divs & 0xFF); 1311 rcout(CD180_RBPRH, divs >> 8); 1312 rcout(CD180_TBPRL, divs & 0xFF); 1313 rcout(CD180_TBPRH, divs >> 8); 1314 1315 /* set timeout value */ 1316 rcout(CD180_RTPR, 0); 1317 1318 /* Establish local loopback */ 1319 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB); 1320 rcout(CD180_COR2, COR2_LLM); 1321 rcout(CD180_COR3, CD180_NFIFO); 1322 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3); 1323 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN); 1324 WAITFORCCR(unit, chan); 1325 rcout(CD180_MSVR, MSVR_RTS); 1326 1327 /* Fill TXBUF with test data */ 1328 for (i = 0; i < CD180_NFIFO; i++) { 1329 tchans[chan].txbuf[i] = ctest[i]; 1330 tchans[chan].rxbuf[i] = 0; 1331 } 1332 tchans[chan].txptr = tchans[chan].rxptr = 0; 1333 1334 /* Now, start transmit */ 1335 rcout(CD180_IER, IER_TxMpty|IER_RxData); 1336 } 1337 /* Pseudo-interrupt poll stuff */ 1338 for (rcnt = 10000; rcnt-- > 0; rcnt--) { 1339 i = ~(rcin(RC_BSR)); 1340 if (i & RC_BSR_TOUT) 1341 ERR(("BSR timeout bit set\n")) 1342 else if (i & RC_BSR_TXINT) { 1343 iack = rcin(RC_PILR_TX); 1344 if (iack != (GIVR_IT_TDI | chipid)) 1345 ERR(("Bad TX intr ack (%02x != %02x)\n", 1346 iack, GIVR_IT_TDI | chipid)); 1347 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1348 /* If no more data to transmit, disable TX intr */ 1349 if (tchans[chan].txptr >= CD180_NFIFO) { 1350 iack = rcin(CD180_IER); 1351 rcout(CD180_IER, iack & ~IER_TxMpty); 1352 } else { 1353 for (iack = tchans[chan].txptr; 1354 iack < CD180_NFIFO; iack++) 1355 rcout(CD180_TDR, 1356 tchans[chan].txbuf[iack]); 1357 tchans[chan].txptr = iack; 1358 } 1359 rcout(CD180_EOIR, 0); 1360 } else if (i & RC_BSR_RXINT) { 1361 u_char ucnt; 1362 1363 iack = rcin(RC_PILR_RX); 1364 if (iack != (GIVR_IT_RGDI | chipid) && 1365 iack != (GIVR_IT_REI | chipid)) 1366 ERR(("Bad RX intr ack (%02x != %02x)\n", 1367 iack, GIVR_IT_RGDI | chipid)) 1368 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH; 1369 ucnt = rcin(CD180_RDCR) & 0xF; 1370 while (ucnt-- > 0) { 1371 iack = rcin(CD180_RCSR); 1372 if (iack & RCSR_Timeout) 1373 break; 1374 if (iack & 0xF) 1375 ERR(("Bad char chan %d (RCSR = %02X)\n", 1376 chan, iack)) 1377 if (tchans[chan].rxptr > CD180_NFIFO) 1378 ERR(("Got extra chars chan %d\n", 1379 chan)) 1380 tchans[chan].rxbuf[tchans[chan].rxptr++] = 1381 rcin(CD180_RDR); 1382 } 1383 rcout(CD180_EOIR, 0); 1384 } 1385 rcout(RC_CTOUT, 0); 1386 for (iack = chan = 0; chan < CD180_NCHAN; chan++) 1387 if (tchans[chan].rxptr >= CD180_NFIFO) 1388 iack++; 1389 if (iack == CD180_NCHAN) 1390 break; 1391 } 1392 for (chan = 0; chan < CD180_NCHAN; chan++) { 1393 /* Select and reset channel */ 1394 rcout(CD180_CAR, chan); 1395 CCRCMD(unit, chan, CCR_ResetChan); 1396 } 1397 1398 if (!rcnt) 1399 ERR(("looses characters during local loopback\n")) 1400 /* Now, check data */ 1401 for (chan = 0; chan < CD180_NCHAN; chan++) 1402 for (i = 0; i < CD180_NFIFO; i++) 1403 if (ctest[i] != tchans[chan].rxbuf[i]) 1404 ERR(("data mismatch chan %d ptr %d (%d != %d)\n", 1405 chan, i, ctest[i], tchans[chan].rxbuf[i])) 1406 (void) splx(old_level); 1407 return 0; 1408} 1409 1410#ifdef RCDEBUG 1411static void printrcflags(rc, comment) 1412struct rc_chans *rc; 1413char *comment; 1414{ 1415 u_short f = rc->rc_flags; 1416 register int nec = rc->rc_rcb->rcb_addr; 1417 1418 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n", 1419 rc->rc_rcb->rcb_unit, rc->rc_chan, comment, 1420 (f & RC_DTR_OFF)?"DTR_OFF " :"", 1421 (f & RC_ACTOUT) ?"ACTOUT " :"", 1422 (f & RC_RTSFLOW)?"RTSFLOW " :"", 1423 (f & RC_CTSFLOW)?"CTSFLOW " :"", 1424 (f & RC_DORXFER)?"DORXFER " :"", 1425 (f & RC_DOXXFER)?"DOXXFER " :"", 1426 (f & RC_MODCHG) ?"MODCHG " :"", 1427 (f & RC_OSUSP) ?"OSUSP " :"", 1428 (f & RC_OSBUSY) ?"OSBUSY " :"", 1429 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"", 1430 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"", 1431 (f & RC_SEND_RDY) ?"SEND_RDY":""); 1432 1433 rcout(CD180_CAR, rc->rc_chan); 1434 1435 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n", 1436 rc->rc_rcb->rcb_unit, rc->rc_chan, 1437 rcin(CD180_MSVR), 1438 rcin(CD180_IER), 1439 rcin(CD180_CCSR)); 1440} 1441#endif /* RCDEBUG */ 1442 1443static struct tty * 1444rcdevtotty(dev) 1445 dev_t dev; 1446{ 1447 int unit; 1448 1449 unit = GET_UNIT(dev); 1450 if (unit >= NRC * CD180_NCHAN) 1451 return NULL; 1452 return (&rc_tty[unit]); 1453} 1454 1455static void 1456rc_dtrwakeup(chan) 1457 void *chan; 1458{ 1459 struct rc_chans *rc; 1460 1461 rc = (struct rc_chans *)chan; 1462 rc->rc_flags &= ~RC_DTR_OFF; 1463 wakeup(&rc->rc_dtrwait); 1464} 1465 1466static void 1467rc_discard_output(rc) 1468 struct rc_chans *rc; 1469{ 1470 disable_intr(); 1471 if (rc->rc_flags & RC_DOXXFER) { 1472 rc_scheduled_event -= LOTS_OF_EVENTS; 1473 rc->rc_flags &= ~RC_DOXXFER; 1474 } 1475 rc->rc_optr = rc->rc_obufend; 1476 rc->rc_tp->t_state &= ~TS_BUSY; 1477 enable_intr(); 1478 ttwwakeup(rc->rc_tp); 1479} 1480 1481static void 1482rc_wakeup(chan) 1483 void *chan; 1484{ 1485 int unit; 1486 1487 timeout(rc_wakeup, (caddr_t)NULL, 1); 1488 1489 if (rc_scheduled_event != 0) { 1490 int s; 1491 1492 s = splsofttty(); 1493 rcpoll(); 1494 splx(s); 1495 } 1496} 1497 1498static void 1499disc_optim(tp, t, rc) 1500 struct tty *tp; 1501 struct termios *t; 1502 struct rc_chans *rc; 1503{ 1504 1505 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 1506 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 1507 && (!(t->c_iflag & PARMRK) 1508 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 1509 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 1510 && linesw[tp->t_line].l_rint == ttyinput) 1511 tp->t_state |= TS_CAN_BYPASS_L_RINT; 1512 else 1513 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 1514 if (tp->t_line == SLIPDISC) 1515 rc->rc_hotchar = 0xc0; 1516 else if (tp->t_line == PPPDISC) 1517 rc->rc_hotchar = 0x7e; 1518 else 1519 rc->rc_hotchar = 0; 1520} 1521 1522static void 1523rc_wait0(nec, unit, chan, line) 1524 int nec, unit, chan, line; 1525{ 1526 int rcnt; 1527 1528 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--) 1529 DELAY(30); 1530 if (rcnt == 0) 1531 printf("rc%d/%d: channel command timeout, rc.c line: %d\n", 1532 unit, chan, line); 1533} 1534 1535static rc_devsw_installed = 0; 1536 1537static void rc_drvinit(void *unused) 1538{ 1539 dev_t dev; 1540 1541 if( ! rc_devsw_installed ) { 1542 dev = makedev(CDEV_MAJOR, 0); 1543 cdevsw_add(&dev,&rc_cdevsw, NULL); 1544 rc_devsw_installed = 1; 1545 } 1546} 1547 1548SYSINIT(rcdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,rc_drvinit,NULL) 1549 1550 1551#endif /* NRC */ 1552