rt2661.c revision 300752
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 300752 2016-05-26 16:05:19Z avos $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 300752 2016-05-26 16:05:19Z avos $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_var.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55 56#include <net80211/ieee80211_var.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_ratectl.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2661reg.h> 68#include <dev/ral/rt2661var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(sc, fmt, ...) do { \ 73 if (sc->sc_debug > 0) \ 74 printf(fmt, __VA_ARGS__); \ 75} while (0) 76#define DPRINTFN(sc, n, fmt, ...) do { \ 77 if (sc->sc_debug >= (n)) \ 78 printf(fmt, __VA_ARGS__); \ 79} while (0) 80#else 81#define DPRINTF(sc, fmt, ...) 82#define DPRINTFN(sc, n, fmt, ...) 83#endif 84 85static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 86 const char [IFNAMSIZ], int, enum ieee80211_opmode, 87 int, const uint8_t [IEEE80211_ADDR_LEN], 88 const uint8_t [IEEE80211_ADDR_LEN]); 89static void rt2661_vap_delete(struct ieee80211vap *); 90static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 91 int); 92static int rt2661_alloc_tx_ring(struct rt2661_softc *, 93 struct rt2661_tx_ring *, int); 94static void rt2661_reset_tx_ring(struct rt2661_softc *, 95 struct rt2661_tx_ring *); 96static void rt2661_free_tx_ring(struct rt2661_softc *, 97 struct rt2661_tx_ring *); 98static int rt2661_alloc_rx_ring(struct rt2661_softc *, 99 struct rt2661_rx_ring *, int); 100static void rt2661_reset_rx_ring(struct rt2661_softc *, 101 struct rt2661_rx_ring *); 102static void rt2661_free_rx_ring(struct rt2661_softc *, 103 struct rt2661_rx_ring *); 104static int rt2661_newstate(struct ieee80211vap *, 105 enum ieee80211_state, int); 106static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 107static void rt2661_rx_intr(struct rt2661_softc *); 108static void rt2661_tx_intr(struct rt2661_softc *); 109static void rt2661_tx_dma_intr(struct rt2661_softc *, 110 struct rt2661_tx_ring *); 111static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 112static void rt2661_mcu_wakeup(struct rt2661_softc *); 113static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 114static void rt2661_scan_start(struct ieee80211com *); 115static void rt2661_scan_end(struct ieee80211com *); 116static void rt2661_getradiocaps(struct ieee80211com *, int, int *, 117 struct ieee80211_channel[]); 118static void rt2661_set_channel(struct ieee80211com *); 119static void rt2661_setup_tx_desc(struct rt2661_softc *, 120 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 121 int, const bus_dma_segment_t *, int, int); 122static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 123 struct ieee80211_node *, int); 124static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *); 126static int rt2661_transmit(struct ieee80211com *, struct mbuf *); 127static void rt2661_start(struct rt2661_softc *); 128static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 129 const struct ieee80211_bpf_params *); 130static void rt2661_watchdog(void *); 131static void rt2661_parent(struct ieee80211com *); 132static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 133 uint8_t); 134static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 135static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 136 uint32_t); 137static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 138 uint16_t); 139static void rt2661_select_antenna(struct rt2661_softc *); 140static void rt2661_enable_mrr(struct rt2661_softc *); 141static void rt2661_set_txpreamble(struct rt2661_softc *); 142static void rt2661_set_basicrates(struct rt2661_softc *, 143 const struct ieee80211_rateset *); 144static void rt2661_select_band(struct rt2661_softc *, 145 struct ieee80211_channel *); 146static void rt2661_set_chan(struct rt2661_softc *, 147 struct ieee80211_channel *); 148static void rt2661_set_bssid(struct rt2661_softc *, 149 const uint8_t *); 150static void rt2661_set_macaddr(struct rt2661_softc *, 151 const uint8_t *); 152static void rt2661_update_promisc(struct ieee80211com *); 153static int rt2661_wme_update(struct ieee80211com *) __unused; 154static void rt2661_update_slot(struct ieee80211com *); 155static const char *rt2661_get_rf(int); 156static void rt2661_read_eeprom(struct rt2661_softc *, 157 uint8_t macaddr[IEEE80211_ADDR_LEN]); 158static int rt2661_bbp_init(struct rt2661_softc *); 159static void rt2661_init_locked(struct rt2661_softc *); 160static void rt2661_init(void *); 161static void rt2661_stop_locked(struct rt2661_softc *); 162static void rt2661_stop(void *); 163static int rt2661_load_microcode(struct rt2661_softc *); 164#ifdef notyet 165static void rt2661_rx_tune(struct rt2661_softc *); 166static void rt2661_radar_start(struct rt2661_softc *); 167static int rt2661_radar_stop(struct rt2661_softc *); 168#endif 169static int rt2661_prepare_beacon(struct rt2661_softc *, 170 struct ieee80211vap *); 171static void rt2661_enable_tsf_sync(struct rt2661_softc *); 172static void rt2661_enable_tsf(struct rt2661_softc *); 173static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 174 175static const struct { 176 uint32_t reg; 177 uint32_t val; 178} rt2661_def_mac[] = { 179 RT2661_DEF_MAC 180}; 181 182static const struct { 183 uint8_t reg; 184 uint8_t val; 185} rt2661_def_bbp[] = { 186 RT2661_DEF_BBP 187}; 188 189static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192} rt2661_rf5225_1[] = { 193 RT2661_RF5225_1 194}, rt2661_rf5225_2[] = { 195 RT2661_RF5225_2 196}; 197 198static const uint8_t rt2661_chan_2ghz[] = 199 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 200static const uint8_t rt2661_chan_5ghz[] = 201 { 36, 40, 44, 48, 52, 56, 60, 64, 202 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 203 149, 153, 157, 161, 165 }; 204 205int 206rt2661_attach(device_t dev, int id) 207{ 208 struct rt2661_softc *sc = device_get_softc(dev); 209 struct ieee80211com *ic = &sc->sc_ic; 210 uint32_t val; 211 int error, ac, ntries; 212 213 sc->sc_id = id; 214 sc->sc_dev = dev; 215 216 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 217 MTX_DEF | MTX_RECURSE); 218 219 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 220 mbufq_init(&sc->sc_snd, ifqmaxlen); 221 222 /* wait for NIC to initialize */ 223 for (ntries = 0; ntries < 1000; ntries++) { 224 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 225 break; 226 DELAY(1000); 227 } 228 if (ntries == 1000) { 229 device_printf(sc->sc_dev, 230 "timeout waiting for NIC to initialize\n"); 231 error = EIO; 232 goto fail1; 233 } 234 235 /* retrieve RF rev. no and various other things from EEPROM */ 236 rt2661_read_eeprom(sc, ic->ic_macaddr); 237 238 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 239 rt2661_get_rf(sc->rf_rev)); 240 241 /* 242 * Allocate Tx and Rx rings. 243 */ 244 for (ac = 0; ac < 4; ac++) { 245 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 246 RT2661_TX_RING_COUNT); 247 if (error != 0) { 248 device_printf(sc->sc_dev, 249 "could not allocate Tx ring %d\n", ac); 250 goto fail2; 251 } 252 } 253 254 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 255 if (error != 0) { 256 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 257 goto fail2; 258 } 259 260 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 261 if (error != 0) { 262 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 263 goto fail3; 264 } 265 266 ic->ic_softc = sc; 267 ic->ic_name = device_get_nameunit(dev); 268 ic->ic_opmode = IEEE80211_M_STA; 269 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 270 271 /* set device capabilities */ 272 ic->ic_caps = 273 IEEE80211_C_STA /* station mode */ 274 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 275 | IEEE80211_C_HOSTAP /* hostap mode */ 276 | IEEE80211_C_MONITOR /* monitor mode */ 277 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 278 | IEEE80211_C_WDS /* 4-address traffic works */ 279 | IEEE80211_C_MBSS /* mesh point link mode */ 280 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 281 | IEEE80211_C_SHSLOT /* short slot time supported */ 282 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 283 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 284#ifdef notyet 285 | IEEE80211_C_TXFRAG /* handle tx frags */ 286 | IEEE80211_C_WME /* 802.11e */ 287#endif 288 ; 289 290 rt2661_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 291 ic->ic_channels); 292 293 ieee80211_ifattach(ic); 294#if 0 295 ic->ic_wme.wme_update = rt2661_wme_update; 296#endif 297 ic->ic_scan_start = rt2661_scan_start; 298 ic->ic_scan_end = rt2661_scan_end; 299 ic->ic_set_channel = rt2661_set_channel; 300 ic->ic_updateslot = rt2661_update_slot; 301 ic->ic_update_promisc = rt2661_update_promisc; 302 ic->ic_raw_xmit = rt2661_raw_xmit; 303 ic->ic_transmit = rt2661_transmit; 304 ic->ic_parent = rt2661_parent; 305 ic->ic_vap_create = rt2661_vap_create; 306 ic->ic_vap_delete = rt2661_vap_delete; 307 308 ieee80211_radiotap_attach(ic, 309 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 310 RT2661_TX_RADIOTAP_PRESENT, 311 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 312 RT2661_RX_RADIOTAP_PRESENT); 313 314#ifdef RAL_DEBUG 315 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 316 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 317 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 318#endif 319 if (bootverbose) 320 ieee80211_announce(ic); 321 322 return 0; 323 324fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 325fail2: while (--ac >= 0) 326 rt2661_free_tx_ring(sc, &sc->txq[ac]); 327fail1: mtx_destroy(&sc->sc_mtx); 328 return error; 329} 330 331int 332rt2661_detach(void *xsc) 333{ 334 struct rt2661_softc *sc = xsc; 335 struct ieee80211com *ic = &sc->sc_ic; 336 337 RAL_LOCK(sc); 338 rt2661_stop_locked(sc); 339 RAL_UNLOCK(sc); 340 341 ieee80211_ifdetach(ic); 342 mbufq_drain(&sc->sc_snd); 343 344 rt2661_free_tx_ring(sc, &sc->txq[0]); 345 rt2661_free_tx_ring(sc, &sc->txq[1]); 346 rt2661_free_tx_ring(sc, &sc->txq[2]); 347 rt2661_free_tx_ring(sc, &sc->txq[3]); 348 rt2661_free_tx_ring(sc, &sc->mgtq); 349 rt2661_free_rx_ring(sc, &sc->rxq); 350 351 mtx_destroy(&sc->sc_mtx); 352 353 return 0; 354} 355 356static struct ieee80211vap * 357rt2661_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 358 enum ieee80211_opmode opmode, int flags, 359 const uint8_t bssid[IEEE80211_ADDR_LEN], 360 const uint8_t mac[IEEE80211_ADDR_LEN]) 361{ 362 struct rt2661_softc *sc = ic->ic_softc; 363 struct rt2661_vap *rvp; 364 struct ieee80211vap *vap; 365 366 switch (opmode) { 367 case IEEE80211_M_STA: 368 case IEEE80211_M_IBSS: 369 case IEEE80211_M_AHDEMO: 370 case IEEE80211_M_MONITOR: 371 case IEEE80211_M_HOSTAP: 372 case IEEE80211_M_MBSS: 373 /* XXXRP: TBD */ 374 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 375 device_printf(sc->sc_dev, "only 1 vap supported\n"); 376 return NULL; 377 } 378 if (opmode == IEEE80211_M_STA) 379 flags |= IEEE80211_CLONE_NOBEACONS; 380 break; 381 case IEEE80211_M_WDS: 382 if (TAILQ_EMPTY(&ic->ic_vaps) || 383 ic->ic_opmode != IEEE80211_M_HOSTAP) { 384 device_printf(sc->sc_dev, 385 "wds only supported in ap mode\n"); 386 return NULL; 387 } 388 /* 389 * Silently remove any request for a unique 390 * bssid; WDS vap's always share the local 391 * mac address. 392 */ 393 flags &= ~IEEE80211_CLONE_BSSID; 394 break; 395 default: 396 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 397 return NULL; 398 } 399 rvp = malloc(sizeof(struct rt2661_vap), M_80211_VAP, M_WAITOK | M_ZERO); 400 vap = &rvp->ral_vap; 401 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 402 403 /* override state transition machine */ 404 rvp->ral_newstate = vap->iv_newstate; 405 vap->iv_newstate = rt2661_newstate; 406#if 0 407 vap->iv_update_beacon = rt2661_beacon_update; 408#endif 409 410 ieee80211_ratectl_init(vap); 411 /* complete setup */ 412 ieee80211_vap_attach(vap, ieee80211_media_change, 413 ieee80211_media_status, mac); 414 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 415 ic->ic_opmode = opmode; 416 return vap; 417} 418 419static void 420rt2661_vap_delete(struct ieee80211vap *vap) 421{ 422 struct rt2661_vap *rvp = RT2661_VAP(vap); 423 424 ieee80211_ratectl_deinit(vap); 425 ieee80211_vap_detach(vap); 426 free(rvp, M_80211_VAP); 427} 428 429void 430rt2661_shutdown(void *xsc) 431{ 432 struct rt2661_softc *sc = xsc; 433 434 rt2661_stop(sc); 435} 436 437void 438rt2661_suspend(void *xsc) 439{ 440 struct rt2661_softc *sc = xsc; 441 442 rt2661_stop(sc); 443} 444 445void 446rt2661_resume(void *xsc) 447{ 448 struct rt2661_softc *sc = xsc; 449 450 if (sc->sc_ic.ic_nrunning > 0) 451 rt2661_init(sc); 452} 453 454static void 455rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 456{ 457 if (error != 0) 458 return; 459 460 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 461 462 *(bus_addr_t *)arg = segs[0].ds_addr; 463} 464 465static int 466rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 467 int count) 468{ 469 int i, error; 470 471 ring->count = count; 472 ring->queued = 0; 473 ring->cur = ring->next = ring->stat = 0; 474 475 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 476 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 477 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 478 0, NULL, NULL, &ring->desc_dmat); 479 if (error != 0) { 480 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 481 goto fail; 482 } 483 484 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 485 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 486 if (error != 0) { 487 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 488 goto fail; 489 } 490 491 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 492 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 493 0); 494 if (error != 0) { 495 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 496 goto fail; 497 } 498 499 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 500 M_NOWAIT | M_ZERO); 501 if (ring->data == NULL) { 502 device_printf(sc->sc_dev, "could not allocate soft data\n"); 503 error = ENOMEM; 504 goto fail; 505 } 506 507 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 508 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 509 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 510 if (error != 0) { 511 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 512 goto fail; 513 } 514 515 for (i = 0; i < count; i++) { 516 error = bus_dmamap_create(ring->data_dmat, 0, 517 &ring->data[i].map); 518 if (error != 0) { 519 device_printf(sc->sc_dev, "could not create DMA map\n"); 520 goto fail; 521 } 522 } 523 524 return 0; 525 526fail: rt2661_free_tx_ring(sc, ring); 527 return error; 528} 529 530static void 531rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 532{ 533 struct rt2661_tx_desc *desc; 534 struct rt2661_tx_data *data; 535 int i; 536 537 for (i = 0; i < ring->count; i++) { 538 desc = &ring->desc[i]; 539 data = &ring->data[i]; 540 541 if (data->m != NULL) { 542 bus_dmamap_sync(ring->data_dmat, data->map, 543 BUS_DMASYNC_POSTWRITE); 544 bus_dmamap_unload(ring->data_dmat, data->map); 545 m_freem(data->m); 546 data->m = NULL; 547 } 548 549 if (data->ni != NULL) { 550 ieee80211_free_node(data->ni); 551 data->ni = NULL; 552 } 553 554 desc->flags = 0; 555 } 556 557 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 558 559 ring->queued = 0; 560 ring->cur = ring->next = ring->stat = 0; 561} 562 563static void 564rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 565{ 566 struct rt2661_tx_data *data; 567 int i; 568 569 if (ring->desc != NULL) { 570 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 571 BUS_DMASYNC_POSTWRITE); 572 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 573 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 574 } 575 576 if (ring->desc_dmat != NULL) 577 bus_dma_tag_destroy(ring->desc_dmat); 578 579 if (ring->data != NULL) { 580 for (i = 0; i < ring->count; i++) { 581 data = &ring->data[i]; 582 583 if (data->m != NULL) { 584 bus_dmamap_sync(ring->data_dmat, data->map, 585 BUS_DMASYNC_POSTWRITE); 586 bus_dmamap_unload(ring->data_dmat, data->map); 587 m_freem(data->m); 588 } 589 590 if (data->ni != NULL) 591 ieee80211_free_node(data->ni); 592 593 if (data->map != NULL) 594 bus_dmamap_destroy(ring->data_dmat, data->map); 595 } 596 597 free(ring->data, M_DEVBUF); 598 } 599 600 if (ring->data_dmat != NULL) 601 bus_dma_tag_destroy(ring->data_dmat); 602} 603 604static int 605rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 606 int count) 607{ 608 struct rt2661_rx_desc *desc; 609 struct rt2661_rx_data *data; 610 bus_addr_t physaddr; 611 int i, error; 612 613 ring->count = count; 614 ring->cur = ring->next = 0; 615 616 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 617 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 618 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 619 0, NULL, NULL, &ring->desc_dmat); 620 if (error != 0) { 621 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 622 goto fail; 623 } 624 625 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 626 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 627 if (error != 0) { 628 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 629 goto fail; 630 } 631 632 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 633 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 634 0); 635 if (error != 0) { 636 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 637 goto fail; 638 } 639 640 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 641 M_NOWAIT | M_ZERO); 642 if (ring->data == NULL) { 643 device_printf(sc->sc_dev, "could not allocate soft data\n"); 644 error = ENOMEM; 645 goto fail; 646 } 647 648 /* 649 * Pre-allocate Rx buffers and populate Rx ring. 650 */ 651 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 652 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 653 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 654 if (error != 0) { 655 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 656 goto fail; 657 } 658 659 for (i = 0; i < count; i++) { 660 desc = &sc->rxq.desc[i]; 661 data = &sc->rxq.data[i]; 662 663 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 664 if (error != 0) { 665 device_printf(sc->sc_dev, "could not create DMA map\n"); 666 goto fail; 667 } 668 669 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 670 if (data->m == NULL) { 671 device_printf(sc->sc_dev, 672 "could not allocate rx mbuf\n"); 673 error = ENOMEM; 674 goto fail; 675 } 676 677 error = bus_dmamap_load(ring->data_dmat, data->map, 678 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 679 &physaddr, 0); 680 if (error != 0) { 681 device_printf(sc->sc_dev, 682 "could not load rx buf DMA map"); 683 goto fail; 684 } 685 686 desc->flags = htole32(RT2661_RX_BUSY); 687 desc->physaddr = htole32(physaddr); 688 } 689 690 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 691 692 return 0; 693 694fail: rt2661_free_rx_ring(sc, ring); 695 return error; 696} 697 698static void 699rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 700{ 701 int i; 702 703 for (i = 0; i < ring->count; i++) 704 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 705 706 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 707 708 ring->cur = ring->next = 0; 709} 710 711static void 712rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 713{ 714 struct rt2661_rx_data *data; 715 int i; 716 717 if (ring->desc != NULL) { 718 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 719 BUS_DMASYNC_POSTWRITE); 720 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 721 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 722 } 723 724 if (ring->desc_dmat != NULL) 725 bus_dma_tag_destroy(ring->desc_dmat); 726 727 if (ring->data != NULL) { 728 for (i = 0; i < ring->count; i++) { 729 data = &ring->data[i]; 730 731 if (data->m != NULL) { 732 bus_dmamap_sync(ring->data_dmat, data->map, 733 BUS_DMASYNC_POSTREAD); 734 bus_dmamap_unload(ring->data_dmat, data->map); 735 m_freem(data->m); 736 } 737 738 if (data->map != NULL) 739 bus_dmamap_destroy(ring->data_dmat, data->map); 740 } 741 742 free(ring->data, M_DEVBUF); 743 } 744 745 if (ring->data_dmat != NULL) 746 bus_dma_tag_destroy(ring->data_dmat); 747} 748 749static int 750rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 751{ 752 struct rt2661_vap *rvp = RT2661_VAP(vap); 753 struct ieee80211com *ic = vap->iv_ic; 754 struct rt2661_softc *sc = ic->ic_softc; 755 int error; 756 757 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 758 uint32_t tmp; 759 760 /* abort TSF synchronization */ 761 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 762 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 763 } 764 765 error = rvp->ral_newstate(vap, nstate, arg); 766 767 if (error == 0 && nstate == IEEE80211_S_RUN) { 768 struct ieee80211_node *ni = vap->iv_bss; 769 770 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 771 rt2661_enable_mrr(sc); 772 rt2661_set_txpreamble(sc); 773 rt2661_set_basicrates(sc, &ni->ni_rates); 774 rt2661_set_bssid(sc, ni->ni_bssid); 775 } 776 777 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 778 vap->iv_opmode == IEEE80211_M_IBSS || 779 vap->iv_opmode == IEEE80211_M_MBSS) { 780 error = rt2661_prepare_beacon(sc, vap); 781 if (error != 0) 782 return error; 783 } 784 if (vap->iv_opmode != IEEE80211_M_MONITOR) 785 rt2661_enable_tsf_sync(sc); 786 else 787 rt2661_enable_tsf(sc); 788 } 789 return error; 790} 791 792/* 793 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 794 * 93C66). 795 */ 796static uint16_t 797rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 798{ 799 uint32_t tmp; 800 uint16_t val; 801 int n; 802 803 /* clock C once before the first command */ 804 RT2661_EEPROM_CTL(sc, 0); 805 806 RT2661_EEPROM_CTL(sc, RT2661_S); 807 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 808 RT2661_EEPROM_CTL(sc, RT2661_S); 809 810 /* write start bit (1) */ 811 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 812 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 813 814 /* write READ opcode (10) */ 815 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 816 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 817 RT2661_EEPROM_CTL(sc, RT2661_S); 818 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 819 820 /* write address (A5-A0 or A7-A0) */ 821 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 822 for (; n >= 0; n--) { 823 RT2661_EEPROM_CTL(sc, RT2661_S | 824 (((addr >> n) & 1) << RT2661_SHIFT_D)); 825 RT2661_EEPROM_CTL(sc, RT2661_S | 826 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 827 } 828 829 RT2661_EEPROM_CTL(sc, RT2661_S); 830 831 /* read data Q15-Q0 */ 832 val = 0; 833 for (n = 15; n >= 0; n--) { 834 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 835 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 836 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 837 RT2661_EEPROM_CTL(sc, RT2661_S); 838 } 839 840 RT2661_EEPROM_CTL(sc, 0); 841 842 /* clear Chip Select and clock C */ 843 RT2661_EEPROM_CTL(sc, RT2661_S); 844 RT2661_EEPROM_CTL(sc, 0); 845 RT2661_EEPROM_CTL(sc, RT2661_C); 846 847 return val; 848} 849 850static void 851rt2661_tx_intr(struct rt2661_softc *sc) 852{ 853 struct rt2661_tx_ring *txq; 854 struct rt2661_tx_data *data; 855 uint32_t val; 856 int error, qid, retrycnt; 857 struct ieee80211vap *vap; 858 859 for (;;) { 860 struct ieee80211_node *ni; 861 struct mbuf *m; 862 863 val = RAL_READ(sc, RT2661_STA_CSR4); 864 if (!(val & RT2661_TX_STAT_VALID)) 865 break; 866 867 /* retrieve the queue in which this frame was sent */ 868 qid = RT2661_TX_QID(val); 869 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 870 871 /* retrieve rate control algorithm context */ 872 data = &txq->data[txq->stat]; 873 m = data->m; 874 data->m = NULL; 875 ni = data->ni; 876 data->ni = NULL; 877 878 /* if no frame has been sent, ignore */ 879 if (ni == NULL) 880 continue; 881 else 882 vap = ni->ni_vap; 883 884 switch (RT2661_TX_RESULT(val)) { 885 case RT2661_TX_SUCCESS: 886 retrycnt = RT2661_TX_RETRYCNT(val); 887 888 DPRINTFN(sc, 10, "data frame sent successfully after " 889 "%d retries\n", retrycnt); 890 if (data->rix != IEEE80211_FIXED_RATE_NONE) 891 ieee80211_ratectl_tx_complete(vap, ni, 892 IEEE80211_RATECTL_TX_SUCCESS, 893 &retrycnt, NULL); 894 error = 0; 895 break; 896 897 case RT2661_TX_RETRY_FAIL: 898 retrycnt = RT2661_TX_RETRYCNT(val); 899 900 DPRINTFN(sc, 9, "%s\n", 901 "sending data frame failed (too much retries)"); 902 if (data->rix != IEEE80211_FIXED_RATE_NONE) 903 ieee80211_ratectl_tx_complete(vap, ni, 904 IEEE80211_RATECTL_TX_FAILURE, 905 &retrycnt, NULL); 906 error = 1; 907 break; 908 909 default: 910 /* other failure */ 911 device_printf(sc->sc_dev, 912 "sending data frame failed 0x%08x\n", val); 913 error = 1; 914 } 915 916 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 917 918 txq->queued--; 919 if (++txq->stat >= txq->count) /* faster than % count */ 920 txq->stat = 0; 921 922 ieee80211_tx_complete(ni, m, error); 923 } 924 925 sc->sc_tx_timer = 0; 926 927 rt2661_start(sc); 928} 929 930static void 931rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 932{ 933 struct rt2661_tx_desc *desc; 934 struct rt2661_tx_data *data; 935 936 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 937 938 for (;;) { 939 desc = &txq->desc[txq->next]; 940 data = &txq->data[txq->next]; 941 942 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 943 !(le32toh(desc->flags) & RT2661_TX_VALID)) 944 break; 945 946 bus_dmamap_sync(txq->data_dmat, data->map, 947 BUS_DMASYNC_POSTWRITE); 948 bus_dmamap_unload(txq->data_dmat, data->map); 949 950 /* descriptor is no longer valid */ 951 desc->flags &= ~htole32(RT2661_TX_VALID); 952 953 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 954 955 if (++txq->next >= txq->count) /* faster than % count */ 956 txq->next = 0; 957 } 958 959 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 960} 961 962static void 963rt2661_rx_intr(struct rt2661_softc *sc) 964{ 965 struct ieee80211com *ic = &sc->sc_ic; 966 struct rt2661_rx_desc *desc; 967 struct rt2661_rx_data *data; 968 bus_addr_t physaddr; 969 struct ieee80211_frame *wh; 970 struct ieee80211_node *ni; 971 struct mbuf *mnew, *m; 972 int error; 973 974 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 975 BUS_DMASYNC_POSTREAD); 976 977 for (;;) { 978 int8_t rssi, nf; 979 980 desc = &sc->rxq.desc[sc->rxq.cur]; 981 data = &sc->rxq.data[sc->rxq.cur]; 982 983 if (le32toh(desc->flags) & RT2661_RX_BUSY) 984 break; 985 986 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 987 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 988 /* 989 * This should not happen since we did not request 990 * to receive those frames when we filled TXRX_CSR0. 991 */ 992 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 993 le32toh(desc->flags)); 994 counter_u64_add(ic->ic_ierrors, 1); 995 goto skip; 996 } 997 998 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 999 counter_u64_add(ic->ic_ierrors, 1); 1000 goto skip; 1001 } 1002 1003 /* 1004 * Try to allocate a new mbuf for this ring element and load it 1005 * before processing the current mbuf. If the ring element 1006 * cannot be loaded, drop the received packet and reuse the old 1007 * mbuf. In the unlikely case that the old mbuf can't be 1008 * reloaded either, explicitly panic. 1009 */ 1010 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1011 if (mnew == NULL) { 1012 counter_u64_add(ic->ic_ierrors, 1); 1013 goto skip; 1014 } 1015 1016 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1017 BUS_DMASYNC_POSTREAD); 1018 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1019 1020 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1021 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1022 &physaddr, 0); 1023 if (error != 0) { 1024 m_freem(mnew); 1025 1026 /* try to reload the old mbuf */ 1027 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1028 mtod(data->m, void *), MCLBYTES, 1029 rt2661_dma_map_addr, &physaddr, 0); 1030 if (error != 0) { 1031 /* very unlikely that it will fail... */ 1032 panic("%s: could not load old rx mbuf", 1033 device_get_name(sc->sc_dev)); 1034 } 1035 counter_u64_add(ic->ic_ierrors, 1); 1036 goto skip; 1037 } 1038 1039 /* 1040 * New mbuf successfully loaded, update Rx ring and continue 1041 * processing. 1042 */ 1043 m = data->m; 1044 data->m = mnew; 1045 desc->physaddr = htole32(physaddr); 1046 1047 /* finalize mbuf */ 1048 m->m_pkthdr.len = m->m_len = 1049 (le32toh(desc->flags) >> 16) & 0xfff; 1050 1051 rssi = rt2661_get_rssi(sc, desc->rssi); 1052 /* Error happened during RSSI conversion. */ 1053 if (rssi < 0) 1054 rssi = -30; /* XXX ignored by net80211 */ 1055 nf = RT2661_NOISE_FLOOR; 1056 1057 if (ieee80211_radiotap_active(ic)) { 1058 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1059 uint32_t tsf_lo, tsf_hi; 1060 1061 /* get timestamp (low and high 32 bits) */ 1062 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1063 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1064 1065 tap->wr_tsf = 1066 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1067 tap->wr_flags = 0; 1068 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1069 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1070 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1071 tap->wr_antsignal = nf + rssi; 1072 tap->wr_antnoise = nf; 1073 } 1074 sc->sc_flags |= RAL_INPUT_RUNNING; 1075 RAL_UNLOCK(sc); 1076 wh = mtod(m, struct ieee80211_frame *); 1077 1078 /* send the frame to the 802.11 layer */ 1079 ni = ieee80211_find_rxnode(ic, 1080 (struct ieee80211_frame_min *)wh); 1081 if (ni != NULL) { 1082 (void) ieee80211_input(ni, m, rssi, nf); 1083 ieee80211_free_node(ni); 1084 } else 1085 (void) ieee80211_input_all(ic, m, rssi, nf); 1086 1087 RAL_LOCK(sc); 1088 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1089 1090skip: desc->flags |= htole32(RT2661_RX_BUSY); 1091 1092 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1093 1094 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1095 } 1096 1097 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1098 BUS_DMASYNC_PREWRITE); 1099} 1100 1101/* ARGSUSED */ 1102static void 1103rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1104{ 1105 /* do nothing */ 1106} 1107 1108static void 1109rt2661_mcu_wakeup(struct rt2661_softc *sc) 1110{ 1111 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1112 1113 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1114 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1115 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1116 1117 /* send wakeup command to MCU */ 1118 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1119} 1120 1121static void 1122rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1123{ 1124 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1125 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1126} 1127 1128void 1129rt2661_intr(void *arg) 1130{ 1131 struct rt2661_softc *sc = arg; 1132 uint32_t r1, r2; 1133 1134 RAL_LOCK(sc); 1135 1136 /* disable MAC and MCU interrupts */ 1137 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1138 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1139 1140 /* don't re-enable interrupts if we're shutting down */ 1141 if (!(sc->sc_flags & RAL_RUNNING)) { 1142 RAL_UNLOCK(sc); 1143 return; 1144 } 1145 1146 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1147 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1148 1149 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1150 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1151 1152 if (r1 & RT2661_MGT_DONE) 1153 rt2661_tx_dma_intr(sc, &sc->mgtq); 1154 1155 if (r1 & RT2661_RX_DONE) 1156 rt2661_rx_intr(sc); 1157 1158 if (r1 & RT2661_TX0_DMA_DONE) 1159 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1160 1161 if (r1 & RT2661_TX1_DMA_DONE) 1162 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1163 1164 if (r1 & RT2661_TX2_DMA_DONE) 1165 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1166 1167 if (r1 & RT2661_TX3_DMA_DONE) 1168 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1169 1170 if (r1 & RT2661_TX_DONE) 1171 rt2661_tx_intr(sc); 1172 1173 if (r2 & RT2661_MCU_CMD_DONE) 1174 rt2661_mcu_cmd_intr(sc); 1175 1176 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1177 rt2661_mcu_beacon_expire(sc); 1178 1179 if (r2 & RT2661_MCU_WAKEUP) 1180 rt2661_mcu_wakeup(sc); 1181 1182 /* re-enable MAC and MCU interrupts */ 1183 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1184 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1185 1186 RAL_UNLOCK(sc); 1187} 1188 1189static uint8_t 1190rt2661_plcp_signal(int rate) 1191{ 1192 switch (rate) { 1193 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1194 case 12: return 0xb; 1195 case 18: return 0xf; 1196 case 24: return 0xa; 1197 case 36: return 0xe; 1198 case 48: return 0x9; 1199 case 72: return 0xd; 1200 case 96: return 0x8; 1201 case 108: return 0xc; 1202 1203 /* CCK rates (NB: not IEEE std, device-specific) */ 1204 case 2: return 0x0; 1205 case 4: return 0x1; 1206 case 11: return 0x2; 1207 case 22: return 0x3; 1208 } 1209 return 0xff; /* XXX unsupported/unknown rate */ 1210} 1211 1212static void 1213rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1214 uint32_t flags, uint16_t xflags, int len, int rate, 1215 const bus_dma_segment_t *segs, int nsegs, int ac) 1216{ 1217 struct ieee80211com *ic = &sc->sc_ic; 1218 uint16_t plcp_length; 1219 int i, remainder; 1220 1221 desc->flags = htole32(flags); 1222 desc->flags |= htole32(len << 16); 1223 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1224 1225 desc->xflags = htole16(xflags); 1226 desc->xflags |= htole16(nsegs << 13); 1227 1228 desc->wme = htole16( 1229 RT2661_QID(ac) | 1230 RT2661_AIFSN(2) | 1231 RT2661_LOGCWMIN(4) | 1232 RT2661_LOGCWMAX(10)); 1233 1234 /* 1235 * Remember in which queue this frame was sent. This field is driver 1236 * private data only. It will be made available by the NIC in STA_CSR4 1237 * on Tx interrupts. 1238 */ 1239 desc->qid = ac; 1240 1241 /* setup PLCP fields */ 1242 desc->plcp_signal = rt2661_plcp_signal(rate); 1243 desc->plcp_service = 4; 1244 1245 len += IEEE80211_CRC_LEN; 1246 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1247 desc->flags |= htole32(RT2661_TX_OFDM); 1248 1249 plcp_length = len & 0xfff; 1250 desc->plcp_length_hi = plcp_length >> 6; 1251 desc->plcp_length_lo = plcp_length & 0x3f; 1252 } else { 1253 plcp_length = howmany(16 * len, rate); 1254 if (rate == 22) { 1255 remainder = (16 * len) % 22; 1256 if (remainder != 0 && remainder < 7) 1257 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1258 } 1259 desc->plcp_length_hi = plcp_length >> 8; 1260 desc->plcp_length_lo = plcp_length & 0xff; 1261 1262 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1263 desc->plcp_signal |= 0x08; 1264 } 1265 1266 /* RT2x61 supports scatter with up to 5 segments */ 1267 for (i = 0; i < nsegs; i++) { 1268 desc->addr[i] = htole32(segs[i].ds_addr); 1269 desc->len [i] = htole16(segs[i].ds_len); 1270 } 1271} 1272 1273static int 1274rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1275 struct ieee80211_node *ni) 1276{ 1277 struct ieee80211vap *vap = ni->ni_vap; 1278 struct ieee80211com *ic = ni->ni_ic; 1279 struct rt2661_tx_desc *desc; 1280 struct rt2661_tx_data *data; 1281 struct ieee80211_frame *wh; 1282 struct ieee80211_key *k; 1283 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1284 uint16_t dur; 1285 uint32_t flags = 0; /* XXX HWSEQ */ 1286 int nsegs, rate, error; 1287 1288 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1289 data = &sc->mgtq.data[sc->mgtq.cur]; 1290 1291 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1292 1293 wh = mtod(m0, struct ieee80211_frame *); 1294 1295 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1296 k = ieee80211_crypto_encap(ni, m0); 1297 if (k == NULL) { 1298 m_freem(m0); 1299 return ENOBUFS; 1300 } 1301 } 1302 1303 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1304 segs, &nsegs, 0); 1305 if (error != 0) { 1306 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1307 error); 1308 m_freem(m0); 1309 return error; 1310 } 1311 1312 if (ieee80211_radiotap_active_vap(vap)) { 1313 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1314 1315 tap->wt_flags = 0; 1316 tap->wt_rate = rate; 1317 1318 ieee80211_radiotap_tx(vap, m0); 1319 } 1320 1321 data->m = m0; 1322 data->ni = ni; 1323 /* management frames are not taken into account for amrr */ 1324 data->rix = IEEE80211_FIXED_RATE_NONE; 1325 1326 wh = mtod(m0, struct ieee80211_frame *); 1327 1328 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1329 flags |= RT2661_TX_NEED_ACK; 1330 1331 dur = ieee80211_ack_duration(ic->ic_rt, 1332 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1333 *(uint16_t *)wh->i_dur = htole16(dur); 1334 1335 /* tell hardware to add timestamp in probe responses */ 1336 if ((wh->i_fc[0] & 1337 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1338 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1339 flags |= RT2661_TX_TIMESTAMP; 1340 } 1341 1342 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1343 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1344 1345 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1346 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1347 BUS_DMASYNC_PREWRITE); 1348 1349 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1350 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1351 1352 /* kick mgt */ 1353 sc->mgtq.queued++; 1354 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1355 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1356 1357 return 0; 1358} 1359 1360static int 1361rt2661_sendprot(struct rt2661_softc *sc, int ac, 1362 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1363{ 1364 struct ieee80211com *ic = ni->ni_ic; 1365 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1366 const struct ieee80211_frame *wh; 1367 struct rt2661_tx_desc *desc; 1368 struct rt2661_tx_data *data; 1369 struct mbuf *mprot; 1370 int protrate, ackrate, pktlen, flags, isshort, error; 1371 uint16_t dur; 1372 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1373 int nsegs; 1374 1375 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1376 ("protection %d", prot)); 1377 1378 wh = mtod(m, const struct ieee80211_frame *); 1379 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1380 1381 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1382 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1383 1384 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1385 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1386 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1387 flags = RT2661_TX_MORE_FRAG; 1388 if (prot == IEEE80211_PROT_RTSCTS) { 1389 /* NB: CTS is the same size as an ACK */ 1390 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1391 flags |= RT2661_TX_NEED_ACK; 1392 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1393 } else { 1394 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1395 } 1396 if (mprot == NULL) { 1397 /* XXX stat + msg */ 1398 return ENOBUFS; 1399 } 1400 1401 data = &txq->data[txq->cur]; 1402 desc = &txq->desc[txq->cur]; 1403 1404 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1405 &nsegs, 0); 1406 if (error != 0) { 1407 device_printf(sc->sc_dev, 1408 "could not map mbuf (error %d)\n", error); 1409 m_freem(mprot); 1410 return error; 1411 } 1412 1413 data->m = mprot; 1414 data->ni = ieee80211_ref_node(ni); 1415 /* ctl frames are not taken into account for amrr */ 1416 data->rix = IEEE80211_FIXED_RATE_NONE; 1417 1418 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1419 protrate, segs, 1, ac); 1420 1421 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1422 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1423 1424 txq->queued++; 1425 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1426 1427 return 0; 1428} 1429 1430static int 1431rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1432 struct ieee80211_node *ni, int ac) 1433{ 1434 struct ieee80211vap *vap = ni->ni_vap; 1435 struct ieee80211com *ic = &sc->sc_ic; 1436 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1437 struct rt2661_tx_desc *desc; 1438 struct rt2661_tx_data *data; 1439 struct ieee80211_frame *wh; 1440 const struct ieee80211_txparam *tp; 1441 struct ieee80211_key *k; 1442 const struct chanAccParams *cap; 1443 struct mbuf *mnew; 1444 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1445 uint16_t dur; 1446 uint32_t flags; 1447 int error, nsegs, rate, noack = 0; 1448 1449 wh = mtod(m0, struct ieee80211_frame *); 1450 1451 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1452 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1453 rate = tp->mcastrate; 1454 } else if (m0->m_flags & M_EAPOL) { 1455 rate = tp->mgmtrate; 1456 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1457 rate = tp->ucastrate; 1458 } else { 1459 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1460 rate = ni->ni_txrate; 1461 } 1462 rate &= IEEE80211_RATE_VAL; 1463 1464 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1465 cap = &ic->ic_wme.wme_chanParams; 1466 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1467 } 1468 1469 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1470 k = ieee80211_crypto_encap(ni, m0); 1471 if (k == NULL) { 1472 m_freem(m0); 1473 return ENOBUFS; 1474 } 1475 1476 /* packet header may have moved, reset our local pointer */ 1477 wh = mtod(m0, struct ieee80211_frame *); 1478 } 1479 1480 flags = 0; 1481 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1482 int prot = IEEE80211_PROT_NONE; 1483 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1484 prot = IEEE80211_PROT_RTSCTS; 1485 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1486 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1487 prot = ic->ic_protmode; 1488 if (prot != IEEE80211_PROT_NONE) { 1489 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1490 if (error) { 1491 m_freem(m0); 1492 return error; 1493 } 1494 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1495 } 1496 } 1497 1498 data = &txq->data[txq->cur]; 1499 desc = &txq->desc[txq->cur]; 1500 1501 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1502 &nsegs, 0); 1503 if (error != 0 && error != EFBIG) { 1504 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1505 error); 1506 m_freem(m0); 1507 return error; 1508 } 1509 if (error != 0) { 1510 mnew = m_defrag(m0, M_NOWAIT); 1511 if (mnew == NULL) { 1512 device_printf(sc->sc_dev, 1513 "could not defragment mbuf\n"); 1514 m_freem(m0); 1515 return ENOBUFS; 1516 } 1517 m0 = mnew; 1518 1519 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1520 segs, &nsegs, 0); 1521 if (error != 0) { 1522 device_printf(sc->sc_dev, 1523 "could not map mbuf (error %d)\n", error); 1524 m_freem(m0); 1525 return error; 1526 } 1527 1528 /* packet header have moved, reset our local pointer */ 1529 wh = mtod(m0, struct ieee80211_frame *); 1530 } 1531 1532 if (ieee80211_radiotap_active_vap(vap)) { 1533 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1534 1535 tap->wt_flags = 0; 1536 tap->wt_rate = rate; 1537 1538 ieee80211_radiotap_tx(vap, m0); 1539 } 1540 1541 data->m = m0; 1542 data->ni = ni; 1543 1544 /* remember link conditions for rate adaptation algorithm */ 1545 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1546 data->rix = ni->ni_txrate; 1547 /* XXX probably need last rssi value and not avg */ 1548 data->rssi = ic->ic_node_getrssi(ni); 1549 } else 1550 data->rix = IEEE80211_FIXED_RATE_NONE; 1551 1552 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1553 flags |= RT2661_TX_NEED_ACK; 1554 1555 dur = ieee80211_ack_duration(ic->ic_rt, 1556 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1557 *(uint16_t *)wh->i_dur = htole16(dur); 1558 } 1559 1560 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1561 nsegs, ac); 1562 1563 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1564 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1565 1566 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1567 m0->m_pkthdr.len, txq->cur, rate); 1568 1569 /* kick Tx */ 1570 txq->queued++; 1571 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1572 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1573 1574 return 0; 1575} 1576 1577static int 1578rt2661_transmit(struct ieee80211com *ic, struct mbuf *m) 1579{ 1580 struct rt2661_softc *sc = ic->ic_softc; 1581 int error; 1582 1583 RAL_LOCK(sc); 1584 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1585 RAL_UNLOCK(sc); 1586 return (ENXIO); 1587 } 1588 error = mbufq_enqueue(&sc->sc_snd, m); 1589 if (error) { 1590 RAL_UNLOCK(sc); 1591 return (error); 1592 } 1593 rt2661_start(sc); 1594 RAL_UNLOCK(sc); 1595 1596 return (0); 1597} 1598 1599static void 1600rt2661_start(struct rt2661_softc *sc) 1601{ 1602 struct mbuf *m; 1603 struct ieee80211_node *ni; 1604 int ac; 1605 1606 RAL_LOCK_ASSERT(sc); 1607 1608 /* prevent management frames from being sent if we're not ready */ 1609 if (!(sc->sc_flags & RAL_RUNNING) || sc->sc_invalid) 1610 return; 1611 1612 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1613 ac = M_WME_GETAC(m); 1614 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1615 /* there is no place left in this ring */ 1616 mbufq_prepend(&sc->sc_snd, m); 1617 break; 1618 } 1619 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1620 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1621 ieee80211_free_node(ni); 1622 if_inc_counter(ni->ni_vap->iv_ifp, 1623 IFCOUNTER_OERRORS, 1); 1624 break; 1625 } 1626 sc->sc_tx_timer = 5; 1627 } 1628} 1629 1630static int 1631rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1632 const struct ieee80211_bpf_params *params) 1633{ 1634 struct ieee80211com *ic = ni->ni_ic; 1635 struct rt2661_softc *sc = ic->ic_softc; 1636 1637 RAL_LOCK(sc); 1638 1639 /* prevent management frames from being sent if we're not ready */ 1640 if (!(sc->sc_flags & RAL_RUNNING)) { 1641 RAL_UNLOCK(sc); 1642 m_freem(m); 1643 return ENETDOWN; 1644 } 1645 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1646 RAL_UNLOCK(sc); 1647 m_freem(m); 1648 return ENOBUFS; /* XXX */ 1649 } 1650 1651 /* 1652 * Legacy path; interpret frame contents to decide 1653 * precisely how to send the frame. 1654 * XXX raw path 1655 */ 1656 if (rt2661_tx_mgt(sc, m, ni) != 0) 1657 goto bad; 1658 sc->sc_tx_timer = 5; 1659 1660 RAL_UNLOCK(sc); 1661 1662 return 0; 1663bad: 1664 RAL_UNLOCK(sc); 1665 return EIO; /* XXX */ 1666} 1667 1668static void 1669rt2661_watchdog(void *arg) 1670{ 1671 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1672 1673 RAL_LOCK_ASSERT(sc); 1674 1675 KASSERT(sc->sc_flags & RAL_RUNNING, ("not running")); 1676 1677 if (sc->sc_invalid) /* card ejected */ 1678 return; 1679 1680 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1681 device_printf(sc->sc_dev, "device timeout\n"); 1682 rt2661_init_locked(sc); 1683 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1684 /* NB: callout is reset in rt2661_init() */ 1685 return; 1686 } 1687 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1688} 1689 1690static void 1691rt2661_parent(struct ieee80211com *ic) 1692{ 1693 struct rt2661_softc *sc = ic->ic_softc; 1694 int startall = 0; 1695 1696 RAL_LOCK(sc); 1697 if (ic->ic_nrunning > 0) { 1698 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1699 rt2661_init_locked(sc); 1700 startall = 1; 1701 } else 1702 rt2661_update_promisc(ic); 1703 } else if (sc->sc_flags & RAL_RUNNING) 1704 rt2661_stop_locked(sc); 1705 RAL_UNLOCK(sc); 1706 if (startall) 1707 ieee80211_start_all(ic); 1708} 1709 1710static void 1711rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1712{ 1713 uint32_t tmp; 1714 int ntries; 1715 1716 for (ntries = 0; ntries < 100; ntries++) { 1717 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1718 break; 1719 DELAY(1); 1720 } 1721 if (ntries == 100) { 1722 device_printf(sc->sc_dev, "could not write to BBP\n"); 1723 return; 1724 } 1725 1726 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1727 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1728 1729 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1730} 1731 1732static uint8_t 1733rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1734{ 1735 uint32_t val; 1736 int ntries; 1737 1738 for (ntries = 0; ntries < 100; ntries++) { 1739 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1740 break; 1741 DELAY(1); 1742 } 1743 if (ntries == 100) { 1744 device_printf(sc->sc_dev, "could not read from BBP\n"); 1745 return 0; 1746 } 1747 1748 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1749 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1750 1751 for (ntries = 0; ntries < 100; ntries++) { 1752 val = RAL_READ(sc, RT2661_PHY_CSR3); 1753 if (!(val & RT2661_BBP_BUSY)) 1754 return val & 0xff; 1755 DELAY(1); 1756 } 1757 1758 device_printf(sc->sc_dev, "could not read from BBP\n"); 1759 return 0; 1760} 1761 1762static void 1763rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1764{ 1765 uint32_t tmp; 1766 int ntries; 1767 1768 for (ntries = 0; ntries < 100; ntries++) { 1769 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1770 break; 1771 DELAY(1); 1772 } 1773 if (ntries == 100) { 1774 device_printf(sc->sc_dev, "could not write to RF\n"); 1775 return; 1776 } 1777 1778 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1779 (reg & 3); 1780 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1781 1782 /* remember last written value in sc */ 1783 sc->rf_regs[reg] = val; 1784 1785 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1786} 1787 1788static int 1789rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1790{ 1791 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1792 return EIO; /* there is already a command pending */ 1793 1794 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1795 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1796 1797 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1798 1799 return 0; 1800} 1801 1802static void 1803rt2661_select_antenna(struct rt2661_softc *sc) 1804{ 1805 uint8_t bbp4, bbp77; 1806 uint32_t tmp; 1807 1808 bbp4 = rt2661_bbp_read(sc, 4); 1809 bbp77 = rt2661_bbp_read(sc, 77); 1810 1811 /* TBD */ 1812 1813 /* make sure Rx is disabled before switching antenna */ 1814 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1815 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1816 1817 rt2661_bbp_write(sc, 4, bbp4); 1818 rt2661_bbp_write(sc, 77, bbp77); 1819 1820 /* restore Rx filter */ 1821 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1822} 1823 1824/* 1825 * Enable multi-rate retries for frames sent at OFDM rates. 1826 * In 802.11b/g mode, allow fallback to CCK rates. 1827 */ 1828static void 1829rt2661_enable_mrr(struct rt2661_softc *sc) 1830{ 1831 struct ieee80211com *ic = &sc->sc_ic; 1832 uint32_t tmp; 1833 1834 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1835 1836 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1837 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1838 tmp |= RT2661_MRR_CCK_FALLBACK; 1839 tmp |= RT2661_MRR_ENABLED; 1840 1841 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1842} 1843 1844static void 1845rt2661_set_txpreamble(struct rt2661_softc *sc) 1846{ 1847 struct ieee80211com *ic = &sc->sc_ic; 1848 uint32_t tmp; 1849 1850 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1851 1852 tmp &= ~RT2661_SHORT_PREAMBLE; 1853 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1854 tmp |= RT2661_SHORT_PREAMBLE; 1855 1856 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1857} 1858 1859static void 1860rt2661_set_basicrates(struct rt2661_softc *sc, 1861 const struct ieee80211_rateset *rs) 1862{ 1863 struct ieee80211com *ic = &sc->sc_ic; 1864 uint32_t mask = 0; 1865 uint8_t rate; 1866 int i; 1867 1868 for (i = 0; i < rs->rs_nrates; i++) { 1869 rate = rs->rs_rates[i]; 1870 1871 if (!(rate & IEEE80211_RATE_BASIC)) 1872 continue; 1873 1874 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 1875 IEEE80211_RV(rate)); 1876 } 1877 1878 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1879 1880 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1881} 1882 1883/* 1884 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1885 * driver. 1886 */ 1887static void 1888rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1889{ 1890 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1891 uint32_t tmp; 1892 1893 /* update all BBP registers that depend on the band */ 1894 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1895 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1896 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1897 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1898 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1899 } 1900 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1901 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1902 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1903 } 1904 1905 rt2661_bbp_write(sc, 17, bbp17); 1906 rt2661_bbp_write(sc, 96, bbp96); 1907 rt2661_bbp_write(sc, 104, bbp104); 1908 1909 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1910 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1911 rt2661_bbp_write(sc, 75, 0x80); 1912 rt2661_bbp_write(sc, 86, 0x80); 1913 rt2661_bbp_write(sc, 88, 0x80); 1914 } 1915 1916 rt2661_bbp_write(sc, 35, bbp35); 1917 rt2661_bbp_write(sc, 97, bbp97); 1918 rt2661_bbp_write(sc, 98, bbp98); 1919 1920 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1921 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1922 if (IEEE80211_IS_CHAN_2GHZ(c)) 1923 tmp |= RT2661_PA_PE_2GHZ; 1924 else 1925 tmp |= RT2661_PA_PE_5GHZ; 1926 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1927} 1928 1929static void 1930rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1931{ 1932 struct ieee80211com *ic = &sc->sc_ic; 1933 const struct rfprog *rfprog; 1934 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 1935 int8_t power; 1936 u_int i, chan; 1937 1938 chan = ieee80211_chan2ieee(ic, c); 1939 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 1940 1941 /* select the appropriate RF settings based on what EEPROM says */ 1942 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 1943 1944 /* find the settings for this channel (we know it exists) */ 1945 for (i = 0; rfprog[i].chan != chan; i++); 1946 1947 power = sc->txpow[i]; 1948 if (power < 0) { 1949 bbp94 += power; 1950 power = 0; 1951 } else if (power > 31) { 1952 bbp94 += power - 31; 1953 power = 31; 1954 } 1955 1956 /* 1957 * If we are switching from the 2GHz band to the 5GHz band or 1958 * vice-versa, BBP registers need to be reprogrammed. 1959 */ 1960 if (c->ic_flags != sc->sc_curchan->ic_flags) { 1961 rt2661_select_band(sc, c); 1962 rt2661_select_antenna(sc); 1963 } 1964 sc->sc_curchan = c; 1965 1966 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1967 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1968 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 1969 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1970 1971 DELAY(200); 1972 1973 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1974 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1975 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 1976 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1977 1978 DELAY(200); 1979 1980 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1981 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1982 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 1983 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1984 1985 /* enable smart mode for MIMO-capable RFs */ 1986 bbp3 = rt2661_bbp_read(sc, 3); 1987 1988 bbp3 &= ~RT2661_SMART_MODE; 1989 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 1990 bbp3 |= RT2661_SMART_MODE; 1991 1992 rt2661_bbp_write(sc, 3, bbp3); 1993 1994 if (bbp94 != RT2661_BBPR94_DEFAULT) 1995 rt2661_bbp_write(sc, 94, bbp94); 1996 1997 /* 5GHz radio needs a 1ms delay here */ 1998 if (IEEE80211_IS_CHAN_5GHZ(c)) 1999 DELAY(1000); 2000} 2001 2002static void 2003rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2004{ 2005 uint32_t tmp; 2006 2007 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2008 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2009 2010 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2011 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2012} 2013 2014static void 2015rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2016{ 2017 uint32_t tmp; 2018 2019 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2020 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2021 2022 tmp = addr[4] | addr[5] << 8; 2023 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2024} 2025 2026static void 2027rt2661_update_promisc(struct ieee80211com *ic) 2028{ 2029 struct rt2661_softc *sc = ic->ic_softc; 2030 uint32_t tmp; 2031 2032 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2033 2034 tmp &= ~RT2661_DROP_NOT_TO_ME; 2035 if (ic->ic_promisc == 0) 2036 tmp |= RT2661_DROP_NOT_TO_ME; 2037 2038 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2039 2040 DPRINTF(sc, "%s promiscuous mode\n", 2041 (ic->ic_promisc > 0) ? "entering" : "leaving"); 2042} 2043 2044/* 2045 * Update QoS (802.11e) settings for each h/w Tx ring. 2046 */ 2047static int 2048rt2661_wme_update(struct ieee80211com *ic) 2049{ 2050 struct rt2661_softc *sc = ic->ic_softc; 2051 const struct wmeParams *wmep; 2052 2053 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2054 2055 /* XXX: not sure about shifts. */ 2056 /* XXX: the reference driver plays with AC_VI settings too. */ 2057 2058 /* update TxOp */ 2059 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2060 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2061 wmep[WME_AC_BK].wmep_txopLimit); 2062 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2063 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2064 wmep[WME_AC_VO].wmep_txopLimit); 2065 2066 /* update CWmin */ 2067 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2068 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2069 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2070 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2071 wmep[WME_AC_VO].wmep_logcwmin); 2072 2073 /* update CWmax */ 2074 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2075 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2076 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2077 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2078 wmep[WME_AC_VO].wmep_logcwmax); 2079 2080 /* update Aifsn */ 2081 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2082 wmep[WME_AC_BE].wmep_aifsn << 12 | 2083 wmep[WME_AC_BK].wmep_aifsn << 8 | 2084 wmep[WME_AC_VI].wmep_aifsn << 4 | 2085 wmep[WME_AC_VO].wmep_aifsn); 2086 2087 return 0; 2088} 2089 2090static void 2091rt2661_update_slot(struct ieee80211com *ic) 2092{ 2093 struct rt2661_softc *sc = ic->ic_softc; 2094 uint8_t slottime; 2095 uint32_t tmp; 2096 2097 slottime = IEEE80211_GET_SLOTTIME(ic); 2098 2099 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2100 tmp = (tmp & ~0xff) | slottime; 2101 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2102} 2103 2104static const char * 2105rt2661_get_rf(int rev) 2106{ 2107 switch (rev) { 2108 case RT2661_RF_5225: return "RT5225"; 2109 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2110 case RT2661_RF_2527: return "RT2527"; 2111 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2112 default: return "unknown"; 2113 } 2114} 2115 2116static void 2117rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2118{ 2119 uint16_t val; 2120 int i; 2121 2122 /* read MAC address */ 2123 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2124 macaddr[0] = val & 0xff; 2125 macaddr[1] = val >> 8; 2126 2127 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2128 macaddr[2] = val & 0xff; 2129 macaddr[3] = val >> 8; 2130 2131 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2132 macaddr[4] = val & 0xff; 2133 macaddr[5] = val >> 8; 2134 2135 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2136 /* XXX: test if different from 0xffff? */ 2137 sc->rf_rev = (val >> 11) & 0x1f; 2138 sc->hw_radio = (val >> 10) & 0x1; 2139 sc->rx_ant = (val >> 4) & 0x3; 2140 sc->tx_ant = (val >> 2) & 0x3; 2141 sc->nb_ant = val & 0x3; 2142 2143 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2144 2145 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2146 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2147 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2148 2149 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2150 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2151 2152 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2153 if ((val & 0xff) != 0xff) 2154 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2155 2156 /* Only [-10, 10] is valid */ 2157 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2158 sc->rssi_2ghz_corr = 0; 2159 2160 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2161 if ((val & 0xff) != 0xff) 2162 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2163 2164 /* Only [-10, 10] is valid */ 2165 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2166 sc->rssi_5ghz_corr = 0; 2167 2168 /* adjust RSSI correction for external low-noise amplifier */ 2169 if (sc->ext_2ghz_lna) 2170 sc->rssi_2ghz_corr -= 14; 2171 if (sc->ext_5ghz_lna) 2172 sc->rssi_5ghz_corr -= 14; 2173 2174 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2175 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2176 2177 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2178 if ((val >> 8) != 0xff) 2179 sc->rfprog = (val >> 8) & 0x3; 2180 if ((val & 0xff) != 0xff) 2181 sc->rffreq = val & 0xff; 2182 2183 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2184 2185 /* read Tx power for all a/b/g channels */ 2186 for (i = 0; i < 19; i++) { 2187 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2188 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2189 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2190 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2191 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2192 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2193 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2194 } 2195 2196 /* read vendor-specific BBP values */ 2197 for (i = 0; i < 16; i++) { 2198 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2199 if (val == 0 || val == 0xffff) 2200 continue; /* skip invalid entries */ 2201 sc->bbp_prom[i].reg = val >> 8; 2202 sc->bbp_prom[i].val = val & 0xff; 2203 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2204 sc->bbp_prom[i].val); 2205 } 2206} 2207 2208static int 2209rt2661_bbp_init(struct rt2661_softc *sc) 2210{ 2211 int i, ntries; 2212 uint8_t val; 2213 2214 /* wait for BBP to be ready */ 2215 for (ntries = 0; ntries < 100; ntries++) { 2216 val = rt2661_bbp_read(sc, 0); 2217 if (val != 0 && val != 0xff) 2218 break; 2219 DELAY(100); 2220 } 2221 if (ntries == 100) { 2222 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2223 return EIO; 2224 } 2225 2226 /* initialize BBP registers to default values */ 2227 for (i = 0; i < nitems(rt2661_def_bbp); i++) { 2228 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2229 rt2661_def_bbp[i].val); 2230 } 2231 2232 /* write vendor-specific BBP values (from EEPROM) */ 2233 for (i = 0; i < 16; i++) { 2234 if (sc->bbp_prom[i].reg == 0) 2235 continue; 2236 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2237 } 2238 2239 return 0; 2240} 2241 2242static void 2243rt2661_init_locked(struct rt2661_softc *sc) 2244{ 2245 struct ieee80211com *ic = &sc->sc_ic; 2246 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2247 uint32_t tmp, sta[3]; 2248 int i, error, ntries; 2249 2250 RAL_LOCK_ASSERT(sc); 2251 2252 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2253 error = rt2661_load_microcode(sc); 2254 if (error != 0) { 2255 device_printf(sc->sc_dev, 2256 "%s: could not load 8051 microcode, error %d\n", 2257 __func__, error); 2258 return; 2259 } 2260 sc->sc_flags |= RAL_FW_LOADED; 2261 } 2262 2263 rt2661_stop_locked(sc); 2264 2265 /* initialize Tx rings */ 2266 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2267 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2268 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2269 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2270 2271 /* initialize Mgt ring */ 2272 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2273 2274 /* initialize Rx ring */ 2275 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2276 2277 /* initialize Tx rings sizes */ 2278 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2279 RT2661_TX_RING_COUNT << 24 | 2280 RT2661_TX_RING_COUNT << 16 | 2281 RT2661_TX_RING_COUNT << 8 | 2282 RT2661_TX_RING_COUNT); 2283 2284 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2285 RT2661_TX_DESC_WSIZE << 16 | 2286 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2287 RT2661_MGT_RING_COUNT); 2288 2289 /* initialize Rx rings */ 2290 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2291 RT2661_RX_DESC_BACK << 16 | 2292 RT2661_RX_DESC_WSIZE << 8 | 2293 RT2661_RX_RING_COUNT); 2294 2295 /* XXX: some magic here */ 2296 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2297 2298 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2299 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2300 2301 /* load base address of Rx ring */ 2302 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2303 2304 /* initialize MAC registers to default values */ 2305 for (i = 0; i < nitems(rt2661_def_mac); i++) 2306 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2307 2308 rt2661_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2309 2310 /* set host ready */ 2311 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2312 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2313 2314 /* wait for BBP/RF to wakeup */ 2315 for (ntries = 0; ntries < 1000; ntries++) { 2316 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2317 break; 2318 DELAY(1000); 2319 } 2320 if (ntries == 1000) { 2321 printf("timeout waiting for BBP/RF to wakeup\n"); 2322 rt2661_stop_locked(sc); 2323 return; 2324 } 2325 2326 if (rt2661_bbp_init(sc) != 0) { 2327 rt2661_stop_locked(sc); 2328 return; 2329 } 2330 2331 /* select default channel */ 2332 sc->sc_curchan = ic->ic_curchan; 2333 rt2661_select_band(sc, sc->sc_curchan); 2334 rt2661_select_antenna(sc); 2335 rt2661_set_chan(sc, sc->sc_curchan); 2336 2337 /* update Rx filter */ 2338 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2339 2340 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2341 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2342 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2343 RT2661_DROP_ACKCTS; 2344 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2345 ic->ic_opmode != IEEE80211_M_MBSS) 2346 tmp |= RT2661_DROP_TODS; 2347 if (ic->ic_promisc == 0) 2348 tmp |= RT2661_DROP_NOT_TO_ME; 2349 } 2350 2351 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2352 2353 /* clear STA registers */ 2354 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta)); 2355 2356 /* initialize ASIC */ 2357 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2358 2359 /* clear any pending interrupt */ 2360 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2361 2362 /* enable interrupts */ 2363 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2364 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2365 2366 /* kick Rx */ 2367 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2368 2369 sc->sc_flags |= RAL_RUNNING; 2370 2371 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2372} 2373 2374static void 2375rt2661_init(void *priv) 2376{ 2377 struct rt2661_softc *sc = priv; 2378 struct ieee80211com *ic = &sc->sc_ic; 2379 2380 RAL_LOCK(sc); 2381 rt2661_init_locked(sc); 2382 RAL_UNLOCK(sc); 2383 2384 if (sc->sc_flags & RAL_RUNNING) 2385 ieee80211_start_all(ic); /* start all vap's */ 2386} 2387 2388void 2389rt2661_stop_locked(struct rt2661_softc *sc) 2390{ 2391 volatile int *flags = &sc->sc_flags; 2392 uint32_t tmp; 2393 2394 while (*flags & RAL_INPUT_RUNNING) 2395 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2396 2397 callout_stop(&sc->watchdog_ch); 2398 sc->sc_tx_timer = 0; 2399 2400 if (sc->sc_flags & RAL_RUNNING) { 2401 sc->sc_flags &= ~RAL_RUNNING; 2402 2403 /* abort Tx (for all 5 Tx rings) */ 2404 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2405 2406 /* disable Rx (value remains after reset!) */ 2407 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2408 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2409 2410 /* reset ASIC */ 2411 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2412 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2413 2414 /* disable interrupts */ 2415 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2416 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2417 2418 /* clear any pending interrupt */ 2419 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2420 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2421 2422 /* reset Tx and Rx rings */ 2423 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2424 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2425 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2426 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2427 rt2661_reset_tx_ring(sc, &sc->mgtq); 2428 rt2661_reset_rx_ring(sc, &sc->rxq); 2429 } 2430} 2431 2432void 2433rt2661_stop(void *priv) 2434{ 2435 struct rt2661_softc *sc = priv; 2436 2437 RAL_LOCK(sc); 2438 rt2661_stop_locked(sc); 2439 RAL_UNLOCK(sc); 2440} 2441 2442static int 2443rt2661_load_microcode(struct rt2661_softc *sc) 2444{ 2445 const struct firmware *fp; 2446 const char *imagename; 2447 int ntries, error; 2448 2449 RAL_LOCK_ASSERT(sc); 2450 2451 switch (sc->sc_id) { 2452 case 0x0301: imagename = "rt2561sfw"; break; 2453 case 0x0302: imagename = "rt2561fw"; break; 2454 case 0x0401: imagename = "rt2661fw"; break; 2455 default: 2456 device_printf(sc->sc_dev, "%s: unexpected pci device id 0x%x, " 2457 "don't know how to retrieve firmware\n", 2458 __func__, sc->sc_id); 2459 return EINVAL; 2460 } 2461 RAL_UNLOCK(sc); 2462 fp = firmware_get(imagename); 2463 RAL_LOCK(sc); 2464 if (fp == NULL) { 2465 device_printf(sc->sc_dev, 2466 "%s: unable to retrieve firmware image %s\n", 2467 __func__, imagename); 2468 return EINVAL; 2469 } 2470 2471 /* 2472 * Load 8051 microcode into NIC. 2473 */ 2474 /* reset 8051 */ 2475 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2476 2477 /* cancel any pending Host to MCU command */ 2478 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2479 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2480 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2481 2482 /* write 8051's microcode */ 2483 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2484 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2485 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2486 2487 /* kick 8051's ass */ 2488 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2489 2490 /* wait for 8051 to initialize */ 2491 for (ntries = 0; ntries < 500; ntries++) { 2492 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2493 break; 2494 DELAY(100); 2495 } 2496 if (ntries == 500) { 2497 device_printf(sc->sc_dev, 2498 "%s: timeout waiting for MCU to initialize\n", __func__); 2499 error = EIO; 2500 } else 2501 error = 0; 2502 2503 firmware_put(fp, FIRMWARE_UNLOAD); 2504 return error; 2505} 2506 2507#ifdef notyet 2508/* 2509 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2510 * false CCA count. This function is called periodically (every seconds) when 2511 * in the RUN state. Values taken from the reference driver. 2512 */ 2513static void 2514rt2661_rx_tune(struct rt2661_softc *sc) 2515{ 2516 uint8_t bbp17; 2517 uint16_t cca; 2518 int lo, hi, dbm; 2519 2520 /* 2521 * Tuning range depends on operating band and on the presence of an 2522 * external low-noise amplifier. 2523 */ 2524 lo = 0x20; 2525 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2526 lo += 0x08; 2527 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2528 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2529 lo += 0x10; 2530 hi = lo + 0x20; 2531 2532 /* retrieve false CCA count since last call (clear on read) */ 2533 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2534 2535 if (dbm >= -35) { 2536 bbp17 = 0x60; 2537 } else if (dbm >= -58) { 2538 bbp17 = hi; 2539 } else if (dbm >= -66) { 2540 bbp17 = lo + 0x10; 2541 } else if (dbm >= -74) { 2542 bbp17 = lo + 0x08; 2543 } else { 2544 /* RSSI < -74dBm, tune using false CCA count */ 2545 2546 bbp17 = sc->bbp17; /* current value */ 2547 2548 hi -= 2 * (-74 - dbm); 2549 if (hi < lo) 2550 hi = lo; 2551 2552 if (bbp17 > hi) { 2553 bbp17 = hi; 2554 2555 } else if (cca > 512) { 2556 if (++bbp17 > hi) 2557 bbp17 = hi; 2558 } else if (cca < 100) { 2559 if (--bbp17 < lo) 2560 bbp17 = lo; 2561 } 2562 } 2563 2564 if (bbp17 != sc->bbp17) { 2565 rt2661_bbp_write(sc, 17, bbp17); 2566 sc->bbp17 = bbp17; 2567 } 2568} 2569 2570/* 2571 * Enter/Leave radar detection mode. 2572 * This is for 802.11h additional regulatory domains. 2573 */ 2574static void 2575rt2661_radar_start(struct rt2661_softc *sc) 2576{ 2577 uint32_t tmp; 2578 2579 /* disable Rx */ 2580 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2581 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2582 2583 rt2661_bbp_write(sc, 82, 0x20); 2584 rt2661_bbp_write(sc, 83, 0x00); 2585 rt2661_bbp_write(sc, 84, 0x40); 2586 2587 /* save current BBP registers values */ 2588 sc->bbp18 = rt2661_bbp_read(sc, 18); 2589 sc->bbp21 = rt2661_bbp_read(sc, 21); 2590 sc->bbp22 = rt2661_bbp_read(sc, 22); 2591 sc->bbp16 = rt2661_bbp_read(sc, 16); 2592 sc->bbp17 = rt2661_bbp_read(sc, 17); 2593 sc->bbp64 = rt2661_bbp_read(sc, 64); 2594 2595 rt2661_bbp_write(sc, 18, 0xff); 2596 rt2661_bbp_write(sc, 21, 0x3f); 2597 rt2661_bbp_write(sc, 22, 0x3f); 2598 rt2661_bbp_write(sc, 16, 0xbd); 2599 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2600 rt2661_bbp_write(sc, 64, 0x21); 2601 2602 /* restore Rx filter */ 2603 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2604} 2605 2606static int 2607rt2661_radar_stop(struct rt2661_softc *sc) 2608{ 2609 uint8_t bbp66; 2610 2611 /* read radar detection result */ 2612 bbp66 = rt2661_bbp_read(sc, 66); 2613 2614 /* restore BBP registers values */ 2615 rt2661_bbp_write(sc, 16, sc->bbp16); 2616 rt2661_bbp_write(sc, 17, sc->bbp17); 2617 rt2661_bbp_write(sc, 18, sc->bbp18); 2618 rt2661_bbp_write(sc, 21, sc->bbp21); 2619 rt2661_bbp_write(sc, 22, sc->bbp22); 2620 rt2661_bbp_write(sc, 64, sc->bbp64); 2621 2622 return bbp66 == 1; 2623} 2624#endif 2625 2626static int 2627rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2628{ 2629 struct ieee80211com *ic = vap->iv_ic; 2630 struct rt2661_tx_desc desc; 2631 struct mbuf *m0; 2632 int rate; 2633 2634 if ((m0 = ieee80211_beacon_alloc(vap->iv_bss))== NULL) { 2635 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2636 return ENOBUFS; 2637 } 2638 2639 /* send beacons at the lowest available rate */ 2640 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2641 2642 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2643 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2644 2645 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2646 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2647 2648 /* copy beacon header and payload into NIC memory */ 2649 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2650 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2651 2652 m_freem(m0); 2653 2654 return 0; 2655} 2656 2657/* 2658 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2659 * and HostAP operating modes. 2660 */ 2661static void 2662rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2663{ 2664 struct ieee80211com *ic = &sc->sc_ic; 2665 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2666 uint32_t tmp; 2667 2668 if (vap->iv_opmode != IEEE80211_M_STA) { 2669 /* 2670 * Change default 16ms TBTT adjustment to 8ms. 2671 * Must be done before enabling beacon generation. 2672 */ 2673 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2674 } 2675 2676 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2677 2678 /* set beacon interval (in 1/16ms unit) */ 2679 tmp |= vap->iv_bss->ni_intval * 16; 2680 2681 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2682 if (vap->iv_opmode == IEEE80211_M_STA) 2683 tmp |= RT2661_TSF_MODE(1); 2684 else 2685 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2686 2687 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2688} 2689 2690static void 2691rt2661_enable_tsf(struct rt2661_softc *sc) 2692{ 2693 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2694 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2695 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2696} 2697 2698/* 2699 * Retrieve the "Received Signal Strength Indicator" from the raw values 2700 * contained in Rx descriptors. The computation depends on which band the 2701 * frame was received. Correction values taken from the reference driver. 2702 */ 2703static int 2704rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2705{ 2706 int lna, agc, rssi; 2707 2708 lna = (raw >> 5) & 0x3; 2709 agc = raw & 0x1f; 2710 2711 if (lna == 0) { 2712 /* 2713 * No mapping available. 2714 * 2715 * NB: Since RSSI is relative to noise floor, -1 is 2716 * adequate for caller to know error happened. 2717 */ 2718 return -1; 2719 } 2720 2721 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2722 2723 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2724 rssi += sc->rssi_2ghz_corr; 2725 2726 if (lna == 1) 2727 rssi -= 64; 2728 else if (lna == 2) 2729 rssi -= 74; 2730 else if (lna == 3) 2731 rssi -= 90; 2732 } else { 2733 rssi += sc->rssi_5ghz_corr; 2734 2735 if (lna == 1) 2736 rssi -= 64; 2737 else if (lna == 2) 2738 rssi -= 86; 2739 else if (lna == 3) 2740 rssi -= 100; 2741 } 2742 return rssi; 2743} 2744 2745static void 2746rt2661_scan_start(struct ieee80211com *ic) 2747{ 2748 struct rt2661_softc *sc = ic->ic_softc; 2749 uint32_t tmp; 2750 2751 /* abort TSF synchronization */ 2752 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2753 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2754 rt2661_set_bssid(sc, ieee80211broadcastaddr); 2755} 2756 2757static void 2758rt2661_scan_end(struct ieee80211com *ic) 2759{ 2760 struct rt2661_softc *sc = ic->ic_softc; 2761 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2762 2763 rt2661_enable_tsf_sync(sc); 2764 /* XXX keep local copy */ 2765 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2766} 2767 2768static void 2769rt2661_getradiocaps(struct ieee80211com *ic, 2770 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2771{ 2772 struct rt2661_softc *sc = ic->ic_softc; 2773 uint8_t bands[IEEE80211_MODE_BYTES]; 2774 2775 memset(bands, 0, sizeof(bands)); 2776 setbit(bands, IEEE80211_MODE_11B); 2777 setbit(bands, IEEE80211_MODE_11G); 2778 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 2779 rt2661_chan_2ghz, nitems(rt2661_chan_2ghz), bands, 0); 2780 2781 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 2782 setbit(bands, IEEE80211_MODE_11A); 2783 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2784 rt2661_chan_5ghz, nitems(rt2661_chan_5ghz), bands, 0); 2785 } 2786} 2787 2788static void 2789rt2661_set_channel(struct ieee80211com *ic) 2790{ 2791 struct rt2661_softc *sc = ic->ic_softc; 2792 2793 RAL_LOCK(sc); 2794 rt2661_set_chan(sc, ic->ic_curchan); 2795 RAL_UNLOCK(sc); 2796 2797} 2798