1/* $FreeBSD: stable/11/sys/dev/ral/rt2661.c 343976 2019-02-10 21:00:02Z avos $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: stable/11/sys/dev/ral/rt2661.c 343976 2019-02-10 21:00:02Z avos $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_var.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55 56#include <net80211/ieee80211_var.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_ratectl.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2661reg.h> 68#include <dev/ral/rt2661var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(sc, fmt, ...) do { \ 73 if (sc->sc_debug > 0) \ 74 printf(fmt, __VA_ARGS__); \ 75} while (0) 76#define DPRINTFN(sc, n, fmt, ...) do { \ 77 if (sc->sc_debug >= (n)) \ 78 printf(fmt, __VA_ARGS__); \ 79} while (0) 80#else 81#define DPRINTF(sc, fmt, ...) 82#define DPRINTFN(sc, n, fmt, ...) 83#endif 84 85static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 86 const char [IFNAMSIZ], int, enum ieee80211_opmode, 87 int, const uint8_t [IEEE80211_ADDR_LEN], 88 const uint8_t [IEEE80211_ADDR_LEN]); 89static void rt2661_vap_delete(struct ieee80211vap *); 90static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 91 int); 92static int rt2661_alloc_tx_ring(struct rt2661_softc *, 93 struct rt2661_tx_ring *, int); 94static void rt2661_reset_tx_ring(struct rt2661_softc *, 95 struct rt2661_tx_ring *); 96static void rt2661_free_tx_ring(struct rt2661_softc *, 97 struct rt2661_tx_ring *); 98static int rt2661_alloc_rx_ring(struct rt2661_softc *, 99 struct rt2661_rx_ring *, int); 100static void rt2661_reset_rx_ring(struct rt2661_softc *, 101 struct rt2661_rx_ring *); 102static void rt2661_free_rx_ring(struct rt2661_softc *, 103 struct rt2661_rx_ring *); 104static int rt2661_newstate(struct ieee80211vap *, 105 enum ieee80211_state, int); 106static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 107static void rt2661_rx_intr(struct rt2661_softc *); 108static void rt2661_tx_intr(struct rt2661_softc *); 109static void rt2661_tx_dma_intr(struct rt2661_softc *, 110 struct rt2661_tx_ring *); 111static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 112static void rt2661_mcu_wakeup(struct rt2661_softc *); 113static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 114static void rt2661_scan_start(struct ieee80211com *); 115static void rt2661_scan_end(struct ieee80211com *); 116static void rt2661_getradiocaps(struct ieee80211com *, int, int *, 117 struct ieee80211_channel[]); 118static void rt2661_set_channel(struct ieee80211com *); 119static void rt2661_setup_tx_desc(struct rt2661_softc *, 120 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 121 int, const bus_dma_segment_t *, int, int); 122static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 123 struct ieee80211_node *, int); 124static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *); 126static int rt2661_transmit(struct ieee80211com *, struct mbuf *); 127static void rt2661_start(struct rt2661_softc *); 128static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 129 const struct ieee80211_bpf_params *); 130static void rt2661_watchdog(void *); 131static void rt2661_parent(struct ieee80211com *); 132static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 133 uint8_t); 134static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 135static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 136 uint32_t); 137static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 138 uint16_t); 139static void rt2661_select_antenna(struct rt2661_softc *); 140static void rt2661_enable_mrr(struct rt2661_softc *); 141static void rt2661_set_txpreamble(struct rt2661_softc *); 142static void rt2661_set_basicrates(struct rt2661_softc *, 143 const struct ieee80211_rateset *); 144static void rt2661_select_band(struct rt2661_softc *, 145 struct ieee80211_channel *); 146static void rt2661_set_chan(struct rt2661_softc *, 147 struct ieee80211_channel *); 148static void rt2661_set_bssid(struct rt2661_softc *, 149 const uint8_t *); 150static void rt2661_set_macaddr(struct rt2661_softc *, 151 const uint8_t *); 152static void rt2661_update_promisc(struct ieee80211com *); 153static int rt2661_wme_update(struct ieee80211com *) __unused; 154static void rt2661_update_slot(struct ieee80211com *); 155static const char *rt2661_get_rf(int); 156static void rt2661_read_eeprom(struct rt2661_softc *, 157 uint8_t macaddr[IEEE80211_ADDR_LEN]); 158static int rt2661_bbp_init(struct rt2661_softc *); 159static void rt2661_init_locked(struct rt2661_softc *); 160static void rt2661_init(void *); 161static void rt2661_stop_locked(struct rt2661_softc *); 162static void rt2661_stop(void *); 163static int rt2661_load_microcode(struct rt2661_softc *); 164#ifdef notyet 165static void rt2661_rx_tune(struct rt2661_softc *); 166static void rt2661_radar_start(struct rt2661_softc *); 167static int rt2661_radar_stop(struct rt2661_softc *); 168#endif 169static int rt2661_prepare_beacon(struct rt2661_softc *, 170 struct ieee80211vap *); 171static void rt2661_enable_tsf_sync(struct rt2661_softc *); 172static void rt2661_enable_tsf(struct rt2661_softc *); 173static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 174 175static const struct { 176 uint32_t reg; 177 uint32_t val; 178} rt2661_def_mac[] = { 179 RT2661_DEF_MAC 180}; 181 182static const struct { 183 uint8_t reg; 184 uint8_t val; 185} rt2661_def_bbp[] = { 186 RT2661_DEF_BBP 187}; 188 189static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192} rt2661_rf5225_1[] = { 193 RT2661_RF5225_1 194}, rt2661_rf5225_2[] = { 195 RT2661_RF5225_2 196}; 197 198static const uint8_t rt2661_chan_5ghz[] = 199 { 36, 40, 44, 48, 52, 56, 60, 64, 200 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 201 149, 153, 157, 161, 165 }; 202 203int 204rt2661_attach(device_t dev, int id) 205{ 206 struct rt2661_softc *sc = device_get_softc(dev); 207 struct ieee80211com *ic = &sc->sc_ic; 208 uint32_t val; 209 int error, ac, ntries; 210 211 sc->sc_id = id; 212 sc->sc_dev = dev; 213 214 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 215 MTX_DEF | MTX_RECURSE); 216 217 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 218 mbufq_init(&sc->sc_snd, ifqmaxlen); 219 220 /* wait for NIC to initialize */ 221 for (ntries = 0; ntries < 1000; ntries++) { 222 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 223 break; 224 DELAY(1000); 225 } 226 if (ntries == 1000) { 227 device_printf(sc->sc_dev, 228 "timeout waiting for NIC to initialize\n"); 229 error = EIO; 230 goto fail1; 231 } 232 233 /* retrieve RF rev. no and various other things from EEPROM */ 234 rt2661_read_eeprom(sc, ic->ic_macaddr); 235 236 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 237 rt2661_get_rf(sc->rf_rev)); 238 239 /* 240 * Allocate Tx and Rx rings. 241 */ 242 for (ac = 0; ac < 4; ac++) { 243 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 244 RT2661_TX_RING_COUNT); 245 if (error != 0) { 246 device_printf(sc->sc_dev, 247 "could not allocate Tx ring %d\n", ac); 248 goto fail2; 249 } 250 } 251 252 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 253 if (error != 0) { 254 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 255 goto fail2; 256 } 257 258 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 259 if (error != 0) { 260 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 261 goto fail3; 262 } 263 264 ic->ic_softc = sc; 265 ic->ic_name = device_get_nameunit(dev); 266 ic->ic_opmode = IEEE80211_M_STA; 267 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 268 269 /* set device capabilities */ 270 ic->ic_caps = 271 IEEE80211_C_STA /* station mode */ 272 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 273 | IEEE80211_C_HOSTAP /* hostap mode */ 274 | IEEE80211_C_MONITOR /* monitor mode */ 275 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 276 | IEEE80211_C_WDS /* 4-address traffic works */ 277 | IEEE80211_C_MBSS /* mesh point link mode */ 278 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 279 | IEEE80211_C_SHSLOT /* short slot time supported */ 280 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 281 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 282#ifdef notyet 283 | IEEE80211_C_TXFRAG /* handle tx frags */ 284 | IEEE80211_C_WME /* 802.11e */ 285#endif 286 ; 287 288 rt2661_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 289 ic->ic_channels); 290 291 ieee80211_ifattach(ic); 292#if 0 293 ic->ic_wme.wme_update = rt2661_wme_update; 294#endif 295 ic->ic_scan_start = rt2661_scan_start; 296 ic->ic_scan_end = rt2661_scan_end; 297 ic->ic_getradiocaps = rt2661_getradiocaps; 298 ic->ic_set_channel = rt2661_set_channel; 299 ic->ic_updateslot = rt2661_update_slot; 300 ic->ic_update_promisc = rt2661_update_promisc; 301 ic->ic_raw_xmit = rt2661_raw_xmit; 302 ic->ic_transmit = rt2661_transmit; 303 ic->ic_parent = rt2661_parent; 304 ic->ic_vap_create = rt2661_vap_create; 305 ic->ic_vap_delete = rt2661_vap_delete; 306 307 ieee80211_radiotap_attach(ic, 308 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 309 RT2661_TX_RADIOTAP_PRESENT, 310 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 311 RT2661_RX_RADIOTAP_PRESENT); 312 313#ifdef RAL_DEBUG 314 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 315 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 316 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 317#endif 318 if (bootverbose) 319 ieee80211_announce(ic); 320 321 return 0; 322 323fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 324fail2: while (--ac >= 0) 325 rt2661_free_tx_ring(sc, &sc->txq[ac]); 326fail1: mtx_destroy(&sc->sc_mtx); 327 return error; 328} 329 330int 331rt2661_detach(void *xsc) 332{ 333 struct rt2661_softc *sc = xsc; 334 struct ieee80211com *ic = &sc->sc_ic; 335 336 RAL_LOCK(sc); 337 rt2661_stop_locked(sc); 338 RAL_UNLOCK(sc); 339 340 ieee80211_ifdetach(ic); 341 mbufq_drain(&sc->sc_snd); 342 343 rt2661_free_tx_ring(sc, &sc->txq[0]); 344 rt2661_free_tx_ring(sc, &sc->txq[1]); 345 rt2661_free_tx_ring(sc, &sc->txq[2]); 346 rt2661_free_tx_ring(sc, &sc->txq[3]); 347 rt2661_free_tx_ring(sc, &sc->mgtq); 348 rt2661_free_rx_ring(sc, &sc->rxq); 349 350 mtx_destroy(&sc->sc_mtx); 351 352 return 0; 353} 354 355static struct ieee80211vap * 356rt2661_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 357 enum ieee80211_opmode opmode, int flags, 358 const uint8_t bssid[IEEE80211_ADDR_LEN], 359 const uint8_t mac[IEEE80211_ADDR_LEN]) 360{ 361 struct rt2661_softc *sc = ic->ic_softc; 362 struct rt2661_vap *rvp; 363 struct ieee80211vap *vap; 364 365 switch (opmode) { 366 case IEEE80211_M_STA: 367 case IEEE80211_M_IBSS: 368 case IEEE80211_M_AHDEMO: 369 case IEEE80211_M_MONITOR: 370 case IEEE80211_M_HOSTAP: 371 case IEEE80211_M_MBSS: 372 /* XXXRP: TBD */ 373 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 374 device_printf(sc->sc_dev, "only 1 vap supported\n"); 375 return NULL; 376 } 377 if (opmode == IEEE80211_M_STA) 378 flags |= IEEE80211_CLONE_NOBEACONS; 379 break; 380 case IEEE80211_M_WDS: 381 if (TAILQ_EMPTY(&ic->ic_vaps) || 382 ic->ic_opmode != IEEE80211_M_HOSTAP) { 383 device_printf(sc->sc_dev, 384 "wds only supported in ap mode\n"); 385 return NULL; 386 } 387 /* 388 * Silently remove any request for a unique 389 * bssid; WDS vap's always share the local 390 * mac address. 391 */ 392 flags &= ~IEEE80211_CLONE_BSSID; 393 break; 394 default: 395 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 396 return NULL; 397 } 398 rvp = malloc(sizeof(struct rt2661_vap), M_80211_VAP, M_WAITOK | M_ZERO); 399 vap = &rvp->ral_vap; 400 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 401 402 /* override state transition machine */ 403 rvp->ral_newstate = vap->iv_newstate; 404 vap->iv_newstate = rt2661_newstate; 405#if 0 406 vap->iv_update_beacon = rt2661_beacon_update; 407#endif 408 409 ieee80211_ratectl_init(vap); 410 /* complete setup */ 411 ieee80211_vap_attach(vap, ieee80211_media_change, 412 ieee80211_media_status, mac); 413 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 414 ic->ic_opmode = opmode; 415 return vap; 416} 417 418static void 419rt2661_vap_delete(struct ieee80211vap *vap) 420{ 421 struct rt2661_vap *rvp = RT2661_VAP(vap); 422 423 ieee80211_ratectl_deinit(vap); 424 ieee80211_vap_detach(vap); 425 free(rvp, M_80211_VAP); 426} 427 428void 429rt2661_shutdown(void *xsc) 430{ 431 struct rt2661_softc *sc = xsc; 432 433 rt2661_stop(sc); 434} 435 436void 437rt2661_suspend(void *xsc) 438{ 439 struct rt2661_softc *sc = xsc; 440 441 rt2661_stop(sc); 442} 443 444void 445rt2661_resume(void *xsc) 446{ 447 struct rt2661_softc *sc = xsc; 448 449 if (sc->sc_ic.ic_nrunning > 0) 450 rt2661_init(sc); 451} 452 453static void 454rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 455{ 456 if (error != 0) 457 return; 458 459 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 460 461 *(bus_addr_t *)arg = segs[0].ds_addr; 462} 463 464static int 465rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 466 int count) 467{ 468 int i, error; 469 470 ring->count = count; 471 ring->queued = 0; 472 ring->cur = ring->next = ring->stat = 0; 473 474 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 475 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 476 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 477 0, NULL, NULL, &ring->desc_dmat); 478 if (error != 0) { 479 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 480 goto fail; 481 } 482 483 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 484 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 485 if (error != 0) { 486 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 487 goto fail; 488 } 489 490 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 491 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 492 0); 493 if (error != 0) { 494 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 495 goto fail; 496 } 497 498 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 499 M_NOWAIT | M_ZERO); 500 if (ring->data == NULL) { 501 device_printf(sc->sc_dev, "could not allocate soft data\n"); 502 error = ENOMEM; 503 goto fail; 504 } 505 506 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 507 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 508 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 509 if (error != 0) { 510 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 511 goto fail; 512 } 513 514 for (i = 0; i < count; i++) { 515 error = bus_dmamap_create(ring->data_dmat, 0, 516 &ring->data[i].map); 517 if (error != 0) { 518 device_printf(sc->sc_dev, "could not create DMA map\n"); 519 goto fail; 520 } 521 } 522 523 return 0; 524 525fail: rt2661_free_tx_ring(sc, ring); 526 return error; 527} 528 529static void 530rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 531{ 532 struct rt2661_tx_desc *desc; 533 struct rt2661_tx_data *data; 534 int i; 535 536 for (i = 0; i < ring->count; i++) { 537 desc = &ring->desc[i]; 538 data = &ring->data[i]; 539 540 if (data->m != NULL) { 541 bus_dmamap_sync(ring->data_dmat, data->map, 542 BUS_DMASYNC_POSTWRITE); 543 bus_dmamap_unload(ring->data_dmat, data->map); 544 m_freem(data->m); 545 data->m = NULL; 546 } 547 548 if (data->ni != NULL) { 549 ieee80211_free_node(data->ni); 550 data->ni = NULL; 551 } 552 553 desc->flags = 0; 554 } 555 556 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 557 558 ring->queued = 0; 559 ring->cur = ring->next = ring->stat = 0; 560} 561 562static void 563rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 564{ 565 struct rt2661_tx_data *data; 566 int i; 567 568 if (ring->desc != NULL) { 569 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 570 BUS_DMASYNC_POSTWRITE); 571 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 572 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 573 } 574 575 if (ring->desc_dmat != NULL) 576 bus_dma_tag_destroy(ring->desc_dmat); 577 578 if (ring->data != NULL) { 579 for (i = 0; i < ring->count; i++) { 580 data = &ring->data[i]; 581 582 if (data->m != NULL) { 583 bus_dmamap_sync(ring->data_dmat, data->map, 584 BUS_DMASYNC_POSTWRITE); 585 bus_dmamap_unload(ring->data_dmat, data->map); 586 m_freem(data->m); 587 } 588 589 if (data->ni != NULL) 590 ieee80211_free_node(data->ni); 591 592 if (data->map != NULL) 593 bus_dmamap_destroy(ring->data_dmat, data->map); 594 } 595 596 free(ring->data, M_DEVBUF); 597 } 598 599 if (ring->data_dmat != NULL) 600 bus_dma_tag_destroy(ring->data_dmat); 601} 602 603static int 604rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 605 int count) 606{ 607 struct rt2661_rx_desc *desc; 608 struct rt2661_rx_data *data; 609 bus_addr_t physaddr; 610 int i, error; 611 612 ring->count = count; 613 ring->cur = ring->next = 0; 614 615 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 616 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 617 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 618 0, NULL, NULL, &ring->desc_dmat); 619 if (error != 0) { 620 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 621 goto fail; 622 } 623 624 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 625 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 626 if (error != 0) { 627 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 628 goto fail; 629 } 630 631 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 632 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 633 0); 634 if (error != 0) { 635 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 636 goto fail; 637 } 638 639 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 640 M_NOWAIT | M_ZERO); 641 if (ring->data == NULL) { 642 device_printf(sc->sc_dev, "could not allocate soft data\n"); 643 error = ENOMEM; 644 goto fail; 645 } 646 647 /* 648 * Pre-allocate Rx buffers and populate Rx ring. 649 */ 650 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 651 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 652 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 653 if (error != 0) { 654 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 655 goto fail; 656 } 657 658 for (i = 0; i < count; i++) { 659 desc = &sc->rxq.desc[i]; 660 data = &sc->rxq.data[i]; 661 662 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 663 if (error != 0) { 664 device_printf(sc->sc_dev, "could not create DMA map\n"); 665 goto fail; 666 } 667 668 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 669 if (data->m == NULL) { 670 device_printf(sc->sc_dev, 671 "could not allocate rx mbuf\n"); 672 error = ENOMEM; 673 goto fail; 674 } 675 676 error = bus_dmamap_load(ring->data_dmat, data->map, 677 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 678 &physaddr, 0); 679 if (error != 0) { 680 device_printf(sc->sc_dev, 681 "could not load rx buf DMA map"); 682 goto fail; 683 } 684 685 desc->flags = htole32(RT2661_RX_BUSY); 686 desc->physaddr = htole32(physaddr); 687 } 688 689 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 690 691 return 0; 692 693fail: rt2661_free_rx_ring(sc, ring); 694 return error; 695} 696 697static void 698rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 699{ 700 int i; 701 702 for (i = 0; i < ring->count; i++) 703 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 704 705 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 706 707 ring->cur = ring->next = 0; 708} 709 710static void 711rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 712{ 713 struct rt2661_rx_data *data; 714 int i; 715 716 if (ring->desc != NULL) { 717 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 718 BUS_DMASYNC_POSTWRITE); 719 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 720 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 721 } 722 723 if (ring->desc_dmat != NULL) 724 bus_dma_tag_destroy(ring->desc_dmat); 725 726 if (ring->data != NULL) { 727 for (i = 0; i < ring->count; i++) { 728 data = &ring->data[i]; 729 730 if (data->m != NULL) { 731 bus_dmamap_sync(ring->data_dmat, data->map, 732 BUS_DMASYNC_POSTREAD); 733 bus_dmamap_unload(ring->data_dmat, data->map); 734 m_freem(data->m); 735 } 736 737 if (data->map != NULL) 738 bus_dmamap_destroy(ring->data_dmat, data->map); 739 } 740 741 free(ring->data, M_DEVBUF); 742 } 743 744 if (ring->data_dmat != NULL) 745 bus_dma_tag_destroy(ring->data_dmat); 746} 747 748static int 749rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 750{ 751 struct rt2661_vap *rvp = RT2661_VAP(vap); 752 struct ieee80211com *ic = vap->iv_ic; 753 struct rt2661_softc *sc = ic->ic_softc; 754 int error; 755 756 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 757 uint32_t tmp; 758 759 /* abort TSF synchronization */ 760 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 761 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 762 } 763 764 error = rvp->ral_newstate(vap, nstate, arg); 765 766 if (error == 0 && nstate == IEEE80211_S_RUN) { 767 struct ieee80211_node *ni = vap->iv_bss; 768 769 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 770 rt2661_enable_mrr(sc); 771 rt2661_set_txpreamble(sc); 772 rt2661_set_basicrates(sc, &ni->ni_rates); 773 rt2661_set_bssid(sc, ni->ni_bssid); 774 } 775 776 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 777 vap->iv_opmode == IEEE80211_M_IBSS || 778 vap->iv_opmode == IEEE80211_M_MBSS) { 779 error = rt2661_prepare_beacon(sc, vap); 780 if (error != 0) 781 return error; 782 } 783 if (vap->iv_opmode != IEEE80211_M_MONITOR) 784 rt2661_enable_tsf_sync(sc); 785 else 786 rt2661_enable_tsf(sc); 787 } 788 return error; 789} 790 791/* 792 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 793 * 93C66). 794 */ 795static uint16_t 796rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 797{ 798 uint32_t tmp; 799 uint16_t val; 800 int n; 801 802 /* clock C once before the first command */ 803 RT2661_EEPROM_CTL(sc, 0); 804 805 RT2661_EEPROM_CTL(sc, RT2661_S); 806 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 807 RT2661_EEPROM_CTL(sc, RT2661_S); 808 809 /* write start bit (1) */ 810 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 811 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 812 813 /* write READ opcode (10) */ 814 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 815 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 816 RT2661_EEPROM_CTL(sc, RT2661_S); 817 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 818 819 /* write address (A5-A0 or A7-A0) */ 820 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 821 for (; n >= 0; n--) { 822 RT2661_EEPROM_CTL(sc, RT2661_S | 823 (((addr >> n) & 1) << RT2661_SHIFT_D)); 824 RT2661_EEPROM_CTL(sc, RT2661_S | 825 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 826 } 827 828 RT2661_EEPROM_CTL(sc, RT2661_S); 829 830 /* read data Q15-Q0 */ 831 val = 0; 832 for (n = 15; n >= 0; n--) { 833 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 834 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 835 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 836 RT2661_EEPROM_CTL(sc, RT2661_S); 837 } 838 839 RT2661_EEPROM_CTL(sc, 0); 840 841 /* clear Chip Select and clock C */ 842 RT2661_EEPROM_CTL(sc, RT2661_S); 843 RT2661_EEPROM_CTL(sc, 0); 844 RT2661_EEPROM_CTL(sc, RT2661_C); 845 846 return val; 847} 848 849static void 850rt2661_tx_intr(struct rt2661_softc *sc) 851{ 852 struct rt2661_tx_ring *txq; 853 struct rt2661_tx_data *data; 854 uint32_t val; 855 int error, qid, retrycnt; 856 struct ieee80211vap *vap; 857 858 for (;;) { 859 struct ieee80211_node *ni; 860 struct mbuf *m; 861 862 val = RAL_READ(sc, RT2661_STA_CSR4); 863 if (!(val & RT2661_TX_STAT_VALID)) 864 break; 865 866 /* retrieve the queue in which this frame was sent */ 867 qid = RT2661_TX_QID(val); 868 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 869 870 /* retrieve rate control algorithm context */ 871 data = &txq->data[txq->stat]; 872 m = data->m; 873 data->m = NULL; 874 ni = data->ni; 875 data->ni = NULL; 876 877 /* if no frame has been sent, ignore */ 878 if (ni == NULL) 879 continue; 880 else 881 vap = ni->ni_vap; 882 883 switch (RT2661_TX_RESULT(val)) { 884 case RT2661_TX_SUCCESS: 885 retrycnt = RT2661_TX_RETRYCNT(val); 886 887 DPRINTFN(sc, 10, "data frame sent successfully after " 888 "%d retries\n", retrycnt); 889 if (data->rix != IEEE80211_FIXED_RATE_NONE) 890 ieee80211_ratectl_tx_complete(vap, ni, 891 IEEE80211_RATECTL_TX_SUCCESS, 892 &retrycnt, NULL); 893 error = 0; 894 break; 895 896 case RT2661_TX_RETRY_FAIL: 897 retrycnt = RT2661_TX_RETRYCNT(val); 898 899 DPRINTFN(sc, 9, "%s\n", 900 "sending data frame failed (too much retries)"); 901 if (data->rix != IEEE80211_FIXED_RATE_NONE) 902 ieee80211_ratectl_tx_complete(vap, ni, 903 IEEE80211_RATECTL_TX_FAILURE, 904 &retrycnt, NULL); 905 error = 1; 906 break; 907 908 default: 909 /* other failure */ 910 device_printf(sc->sc_dev, 911 "sending data frame failed 0x%08x\n", val); 912 error = 1; 913 } 914 915 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 916 917 txq->queued--; 918 if (++txq->stat >= txq->count) /* faster than % count */ 919 txq->stat = 0; 920 921 ieee80211_tx_complete(ni, m, error); 922 } 923 924 sc->sc_tx_timer = 0; 925 926 rt2661_start(sc); 927} 928 929static void 930rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 931{ 932 struct rt2661_tx_desc *desc; 933 struct rt2661_tx_data *data; 934 935 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 936 937 for (;;) { 938 desc = &txq->desc[txq->next]; 939 data = &txq->data[txq->next]; 940 941 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 942 !(le32toh(desc->flags) & RT2661_TX_VALID)) 943 break; 944 945 bus_dmamap_sync(txq->data_dmat, data->map, 946 BUS_DMASYNC_POSTWRITE); 947 bus_dmamap_unload(txq->data_dmat, data->map); 948 949 /* descriptor is no longer valid */ 950 desc->flags &= ~htole32(RT2661_TX_VALID); 951 952 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 953 954 if (++txq->next >= txq->count) /* faster than % count */ 955 txq->next = 0; 956 } 957 958 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 959} 960 961static void 962rt2661_rx_intr(struct rt2661_softc *sc) 963{ 964 struct ieee80211com *ic = &sc->sc_ic; 965 struct rt2661_rx_desc *desc; 966 struct rt2661_rx_data *data; 967 bus_addr_t physaddr; 968 struct ieee80211_frame *wh; 969 struct ieee80211_node *ni; 970 struct mbuf *mnew, *m; 971 int error; 972 973 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 974 BUS_DMASYNC_POSTREAD); 975 976 for (;;) { 977 int8_t rssi, nf; 978 979 desc = &sc->rxq.desc[sc->rxq.cur]; 980 data = &sc->rxq.data[sc->rxq.cur]; 981 982 if (le32toh(desc->flags) & RT2661_RX_BUSY) 983 break; 984 985 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 986 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 987 /* 988 * This should not happen since we did not request 989 * to receive those frames when we filled TXRX_CSR0. 990 */ 991 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 992 le32toh(desc->flags)); 993 counter_u64_add(ic->ic_ierrors, 1); 994 goto skip; 995 } 996 997 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 998 counter_u64_add(ic->ic_ierrors, 1); 999 goto skip; 1000 } 1001 1002 /* 1003 * Try to allocate a new mbuf for this ring element and load it 1004 * before processing the current mbuf. If the ring element 1005 * cannot be loaded, drop the received packet and reuse the old 1006 * mbuf. In the unlikely case that the old mbuf can't be 1007 * reloaded either, explicitly panic. 1008 */ 1009 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1010 if (mnew == NULL) { 1011 counter_u64_add(ic->ic_ierrors, 1); 1012 goto skip; 1013 } 1014 1015 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1016 BUS_DMASYNC_POSTREAD); 1017 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1018 1019 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1020 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1021 &physaddr, 0); 1022 if (error != 0) { 1023 m_freem(mnew); 1024 1025 /* try to reload the old mbuf */ 1026 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1027 mtod(data->m, void *), MCLBYTES, 1028 rt2661_dma_map_addr, &physaddr, 0); 1029 if (error != 0) { 1030 /* very unlikely that it will fail... */ 1031 panic("%s: could not load old rx mbuf", 1032 device_get_name(sc->sc_dev)); 1033 } 1034 counter_u64_add(ic->ic_ierrors, 1); 1035 goto skip; 1036 } 1037 1038 /* 1039 * New mbuf successfully loaded, update Rx ring and continue 1040 * processing. 1041 */ 1042 m = data->m; 1043 data->m = mnew; 1044 desc->physaddr = htole32(physaddr); 1045 1046 /* finalize mbuf */ 1047 m->m_pkthdr.len = m->m_len = 1048 (le32toh(desc->flags) >> 16) & 0xfff; 1049 1050 rssi = rt2661_get_rssi(sc, desc->rssi); 1051 /* Error happened during RSSI conversion. */ 1052 if (rssi < 0) 1053 rssi = -30; /* XXX ignored by net80211 */ 1054 nf = RT2661_NOISE_FLOOR; 1055 1056 if (ieee80211_radiotap_active(ic)) { 1057 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1058 uint32_t tsf_lo, tsf_hi; 1059 1060 /* get timestamp (low and high 32 bits) */ 1061 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1062 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1063 1064 tap->wr_tsf = 1065 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1066 tap->wr_flags = 0; 1067 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1068 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1069 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1070 tap->wr_antsignal = nf + rssi; 1071 tap->wr_antnoise = nf; 1072 } 1073 sc->sc_flags |= RAL_INPUT_RUNNING; 1074 RAL_UNLOCK(sc); 1075 wh = mtod(m, struct ieee80211_frame *); 1076 1077 /* send the frame to the 802.11 layer */ 1078 ni = ieee80211_find_rxnode(ic, 1079 (struct ieee80211_frame_min *)wh); 1080 if (ni != NULL) { 1081 (void) ieee80211_input(ni, m, rssi, nf); 1082 ieee80211_free_node(ni); 1083 } else 1084 (void) ieee80211_input_all(ic, m, rssi, nf); 1085 1086 RAL_LOCK(sc); 1087 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1088 1089skip: desc->flags |= htole32(RT2661_RX_BUSY); 1090 1091 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1092 1093 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1094 } 1095 1096 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1097 BUS_DMASYNC_PREWRITE); 1098} 1099 1100/* ARGSUSED */ 1101static void 1102rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1103{ 1104 /* do nothing */ 1105} 1106 1107static void 1108rt2661_mcu_wakeup(struct rt2661_softc *sc) 1109{ 1110 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1111 1112 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1113 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1114 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1115 1116 /* send wakeup command to MCU */ 1117 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1118} 1119 1120static void 1121rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1122{ 1123 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1124 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1125} 1126 1127void 1128rt2661_intr(void *arg) 1129{ 1130 struct rt2661_softc *sc = arg; 1131 uint32_t r1, r2; 1132 1133 RAL_LOCK(sc); 1134 1135 /* disable MAC and MCU interrupts */ 1136 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1137 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1138 1139 /* don't re-enable interrupts if we're shutting down */ 1140 if (!(sc->sc_flags & RAL_RUNNING)) { 1141 RAL_UNLOCK(sc); 1142 return; 1143 } 1144 1145 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1146 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1147 1148 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1149 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1150 1151 if (r1 & RT2661_MGT_DONE) 1152 rt2661_tx_dma_intr(sc, &sc->mgtq); 1153 1154 if (r1 & RT2661_RX_DONE) 1155 rt2661_rx_intr(sc); 1156 1157 if (r1 & RT2661_TX0_DMA_DONE) 1158 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1159 1160 if (r1 & RT2661_TX1_DMA_DONE) 1161 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1162 1163 if (r1 & RT2661_TX2_DMA_DONE) 1164 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1165 1166 if (r1 & RT2661_TX3_DMA_DONE) 1167 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1168 1169 if (r1 & RT2661_TX_DONE) 1170 rt2661_tx_intr(sc); 1171 1172 if (r2 & RT2661_MCU_CMD_DONE) 1173 rt2661_mcu_cmd_intr(sc); 1174 1175 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1176 rt2661_mcu_beacon_expire(sc); 1177 1178 if (r2 & RT2661_MCU_WAKEUP) 1179 rt2661_mcu_wakeup(sc); 1180 1181 /* re-enable MAC and MCU interrupts */ 1182 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1183 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1184 1185 RAL_UNLOCK(sc); 1186} 1187 1188static uint8_t 1189rt2661_plcp_signal(int rate) 1190{ 1191 switch (rate) { 1192 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1193 case 12: return 0xb; 1194 case 18: return 0xf; 1195 case 24: return 0xa; 1196 case 36: return 0xe; 1197 case 48: return 0x9; 1198 case 72: return 0xd; 1199 case 96: return 0x8; 1200 case 108: return 0xc; 1201 1202 /* CCK rates (NB: not IEEE std, device-specific) */ 1203 case 2: return 0x0; 1204 case 4: return 0x1; 1205 case 11: return 0x2; 1206 case 22: return 0x3; 1207 } 1208 return 0xff; /* XXX unsupported/unknown rate */ 1209} 1210 1211static void 1212rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1213 uint32_t flags, uint16_t xflags, int len, int rate, 1214 const bus_dma_segment_t *segs, int nsegs, int ac) 1215{ 1216 struct ieee80211com *ic = &sc->sc_ic; 1217 uint16_t plcp_length; 1218 int i, remainder; 1219 1220 desc->flags = htole32(flags); 1221 desc->flags |= htole32(len << 16); 1222 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1223 1224 desc->xflags = htole16(xflags); 1225 desc->xflags |= htole16(nsegs << 13); 1226 1227 desc->wme = htole16( 1228 RT2661_QID(ac) | 1229 RT2661_AIFSN(2) | 1230 RT2661_LOGCWMIN(4) | 1231 RT2661_LOGCWMAX(10)); 1232 1233 /* 1234 * Remember in which queue this frame was sent. This field is driver 1235 * private data only. It will be made available by the NIC in STA_CSR4 1236 * on Tx interrupts. 1237 */ 1238 desc->qid = ac; 1239 1240 /* setup PLCP fields */ 1241 desc->plcp_signal = rt2661_plcp_signal(rate); 1242 desc->plcp_service = 4; 1243 1244 len += IEEE80211_CRC_LEN; 1245 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1246 desc->flags |= htole32(RT2661_TX_OFDM); 1247 1248 plcp_length = len & 0xfff; 1249 desc->plcp_length_hi = plcp_length >> 6; 1250 desc->plcp_length_lo = plcp_length & 0x3f; 1251 } else { 1252 plcp_length = howmany(16 * len, rate); 1253 if (rate == 22) { 1254 remainder = (16 * len) % 22; 1255 if (remainder != 0 && remainder < 7) 1256 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1257 } 1258 desc->plcp_length_hi = plcp_length >> 8; 1259 desc->plcp_length_lo = plcp_length & 0xff; 1260 1261 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1262 desc->plcp_signal |= 0x08; 1263 } 1264 1265 /* RT2x61 supports scatter with up to 5 segments */ 1266 for (i = 0; i < nsegs; i++) { 1267 desc->addr[i] = htole32(segs[i].ds_addr); 1268 desc->len [i] = htole16(segs[i].ds_len); 1269 } 1270} 1271 1272static int 1273rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1274 struct ieee80211_node *ni) 1275{ 1276 struct ieee80211vap *vap = ni->ni_vap; 1277 struct ieee80211com *ic = ni->ni_ic; 1278 struct rt2661_tx_desc *desc; 1279 struct rt2661_tx_data *data; 1280 struct ieee80211_frame *wh; 1281 struct ieee80211_key *k; 1282 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1283 uint16_t dur; 1284 uint32_t flags = 0; /* XXX HWSEQ */ 1285 int nsegs, rate, error; 1286 1287 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1288 data = &sc->mgtq.data[sc->mgtq.cur]; 1289 1290 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1291 1292 wh = mtod(m0, struct ieee80211_frame *); 1293 1294 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1295 k = ieee80211_crypto_encap(ni, m0); 1296 if (k == NULL) { 1297 m_freem(m0); 1298 return ENOBUFS; 1299 } 1300 } 1301 1302 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1303 segs, &nsegs, 0); 1304 if (error != 0) { 1305 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1306 error); 1307 m_freem(m0); 1308 return error; 1309 } 1310 1311 if (ieee80211_radiotap_active_vap(vap)) { 1312 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1313 1314 tap->wt_flags = 0; 1315 tap->wt_rate = rate; 1316 1317 ieee80211_radiotap_tx(vap, m0); 1318 } 1319 1320 data->m = m0; 1321 data->ni = ni; 1322 /* management frames are not taken into account for amrr */ 1323 data->rix = IEEE80211_FIXED_RATE_NONE; 1324 1325 wh = mtod(m0, struct ieee80211_frame *); 1326 1327 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1328 flags |= RT2661_TX_NEED_ACK; 1329 1330 dur = ieee80211_ack_duration(ic->ic_rt, 1331 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1332 *(uint16_t *)wh->i_dur = htole16(dur); 1333 1334 /* tell hardware to add timestamp in probe responses */ 1335 if ((wh->i_fc[0] & 1336 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1337 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1338 flags |= RT2661_TX_TIMESTAMP; 1339 } 1340 1341 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1342 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1343 1344 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1345 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1346 BUS_DMASYNC_PREWRITE); 1347 1348 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1349 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1350 1351 /* kick mgt */ 1352 sc->mgtq.queued++; 1353 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1354 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1355 1356 return 0; 1357} 1358 1359static int 1360rt2661_sendprot(struct rt2661_softc *sc, int ac, 1361 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1362{ 1363 struct ieee80211com *ic = ni->ni_ic; 1364 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1365 const struct ieee80211_frame *wh; 1366 struct rt2661_tx_desc *desc; 1367 struct rt2661_tx_data *data; 1368 struct mbuf *mprot; 1369 int protrate, ackrate, pktlen, flags, isshort, error; 1370 uint16_t dur; 1371 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1372 int nsegs; 1373 1374 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1375 ("protection %d", prot)); 1376 1377 wh = mtod(m, const struct ieee80211_frame *); 1378 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1379 1380 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1381 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1382 1383 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1384 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1385 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1386 flags = RT2661_TX_MORE_FRAG; 1387 if (prot == IEEE80211_PROT_RTSCTS) { 1388 /* NB: CTS is the same size as an ACK */ 1389 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1390 flags |= RT2661_TX_NEED_ACK; 1391 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1392 } else { 1393 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1394 } 1395 if (mprot == NULL) { 1396 /* XXX stat + msg */ 1397 return ENOBUFS; 1398 } 1399 1400 data = &txq->data[txq->cur]; 1401 desc = &txq->desc[txq->cur]; 1402 1403 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1404 &nsegs, 0); 1405 if (error != 0) { 1406 device_printf(sc->sc_dev, 1407 "could not map mbuf (error %d)\n", error); 1408 m_freem(mprot); 1409 return error; 1410 } 1411 1412 data->m = mprot; 1413 data->ni = ieee80211_ref_node(ni); 1414 /* ctl frames are not taken into account for amrr */ 1415 data->rix = IEEE80211_FIXED_RATE_NONE; 1416 1417 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1418 protrate, segs, 1, ac); 1419 1420 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1421 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1422 1423 txq->queued++; 1424 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1425 1426 return 0; 1427} 1428 1429static int 1430rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1431 struct ieee80211_node *ni, int ac) 1432{ 1433 struct ieee80211vap *vap = ni->ni_vap; 1434 struct ieee80211com *ic = &sc->sc_ic; 1435 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1436 struct rt2661_tx_desc *desc; 1437 struct rt2661_tx_data *data; 1438 struct ieee80211_frame *wh; 1439 const struct ieee80211_txparam *tp; 1440 struct ieee80211_key *k; 1441 const struct chanAccParams *cap; 1442 struct mbuf *mnew; 1443 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1444 uint16_t dur; 1445 uint32_t flags; 1446 int error, nsegs, rate, noack = 0; 1447 1448 wh = mtod(m0, struct ieee80211_frame *); 1449 1450 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1451 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1452 rate = tp->mcastrate; 1453 } else if (m0->m_flags & M_EAPOL) { 1454 rate = tp->mgmtrate; 1455 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1456 rate = tp->ucastrate; 1457 } else { 1458 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1459 rate = ni->ni_txrate; 1460 } 1461 rate &= IEEE80211_RATE_VAL; 1462 1463 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1464 cap = &ic->ic_wme.wme_chanParams; 1465 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1466 } 1467 1468 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1469 k = ieee80211_crypto_encap(ni, m0); 1470 if (k == NULL) { 1471 m_freem(m0); 1472 return ENOBUFS; 1473 } 1474 1475 /* packet header may have moved, reset our local pointer */ 1476 wh = mtod(m0, struct ieee80211_frame *); 1477 } 1478 1479 flags = 0; 1480 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1481 int prot = IEEE80211_PROT_NONE; 1482 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1483 prot = IEEE80211_PROT_RTSCTS; 1484 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1485 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1486 prot = ic->ic_protmode; 1487 if (prot != IEEE80211_PROT_NONE) { 1488 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1489 if (error) { 1490 m_freem(m0); 1491 return error; 1492 } 1493 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1494 } 1495 } 1496 1497 data = &txq->data[txq->cur]; 1498 desc = &txq->desc[txq->cur]; 1499 1500 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1501 &nsegs, 0); 1502 if (error != 0 && error != EFBIG) { 1503 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1504 error); 1505 m_freem(m0); 1506 return error; 1507 } 1508 if (error != 0) { 1509 mnew = m_defrag(m0, M_NOWAIT); 1510 if (mnew == NULL) { 1511 device_printf(sc->sc_dev, 1512 "could not defragment mbuf\n"); 1513 m_freem(m0); 1514 return ENOBUFS; 1515 } 1516 m0 = mnew; 1517 1518 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1519 segs, &nsegs, 0); 1520 if (error != 0) { 1521 device_printf(sc->sc_dev, 1522 "could not map mbuf (error %d)\n", error); 1523 m_freem(m0); 1524 return error; 1525 } 1526 1527 /* packet header have moved, reset our local pointer */ 1528 wh = mtod(m0, struct ieee80211_frame *); 1529 } 1530 1531 if (ieee80211_radiotap_active_vap(vap)) { 1532 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1533 1534 tap->wt_flags = 0; 1535 tap->wt_rate = rate; 1536 1537 ieee80211_radiotap_tx(vap, m0); 1538 } 1539 1540 data->m = m0; 1541 data->ni = ni; 1542 1543 /* remember link conditions for rate adaptation algorithm */ 1544 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1545 data->rix = ni->ni_txrate; 1546 /* XXX probably need last rssi value and not avg */ 1547 data->rssi = ic->ic_node_getrssi(ni); 1548 } else 1549 data->rix = IEEE80211_FIXED_RATE_NONE; 1550 1551 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1552 flags |= RT2661_TX_NEED_ACK; 1553 1554 dur = ieee80211_ack_duration(ic->ic_rt, 1555 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1556 *(uint16_t *)wh->i_dur = htole16(dur); 1557 } 1558 1559 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1560 nsegs, ac); 1561 1562 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1563 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1564 1565 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1566 m0->m_pkthdr.len, txq->cur, rate); 1567 1568 /* kick Tx */ 1569 txq->queued++; 1570 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1571 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1572 1573 return 0; 1574} 1575 1576static int 1577rt2661_transmit(struct ieee80211com *ic, struct mbuf *m) 1578{ 1579 struct rt2661_softc *sc = ic->ic_softc; 1580 int error; 1581 1582 RAL_LOCK(sc); 1583 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1584 RAL_UNLOCK(sc); 1585 return (ENXIO); 1586 } 1587 error = mbufq_enqueue(&sc->sc_snd, m); 1588 if (error) { 1589 RAL_UNLOCK(sc); 1590 return (error); 1591 } 1592 rt2661_start(sc); 1593 RAL_UNLOCK(sc); 1594 1595 return (0); 1596} 1597 1598static void 1599rt2661_start(struct rt2661_softc *sc) 1600{ 1601 struct mbuf *m; 1602 struct ieee80211_node *ni; 1603 int ac; 1604 1605 RAL_LOCK_ASSERT(sc); 1606 1607 /* prevent management frames from being sent if we're not ready */ 1608 if (!(sc->sc_flags & RAL_RUNNING) || sc->sc_invalid) 1609 return; 1610 1611 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1612 ac = M_WME_GETAC(m); 1613 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1614 /* there is no place left in this ring */ 1615 mbufq_prepend(&sc->sc_snd, m); 1616 break; 1617 } 1618 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1619 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1620 if_inc_counter(ni->ni_vap->iv_ifp, 1621 IFCOUNTER_OERRORS, 1); 1622 ieee80211_free_node(ni); 1623 break; 1624 } 1625 sc->sc_tx_timer = 5; 1626 } 1627} 1628 1629static int 1630rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1631 const struct ieee80211_bpf_params *params) 1632{ 1633 struct ieee80211com *ic = ni->ni_ic; 1634 struct rt2661_softc *sc = ic->ic_softc; 1635 1636 RAL_LOCK(sc); 1637 1638 /* prevent management frames from being sent if we're not ready */ 1639 if (!(sc->sc_flags & RAL_RUNNING)) { 1640 RAL_UNLOCK(sc); 1641 m_freem(m); 1642 return ENETDOWN; 1643 } 1644 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1645 RAL_UNLOCK(sc); 1646 m_freem(m); 1647 return ENOBUFS; /* XXX */ 1648 } 1649 1650 /* 1651 * Legacy path; interpret frame contents to decide 1652 * precisely how to send the frame. 1653 * XXX raw path 1654 */ 1655 if (rt2661_tx_mgt(sc, m, ni) != 0) 1656 goto bad; 1657 sc->sc_tx_timer = 5; 1658 1659 RAL_UNLOCK(sc); 1660 1661 return 0; 1662bad: 1663 RAL_UNLOCK(sc); 1664 return EIO; /* XXX */ 1665} 1666 1667static void 1668rt2661_watchdog(void *arg) 1669{ 1670 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1671 1672 RAL_LOCK_ASSERT(sc); 1673 1674 KASSERT(sc->sc_flags & RAL_RUNNING, ("not running")); 1675 1676 if (sc->sc_invalid) /* card ejected */ 1677 return; 1678 1679 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1680 device_printf(sc->sc_dev, "device timeout\n"); 1681 rt2661_init_locked(sc); 1682 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1683 /* NB: callout is reset in rt2661_init() */ 1684 return; 1685 } 1686 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1687} 1688 1689static void 1690rt2661_parent(struct ieee80211com *ic) 1691{ 1692 struct rt2661_softc *sc = ic->ic_softc; 1693 int startall = 0; 1694 1695 RAL_LOCK(sc); 1696 if (ic->ic_nrunning > 0) { 1697 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1698 rt2661_init_locked(sc); 1699 startall = 1; 1700 } else 1701 rt2661_update_promisc(ic); 1702 } else if (sc->sc_flags & RAL_RUNNING) 1703 rt2661_stop_locked(sc); 1704 RAL_UNLOCK(sc); 1705 if (startall) 1706 ieee80211_start_all(ic); 1707} 1708 1709static void 1710rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1711{ 1712 uint32_t tmp; 1713 int ntries; 1714 1715 for (ntries = 0; ntries < 100; ntries++) { 1716 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1717 break; 1718 DELAY(1); 1719 } 1720 if (ntries == 100) { 1721 device_printf(sc->sc_dev, "could not write to BBP\n"); 1722 return; 1723 } 1724 1725 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1726 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1727 1728 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1729} 1730 1731static uint8_t 1732rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1733{ 1734 uint32_t val; 1735 int ntries; 1736 1737 for (ntries = 0; ntries < 100; ntries++) { 1738 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1739 break; 1740 DELAY(1); 1741 } 1742 if (ntries == 100) { 1743 device_printf(sc->sc_dev, "could not read from BBP\n"); 1744 return 0; 1745 } 1746 1747 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1748 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1749 1750 for (ntries = 0; ntries < 100; ntries++) { 1751 val = RAL_READ(sc, RT2661_PHY_CSR3); 1752 if (!(val & RT2661_BBP_BUSY)) 1753 return val & 0xff; 1754 DELAY(1); 1755 } 1756 1757 device_printf(sc->sc_dev, "could not read from BBP\n"); 1758 return 0; 1759} 1760 1761static void 1762rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1763{ 1764 uint32_t tmp; 1765 int ntries; 1766 1767 for (ntries = 0; ntries < 100; ntries++) { 1768 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1769 break; 1770 DELAY(1); 1771 } 1772 if (ntries == 100) { 1773 device_printf(sc->sc_dev, "could not write to RF\n"); 1774 return; 1775 } 1776 1777 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1778 (reg & 3); 1779 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1780 1781 /* remember last written value in sc */ 1782 sc->rf_regs[reg] = val; 1783 1784 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1785} 1786 1787static int 1788rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1789{ 1790 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1791 return EIO; /* there is already a command pending */ 1792 1793 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1794 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1795 1796 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1797 1798 return 0; 1799} 1800 1801static void 1802rt2661_select_antenna(struct rt2661_softc *sc) 1803{ 1804 uint8_t bbp4, bbp77; 1805 uint32_t tmp; 1806 1807 bbp4 = rt2661_bbp_read(sc, 4); 1808 bbp77 = rt2661_bbp_read(sc, 77); 1809 1810 /* TBD */ 1811 1812 /* make sure Rx is disabled before switching antenna */ 1813 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1814 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1815 1816 rt2661_bbp_write(sc, 4, bbp4); 1817 rt2661_bbp_write(sc, 77, bbp77); 1818 1819 /* restore Rx filter */ 1820 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1821} 1822 1823/* 1824 * Enable multi-rate retries for frames sent at OFDM rates. 1825 * In 802.11b/g mode, allow fallback to CCK rates. 1826 */ 1827static void 1828rt2661_enable_mrr(struct rt2661_softc *sc) 1829{ 1830 struct ieee80211com *ic = &sc->sc_ic; 1831 uint32_t tmp; 1832 1833 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1834 1835 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1836 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1837 tmp |= RT2661_MRR_CCK_FALLBACK; 1838 tmp |= RT2661_MRR_ENABLED; 1839 1840 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1841} 1842 1843static void 1844rt2661_set_txpreamble(struct rt2661_softc *sc) 1845{ 1846 struct ieee80211com *ic = &sc->sc_ic; 1847 uint32_t tmp; 1848 1849 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1850 1851 tmp &= ~RT2661_SHORT_PREAMBLE; 1852 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1853 tmp |= RT2661_SHORT_PREAMBLE; 1854 1855 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1856} 1857 1858static void 1859rt2661_set_basicrates(struct rt2661_softc *sc, 1860 const struct ieee80211_rateset *rs) 1861{ 1862 struct ieee80211com *ic = &sc->sc_ic; 1863 uint32_t mask = 0; 1864 uint8_t rate; 1865 int i; 1866 1867 for (i = 0; i < rs->rs_nrates; i++) { 1868 rate = rs->rs_rates[i]; 1869 1870 if (!(rate & IEEE80211_RATE_BASIC)) 1871 continue; 1872 1873 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 1874 IEEE80211_RV(rate)); 1875 } 1876 1877 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1878 1879 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1880} 1881 1882/* 1883 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1884 * driver. 1885 */ 1886static void 1887rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1888{ 1889 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1890 uint32_t tmp; 1891 1892 /* update all BBP registers that depend on the band */ 1893 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1894 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1895 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1896 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1897 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1898 } 1899 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1900 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1901 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1902 } 1903 1904 rt2661_bbp_write(sc, 17, bbp17); 1905 rt2661_bbp_write(sc, 96, bbp96); 1906 rt2661_bbp_write(sc, 104, bbp104); 1907 1908 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1909 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1910 rt2661_bbp_write(sc, 75, 0x80); 1911 rt2661_bbp_write(sc, 86, 0x80); 1912 rt2661_bbp_write(sc, 88, 0x80); 1913 } 1914 1915 rt2661_bbp_write(sc, 35, bbp35); 1916 rt2661_bbp_write(sc, 97, bbp97); 1917 rt2661_bbp_write(sc, 98, bbp98); 1918 1919 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1920 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1921 if (IEEE80211_IS_CHAN_2GHZ(c)) 1922 tmp |= RT2661_PA_PE_2GHZ; 1923 else 1924 tmp |= RT2661_PA_PE_5GHZ; 1925 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1926} 1927 1928static void 1929rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1930{ 1931 struct ieee80211com *ic = &sc->sc_ic; 1932 const struct rfprog *rfprog; 1933 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 1934 int8_t power; 1935 u_int i, chan; 1936 1937 chan = ieee80211_chan2ieee(ic, c); 1938 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 1939 1940 /* select the appropriate RF settings based on what EEPROM says */ 1941 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 1942 1943 /* find the settings for this channel (we know it exists) */ 1944 for (i = 0; rfprog[i].chan != chan; i++); 1945 1946 power = sc->txpow[i]; 1947 if (power < 0) { 1948 bbp94 += power; 1949 power = 0; 1950 } else if (power > 31) { 1951 bbp94 += power - 31; 1952 power = 31; 1953 } 1954 1955 /* 1956 * If we are switching from the 2GHz band to the 5GHz band or 1957 * vice-versa, BBP registers need to be reprogrammed. 1958 */ 1959 if (c->ic_flags != sc->sc_curchan->ic_flags) { 1960 rt2661_select_band(sc, c); 1961 rt2661_select_antenna(sc); 1962 } 1963 sc->sc_curchan = c; 1964 1965 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1966 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1967 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 1968 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1969 1970 DELAY(200); 1971 1972 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1973 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1974 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 1975 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1976 1977 DELAY(200); 1978 1979 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1980 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1981 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 1982 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1983 1984 /* enable smart mode for MIMO-capable RFs */ 1985 bbp3 = rt2661_bbp_read(sc, 3); 1986 1987 bbp3 &= ~RT2661_SMART_MODE; 1988 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 1989 bbp3 |= RT2661_SMART_MODE; 1990 1991 rt2661_bbp_write(sc, 3, bbp3); 1992 1993 if (bbp94 != RT2661_BBPR94_DEFAULT) 1994 rt2661_bbp_write(sc, 94, bbp94); 1995 1996 /* 5GHz radio needs a 1ms delay here */ 1997 if (IEEE80211_IS_CHAN_5GHZ(c)) 1998 DELAY(1000); 1999} 2000 2001static void 2002rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2003{ 2004 uint32_t tmp; 2005 2006 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2007 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2008 2009 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2010 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2011} 2012 2013static void 2014rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2015{ 2016 uint32_t tmp; 2017 2018 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2019 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2020 2021 tmp = addr[4] | addr[5] << 8; 2022 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2023} 2024 2025static void 2026rt2661_update_promisc(struct ieee80211com *ic) 2027{ 2028 struct rt2661_softc *sc = ic->ic_softc; 2029 uint32_t tmp; 2030 2031 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2032 2033 tmp &= ~RT2661_DROP_NOT_TO_ME; 2034 if (ic->ic_promisc == 0) 2035 tmp |= RT2661_DROP_NOT_TO_ME; 2036 2037 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2038 2039 DPRINTF(sc, "%s promiscuous mode\n", 2040 (ic->ic_promisc > 0) ? "entering" : "leaving"); 2041} 2042 2043/* 2044 * Update QoS (802.11e) settings for each h/w Tx ring. 2045 */ 2046static int 2047rt2661_wme_update(struct ieee80211com *ic) 2048{ 2049 struct rt2661_softc *sc = ic->ic_softc; 2050 const struct wmeParams *wmep; 2051 2052 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2053 2054 /* XXX: not sure about shifts. */ 2055 /* XXX: the reference driver plays with AC_VI settings too. */ 2056 2057 /* update TxOp */ 2058 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2059 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2060 wmep[WME_AC_BK].wmep_txopLimit); 2061 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2062 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2063 wmep[WME_AC_VO].wmep_txopLimit); 2064 2065 /* update CWmin */ 2066 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2067 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2068 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2069 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2070 wmep[WME_AC_VO].wmep_logcwmin); 2071 2072 /* update CWmax */ 2073 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2074 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2075 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2076 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2077 wmep[WME_AC_VO].wmep_logcwmax); 2078 2079 /* update Aifsn */ 2080 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2081 wmep[WME_AC_BE].wmep_aifsn << 12 | 2082 wmep[WME_AC_BK].wmep_aifsn << 8 | 2083 wmep[WME_AC_VI].wmep_aifsn << 4 | 2084 wmep[WME_AC_VO].wmep_aifsn); 2085 2086 return 0; 2087} 2088 2089static void 2090rt2661_update_slot(struct ieee80211com *ic) 2091{ 2092 struct rt2661_softc *sc = ic->ic_softc; 2093 uint8_t slottime; 2094 uint32_t tmp; 2095 2096 slottime = IEEE80211_GET_SLOTTIME(ic); 2097 2098 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2099 tmp = (tmp & ~0xff) | slottime; 2100 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2101} 2102 2103static const char * 2104rt2661_get_rf(int rev) 2105{ 2106 switch (rev) { 2107 case RT2661_RF_5225: return "RT5225"; 2108 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2109 case RT2661_RF_2527: return "RT2527"; 2110 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2111 default: return "unknown"; 2112 } 2113} 2114 2115static void 2116rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2117{ 2118 uint16_t val; 2119 int i; 2120 2121 /* read MAC address */ 2122 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2123 macaddr[0] = val & 0xff; 2124 macaddr[1] = val >> 8; 2125 2126 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2127 macaddr[2] = val & 0xff; 2128 macaddr[3] = val >> 8; 2129 2130 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2131 macaddr[4] = val & 0xff; 2132 macaddr[5] = val >> 8; 2133 2134 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2135 /* XXX: test if different from 0xffff? */ 2136 sc->rf_rev = (val >> 11) & 0x1f; 2137 sc->hw_radio = (val >> 10) & 0x1; 2138 sc->rx_ant = (val >> 4) & 0x3; 2139 sc->tx_ant = (val >> 2) & 0x3; 2140 sc->nb_ant = val & 0x3; 2141 2142 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2143 2144 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2145 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2146 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2147 2148 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2149 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2150 2151 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2152 if ((val & 0xff) != 0xff) 2153 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2154 2155 /* Only [-10, 10] is valid */ 2156 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2157 sc->rssi_2ghz_corr = 0; 2158 2159 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2160 if ((val & 0xff) != 0xff) 2161 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2162 2163 /* Only [-10, 10] is valid */ 2164 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2165 sc->rssi_5ghz_corr = 0; 2166 2167 /* adjust RSSI correction for external low-noise amplifier */ 2168 if (sc->ext_2ghz_lna) 2169 sc->rssi_2ghz_corr -= 14; 2170 if (sc->ext_5ghz_lna) 2171 sc->rssi_5ghz_corr -= 14; 2172 2173 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2174 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2175 2176 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2177 if ((val >> 8) != 0xff) 2178 sc->rfprog = (val >> 8) & 0x3; 2179 if ((val & 0xff) != 0xff) 2180 sc->rffreq = val & 0xff; 2181 2182 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2183 2184 /* read Tx power for all a/b/g channels */ 2185 for (i = 0; i < 19; i++) { 2186 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2187 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2188 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2189 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2190 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2191 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2192 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2193 } 2194 2195 /* read vendor-specific BBP values */ 2196 for (i = 0; i < 16; i++) { 2197 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2198 if (val == 0 || val == 0xffff) 2199 continue; /* skip invalid entries */ 2200 sc->bbp_prom[i].reg = val >> 8; 2201 sc->bbp_prom[i].val = val & 0xff; 2202 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2203 sc->bbp_prom[i].val); 2204 } 2205} 2206 2207static int 2208rt2661_bbp_init(struct rt2661_softc *sc) 2209{ 2210 int i, ntries; 2211 uint8_t val; 2212 2213 /* wait for BBP to be ready */ 2214 for (ntries = 0; ntries < 100; ntries++) { 2215 val = rt2661_bbp_read(sc, 0); 2216 if (val != 0 && val != 0xff) 2217 break; 2218 DELAY(100); 2219 } 2220 if (ntries == 100) { 2221 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2222 return EIO; 2223 } 2224 2225 /* initialize BBP registers to default values */ 2226 for (i = 0; i < nitems(rt2661_def_bbp); i++) { 2227 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2228 rt2661_def_bbp[i].val); 2229 } 2230 2231 /* write vendor-specific BBP values (from EEPROM) */ 2232 for (i = 0; i < 16; i++) { 2233 if (sc->bbp_prom[i].reg == 0) 2234 continue; 2235 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2236 } 2237 2238 return 0; 2239} 2240 2241static void 2242rt2661_init_locked(struct rt2661_softc *sc) 2243{ 2244 struct ieee80211com *ic = &sc->sc_ic; 2245 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2246 uint32_t tmp, sta[3]; 2247 int i, error, ntries; 2248 2249 RAL_LOCK_ASSERT(sc); 2250 2251 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2252 error = rt2661_load_microcode(sc); 2253 if (error != 0) { 2254 device_printf(sc->sc_dev, 2255 "%s: could not load 8051 microcode, error %d\n", 2256 __func__, error); 2257 return; 2258 } 2259 sc->sc_flags |= RAL_FW_LOADED; 2260 } 2261 2262 rt2661_stop_locked(sc); 2263 2264 /* initialize Tx rings */ 2265 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2266 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2267 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2268 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2269 2270 /* initialize Mgt ring */ 2271 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2272 2273 /* initialize Rx ring */ 2274 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2275 2276 /* initialize Tx rings sizes */ 2277 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2278 RT2661_TX_RING_COUNT << 24 | 2279 RT2661_TX_RING_COUNT << 16 | 2280 RT2661_TX_RING_COUNT << 8 | 2281 RT2661_TX_RING_COUNT); 2282 2283 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2284 RT2661_TX_DESC_WSIZE << 16 | 2285 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2286 RT2661_MGT_RING_COUNT); 2287 2288 /* initialize Rx rings */ 2289 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2290 RT2661_RX_DESC_BACK << 16 | 2291 RT2661_RX_DESC_WSIZE << 8 | 2292 RT2661_RX_RING_COUNT); 2293 2294 /* XXX: some magic here */ 2295 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2296 2297 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2298 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2299 2300 /* load base address of Rx ring */ 2301 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2302 2303 /* initialize MAC registers to default values */ 2304 for (i = 0; i < nitems(rt2661_def_mac); i++) 2305 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2306 2307 rt2661_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2308 2309 /* set host ready */ 2310 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2311 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2312 2313 /* wait for BBP/RF to wakeup */ 2314 for (ntries = 0; ntries < 1000; ntries++) { 2315 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2316 break; 2317 DELAY(1000); 2318 } 2319 if (ntries == 1000) { 2320 printf("timeout waiting for BBP/RF to wakeup\n"); 2321 rt2661_stop_locked(sc); 2322 return; 2323 } 2324 2325 if (rt2661_bbp_init(sc) != 0) { 2326 rt2661_stop_locked(sc); 2327 return; 2328 } 2329 2330 /* select default channel */ 2331 sc->sc_curchan = ic->ic_curchan; 2332 rt2661_select_band(sc, sc->sc_curchan); 2333 rt2661_select_antenna(sc); 2334 rt2661_set_chan(sc, sc->sc_curchan); 2335 2336 /* update Rx filter */ 2337 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2338 2339 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2340 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2341 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2342 RT2661_DROP_ACKCTS; 2343 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2344 ic->ic_opmode != IEEE80211_M_MBSS) 2345 tmp |= RT2661_DROP_TODS; 2346 if (ic->ic_promisc == 0) 2347 tmp |= RT2661_DROP_NOT_TO_ME; 2348 } 2349 2350 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2351 2352 /* clear STA registers */ 2353 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta)); 2354 2355 /* initialize ASIC */ 2356 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2357 2358 /* clear any pending interrupt */ 2359 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2360 2361 /* enable interrupts */ 2362 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2363 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2364 2365 /* kick Rx */ 2366 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2367 2368 sc->sc_flags |= RAL_RUNNING; 2369 2370 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2371} 2372 2373static void 2374rt2661_init(void *priv) 2375{ 2376 struct rt2661_softc *sc = priv; 2377 struct ieee80211com *ic = &sc->sc_ic; 2378 2379 RAL_LOCK(sc); 2380 rt2661_init_locked(sc); 2381 RAL_UNLOCK(sc); 2382 2383 if (sc->sc_flags & RAL_RUNNING) 2384 ieee80211_start_all(ic); /* start all vap's */ 2385} 2386 2387void 2388rt2661_stop_locked(struct rt2661_softc *sc) 2389{ 2390 volatile int *flags = &sc->sc_flags; 2391 uint32_t tmp; 2392 2393 while (*flags & RAL_INPUT_RUNNING) 2394 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2395 2396 callout_stop(&sc->watchdog_ch); 2397 sc->sc_tx_timer = 0; 2398 2399 if (sc->sc_flags & RAL_RUNNING) { 2400 sc->sc_flags &= ~RAL_RUNNING; 2401 2402 /* abort Tx (for all 5 Tx rings) */ 2403 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2404 2405 /* disable Rx (value remains after reset!) */ 2406 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2407 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2408 2409 /* reset ASIC */ 2410 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2411 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2412 2413 /* disable interrupts */ 2414 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2415 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2416 2417 /* clear any pending interrupt */ 2418 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2419 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2420 2421 /* reset Tx and Rx rings */ 2422 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2423 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2424 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2425 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2426 rt2661_reset_tx_ring(sc, &sc->mgtq); 2427 rt2661_reset_rx_ring(sc, &sc->rxq); 2428 } 2429} 2430 2431void 2432rt2661_stop(void *priv) 2433{ 2434 struct rt2661_softc *sc = priv; 2435 2436 RAL_LOCK(sc); 2437 rt2661_stop_locked(sc); 2438 RAL_UNLOCK(sc); 2439} 2440 2441static int 2442rt2661_load_microcode(struct rt2661_softc *sc) 2443{ 2444 const struct firmware *fp; 2445 const char *imagename; 2446 int ntries, error; 2447 2448 RAL_LOCK_ASSERT(sc); 2449 2450 switch (sc->sc_id) { 2451 case 0x0301: imagename = "rt2561sfw"; break; 2452 case 0x0302: imagename = "rt2561fw"; break; 2453 case 0x0401: imagename = "rt2661fw"; break; 2454 default: 2455 device_printf(sc->sc_dev, "%s: unexpected pci device id 0x%x, " 2456 "don't know how to retrieve firmware\n", 2457 __func__, sc->sc_id); 2458 return EINVAL; 2459 } 2460 RAL_UNLOCK(sc); 2461 fp = firmware_get(imagename); 2462 RAL_LOCK(sc); 2463 if (fp == NULL) { 2464 device_printf(sc->sc_dev, 2465 "%s: unable to retrieve firmware image %s\n", 2466 __func__, imagename); 2467 return EINVAL; 2468 } 2469 2470 /* 2471 * Load 8051 microcode into NIC. 2472 */ 2473 /* reset 8051 */ 2474 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2475 2476 /* cancel any pending Host to MCU command */ 2477 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2478 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2479 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2480 2481 /* write 8051's microcode */ 2482 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2483 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2484 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2485 2486 /* kick 8051's ass */ 2487 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2488 2489 /* wait for 8051 to initialize */ 2490 for (ntries = 0; ntries < 500; ntries++) { 2491 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2492 break; 2493 DELAY(100); 2494 } 2495 if (ntries == 500) { 2496 device_printf(sc->sc_dev, 2497 "%s: timeout waiting for MCU to initialize\n", __func__); 2498 error = EIO; 2499 } else 2500 error = 0; 2501 2502 firmware_put(fp, FIRMWARE_UNLOAD); 2503 return error; 2504} 2505 2506#ifdef notyet 2507/* 2508 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2509 * false CCA count. This function is called periodically (every seconds) when 2510 * in the RUN state. Values taken from the reference driver. 2511 */ 2512static void 2513rt2661_rx_tune(struct rt2661_softc *sc) 2514{ 2515 uint8_t bbp17; 2516 uint16_t cca; 2517 int lo, hi, dbm; 2518 2519 /* 2520 * Tuning range depends on operating band and on the presence of an 2521 * external low-noise amplifier. 2522 */ 2523 lo = 0x20; 2524 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2525 lo += 0x08; 2526 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2527 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2528 lo += 0x10; 2529 hi = lo + 0x20; 2530 2531 /* retrieve false CCA count since last call (clear on read) */ 2532 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2533 2534 if (dbm >= -35) { 2535 bbp17 = 0x60; 2536 } else if (dbm >= -58) { 2537 bbp17 = hi; 2538 } else if (dbm >= -66) { 2539 bbp17 = lo + 0x10; 2540 } else if (dbm >= -74) { 2541 bbp17 = lo + 0x08; 2542 } else { 2543 /* RSSI < -74dBm, tune using false CCA count */ 2544 2545 bbp17 = sc->bbp17; /* current value */ 2546 2547 hi -= 2 * (-74 - dbm); 2548 if (hi < lo) 2549 hi = lo; 2550 2551 if (bbp17 > hi) { 2552 bbp17 = hi; 2553 2554 } else if (cca > 512) { 2555 if (++bbp17 > hi) 2556 bbp17 = hi; 2557 } else if (cca < 100) { 2558 if (--bbp17 < lo) 2559 bbp17 = lo; 2560 } 2561 } 2562 2563 if (bbp17 != sc->bbp17) { 2564 rt2661_bbp_write(sc, 17, bbp17); 2565 sc->bbp17 = bbp17; 2566 } 2567} 2568 2569/* 2570 * Enter/Leave radar detection mode. 2571 * This is for 802.11h additional regulatory domains. 2572 */ 2573static void 2574rt2661_radar_start(struct rt2661_softc *sc) 2575{ 2576 uint32_t tmp; 2577 2578 /* disable Rx */ 2579 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2580 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2581 2582 rt2661_bbp_write(sc, 82, 0x20); 2583 rt2661_bbp_write(sc, 83, 0x00); 2584 rt2661_bbp_write(sc, 84, 0x40); 2585 2586 /* save current BBP registers values */ 2587 sc->bbp18 = rt2661_bbp_read(sc, 18); 2588 sc->bbp21 = rt2661_bbp_read(sc, 21); 2589 sc->bbp22 = rt2661_bbp_read(sc, 22); 2590 sc->bbp16 = rt2661_bbp_read(sc, 16); 2591 sc->bbp17 = rt2661_bbp_read(sc, 17); 2592 sc->bbp64 = rt2661_bbp_read(sc, 64); 2593 2594 rt2661_bbp_write(sc, 18, 0xff); 2595 rt2661_bbp_write(sc, 21, 0x3f); 2596 rt2661_bbp_write(sc, 22, 0x3f); 2597 rt2661_bbp_write(sc, 16, 0xbd); 2598 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2599 rt2661_bbp_write(sc, 64, 0x21); 2600 2601 /* restore Rx filter */ 2602 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2603} 2604 2605static int 2606rt2661_radar_stop(struct rt2661_softc *sc) 2607{ 2608 uint8_t bbp66; 2609 2610 /* read radar detection result */ 2611 bbp66 = rt2661_bbp_read(sc, 66); 2612 2613 /* restore BBP registers values */ 2614 rt2661_bbp_write(sc, 16, sc->bbp16); 2615 rt2661_bbp_write(sc, 17, sc->bbp17); 2616 rt2661_bbp_write(sc, 18, sc->bbp18); 2617 rt2661_bbp_write(sc, 21, sc->bbp21); 2618 rt2661_bbp_write(sc, 22, sc->bbp22); 2619 rt2661_bbp_write(sc, 64, sc->bbp64); 2620 2621 return bbp66 == 1; 2622} 2623#endif 2624 2625static int 2626rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2627{ 2628 struct ieee80211com *ic = vap->iv_ic; 2629 struct rt2661_tx_desc desc; 2630 struct mbuf *m0; 2631 int rate; 2632 2633 if ((m0 = ieee80211_beacon_alloc(vap->iv_bss))== NULL) { 2634 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2635 return ENOBUFS; 2636 } 2637 2638 /* send beacons at the lowest available rate */ 2639 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2640 2641 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2642 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2643 2644 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2645 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2646 2647 /* copy beacon header and payload into NIC memory */ 2648 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2649 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2650 2651 m_freem(m0); 2652 2653 return 0; 2654} 2655 2656/* 2657 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2658 * and HostAP operating modes. 2659 */ 2660static void 2661rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2662{ 2663 struct ieee80211com *ic = &sc->sc_ic; 2664 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2665 uint32_t tmp; 2666 2667 if (vap->iv_opmode != IEEE80211_M_STA) { 2668 /* 2669 * Change default 16ms TBTT adjustment to 8ms. 2670 * Must be done before enabling beacon generation. 2671 */ 2672 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2673 } 2674 2675 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2676 2677 /* set beacon interval (in 1/16ms unit) */ 2678 tmp |= vap->iv_bss->ni_intval * 16; 2679 2680 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2681 if (vap->iv_opmode == IEEE80211_M_STA) 2682 tmp |= RT2661_TSF_MODE(1); 2683 else 2684 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2685 2686 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2687} 2688 2689static void 2690rt2661_enable_tsf(struct rt2661_softc *sc) 2691{ 2692 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2693 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2694 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2695} 2696 2697/* 2698 * Retrieve the "Received Signal Strength Indicator" from the raw values 2699 * contained in Rx descriptors. The computation depends on which band the 2700 * frame was received. Correction values taken from the reference driver. 2701 */ 2702static int 2703rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2704{ 2705 int lna, agc, rssi; 2706 2707 lna = (raw >> 5) & 0x3; 2708 agc = raw & 0x1f; 2709 2710 if (lna == 0) { 2711 /* 2712 * No mapping available. 2713 * 2714 * NB: Since RSSI is relative to noise floor, -1 is 2715 * adequate for caller to know error happened. 2716 */ 2717 return -1; 2718 } 2719 2720 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2721 2722 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2723 rssi += sc->rssi_2ghz_corr; 2724 2725 if (lna == 1) 2726 rssi -= 64; 2727 else if (lna == 2) 2728 rssi -= 74; 2729 else if (lna == 3) 2730 rssi -= 90; 2731 } else { 2732 rssi += sc->rssi_5ghz_corr; 2733 2734 if (lna == 1) 2735 rssi -= 64; 2736 else if (lna == 2) 2737 rssi -= 86; 2738 else if (lna == 3) 2739 rssi -= 100; 2740 } 2741 return rssi; 2742} 2743 2744static void 2745rt2661_scan_start(struct ieee80211com *ic) 2746{ 2747 struct rt2661_softc *sc = ic->ic_softc; 2748 uint32_t tmp; 2749 2750 /* abort TSF synchronization */ 2751 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2752 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2753 rt2661_set_bssid(sc, ieee80211broadcastaddr); 2754} 2755 2756static void 2757rt2661_scan_end(struct ieee80211com *ic) 2758{ 2759 struct rt2661_softc *sc = ic->ic_softc; 2760 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2761 2762 rt2661_enable_tsf_sync(sc); 2763 /* XXX keep local copy */ 2764 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2765} 2766 2767static void 2768rt2661_getradiocaps(struct ieee80211com *ic, 2769 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2770{ 2771 struct rt2661_softc *sc = ic->ic_softc; 2772 uint8_t bands[IEEE80211_MODE_BYTES]; 2773 2774 memset(bands, 0, sizeof(bands)); 2775 setbit(bands, IEEE80211_MODE_11B); 2776 setbit(bands, IEEE80211_MODE_11G); 2777 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2778 2779 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 2780 setbit(bands, IEEE80211_MODE_11A); 2781 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2782 rt2661_chan_5ghz, nitems(rt2661_chan_5ghz), bands, 0); 2783 } 2784} 2785 2786static void 2787rt2661_set_channel(struct ieee80211com *ic) 2788{ 2789 struct rt2661_softc *sc = ic->ic_softc; 2790 2791 RAL_LOCK(sc); 2792 rt2661_set_chan(sc, ic->ic_curchan); 2793 RAL_UNLOCK(sc); 2794 2795} 2796