rt2661.c revision 178957
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 178957 2008-05-12 00:15:30Z sam $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 178957 2008-05-12 00:15:30Z sam $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_phy.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_amrr.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2661reg.h> 68#include <dev/ral/rt2661var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(sc, fmt, ...) do { \ 73 if (sc->sc_debug > 0) \ 74 printf(fmt, __VA_ARGS__); \ 75} while (0) 76#define DPRINTFN(sc, n, fmt, ...) do { \ 77 if (sc->sc_debug >= (n)) \ 78 printf(fmt, __VA_ARGS__); \ 79} while (0) 80#else 81#define DPRINTF(sc, fmt, ...) 82#define DPRINTFN(sc, n, fmt, ...) 83#endif 84 85static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 86 const char name[IFNAMSIZ], int unit, int opmode, 87 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 88 const uint8_t mac[IEEE80211_ADDR_LEN]); 89static void rt2661_vap_delete(struct ieee80211vap *); 90static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 91 int); 92static int rt2661_alloc_tx_ring(struct rt2661_softc *, 93 struct rt2661_tx_ring *, int); 94static void rt2661_reset_tx_ring(struct rt2661_softc *, 95 struct rt2661_tx_ring *); 96static void rt2661_free_tx_ring(struct rt2661_softc *, 97 struct rt2661_tx_ring *); 98static int rt2661_alloc_rx_ring(struct rt2661_softc *, 99 struct rt2661_rx_ring *, int); 100static void rt2661_reset_rx_ring(struct rt2661_softc *, 101 struct rt2661_rx_ring *); 102static void rt2661_free_rx_ring(struct rt2661_softc *, 103 struct rt2661_rx_ring *); 104static struct ieee80211_node *rt2661_node_alloc( 105 struct ieee80211_node_table *); 106static void rt2661_newassoc(struct ieee80211_node *, int); 107static int rt2661_newstate(struct ieee80211vap *, 108 enum ieee80211_state, int); 109static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 110static void rt2661_rx_intr(struct rt2661_softc *); 111static void rt2661_tx_intr(struct rt2661_softc *); 112static void rt2661_tx_dma_intr(struct rt2661_softc *, 113 struct rt2661_tx_ring *); 114static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 115static void rt2661_mcu_wakeup(struct rt2661_softc *); 116static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 117static void rt2661_scan_start(struct ieee80211com *); 118static void rt2661_scan_end(struct ieee80211com *); 119static void rt2661_set_channel(struct ieee80211com *); 120static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 122 int, const bus_dma_segment_t *, int, int); 123static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *, int); 125static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 126 struct ieee80211_node *); 127static void rt2661_start_locked(struct ifnet *); 128static void rt2661_start(struct ifnet *); 129static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 130 const struct ieee80211_bpf_params *); 131static void rt2661_watchdog(void *); 132static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 133static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 134 uint8_t); 135static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 137 uint32_t); 138static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 139 uint16_t); 140static void rt2661_select_antenna(struct rt2661_softc *); 141static void rt2661_enable_mrr(struct rt2661_softc *); 142static void rt2661_set_txpreamble(struct rt2661_softc *); 143static void rt2661_set_basicrates(struct rt2661_softc *, 144 const struct ieee80211_rateset *); 145static void rt2661_select_band(struct rt2661_softc *, 146 struct ieee80211_channel *); 147static void rt2661_set_chan(struct rt2661_softc *, 148 struct ieee80211_channel *); 149static void rt2661_set_bssid(struct rt2661_softc *, 150 const uint8_t *); 151static void rt2661_set_macaddr(struct rt2661_softc *, 152 const uint8_t *); 153static void rt2661_update_promisc(struct ifnet *); 154static int rt2661_wme_update(struct ieee80211com *) __unused; 155static void rt2661_update_slot(struct ifnet *); 156static const char *rt2661_get_rf(int); 157static void rt2661_read_eeprom(struct rt2661_softc *, 158 struct ieee80211com *); 159static int rt2661_bbp_init(struct rt2661_softc *); 160static void rt2661_init_locked(struct rt2661_softc *); 161static void rt2661_init(void *); 162static void rt2661_stop_locked(struct rt2661_softc *); 163static void rt2661_stop(void *); 164static int rt2661_load_microcode(struct rt2661_softc *); 165#ifdef notyet 166static void rt2661_rx_tune(struct rt2661_softc *); 167static void rt2661_radar_start(struct rt2661_softc *); 168static int rt2661_radar_stop(struct rt2661_softc *); 169#endif 170static int rt2661_prepare_beacon(struct rt2661_softc *, 171 struct ieee80211vap *); 172static void rt2661_enable_tsf_sync(struct rt2661_softc *); 173static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 174 175static const struct { 176 uint32_t reg; 177 uint32_t val; 178} rt2661_def_mac[] = { 179 RT2661_DEF_MAC 180}; 181 182static const struct { 183 uint8_t reg; 184 uint8_t val; 185} rt2661_def_bbp[] = { 186 RT2661_DEF_BBP 187}; 188 189static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192} rt2661_rf5225_1[] = { 193 RT2661_RF5225_1 194}, rt2661_rf5225_2[] = { 195 RT2661_RF5225_2 196}; 197 198int 199rt2661_attach(device_t dev, int id) 200{ 201 struct rt2661_softc *sc = device_get_softc(dev); 202 struct ieee80211com *ic; 203 struct ifnet *ifp; 204 uint32_t val; 205 int error, ac, ntries; 206 uint8_t bands; 207 208 sc->sc_id = id; 209 sc->sc_dev = dev; 210 211 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 212 if (ifp == NULL) { 213 device_printf(sc->sc_dev, "can not if_alloc()\n"); 214 return ENOMEM; 215 } 216 ic = ifp->if_l2com; 217 218 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 219 MTX_DEF | MTX_RECURSE); 220 221 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 222 223 /* wait for NIC to initialize */ 224 for (ntries = 0; ntries < 1000; ntries++) { 225 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 226 break; 227 DELAY(1000); 228 } 229 if (ntries == 1000) { 230 device_printf(sc->sc_dev, 231 "timeout waiting for NIC to initialize\n"); 232 error = EIO; 233 goto fail1; 234 } 235 236 /* retrieve RF rev. no and various other things from EEPROM */ 237 rt2661_read_eeprom(sc, ic); 238 239 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 240 rt2661_get_rf(sc->rf_rev)); 241 242 /* 243 * Allocate Tx and Rx rings. 244 */ 245 for (ac = 0; ac < 4; ac++) { 246 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 247 RT2661_TX_RING_COUNT); 248 if (error != 0) { 249 device_printf(sc->sc_dev, 250 "could not allocate Tx ring %d\n", ac); 251 goto fail2; 252 } 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 256 if (error != 0) { 257 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 258 goto fail2; 259 } 260 261 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 262 if (error != 0) { 263 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 264 goto fail3; 265 } 266 267 ifp->if_softc = sc; 268 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_init = rt2661_init; 271 ifp->if_ioctl = rt2661_ioctl; 272 ifp->if_start = rt2661_start; 273 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 274 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 275 IFQ_SET_READY(&ifp->if_snd); 276 277 ic->ic_ifp = ifp; 278 ic->ic_opmode = IEEE80211_M_STA; 279 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 280 281 /* set device capabilities */ 282 ic->ic_caps = 283 IEEE80211_C_STA /* station mode */ 284 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 285 | IEEE80211_C_HOSTAP /* hostap mode */ 286 | IEEE80211_C_MONITOR /* monitor mode */ 287 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 288 | IEEE80211_C_WDS /* 4-address traffic works */ 289 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 290 | IEEE80211_C_SHSLOT /* short slot time supported */ 291 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 292 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 293#ifdef notyet 294 | IEEE80211_C_TXFRAG /* handle tx frags */ 295 | IEEE80211_C_WME /* 802.11e */ 296#endif 297 ; 298 299 bands = 0; 300 setbit(&bands, IEEE80211_MODE_11B); 301 setbit(&bands, IEEE80211_MODE_11G); 302 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 303 setbit(&bands, IEEE80211_MODE_11A); 304 ieee80211_init_channels(ic, NULL, &bands); 305 306 ieee80211_ifattach(ic); 307 ic->ic_newassoc = rt2661_newassoc; 308 ic->ic_node_alloc = rt2661_node_alloc; 309#if 0 310 ic->ic_wme.wme_update = rt2661_wme_update; 311#endif 312 ic->ic_scan_start = rt2661_scan_start; 313 ic->ic_scan_end = rt2661_scan_end; 314 ic->ic_set_channel = rt2661_set_channel; 315 ic->ic_updateslot = rt2661_update_slot; 316 ic->ic_update_promisc = rt2661_update_promisc; 317 ic->ic_raw_xmit = rt2661_raw_xmit; 318 319 ic->ic_vap_create = rt2661_vap_create; 320 ic->ic_vap_delete = rt2661_vap_delete; 321 322 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 323 324 bpfattach(ifp, DLT_IEEE802_11_RADIO, 325 sizeof (struct ieee80211_frame) + sizeof (sc->sc_txtap)); 326 327 sc->sc_rxtap_len = sizeof sc->sc_rxtap; 328 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 329 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 330 331 sc->sc_txtap_len = sizeof sc->sc_txtap; 332 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 333 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 334 335#ifdef RAL_DEBUG 336 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 337 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 338 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 339#endif 340 if (bootverbose) 341 ieee80211_announce(ic); 342 343 return 0; 344 345fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 346fail2: while (--ac >= 0) 347 rt2661_free_tx_ring(sc, &sc->txq[ac]); 348fail1: mtx_destroy(&sc->sc_mtx); 349 if_free(ifp); 350 return error; 351} 352 353int 354rt2661_detach(void *xsc) 355{ 356 struct rt2661_softc *sc = xsc; 357 struct ifnet *ifp = sc->sc_ifp; 358 struct ieee80211com *ic = ifp->if_l2com; 359 360 RAL_LOCK(sc); 361 rt2661_stop_locked(sc); 362 RAL_UNLOCK(sc); 363 364 bpfdetach(ifp); 365 ieee80211_ifdetach(ic); 366 367 rt2661_free_tx_ring(sc, &sc->txq[0]); 368 rt2661_free_tx_ring(sc, &sc->txq[1]); 369 rt2661_free_tx_ring(sc, &sc->txq[2]); 370 rt2661_free_tx_ring(sc, &sc->txq[3]); 371 rt2661_free_tx_ring(sc, &sc->mgtq); 372 rt2661_free_rx_ring(sc, &sc->rxq); 373 374 if_free(ifp); 375 376 mtx_destroy(&sc->sc_mtx); 377 378 return 0; 379} 380 381static struct ieee80211vap * 382rt2661_vap_create(struct ieee80211com *ic, 383 const char name[IFNAMSIZ], int unit, int opmode, int flags, 384 const uint8_t bssid[IEEE80211_ADDR_LEN], 385 const uint8_t mac[IEEE80211_ADDR_LEN]) 386{ 387 struct ifnet *ifp = ic->ic_ifp; 388 struct rt2661_vap *rvp; 389 struct ieee80211vap *vap; 390 391 switch (opmode) { 392 case IEEE80211_M_STA: 393 case IEEE80211_M_IBSS: 394 case IEEE80211_M_AHDEMO: 395 case IEEE80211_M_MONITOR: 396 case IEEE80211_M_HOSTAP: 397 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 398 if_printf(ifp, "only 1 vap supported\n"); 399 return NULL; 400 } 401 if (opmode == IEEE80211_M_STA) 402 flags |= IEEE80211_CLONE_NOBEACONS; 403 break; 404 case IEEE80211_M_WDS: 405 if (TAILQ_EMPTY(&ic->ic_vaps) || 406 ic->ic_opmode != IEEE80211_M_HOSTAP) { 407 if_printf(ifp, "wds only supported in ap mode\n"); 408 return NULL; 409 } 410 /* 411 * Silently remove any request for a unique 412 * bssid; WDS vap's always share the local 413 * mac address. 414 */ 415 flags &= ~IEEE80211_CLONE_BSSID; 416 break; 417 default: 418 if_printf(ifp, "unknown opmode %d\n", opmode); 419 return NULL; 420 } 421 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), 422 M_80211_VAP, M_NOWAIT | M_ZERO); 423 if (rvp == NULL) 424 return NULL; 425 vap = &rvp->ral_vap; 426 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 427 428 /* override state transition machine */ 429 rvp->ral_newstate = vap->iv_newstate; 430 vap->iv_newstate = rt2661_newstate; 431#if 0 432 vap->iv_update_beacon = rt2661_beacon_update; 433#endif 434 435 ieee80211_amrr_init(&rvp->amrr, vap, 436 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 437 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 438 500 /* ms */); 439 440 /* complete setup */ 441 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 442 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 443 ic->ic_opmode = opmode; 444 return vap; 445} 446 447static void 448rt2661_vap_delete(struct ieee80211vap *vap) 449{ 450 struct rt2661_vap *rvp = RT2661_VAP(vap); 451 452 ieee80211_amrr_cleanup(&rvp->amrr); 453 ieee80211_vap_detach(vap); 454 free(rvp, M_80211_VAP); 455} 456 457void 458rt2661_shutdown(void *xsc) 459{ 460 struct rt2661_softc *sc = xsc; 461 462 rt2661_stop(sc); 463} 464 465void 466rt2661_suspend(void *xsc) 467{ 468 struct rt2661_softc *sc = xsc; 469 470 rt2661_stop(sc); 471} 472 473void 474rt2661_resume(void *xsc) 475{ 476 struct rt2661_softc *sc = xsc; 477 struct ifnet *ifp = sc->sc_ifp; 478 479 if (ifp->if_flags & IFF_UP) 480 rt2661_init(sc); 481} 482 483static void 484rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 485{ 486 if (error != 0) 487 return; 488 489 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 490 491 *(bus_addr_t *)arg = segs[0].ds_addr; 492} 493 494static int 495rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 496 int count) 497{ 498 int i, error; 499 500 ring->count = count; 501 ring->queued = 0; 502 ring->cur = ring->next = ring->stat = 0; 503 504 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 505 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 506 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 507 0, NULL, NULL, &ring->desc_dmat); 508 if (error != 0) { 509 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 510 goto fail; 511 } 512 513 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 514 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 517 goto fail; 518 } 519 520 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 521 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 522 0); 523 if (error != 0) { 524 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 525 goto fail; 526 } 527 528 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 529 M_NOWAIT | M_ZERO); 530 if (ring->data == NULL) { 531 device_printf(sc->sc_dev, "could not allocate soft data\n"); 532 error = ENOMEM; 533 goto fail; 534 } 535 536 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 537 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 538 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 539 if (error != 0) { 540 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 541 goto fail; 542 } 543 544 for (i = 0; i < count; i++) { 545 error = bus_dmamap_create(ring->data_dmat, 0, 546 &ring->data[i].map); 547 if (error != 0) { 548 device_printf(sc->sc_dev, "could not create DMA map\n"); 549 goto fail; 550 } 551 } 552 553 return 0; 554 555fail: rt2661_free_tx_ring(sc, ring); 556 return error; 557} 558 559static void 560rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 561{ 562 struct rt2661_tx_desc *desc; 563 struct rt2661_tx_data *data; 564 int i; 565 566 for (i = 0; i < ring->count; i++) { 567 desc = &ring->desc[i]; 568 data = &ring->data[i]; 569 570 if (data->m != NULL) { 571 bus_dmamap_sync(ring->data_dmat, data->map, 572 BUS_DMASYNC_POSTWRITE); 573 bus_dmamap_unload(ring->data_dmat, data->map); 574 m_freem(data->m); 575 data->m = NULL; 576 } 577 578 if (data->ni != NULL) { 579 ieee80211_free_node(data->ni); 580 data->ni = NULL; 581 } 582 583 desc->flags = 0; 584 } 585 586 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 587 588 ring->queued = 0; 589 ring->cur = ring->next = ring->stat = 0; 590} 591 592static void 593rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 594{ 595 struct rt2661_tx_data *data; 596 int i; 597 598 if (ring->desc != NULL) { 599 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 600 BUS_DMASYNC_POSTWRITE); 601 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 602 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 603 } 604 605 if (ring->desc_dmat != NULL) 606 bus_dma_tag_destroy(ring->desc_dmat); 607 608 if (ring->data != NULL) { 609 for (i = 0; i < ring->count; i++) { 610 data = &ring->data[i]; 611 612 if (data->m != NULL) { 613 bus_dmamap_sync(ring->data_dmat, data->map, 614 BUS_DMASYNC_POSTWRITE); 615 bus_dmamap_unload(ring->data_dmat, data->map); 616 m_freem(data->m); 617 } 618 619 if (data->ni != NULL) 620 ieee80211_free_node(data->ni); 621 622 if (data->map != NULL) 623 bus_dmamap_destroy(ring->data_dmat, data->map); 624 } 625 626 free(ring->data, M_DEVBUF); 627 } 628 629 if (ring->data_dmat != NULL) 630 bus_dma_tag_destroy(ring->data_dmat); 631} 632 633static int 634rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 635 int count) 636{ 637 struct rt2661_rx_desc *desc; 638 struct rt2661_rx_data *data; 639 bus_addr_t physaddr; 640 int i, error; 641 642 ring->count = count; 643 ring->cur = ring->next = 0; 644 645 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 646 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 647 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 648 0, NULL, NULL, &ring->desc_dmat); 649 if (error != 0) { 650 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 651 goto fail; 652 } 653 654 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 655 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 656 if (error != 0) { 657 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 658 goto fail; 659 } 660 661 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 662 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 663 0); 664 if (error != 0) { 665 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 666 goto fail; 667 } 668 669 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 670 M_NOWAIT | M_ZERO); 671 if (ring->data == NULL) { 672 device_printf(sc->sc_dev, "could not allocate soft data\n"); 673 error = ENOMEM; 674 goto fail; 675 } 676 677 /* 678 * Pre-allocate Rx buffers and populate Rx ring. 679 */ 680 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 681 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 682 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 683 if (error != 0) { 684 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 685 goto fail; 686 } 687 688 for (i = 0; i < count; i++) { 689 desc = &sc->rxq.desc[i]; 690 data = &sc->rxq.data[i]; 691 692 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 693 if (error != 0) { 694 device_printf(sc->sc_dev, "could not create DMA map\n"); 695 goto fail; 696 } 697 698 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 699 if (data->m == NULL) { 700 device_printf(sc->sc_dev, 701 "could not allocate rx mbuf\n"); 702 error = ENOMEM; 703 goto fail; 704 } 705 706 error = bus_dmamap_load(ring->data_dmat, data->map, 707 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 708 &physaddr, 0); 709 if (error != 0) { 710 device_printf(sc->sc_dev, 711 "could not load rx buf DMA map"); 712 goto fail; 713 } 714 715 desc->flags = htole32(RT2661_RX_BUSY); 716 desc->physaddr = htole32(physaddr); 717 } 718 719 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 720 721 return 0; 722 723fail: rt2661_free_rx_ring(sc, ring); 724 return error; 725} 726 727static void 728rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 729{ 730 int i; 731 732 for (i = 0; i < ring->count; i++) 733 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 734 735 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 736 737 ring->cur = ring->next = 0; 738} 739 740static void 741rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 742{ 743 struct rt2661_rx_data *data; 744 int i; 745 746 if (ring->desc != NULL) { 747 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 748 BUS_DMASYNC_POSTWRITE); 749 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 750 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 751 } 752 753 if (ring->desc_dmat != NULL) 754 bus_dma_tag_destroy(ring->desc_dmat); 755 756 if (ring->data != NULL) { 757 for (i = 0; i < ring->count; i++) { 758 data = &ring->data[i]; 759 760 if (data->m != NULL) { 761 bus_dmamap_sync(ring->data_dmat, data->map, 762 BUS_DMASYNC_POSTREAD); 763 bus_dmamap_unload(ring->data_dmat, data->map); 764 m_freem(data->m); 765 } 766 767 if (data->map != NULL) 768 bus_dmamap_destroy(ring->data_dmat, data->map); 769 } 770 771 free(ring->data, M_DEVBUF); 772 } 773 774 if (ring->data_dmat != NULL) 775 bus_dma_tag_destroy(ring->data_dmat); 776} 777 778static struct ieee80211_node * 779rt2661_node_alloc(struct ieee80211_node_table *nt) 780{ 781 struct rt2661_node *rn; 782 783 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 784 M_NOWAIT | M_ZERO); 785 786 return (rn != NULL) ? &rn->ni : NULL; 787} 788 789static void 790rt2661_newassoc(struct ieee80211_node *ni, int isnew) 791{ 792 struct ieee80211vap *vap = ni->ni_vap; 793 794 ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr, 795 &RT2661_NODE(ni)->amrr, ni); 796} 797 798static int 799rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 800{ 801 struct rt2661_vap *rvp = RT2661_VAP(vap); 802 struct ieee80211com *ic = vap->iv_ic; 803 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 804 int error; 805 806 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 807 uint32_t tmp; 808 809 /* abort TSF synchronization */ 810 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 811 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 812 } 813 814 error = rvp->ral_newstate(vap, nstate, arg); 815 816 if (error == 0 && nstate == IEEE80211_S_RUN) { 817 struct ieee80211_node *ni = vap->iv_bss; 818 819 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 820 rt2661_enable_mrr(sc); 821 rt2661_set_txpreamble(sc); 822 rt2661_set_basicrates(sc, &ni->ni_rates); 823 rt2661_set_bssid(sc, ni->ni_bssid); 824 } 825 826 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 827 vap->iv_opmode == IEEE80211_M_IBSS) { 828 error = rt2661_prepare_beacon(sc, vap); 829 if (error != 0) 830 return error; 831 } 832 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 833 if (vap->iv_opmode == IEEE80211_M_STA) { 834 /* fake a join to init the tx rate */ 835 rt2661_newassoc(ni, 1); 836 } 837 rt2661_enable_tsf_sync(sc); 838 } 839 } 840 return error; 841} 842 843/* 844 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 845 * 93C66). 846 */ 847static uint16_t 848rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 849{ 850 uint32_t tmp; 851 uint16_t val; 852 int n; 853 854 /* clock C once before the first command */ 855 RT2661_EEPROM_CTL(sc, 0); 856 857 RT2661_EEPROM_CTL(sc, RT2661_S); 858 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 859 RT2661_EEPROM_CTL(sc, RT2661_S); 860 861 /* write start bit (1) */ 862 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 863 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 864 865 /* write READ opcode (10) */ 866 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 867 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 868 RT2661_EEPROM_CTL(sc, RT2661_S); 869 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 870 871 /* write address (A5-A0 or A7-A0) */ 872 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 873 for (; n >= 0; n--) { 874 RT2661_EEPROM_CTL(sc, RT2661_S | 875 (((addr >> n) & 1) << RT2661_SHIFT_D)); 876 RT2661_EEPROM_CTL(sc, RT2661_S | 877 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 878 } 879 880 RT2661_EEPROM_CTL(sc, RT2661_S); 881 882 /* read data Q15-Q0 */ 883 val = 0; 884 for (n = 15; n >= 0; n--) { 885 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 886 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 887 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 888 RT2661_EEPROM_CTL(sc, RT2661_S); 889 } 890 891 RT2661_EEPROM_CTL(sc, 0); 892 893 /* clear Chip Select and clock C */ 894 RT2661_EEPROM_CTL(sc, RT2661_S); 895 RT2661_EEPROM_CTL(sc, 0); 896 RT2661_EEPROM_CTL(sc, RT2661_C); 897 898 return val; 899} 900 901static void 902rt2661_tx_intr(struct rt2661_softc *sc) 903{ 904 struct ifnet *ifp = sc->sc_ifp; 905 struct rt2661_tx_ring *txq; 906 struct rt2661_tx_data *data; 907 struct rt2661_node *rn; 908 uint32_t val; 909 int qid, retrycnt; 910 911 for (;;) { 912 struct ieee80211_node *ni; 913 struct mbuf *m; 914 915 val = RAL_READ(sc, RT2661_STA_CSR4); 916 if (!(val & RT2661_TX_STAT_VALID)) 917 break; 918 919 /* retrieve the queue in which this frame was sent */ 920 qid = RT2661_TX_QID(val); 921 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 922 923 /* retrieve rate control algorithm context */ 924 data = &txq->data[txq->stat]; 925 m = data->m; 926 data->m = NULL; 927 ni = data->ni; 928 data->ni = NULL; 929 930 /* if no frame has been sent, ignore */ 931 if (ni == NULL) 932 continue; 933 934 rn = RT2661_NODE(ni); 935 936 switch (RT2661_TX_RESULT(val)) { 937 case RT2661_TX_SUCCESS: 938 retrycnt = RT2661_TX_RETRYCNT(val); 939 940 DPRINTFN(sc, 10, "data frame sent successfully after " 941 "%d retries\n", retrycnt); 942 if (data->rix != IEEE80211_FIXED_RATE_NONE) 943 ieee80211_amrr_tx_complete(&rn->amrr, 944 IEEE80211_AMRR_SUCCESS, retrycnt); 945 ifp->if_opackets++; 946 break; 947 948 case RT2661_TX_RETRY_FAIL: 949 retrycnt = RT2661_TX_RETRYCNT(val); 950 951 DPRINTFN(sc, 9, "%s\n", 952 "sending data frame failed (too much retries)"); 953 if (data->rix != IEEE80211_FIXED_RATE_NONE) 954 ieee80211_amrr_tx_complete(&rn->amrr, 955 IEEE80211_AMRR_FAILURE, retrycnt); 956 ifp->if_oerrors++; 957 break; 958 959 default: 960 /* other failure */ 961 device_printf(sc->sc_dev, 962 "sending data frame failed 0x%08x\n", val); 963 ifp->if_oerrors++; 964 } 965 966 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 967 968 txq->queued--; 969 if (++txq->stat >= txq->count) /* faster than % count */ 970 txq->stat = 0; 971 972 if (m->m_flags & M_TXCB) 973 ieee80211_process_callback(ni, m, 974 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 975 m_freem(m); 976 ieee80211_free_node(ni); 977 } 978 979 sc->sc_tx_timer = 0; 980 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 981 982 rt2661_start_locked(ifp); 983} 984 985static void 986rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 987{ 988 struct rt2661_tx_desc *desc; 989 struct rt2661_tx_data *data; 990 991 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 992 993 for (;;) { 994 desc = &txq->desc[txq->next]; 995 data = &txq->data[txq->next]; 996 997 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 998 !(le32toh(desc->flags) & RT2661_TX_VALID)) 999 break; 1000 1001 bus_dmamap_sync(txq->data_dmat, data->map, 1002 BUS_DMASYNC_POSTWRITE); 1003 bus_dmamap_unload(txq->data_dmat, data->map); 1004 1005 /* descriptor is no longer valid */ 1006 desc->flags &= ~htole32(RT2661_TX_VALID); 1007 1008 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 1009 1010 if (++txq->next >= txq->count) /* faster than % count */ 1011 txq->next = 0; 1012 } 1013 1014 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1015} 1016 1017static void 1018rt2661_rx_intr(struct rt2661_softc *sc) 1019{ 1020 struct ifnet *ifp = sc->sc_ifp; 1021 struct ieee80211com *ic = ifp->if_l2com; 1022 struct rt2661_rx_desc *desc; 1023 struct rt2661_rx_data *data; 1024 bus_addr_t physaddr; 1025 struct ieee80211_frame *wh; 1026 struct ieee80211_node *ni; 1027 struct mbuf *mnew, *m; 1028 int error; 1029 1030 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1031 BUS_DMASYNC_POSTREAD); 1032 1033 for (;;) { 1034 int rssi; 1035 1036 desc = &sc->rxq.desc[sc->rxq.cur]; 1037 data = &sc->rxq.data[sc->rxq.cur]; 1038 1039 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1040 break; 1041 1042 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1043 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1044 /* 1045 * This should not happen since we did not request 1046 * to receive those frames when we filled TXRX_CSR0. 1047 */ 1048 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1049 le32toh(desc->flags)); 1050 ifp->if_ierrors++; 1051 goto skip; 1052 } 1053 1054 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1055 ifp->if_ierrors++; 1056 goto skip; 1057 } 1058 1059 /* 1060 * Try to allocate a new mbuf for this ring element and load it 1061 * before processing the current mbuf. If the ring element 1062 * cannot be loaded, drop the received packet and reuse the old 1063 * mbuf. In the unlikely case that the old mbuf can't be 1064 * reloaded either, explicitly panic. 1065 */ 1066 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1067 if (mnew == NULL) { 1068 ifp->if_ierrors++; 1069 goto skip; 1070 } 1071 1072 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1073 BUS_DMASYNC_POSTREAD); 1074 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1075 1076 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1077 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1078 &physaddr, 0); 1079 if (error != 0) { 1080 m_freem(mnew); 1081 1082 /* try to reload the old mbuf */ 1083 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1084 mtod(data->m, void *), MCLBYTES, 1085 rt2661_dma_map_addr, &physaddr, 0); 1086 if (error != 0) { 1087 /* very unlikely that it will fail... */ 1088 panic("%s: could not load old rx mbuf", 1089 device_get_name(sc->sc_dev)); 1090 } 1091 ifp->if_ierrors++; 1092 goto skip; 1093 } 1094 1095 /* 1096 * New mbuf successfully loaded, update Rx ring and continue 1097 * processing. 1098 */ 1099 m = data->m; 1100 data->m = mnew; 1101 desc->physaddr = htole32(physaddr); 1102 1103 /* finalize mbuf */ 1104 m->m_pkthdr.rcvif = ifp; 1105 m->m_pkthdr.len = m->m_len = 1106 (le32toh(desc->flags) >> 16) & 0xfff; 1107 1108 rssi = rt2661_get_rssi(sc, desc->rssi); 1109 1110 if (bpf_peers_present(ifp->if_bpf)) { 1111 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1112 uint32_t tsf_lo, tsf_hi; 1113 1114 /* get timestamp (low and high 32 bits) */ 1115 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1116 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1117 1118 tap->wr_tsf = 1119 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1120 tap->wr_flags = 0; 1121 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1122 le32toh(desc->flags) & RT2661_RX_OFDM); 1123 tap->wr_antsignal = rssi < 0 ? 0 : rssi; 1124 1125 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1126 } 1127 sc->sc_flags |= RAL_INPUT_RUNNING; 1128 RAL_UNLOCK(sc); 1129 wh = mtod(m, struct ieee80211_frame *); 1130 1131 /* send the frame to the 802.11 layer */ 1132 ni = ieee80211_find_rxnode(ic, 1133 (struct ieee80211_frame_min *)wh); 1134 if (ni != NULL) { 1135 /* Error happened during RSSI conversion. */ 1136 if (rssi < 0) 1137 rssi = -30; /* XXX ignored by net80211 */ 1138 1139 (void) ieee80211_input(ni, m, rssi, 1140 RT2661_NOISE_FLOOR, 0); 1141 ieee80211_free_node(ni); 1142 } else 1143 (void) ieee80211_input_all(ic, m, rssi, 1144 RT2661_NOISE_FLOOR, 0); 1145 1146 RAL_LOCK(sc); 1147 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1148 1149skip: desc->flags |= htole32(RT2661_RX_BUSY); 1150 1151 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1152 1153 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1154 } 1155 1156 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1157 BUS_DMASYNC_PREWRITE); 1158} 1159 1160/* ARGSUSED */ 1161static void 1162rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1163{ 1164 /* do nothing */ 1165} 1166 1167static void 1168rt2661_mcu_wakeup(struct rt2661_softc *sc) 1169{ 1170 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1171 1172 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1173 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1174 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1175 1176 /* send wakeup command to MCU */ 1177 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1178} 1179 1180static void 1181rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1182{ 1183 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1184 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1185} 1186 1187void 1188rt2661_intr(void *arg) 1189{ 1190 struct rt2661_softc *sc = arg; 1191 struct ifnet *ifp = sc->sc_ifp; 1192 uint32_t r1, r2; 1193 1194 RAL_LOCK(sc); 1195 1196 /* disable MAC and MCU interrupts */ 1197 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1198 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1199 1200 /* don't re-enable interrupts if we're shutting down */ 1201 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1202 RAL_UNLOCK(sc); 1203 return; 1204 } 1205 1206 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1207 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1208 1209 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1210 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1211 1212 if (r1 & RT2661_MGT_DONE) 1213 rt2661_tx_dma_intr(sc, &sc->mgtq); 1214 1215 if (r1 & RT2661_RX_DONE) 1216 rt2661_rx_intr(sc); 1217 1218 if (r1 & RT2661_TX0_DMA_DONE) 1219 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1220 1221 if (r1 & RT2661_TX1_DMA_DONE) 1222 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1223 1224 if (r1 & RT2661_TX2_DMA_DONE) 1225 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1226 1227 if (r1 & RT2661_TX3_DMA_DONE) 1228 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1229 1230 if (r1 & RT2661_TX_DONE) 1231 rt2661_tx_intr(sc); 1232 1233 if (r2 & RT2661_MCU_CMD_DONE) 1234 rt2661_mcu_cmd_intr(sc); 1235 1236 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1237 rt2661_mcu_beacon_expire(sc); 1238 1239 if (r2 & RT2661_MCU_WAKEUP) 1240 rt2661_mcu_wakeup(sc); 1241 1242 /* re-enable MAC and MCU interrupts */ 1243 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1244 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1245 1246 RAL_UNLOCK(sc); 1247} 1248 1249static void 1250rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1251 uint32_t flags, uint16_t xflags, int len, int rate, 1252 const bus_dma_segment_t *segs, int nsegs, int ac) 1253{ 1254 struct ifnet *ifp = sc->sc_ifp; 1255 struct ieee80211com *ic = ifp->if_l2com; 1256 uint16_t plcp_length; 1257 int i, remainder; 1258 1259 desc->flags = htole32(flags); 1260 desc->flags |= htole32(len << 16); 1261 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1262 1263 desc->xflags = htole16(xflags); 1264 desc->xflags |= htole16(nsegs << 13); 1265 1266 desc->wme = htole16( 1267 RT2661_QID(ac) | 1268 RT2661_AIFSN(2) | 1269 RT2661_LOGCWMIN(4) | 1270 RT2661_LOGCWMAX(10)); 1271 1272 /* 1273 * Remember in which queue this frame was sent. This field is driver 1274 * private data only. It will be made available by the NIC in STA_CSR4 1275 * on Tx interrupts. 1276 */ 1277 desc->qid = ac; 1278 1279 /* setup PLCP fields */ 1280 desc->plcp_signal = ieee80211_rate2plcp(rate); 1281 desc->plcp_service = 4; 1282 1283 len += IEEE80211_CRC_LEN; 1284 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 1285 desc->flags |= htole32(RT2661_TX_OFDM); 1286 1287 plcp_length = len & 0xfff; 1288 desc->plcp_length_hi = plcp_length >> 6; 1289 desc->plcp_length_lo = plcp_length & 0x3f; 1290 } else { 1291 plcp_length = (16 * len + rate - 1) / rate; 1292 if (rate == 22) { 1293 remainder = (16 * len) % 22; 1294 if (remainder != 0 && remainder < 7) 1295 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1296 } 1297 desc->plcp_length_hi = plcp_length >> 8; 1298 desc->plcp_length_lo = plcp_length & 0xff; 1299 1300 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1301 desc->plcp_signal |= 0x08; 1302 } 1303 1304 /* RT2x61 supports scatter with up to 5 segments */ 1305 for (i = 0; i < nsegs; i++) { 1306 desc->addr[i] = htole32(segs[i].ds_addr); 1307 desc->len [i] = htole16(segs[i].ds_len); 1308 } 1309} 1310 1311static int 1312rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1313 struct ieee80211_node *ni) 1314{ 1315 struct ieee80211vap *vap = ni->ni_vap; 1316 struct ieee80211com *ic = ni->ni_ic; 1317 struct ifnet *ifp = sc->sc_ifp; 1318 struct rt2661_tx_desc *desc; 1319 struct rt2661_tx_data *data; 1320 struct ieee80211_frame *wh; 1321 struct ieee80211_key *k; 1322 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1323 uint16_t dur; 1324 uint32_t flags = 0; /* XXX HWSEQ */ 1325 int nsegs, rate, error; 1326 1327 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1328 data = &sc->mgtq.data[sc->mgtq.cur]; 1329 1330 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1331 1332 wh = mtod(m0, struct ieee80211_frame *); 1333 1334 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1335 k = ieee80211_crypto_encap(ni, m0); 1336 if (k == NULL) { 1337 m_freem(m0); 1338 return ENOBUFS; 1339 } 1340 } 1341 1342 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1343 segs, &nsegs, 0); 1344 if (error != 0) { 1345 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1346 error); 1347 m_freem(m0); 1348 return error; 1349 } 1350 1351 if (bpf_peers_present(ifp->if_bpf)) { 1352 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1353 1354 tap->wt_flags = 0; 1355 tap->wt_rate = rate; 1356 1357 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1358 } 1359 1360 data->m = m0; 1361 data->ni = ni; 1362 /* management frames are not taken into account for amrr */ 1363 data->rix = IEEE80211_FIXED_RATE_NONE; 1364 1365 wh = mtod(m0, struct ieee80211_frame *); 1366 1367 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1368 flags |= RT2661_TX_NEED_ACK; 1369 1370 dur = ieee80211_ack_duration(sc->sc_rates, 1371 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1372 *(uint16_t *)wh->i_dur = htole16(dur); 1373 1374 /* tell hardware to add timestamp in probe responses */ 1375 if ((wh->i_fc[0] & 1376 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1377 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1378 flags |= RT2661_TX_TIMESTAMP; 1379 } 1380 1381 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1382 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1383 1384 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1385 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1386 BUS_DMASYNC_PREWRITE); 1387 1388 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1389 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1390 1391 /* kick mgt */ 1392 sc->mgtq.queued++; 1393 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1394 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1395 1396 return 0; 1397} 1398 1399static int 1400rt2661_sendprot(struct rt2661_softc *sc, int ac, 1401 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1402{ 1403 struct ieee80211com *ic = ni->ni_ic; 1404 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1405 const struct ieee80211_frame *wh; 1406 struct rt2661_tx_desc *desc; 1407 struct rt2661_tx_data *data; 1408 struct mbuf *mprot; 1409 int protrate, ackrate, pktlen, flags, isshort, error; 1410 uint16_t dur; 1411 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1412 int nsegs; 1413 1414 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1415 ("protection %d", prot)); 1416 1417 wh = mtod(m, const struct ieee80211_frame *); 1418 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1419 1420 protrate = ieee80211_ctl_rate(sc->sc_rates, rate); 1421 ackrate = ieee80211_ack_rate(sc->sc_rates, rate); 1422 1423 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1424 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort) 1425 + ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1426 flags = RT2661_TX_MORE_FRAG; 1427 if (prot == IEEE80211_PROT_RTSCTS) { 1428 /* NB: CTS is the same size as an ACK */ 1429 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1430 flags |= RT2661_TX_NEED_ACK; 1431 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1432 } else { 1433 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1434 } 1435 if (mprot == NULL) { 1436 /* XXX stat + msg */ 1437 return ENOBUFS; 1438 } 1439 1440 data = &txq->data[txq->cur]; 1441 desc = &txq->desc[txq->cur]; 1442 1443 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1444 &nsegs, 0); 1445 if (error != 0) { 1446 device_printf(sc->sc_dev, 1447 "could not map mbuf (error %d)\n", error); 1448 m_freem(mprot); 1449 return error; 1450 } 1451 1452 data->m = mprot; 1453 data->ni = ieee80211_ref_node(ni); 1454 /* ctl frames are not taken into account for amrr */ 1455 data->rix = IEEE80211_FIXED_RATE_NONE; 1456 1457 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1458 protrate, segs, 1, ac); 1459 1460 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1461 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1462 1463 txq->queued++; 1464 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1465 1466 return 0; 1467} 1468 1469static int 1470rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1471 struct ieee80211_node *ni, int ac) 1472{ 1473 struct ieee80211vap *vap = ni->ni_vap; 1474 struct ifnet *ifp = sc->sc_ifp; 1475 struct ieee80211com *ic = ifp->if_l2com; 1476 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1477 struct rt2661_tx_desc *desc; 1478 struct rt2661_tx_data *data; 1479 struct ieee80211_frame *wh; 1480 const struct ieee80211_txparam *tp; 1481 struct ieee80211_key *k; 1482 const struct chanAccParams *cap; 1483 struct mbuf *mnew; 1484 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1485 uint16_t dur; 1486 uint32_t flags; 1487 int error, nsegs, rate, noack = 0; 1488 1489 wh = mtod(m0, struct ieee80211_frame *); 1490 1491 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1492 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1493 rate = tp->mcastrate; 1494 } else if (m0->m_flags & M_EAPOL) { 1495 rate = tp->mgmtrate; 1496 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1497 rate = tp->ucastrate; 1498 } else { 1499 (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr); 1500 rate = ni->ni_txrate; 1501 } 1502 rate &= IEEE80211_RATE_VAL; 1503 1504 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1505 cap = &ic->ic_wme.wme_chanParams; 1506 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1507 } 1508 1509 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1510 k = ieee80211_crypto_encap(ni, m0); 1511 if (k == NULL) { 1512 m_freem(m0); 1513 return ENOBUFS; 1514 } 1515 1516 /* packet header may have moved, reset our local pointer */ 1517 wh = mtod(m0, struct ieee80211_frame *); 1518 } 1519 1520 flags = 0; 1521 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1522 int prot = IEEE80211_PROT_NONE; 1523 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1524 prot = IEEE80211_PROT_RTSCTS; 1525 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1526 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 1527 prot = ic->ic_protmode; 1528 if (prot != IEEE80211_PROT_NONE) { 1529 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1530 if (error) { 1531 m_freem(m0); 1532 return error; 1533 } 1534 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1535 } 1536 } 1537 1538 data = &txq->data[txq->cur]; 1539 desc = &txq->desc[txq->cur]; 1540 1541 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1542 &nsegs, 0); 1543 if (error != 0 && error != EFBIG) { 1544 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1545 error); 1546 m_freem(m0); 1547 return error; 1548 } 1549 if (error != 0) { 1550 mnew = m_defrag(m0, M_DONTWAIT); 1551 if (mnew == NULL) { 1552 device_printf(sc->sc_dev, 1553 "could not defragment mbuf\n"); 1554 m_freem(m0); 1555 return ENOBUFS; 1556 } 1557 m0 = mnew; 1558 1559 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1560 segs, &nsegs, 0); 1561 if (error != 0) { 1562 device_printf(sc->sc_dev, 1563 "could not map mbuf (error %d)\n", error); 1564 m_freem(m0); 1565 return error; 1566 } 1567 1568 /* packet header have moved, reset our local pointer */ 1569 wh = mtod(m0, struct ieee80211_frame *); 1570 } 1571 1572 if (bpf_peers_present(ifp->if_bpf)) { 1573 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1574 1575 tap->wt_flags = 0; 1576 tap->wt_rate = rate; 1577 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1578 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1579 1580 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1581 } 1582 1583 data->m = m0; 1584 data->ni = ni; 1585 1586 /* remember link conditions for rate adaptation algorithm */ 1587 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1588 data->rix = ni->ni_txrate; 1589 /* XXX probably need last rssi value and not avg */ 1590 data->rssi = ic->ic_node_getrssi(ni); 1591 } else 1592 data->rix = IEEE80211_FIXED_RATE_NONE; 1593 1594 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1595 flags |= RT2661_TX_NEED_ACK; 1596 1597 dur = ieee80211_ack_duration(sc->sc_rates, 1598 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1599 *(uint16_t *)wh->i_dur = htole16(dur); 1600 } 1601 1602 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1603 nsegs, ac); 1604 1605 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1606 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1607 1608 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1609 m0->m_pkthdr.len, txq->cur, rate); 1610 1611 /* kick Tx */ 1612 txq->queued++; 1613 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1614 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1615 1616 return 0; 1617} 1618 1619static void 1620rt2661_start_locked(struct ifnet *ifp) 1621{ 1622 struct rt2661_softc *sc = ifp->if_softc; 1623 struct mbuf *m; 1624 struct ieee80211_node *ni; 1625 int ac; 1626 1627 RAL_LOCK_ASSERT(sc); 1628 1629 /* prevent management frames from being sent if we're not ready */ 1630 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) 1631 return; 1632 1633 for (;;) { 1634 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1635 if (m == NULL) 1636 break; 1637 1638 ac = M_WME_GETAC(m); 1639 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1640 /* there is no place left in this ring */ 1641 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1642 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1643 break; 1644 } 1645 1646 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1647 m = ieee80211_encap(ni, m); 1648 if (m == NULL) { 1649 ieee80211_free_node(ni); 1650 ifp->if_oerrors++; 1651 continue; 1652 } 1653 1654 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1655 ieee80211_free_node(ni); 1656 ifp->if_oerrors++; 1657 break; 1658 } 1659 1660 sc->sc_tx_timer = 5; 1661 } 1662} 1663 1664static void 1665rt2661_start(struct ifnet *ifp) 1666{ 1667 struct rt2661_softc *sc = ifp->if_softc; 1668 1669 RAL_LOCK(sc); 1670 rt2661_start_locked(ifp); 1671 RAL_UNLOCK(sc); 1672} 1673 1674static int 1675rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1676 const struct ieee80211_bpf_params *params) 1677{ 1678 struct ieee80211com *ic = ni->ni_ic; 1679 struct ifnet *ifp = ic->ic_ifp; 1680 struct rt2661_softc *sc = ifp->if_softc; 1681 1682 RAL_LOCK(sc); 1683 1684 /* prevent management frames from being sent if we're not ready */ 1685 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1686 RAL_UNLOCK(sc); 1687 m_freem(m); 1688 ieee80211_free_node(ni); 1689 return ENETDOWN; 1690 } 1691 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1692 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1693 RAL_UNLOCK(sc); 1694 m_freem(m); 1695 ieee80211_free_node(ni); 1696 return ENOBUFS; /* XXX */ 1697 } 1698 1699 ifp->if_opackets++; 1700 1701 /* 1702 * Legacy path; interpret frame contents to decide 1703 * precisely how to send the frame. 1704 * XXX raw path 1705 */ 1706 if (rt2661_tx_mgt(sc, m, ni) != 0) 1707 goto bad; 1708 sc->sc_tx_timer = 5; 1709 1710 RAL_UNLOCK(sc); 1711 1712 return 0; 1713bad: 1714 ifp->if_oerrors++; 1715 ieee80211_free_node(ni); 1716 RAL_UNLOCK(sc); 1717 return EIO; /* XXX */ 1718} 1719 1720static void 1721rt2661_watchdog(void *arg) 1722{ 1723 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1724 struct ifnet *ifp = sc->sc_ifp; 1725 1726 RAL_LOCK_ASSERT(sc); 1727 1728 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 1729 1730 if (sc->sc_invalid) /* card ejected */ 1731 return; 1732 1733 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1734 if_printf(ifp, "device timeout\n"); 1735 rt2661_init_locked(sc); 1736 ifp->if_oerrors++; 1737 /* NB: callout is reset in rt2661_init() */ 1738 return; 1739 } 1740 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1741} 1742 1743static int 1744rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1745{ 1746 struct rt2661_softc *sc = ifp->if_softc; 1747 struct ieee80211com *ic = ifp->if_l2com; 1748 struct ifreq *ifr = (struct ifreq *) data; 1749 int error = 0, startall = 0; 1750 1751 switch (cmd) { 1752 case SIOCSIFFLAGS: 1753 RAL_LOCK(sc); 1754 if (ifp->if_flags & IFF_UP) { 1755 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1756 rt2661_init_locked(sc); 1757 startall = 1; 1758 } else 1759 rt2661_update_promisc(ifp); 1760 } else { 1761 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1762 rt2661_stop_locked(sc); 1763 } 1764 RAL_UNLOCK(sc); 1765 if (startall) 1766 ieee80211_start_all(ic); 1767 break; 1768 case SIOCGIFMEDIA: 1769 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1770 break; 1771 case SIOCGIFADDR: 1772 error = ether_ioctl(ifp, cmd, data); 1773 break; 1774 default: 1775 error = EINVAL; 1776 break; 1777 } 1778 return error; 1779} 1780 1781static void 1782rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1783{ 1784 uint32_t tmp; 1785 int ntries; 1786 1787 for (ntries = 0; ntries < 100; ntries++) { 1788 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1789 break; 1790 DELAY(1); 1791 } 1792 if (ntries == 100) { 1793 device_printf(sc->sc_dev, "could not write to BBP\n"); 1794 return; 1795 } 1796 1797 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1798 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1799 1800 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1801} 1802 1803static uint8_t 1804rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1805{ 1806 uint32_t val; 1807 int ntries; 1808 1809 for (ntries = 0; ntries < 100; ntries++) { 1810 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1811 break; 1812 DELAY(1); 1813 } 1814 if (ntries == 100) { 1815 device_printf(sc->sc_dev, "could not read from BBP\n"); 1816 return 0; 1817 } 1818 1819 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1820 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1821 1822 for (ntries = 0; ntries < 100; ntries++) { 1823 val = RAL_READ(sc, RT2661_PHY_CSR3); 1824 if (!(val & RT2661_BBP_BUSY)) 1825 return val & 0xff; 1826 DELAY(1); 1827 } 1828 1829 device_printf(sc->sc_dev, "could not read from BBP\n"); 1830 return 0; 1831} 1832 1833static void 1834rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1835{ 1836 uint32_t tmp; 1837 int ntries; 1838 1839 for (ntries = 0; ntries < 100; ntries++) { 1840 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1841 break; 1842 DELAY(1); 1843 } 1844 if (ntries == 100) { 1845 device_printf(sc->sc_dev, "could not write to RF\n"); 1846 return; 1847 } 1848 1849 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1850 (reg & 3); 1851 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1852 1853 /* remember last written value in sc */ 1854 sc->rf_regs[reg] = val; 1855 1856 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1857} 1858 1859static int 1860rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1861{ 1862 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1863 return EIO; /* there is already a command pending */ 1864 1865 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1866 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1867 1868 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1869 1870 return 0; 1871} 1872 1873static void 1874rt2661_select_antenna(struct rt2661_softc *sc) 1875{ 1876 uint8_t bbp4, bbp77; 1877 uint32_t tmp; 1878 1879 bbp4 = rt2661_bbp_read(sc, 4); 1880 bbp77 = rt2661_bbp_read(sc, 77); 1881 1882 /* TBD */ 1883 1884 /* make sure Rx is disabled before switching antenna */ 1885 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1886 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1887 1888 rt2661_bbp_write(sc, 4, bbp4); 1889 rt2661_bbp_write(sc, 77, bbp77); 1890 1891 /* restore Rx filter */ 1892 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1893} 1894 1895/* 1896 * Enable multi-rate retries for frames sent at OFDM rates. 1897 * In 802.11b/g mode, allow fallback to CCK rates. 1898 */ 1899static void 1900rt2661_enable_mrr(struct rt2661_softc *sc) 1901{ 1902 struct ifnet *ifp = sc->sc_ifp; 1903 struct ieee80211com *ic = ifp->if_l2com; 1904 uint32_t tmp; 1905 1906 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1907 1908 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1909 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1910 tmp |= RT2661_MRR_CCK_FALLBACK; 1911 tmp |= RT2661_MRR_ENABLED; 1912 1913 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1914} 1915 1916static void 1917rt2661_set_txpreamble(struct rt2661_softc *sc) 1918{ 1919 struct ifnet *ifp = sc->sc_ifp; 1920 struct ieee80211com *ic = ifp->if_l2com; 1921 uint32_t tmp; 1922 1923 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1924 1925 tmp &= ~RT2661_SHORT_PREAMBLE; 1926 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1927 tmp |= RT2661_SHORT_PREAMBLE; 1928 1929 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1930} 1931 1932static void 1933rt2661_set_basicrates(struct rt2661_softc *sc, 1934 const struct ieee80211_rateset *rs) 1935{ 1936#define RV(r) ((r) & IEEE80211_RATE_VAL) 1937 struct ifnet *ifp = sc->sc_ifp; 1938 struct ieee80211com *ic = ifp->if_l2com; 1939 uint32_t mask = 0; 1940 uint8_t rate; 1941 int i, j; 1942 1943 for (i = 0; i < rs->rs_nrates; i++) { 1944 rate = rs->rs_rates[i]; 1945 1946 if (!(rate & IEEE80211_RATE_BASIC)) 1947 continue; 1948 1949 /* 1950 * Find h/w rate index. We know it exists because the rate 1951 * set has already been negotiated. 1952 */ 1953 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1954 1955 mask |= 1 << j; 1956 } 1957 1958 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1959 1960 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1961#undef RV 1962} 1963 1964/* 1965 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1966 * driver. 1967 */ 1968static void 1969rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1970{ 1971 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1972 uint32_t tmp; 1973 1974 /* update all BBP registers that depend on the band */ 1975 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1976 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1977 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1978 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1979 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1980 } 1981 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1982 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1983 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1984 } 1985 1986 rt2661_bbp_write(sc, 17, bbp17); 1987 rt2661_bbp_write(sc, 96, bbp96); 1988 rt2661_bbp_write(sc, 104, bbp104); 1989 1990 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1991 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1992 rt2661_bbp_write(sc, 75, 0x80); 1993 rt2661_bbp_write(sc, 86, 0x80); 1994 rt2661_bbp_write(sc, 88, 0x80); 1995 } 1996 1997 rt2661_bbp_write(sc, 35, bbp35); 1998 rt2661_bbp_write(sc, 97, bbp97); 1999 rt2661_bbp_write(sc, 98, bbp98); 2000 2001 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2002 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2003 if (IEEE80211_IS_CHAN_2GHZ(c)) 2004 tmp |= RT2661_PA_PE_2GHZ; 2005 else 2006 tmp |= RT2661_PA_PE_5GHZ; 2007 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2008} 2009 2010static void 2011rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2012{ 2013 struct ifnet *ifp = sc->sc_ifp; 2014 struct ieee80211com *ic = ifp->if_l2com; 2015 const struct rfprog *rfprog; 2016 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2017 int8_t power; 2018 u_int i, chan; 2019 2020 chan = ieee80211_chan2ieee(ic, c); 2021 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2022 2023 sc->sc_rates = ieee80211_get_ratetable(c); 2024 2025 /* select the appropriate RF settings based on what EEPROM says */ 2026 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2027 2028 /* find the settings for this channel (we know it exists) */ 2029 for (i = 0; rfprog[i].chan != chan; i++); 2030 2031 power = sc->txpow[i]; 2032 if (power < 0) { 2033 bbp94 += power; 2034 power = 0; 2035 } else if (power > 31) { 2036 bbp94 += power - 31; 2037 power = 31; 2038 } 2039 2040 /* 2041 * If we are switching from the 2GHz band to the 5GHz band or 2042 * vice-versa, BBP registers need to be reprogrammed. 2043 */ 2044 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2045 rt2661_select_band(sc, c); 2046 rt2661_select_antenna(sc); 2047 } 2048 sc->sc_curchan = c; 2049 2050 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2051 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2052 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2053 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2054 2055 DELAY(200); 2056 2057 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2058 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2059 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2060 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2061 2062 DELAY(200); 2063 2064 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2065 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2066 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2067 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2068 2069 /* enable smart mode for MIMO-capable RFs */ 2070 bbp3 = rt2661_bbp_read(sc, 3); 2071 2072 bbp3 &= ~RT2661_SMART_MODE; 2073 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2074 bbp3 |= RT2661_SMART_MODE; 2075 2076 rt2661_bbp_write(sc, 3, bbp3); 2077 2078 if (bbp94 != RT2661_BBPR94_DEFAULT) 2079 rt2661_bbp_write(sc, 94, bbp94); 2080 2081 /* 5GHz radio needs a 1ms delay here */ 2082 if (IEEE80211_IS_CHAN_5GHZ(c)) 2083 DELAY(1000); 2084} 2085 2086static void 2087rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2088{ 2089 uint32_t tmp; 2090 2091 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2092 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2093 2094 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2095 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2096} 2097 2098static void 2099rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2100{ 2101 uint32_t tmp; 2102 2103 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2104 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2105 2106 tmp = addr[4] | addr[5] << 8; 2107 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2108} 2109 2110static void 2111rt2661_update_promisc(struct ifnet *ifp) 2112{ 2113 struct rt2661_softc *sc = ifp->if_softc; 2114 uint32_t tmp; 2115 2116 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2117 2118 tmp &= ~RT2661_DROP_NOT_TO_ME; 2119 if (!(ifp->if_flags & IFF_PROMISC)) 2120 tmp |= RT2661_DROP_NOT_TO_ME; 2121 2122 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2123 2124 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2125 "entering" : "leaving"); 2126} 2127 2128/* 2129 * Update QoS (802.11e) settings for each h/w Tx ring. 2130 */ 2131static int 2132rt2661_wme_update(struct ieee80211com *ic) 2133{ 2134 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2135 const struct wmeParams *wmep; 2136 2137 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2138 2139 /* XXX: not sure about shifts. */ 2140 /* XXX: the reference driver plays with AC_VI settings too. */ 2141 2142 /* update TxOp */ 2143 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2144 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2145 wmep[WME_AC_BK].wmep_txopLimit); 2146 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2147 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2148 wmep[WME_AC_VO].wmep_txopLimit); 2149 2150 /* update CWmin */ 2151 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2152 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2153 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2154 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2155 wmep[WME_AC_VO].wmep_logcwmin); 2156 2157 /* update CWmax */ 2158 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2159 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2160 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2161 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2162 wmep[WME_AC_VO].wmep_logcwmax); 2163 2164 /* update Aifsn */ 2165 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2166 wmep[WME_AC_BE].wmep_aifsn << 12 | 2167 wmep[WME_AC_BK].wmep_aifsn << 8 | 2168 wmep[WME_AC_VI].wmep_aifsn << 4 | 2169 wmep[WME_AC_VO].wmep_aifsn); 2170 2171 return 0; 2172} 2173 2174static void 2175rt2661_update_slot(struct ifnet *ifp) 2176{ 2177 struct rt2661_softc *sc = ifp->if_softc; 2178 struct ieee80211com *ic = ifp->if_l2com; 2179 uint8_t slottime; 2180 uint32_t tmp; 2181 2182 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2183 2184 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2185 tmp = (tmp & ~0xff) | slottime; 2186 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2187} 2188 2189static const char * 2190rt2661_get_rf(int rev) 2191{ 2192 switch (rev) { 2193 case RT2661_RF_5225: return "RT5225"; 2194 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2195 case RT2661_RF_2527: return "RT2527"; 2196 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2197 default: return "unknown"; 2198 } 2199} 2200 2201static void 2202rt2661_read_eeprom(struct rt2661_softc *sc, struct ieee80211com *ic) 2203{ 2204 uint16_t val; 2205 int i; 2206 2207 /* read MAC address */ 2208 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2209 ic->ic_myaddr[0] = val & 0xff; 2210 ic->ic_myaddr[1] = val >> 8; 2211 2212 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2213 ic->ic_myaddr[2] = val & 0xff; 2214 ic->ic_myaddr[3] = val >> 8; 2215 2216 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2217 ic->ic_myaddr[4] = val & 0xff; 2218 ic->ic_myaddr[5] = val >> 8; 2219 2220 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2221 /* XXX: test if different from 0xffff? */ 2222 sc->rf_rev = (val >> 11) & 0x1f; 2223 sc->hw_radio = (val >> 10) & 0x1; 2224 sc->rx_ant = (val >> 4) & 0x3; 2225 sc->tx_ant = (val >> 2) & 0x3; 2226 sc->nb_ant = val & 0x3; 2227 2228 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2229 2230 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2231 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2232 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2233 2234 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2235 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2236 2237 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2238 if ((val & 0xff) != 0xff) 2239 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2240 2241 /* Only [-10, 10] is valid */ 2242 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2243 sc->rssi_2ghz_corr = 0; 2244 2245 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2246 if ((val & 0xff) != 0xff) 2247 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2248 2249 /* Only [-10, 10] is valid */ 2250 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2251 sc->rssi_5ghz_corr = 0; 2252 2253 /* adjust RSSI correction for external low-noise amplifier */ 2254 if (sc->ext_2ghz_lna) 2255 sc->rssi_2ghz_corr -= 14; 2256 if (sc->ext_5ghz_lna) 2257 sc->rssi_5ghz_corr -= 14; 2258 2259 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2260 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2261 2262 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2263 if ((val >> 8) != 0xff) 2264 sc->rfprog = (val >> 8) & 0x3; 2265 if ((val & 0xff) != 0xff) 2266 sc->rffreq = val & 0xff; 2267 2268 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2269 2270 /* read Tx power for all a/b/g channels */ 2271 for (i = 0; i < 19; i++) { 2272 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2273 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2274 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2275 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2276 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2277 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2278 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2279 } 2280 2281 /* read vendor-specific BBP values */ 2282 for (i = 0; i < 16; i++) { 2283 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2284 if (val == 0 || val == 0xffff) 2285 continue; /* skip invalid entries */ 2286 sc->bbp_prom[i].reg = val >> 8; 2287 sc->bbp_prom[i].val = val & 0xff; 2288 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2289 sc->bbp_prom[i].val); 2290 } 2291} 2292 2293static int 2294rt2661_bbp_init(struct rt2661_softc *sc) 2295{ 2296#define N(a) (sizeof (a) / sizeof ((a)[0])) 2297 int i, ntries; 2298 uint8_t val; 2299 2300 /* wait for BBP to be ready */ 2301 for (ntries = 0; ntries < 100; ntries++) { 2302 val = rt2661_bbp_read(sc, 0); 2303 if (val != 0 && val != 0xff) 2304 break; 2305 DELAY(100); 2306 } 2307 if (ntries == 100) { 2308 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2309 return EIO; 2310 } 2311 2312 /* initialize BBP registers to default values */ 2313 for (i = 0; i < N(rt2661_def_bbp); i++) { 2314 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2315 rt2661_def_bbp[i].val); 2316 } 2317 2318 /* write vendor-specific BBP values (from EEPROM) */ 2319 for (i = 0; i < 16; i++) { 2320 if (sc->bbp_prom[i].reg == 0) 2321 continue; 2322 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2323 } 2324 2325 return 0; 2326#undef N 2327} 2328 2329static void 2330rt2661_init_locked(struct rt2661_softc *sc) 2331{ 2332#define N(a) (sizeof (a) / sizeof ((a)[0])) 2333 struct ifnet *ifp = sc->sc_ifp; 2334 struct ieee80211com *ic = ifp->if_l2com; 2335 uint32_t tmp, sta[3]; 2336 int i, error, ntries; 2337 2338 RAL_LOCK_ASSERT(sc); 2339 2340 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2341 error = rt2661_load_microcode(sc); 2342 if (error != 0) { 2343 if_printf(ifp, 2344 "%s: could not load 8051 microcode, error %d\n", 2345 __func__, error); 2346 return; 2347 } 2348 sc->sc_flags |= RAL_FW_LOADED; 2349 } 2350 2351 rt2661_stop_locked(sc); 2352 2353 /* initialize Tx rings */ 2354 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2355 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2356 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2357 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2358 2359 /* initialize Mgt ring */ 2360 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2361 2362 /* initialize Rx ring */ 2363 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2364 2365 /* initialize Tx rings sizes */ 2366 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2367 RT2661_TX_RING_COUNT << 24 | 2368 RT2661_TX_RING_COUNT << 16 | 2369 RT2661_TX_RING_COUNT << 8 | 2370 RT2661_TX_RING_COUNT); 2371 2372 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2373 RT2661_TX_DESC_WSIZE << 16 | 2374 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2375 RT2661_MGT_RING_COUNT); 2376 2377 /* initialize Rx rings */ 2378 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2379 RT2661_RX_DESC_BACK << 16 | 2380 RT2661_RX_DESC_WSIZE << 8 | 2381 RT2661_RX_RING_COUNT); 2382 2383 /* XXX: some magic here */ 2384 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2385 2386 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2387 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2388 2389 /* load base address of Rx ring */ 2390 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2391 2392 /* initialize MAC registers to default values */ 2393 for (i = 0; i < N(rt2661_def_mac); i++) 2394 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2395 2396 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2397 rt2661_set_macaddr(sc, ic->ic_myaddr); 2398 2399 /* set host ready */ 2400 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2401 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2402 2403 /* wait for BBP/RF to wakeup */ 2404 for (ntries = 0; ntries < 1000; ntries++) { 2405 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2406 break; 2407 DELAY(1000); 2408 } 2409 if (ntries == 1000) { 2410 printf("timeout waiting for BBP/RF to wakeup\n"); 2411 rt2661_stop_locked(sc); 2412 return; 2413 } 2414 2415 if (rt2661_bbp_init(sc) != 0) { 2416 rt2661_stop_locked(sc); 2417 return; 2418 } 2419 2420 /* select default channel */ 2421 sc->sc_curchan = ic->ic_curchan; 2422 rt2661_select_band(sc, sc->sc_curchan); 2423 rt2661_select_antenna(sc); 2424 rt2661_set_chan(sc, sc->sc_curchan); 2425 2426 /* update Rx filter */ 2427 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2428 2429 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2430 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2431 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2432 RT2661_DROP_ACKCTS; 2433 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2434 tmp |= RT2661_DROP_TODS; 2435 if (!(ifp->if_flags & IFF_PROMISC)) 2436 tmp |= RT2661_DROP_NOT_TO_ME; 2437 } 2438 2439 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2440 2441 /* clear STA registers */ 2442 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2443 2444 /* initialize ASIC */ 2445 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2446 2447 /* clear any pending interrupt */ 2448 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2449 2450 /* enable interrupts */ 2451 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2452 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2453 2454 /* kick Rx */ 2455 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2456 2457 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2458 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2459 2460 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2461#undef N 2462} 2463 2464static void 2465rt2661_init(void *priv) 2466{ 2467 struct rt2661_softc *sc = priv; 2468 struct ifnet *ifp = sc->sc_ifp; 2469 struct ieee80211com *ic = ifp->if_l2com; 2470 2471 RAL_LOCK(sc); 2472 rt2661_init_locked(sc); 2473 RAL_UNLOCK(sc); 2474 2475 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2476 ieee80211_start_all(ic); /* start all vap's */ 2477} 2478 2479void 2480rt2661_stop_locked(struct rt2661_softc *sc) 2481{ 2482 struct ifnet *ifp = sc->sc_ifp; 2483 uint32_t tmp; 2484 volatile int *flags = &sc->sc_flags; 2485 2486 while (*flags & RAL_INPUT_RUNNING) 2487 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2488 2489 callout_stop(&sc->watchdog_ch); 2490 sc->sc_tx_timer = 0; 2491 2492 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2493 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2494 2495 /* abort Tx (for all 5 Tx rings) */ 2496 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2497 2498 /* disable Rx (value remains after reset!) */ 2499 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2500 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2501 2502 /* reset ASIC */ 2503 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2504 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2505 2506 /* disable interrupts */ 2507 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2508 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2509 2510 /* clear any pending interrupt */ 2511 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2512 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2513 2514 /* reset Tx and Rx rings */ 2515 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2516 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2517 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2518 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2519 rt2661_reset_tx_ring(sc, &sc->mgtq); 2520 rt2661_reset_rx_ring(sc, &sc->rxq); 2521 } 2522} 2523 2524void 2525rt2661_stop(void *priv) 2526{ 2527 struct rt2661_softc *sc = priv; 2528 2529 RAL_LOCK(sc); 2530 rt2661_stop_locked(sc); 2531 RAL_UNLOCK(sc); 2532} 2533 2534static int 2535rt2661_load_microcode(struct rt2661_softc *sc) 2536{ 2537 struct ifnet *ifp = sc->sc_ifp; 2538 const struct firmware *fp; 2539 const char *imagename; 2540 int ntries, error; 2541 2542 RAL_LOCK_ASSERT(sc); 2543 2544 switch (sc->sc_id) { 2545 case 0x0301: imagename = "rt2561sfw"; break; 2546 case 0x0302: imagename = "rt2561fw"; break; 2547 case 0x0401: imagename = "rt2661fw"; break; 2548 default: 2549 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2550 "don't know how to retrieve firmware\n", 2551 __func__, sc->sc_id); 2552 return EINVAL; 2553 } 2554 RAL_UNLOCK(sc); 2555 fp = firmware_get(imagename); 2556 RAL_LOCK(sc); 2557 if (fp == NULL) { 2558 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2559 __func__, imagename); 2560 return EINVAL; 2561 } 2562 2563 /* 2564 * Load 8051 microcode into NIC. 2565 */ 2566 /* reset 8051 */ 2567 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2568 2569 /* cancel any pending Host to MCU command */ 2570 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2571 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2572 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2573 2574 /* write 8051's microcode */ 2575 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2576 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2577 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2578 2579 /* kick 8051's ass */ 2580 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2581 2582 /* wait for 8051 to initialize */ 2583 for (ntries = 0; ntries < 500; ntries++) { 2584 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2585 break; 2586 DELAY(100); 2587 } 2588 if (ntries == 500) { 2589 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2590 __func__); 2591 error = EIO; 2592 } else 2593 error = 0; 2594 2595 firmware_put(fp, FIRMWARE_UNLOAD); 2596 return error; 2597} 2598 2599#ifdef notyet 2600/* 2601 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2602 * false CCA count. This function is called periodically (every seconds) when 2603 * in the RUN state. Values taken from the reference driver. 2604 */ 2605static void 2606rt2661_rx_tune(struct rt2661_softc *sc) 2607{ 2608 uint8_t bbp17; 2609 uint16_t cca; 2610 int lo, hi, dbm; 2611 2612 /* 2613 * Tuning range depends on operating band and on the presence of an 2614 * external low-noise amplifier. 2615 */ 2616 lo = 0x20; 2617 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2618 lo += 0x08; 2619 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2620 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2621 lo += 0x10; 2622 hi = lo + 0x20; 2623 2624 /* retrieve false CCA count since last call (clear on read) */ 2625 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2626 2627 if (dbm >= -35) { 2628 bbp17 = 0x60; 2629 } else if (dbm >= -58) { 2630 bbp17 = hi; 2631 } else if (dbm >= -66) { 2632 bbp17 = lo + 0x10; 2633 } else if (dbm >= -74) { 2634 bbp17 = lo + 0x08; 2635 } else { 2636 /* RSSI < -74dBm, tune using false CCA count */ 2637 2638 bbp17 = sc->bbp17; /* current value */ 2639 2640 hi -= 2 * (-74 - dbm); 2641 if (hi < lo) 2642 hi = lo; 2643 2644 if (bbp17 > hi) { 2645 bbp17 = hi; 2646 2647 } else if (cca > 512) { 2648 if (++bbp17 > hi) 2649 bbp17 = hi; 2650 } else if (cca < 100) { 2651 if (--bbp17 < lo) 2652 bbp17 = lo; 2653 } 2654 } 2655 2656 if (bbp17 != sc->bbp17) { 2657 rt2661_bbp_write(sc, 17, bbp17); 2658 sc->bbp17 = bbp17; 2659 } 2660} 2661 2662/* 2663 * Enter/Leave radar detection mode. 2664 * This is for 802.11h additional regulatory domains. 2665 */ 2666static void 2667rt2661_radar_start(struct rt2661_softc *sc) 2668{ 2669 uint32_t tmp; 2670 2671 /* disable Rx */ 2672 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2673 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2674 2675 rt2661_bbp_write(sc, 82, 0x20); 2676 rt2661_bbp_write(sc, 83, 0x00); 2677 rt2661_bbp_write(sc, 84, 0x40); 2678 2679 /* save current BBP registers values */ 2680 sc->bbp18 = rt2661_bbp_read(sc, 18); 2681 sc->bbp21 = rt2661_bbp_read(sc, 21); 2682 sc->bbp22 = rt2661_bbp_read(sc, 22); 2683 sc->bbp16 = rt2661_bbp_read(sc, 16); 2684 sc->bbp17 = rt2661_bbp_read(sc, 17); 2685 sc->bbp64 = rt2661_bbp_read(sc, 64); 2686 2687 rt2661_bbp_write(sc, 18, 0xff); 2688 rt2661_bbp_write(sc, 21, 0x3f); 2689 rt2661_bbp_write(sc, 22, 0x3f); 2690 rt2661_bbp_write(sc, 16, 0xbd); 2691 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2692 rt2661_bbp_write(sc, 64, 0x21); 2693 2694 /* restore Rx filter */ 2695 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2696} 2697 2698static int 2699rt2661_radar_stop(struct rt2661_softc *sc) 2700{ 2701 uint8_t bbp66; 2702 2703 /* read radar detection result */ 2704 bbp66 = rt2661_bbp_read(sc, 66); 2705 2706 /* restore BBP registers values */ 2707 rt2661_bbp_write(sc, 16, sc->bbp16); 2708 rt2661_bbp_write(sc, 17, sc->bbp17); 2709 rt2661_bbp_write(sc, 18, sc->bbp18); 2710 rt2661_bbp_write(sc, 21, sc->bbp21); 2711 rt2661_bbp_write(sc, 22, sc->bbp22); 2712 rt2661_bbp_write(sc, 64, sc->bbp64); 2713 2714 return bbp66 == 1; 2715} 2716#endif 2717 2718static int 2719rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2720{ 2721 struct ieee80211com *ic = vap->iv_ic; 2722 struct ieee80211_beacon_offsets bo; 2723 struct rt2661_tx_desc desc; 2724 struct mbuf *m0; 2725 int rate; 2726 2727 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2728 if (m0 == NULL) { 2729 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2730 return ENOBUFS; 2731 } 2732 2733 /* send beacons at the lowest available rate */ 2734 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2735 2736 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2737 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2738 2739 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2740 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2741 2742 /* copy beacon header and payload into NIC memory */ 2743 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2744 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2745 2746 m_freem(m0); 2747 2748 return 0; 2749} 2750 2751/* 2752 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2753 * and HostAP operating modes. 2754 */ 2755static void 2756rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2757{ 2758 struct ifnet *ifp = sc->sc_ifp; 2759 struct ieee80211com *ic = ifp->if_l2com; 2760 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2761 uint32_t tmp; 2762 2763 if (vap->iv_opmode != IEEE80211_M_STA) { 2764 /* 2765 * Change default 16ms TBTT adjustment to 8ms. 2766 * Must be done before enabling beacon generation. 2767 */ 2768 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2769 } 2770 2771 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2772 2773 /* set beacon interval (in 1/16ms unit) */ 2774 tmp |= vap->iv_bss->ni_intval * 16; 2775 2776 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2777 if (vap->iv_opmode == IEEE80211_M_STA) 2778 tmp |= RT2661_TSF_MODE(1); 2779 else 2780 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2781 2782 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2783} 2784 2785/* 2786 * Retrieve the "Received Signal Strength Indicator" from the raw values 2787 * contained in Rx descriptors. The computation depends on which band the 2788 * frame was received. Correction values taken from the reference driver. 2789 */ 2790static int 2791rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2792{ 2793 int lna, agc, rssi; 2794 2795 lna = (raw >> 5) & 0x3; 2796 agc = raw & 0x1f; 2797 2798 if (lna == 0) { 2799 /* 2800 * No mapping available. 2801 * 2802 * NB: Since RSSI is relative to noise floor, -1 is 2803 * adequate for caller to know error happened. 2804 */ 2805 return -1; 2806 } 2807 2808 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2809 2810 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2811 rssi += sc->rssi_2ghz_corr; 2812 2813 if (lna == 1) 2814 rssi -= 64; 2815 else if (lna == 2) 2816 rssi -= 74; 2817 else if (lna == 3) 2818 rssi -= 90; 2819 } else { 2820 rssi += sc->rssi_5ghz_corr; 2821 2822 if (lna == 1) 2823 rssi -= 64; 2824 else if (lna == 2) 2825 rssi -= 86; 2826 else if (lna == 3) 2827 rssi -= 100; 2828 } 2829 return rssi; 2830} 2831 2832static void 2833rt2661_scan_start(struct ieee80211com *ic) 2834{ 2835 struct ifnet *ifp = ic->ic_ifp; 2836 struct rt2661_softc *sc = ifp->if_softc; 2837 uint32_t tmp; 2838 2839 /* abort TSF synchronization */ 2840 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2841 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2842 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2843} 2844 2845static void 2846rt2661_scan_end(struct ieee80211com *ic) 2847{ 2848 struct ifnet *ifp = ic->ic_ifp; 2849 struct rt2661_softc *sc = ifp->if_softc; 2850 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2851 2852 rt2661_enable_tsf_sync(sc); 2853 /* XXX keep local copy */ 2854 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2855} 2856 2857static void 2858rt2661_set_channel(struct ieee80211com *ic) 2859{ 2860 struct ifnet *ifp = ic->ic_ifp; 2861 struct rt2661_softc *sc = ifp->if_softc; 2862 2863 RAL_LOCK(sc); 2864 rt2661_set_chan(sc, ic->ic_curchan); 2865 2866 sc->sc_txtap.wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2867 sc->sc_txtap.wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2868 sc->sc_rxtap.wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2869 sc->sc_rxtap.wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2870 RAL_UNLOCK(sc); 2871 2872} 2873