rt2661.c revision 165352
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 165352 2006-12-19 17:37:41Z bms $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 165352 2006-12-19 17:37:41Z bms $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <sys/rman.h> 45 46#include <net/bpf.h> 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/ethernet.h> 50#include <net/if_dl.h> 51#include <net/if_media.h> 52#include <net/if_types.h> 53 54#include <net80211/ieee80211_var.h> 55#include <net80211/ieee80211_radiotap.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62 63#include <dev/ral/if_ralrate.h> 64#include <dev/ral/rt2661reg.h> 65#include <dev/ral/rt2661var.h> 66#include <dev/ral/rt2661_ucode.h> 67 68#ifdef RAL_DEBUG 69#define DPRINTF(x) do { if (ral_debug > 0) printf x; } while (0) 70#define DPRINTFN(n, x) do { if (ral_debug >= (n)) printf x; } while (0) 71int ral_debug = 0; 72SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level"); 73#else 74#define DPRINTF(x) 75#define DPRINTFN(n, x) 76#endif 77 78static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 79 int); 80static int rt2661_alloc_tx_ring(struct rt2661_softc *, 81 struct rt2661_tx_ring *, int); 82static void rt2661_reset_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *); 84static void rt2661_free_tx_ring(struct rt2661_softc *, 85 struct rt2661_tx_ring *); 86static int rt2661_alloc_rx_ring(struct rt2661_softc *, 87 struct rt2661_rx_ring *, int); 88static void rt2661_reset_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *); 90static void rt2661_free_rx_ring(struct rt2661_softc *, 91 struct rt2661_rx_ring *); 92static struct ieee80211_node *rt2661_node_alloc( 93 struct ieee80211_node_table *); 94static int rt2661_media_change(struct ifnet *); 95static void rt2661_next_scan(void *); 96static int rt2661_newstate(struct ieee80211com *, 97 enum ieee80211_state, int); 98static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 99static void rt2661_rx_intr(struct rt2661_softc *); 100static void rt2661_tx_intr(struct rt2661_softc *); 101static void rt2661_tx_dma_intr(struct rt2661_softc *, 102 struct rt2661_tx_ring *); 103static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 104static void rt2661_mcu_wakeup(struct rt2661_softc *); 105static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 106static int rt2661_ack_rate(struct ieee80211com *, int); 107static uint16_t rt2661_txtime(int, int, uint32_t); 108static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 109static uint8_t rt2661_plcp_signal(int); 110static void rt2661_setup_tx_desc(struct rt2661_softc *, 111 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 112 int, const bus_dma_segment_t *, int, int); 113static struct mbuf * rt2661_get_rts(struct rt2661_softc *, 114 struct ieee80211_frame *, uint16_t); 115static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 116 struct ieee80211_node *, int); 117static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 118 struct ieee80211_node *); 119static void rt2661_start(struct ifnet *); 120static void rt2661_watchdog(void *); 121static int rt2661_reset(struct ifnet *); 122static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 123static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 124 uint8_t); 125static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 126static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 127 uint32_t); 128static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 129 uint16_t); 130static void rt2661_select_antenna(struct rt2661_softc *); 131static void rt2661_enable_mrr(struct rt2661_softc *); 132static void rt2661_set_txpreamble(struct rt2661_softc *); 133static void rt2661_set_basicrates(struct rt2661_softc *, 134 const struct ieee80211_rateset *); 135static void rt2661_select_band(struct rt2661_softc *, 136 struct ieee80211_channel *); 137static void rt2661_set_chan(struct rt2661_softc *, 138 struct ieee80211_channel *); 139static void rt2661_set_bssid(struct rt2661_softc *, 140 const uint8_t *); 141static void rt2661_set_macaddr(struct rt2661_softc *, 142 const uint8_t *); 143static void rt2661_update_promisc(struct rt2661_softc *); 144static int rt2661_wme_update(struct ieee80211com *) __unused; 145static void rt2661_update_slot(struct ifnet *); 146static const char *rt2661_get_rf(int); 147static void rt2661_read_eeprom(struct rt2661_softc *); 148static int rt2661_bbp_init(struct rt2661_softc *); 149static void rt2661_init(void *); 150static void rt2661_stop(void *); 151static int rt2661_load_microcode(struct rt2661_softc *, 152 const uint8_t *, int); 153#ifdef notyet 154static void rt2661_rx_tune(struct rt2661_softc *); 155static void rt2661_radar_start(struct rt2661_softc *); 156static int rt2661_radar_stop(struct rt2661_softc *); 157#endif 158static int rt2661_prepare_beacon(struct rt2661_softc *); 159static void rt2661_enable_tsf_sync(struct rt2661_softc *); 160static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 161 162/* 163 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 164 */ 165static const struct ieee80211_rateset rt2661_rateset_11a = 166 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 167 168static const struct ieee80211_rateset rt2661_rateset_11b = 169 { 4, { 2, 4, 11, 22 } }; 170 171static const struct ieee80211_rateset rt2661_rateset_11g = 172 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 173 174static const struct { 175 uint32_t reg; 176 uint32_t val; 177} rt2661_def_mac[] = { 178 RT2661_DEF_MAC 179}; 180 181static const struct { 182 uint8_t reg; 183 uint8_t val; 184} rt2661_def_bbp[] = { 185 RT2661_DEF_BBP 186}; 187 188static const struct rfprog { 189 uint8_t chan; 190 uint32_t r1, r2, r3, r4; 191} rt2661_rf5225_1[] = { 192 RT2661_RF5225_1 193}, rt2661_rf5225_2[] = { 194 RT2661_RF5225_2 195}; 196 197int 198rt2661_attach(device_t dev, int id) 199{ 200 struct rt2661_softc *sc = device_get_softc(dev); 201 struct ieee80211com *ic = &sc->sc_ic; 202 struct ifnet *ifp; 203 uint32_t val; 204 const uint8_t *ucode = NULL; 205 int error, i, ac, ntries, size = 0; 206 207 sc->sc_dev = dev; 208 209 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 210 MTX_DEF | MTX_RECURSE); 211 212 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 213 callout_init(&sc->scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 214 callout_init(&sc->rssadapt_ch, CALLOUT_MPSAFE); 215 216 /* wait for NIC to initialize */ 217 for (ntries = 0; ntries < 1000; ntries++) { 218 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 219 break; 220 DELAY(1000); 221 } 222 if (ntries == 1000) { 223 device_printf(sc->sc_dev, 224 "timeout waiting for NIC to initialize\n"); 225 error = EIO; 226 goto fail1; 227 } 228 229 /* retrieve RF rev. no and various other things from EEPROM */ 230 rt2661_read_eeprom(sc); 231 232 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 233 rt2661_get_rf(sc->rf_rev)); 234 235 /* 236 * Load 8051 microcode into NIC. 237 */ 238 switch (id) { 239 case 0x0301: 240 ucode = rt2561s_ucode; 241 size = sizeof rt2561s_ucode; 242 break; 243 case 0x0302: 244 ucode = rt2561_ucode; 245 size = sizeof rt2561_ucode; 246 break; 247 case 0x0401: 248 ucode = rt2661_ucode; 249 size = sizeof rt2661_ucode; 250 break; 251 } 252 253 error = rt2661_load_microcode(sc, ucode, size); 254 if (error != 0) { 255 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 256 goto fail1; 257 } 258 259 /* 260 * Allocate Tx and Rx rings. 261 */ 262 for (ac = 0; ac < 4; ac++) { 263 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 264 RT2661_TX_RING_COUNT); 265 if (error != 0) { 266 device_printf(sc->sc_dev, 267 "could not allocate Tx ring %d\n", ac); 268 goto fail2; 269 } 270 } 271 272 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 273 if (error != 0) { 274 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 275 goto fail2; 276 } 277 278 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 279 if (error != 0) { 280 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 281 goto fail3; 282 } 283 284 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 285 if (ifp == NULL) { 286 device_printf(sc->sc_dev, "can not if_alloc()\n"); 287 error = ENOMEM; 288 goto fail4; 289 } 290 291 ifp->if_softc = sc; 292 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 293 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 294 ifp->if_init = rt2661_init; 295 ifp->if_ioctl = rt2661_ioctl; 296 ifp->if_start = rt2661_start; 297 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 298 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 299 IFQ_SET_READY(&ifp->if_snd); 300 301 ic->ic_ifp = ifp; 302 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 303 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 304 ic->ic_state = IEEE80211_S_INIT; 305 306 /* set device capabilities */ 307 ic->ic_caps = 308 IEEE80211_C_IBSS | /* IBSS mode supported */ 309 IEEE80211_C_MONITOR | /* monitor mode supported */ 310 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 311 IEEE80211_C_TXPMGT | /* tx power management */ 312 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 313 IEEE80211_C_SHSLOT | /* short slot time supported */ 314#ifdef notyet 315 IEEE80211_C_WME | /* 802.11e */ 316#endif 317 IEEE80211_C_WPA; /* 802.11i */ 318 319 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 320 /* set supported .11a rates */ 321 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 322 323 /* set supported .11a channels */ 324 for (i = 36; i <= 64; i += 4) { 325 ic->ic_channels[i].ic_freq = 326 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 327 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 328 } 329 for (i = 100; i <= 140; i += 4) { 330 ic->ic_channels[i].ic_freq = 331 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 332 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 333 } 334 for (i = 149; i <= 165; i += 4) { 335 ic->ic_channels[i].ic_freq = 336 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 337 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 338 } 339 } 340 341 /* set supported .11b and .11g rates */ 342 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 343 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 344 345 /* set supported .11b and .11g channels (1 through 14) */ 346 for (i = 1; i <= 14; i++) { 347 ic->ic_channels[i].ic_freq = 348 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 349 ic->ic_channels[i].ic_flags = 350 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 351 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 352 } 353 354 ieee80211_ifattach(ic); 355 ic->ic_node_alloc = rt2661_node_alloc; 356/* ic->ic_wme.wme_update = rt2661_wme_update;*/ 357 ic->ic_updateslot = rt2661_update_slot; 358 ic->ic_reset = rt2661_reset; 359 /* enable s/w bmiss handling in sta mode */ 360 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; 361 362 /* override state transition machine */ 363 sc->sc_newstate = ic->ic_newstate; 364 ic->ic_newstate = rt2661_newstate; 365 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 366 367 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 368 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 369 370 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 371 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 372 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 373 374 sc->sc_txtap_len = sizeof sc->sc_txtapu; 375 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 376 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 377 378 /* 379 * Add a few sysctl knobs. 380 */ 381 sc->dwelltime = 200; 382 383 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 384 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 385 CTLFLAG_RW, &sc->dwelltime, 0, 386 "channel dwell time (ms) for AP/station scanning"); 387 388 if (bootverbose) 389 ieee80211_announce(ic); 390 391 return 0; 392 393fail4: rt2661_free_rx_ring(sc, &sc->rxq); 394fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 395fail2: while (--ac >= 0) 396 rt2661_free_tx_ring(sc, &sc->txq[ac]); 397fail1: mtx_destroy(&sc->sc_mtx); 398 399 return error; 400} 401 402int 403rt2661_detach(void *xsc) 404{ 405 struct rt2661_softc *sc = xsc; 406 struct ieee80211com *ic = &sc->sc_ic; 407 struct ifnet *ifp = ic->ic_ifp; 408 409 rt2661_stop(sc); 410 callout_stop(&sc->watchdog_ch); 411 callout_stop(&sc->scan_ch); 412 callout_stop(&sc->rssadapt_ch); 413 414 bpfdetach(ifp); 415 ieee80211_ifdetach(ic); 416 417 rt2661_free_tx_ring(sc, &sc->txq[0]); 418 rt2661_free_tx_ring(sc, &sc->txq[1]); 419 rt2661_free_tx_ring(sc, &sc->txq[2]); 420 rt2661_free_tx_ring(sc, &sc->txq[3]); 421 rt2661_free_tx_ring(sc, &sc->mgtq); 422 rt2661_free_rx_ring(sc, &sc->rxq); 423 424 if_free(ifp); 425 426 mtx_destroy(&sc->sc_mtx); 427 428 return 0; 429} 430 431void 432rt2661_shutdown(void *xsc) 433{ 434 struct rt2661_softc *sc = xsc; 435 436 rt2661_stop(sc); 437} 438 439void 440rt2661_suspend(void *xsc) 441{ 442 struct rt2661_softc *sc = xsc; 443 444 rt2661_stop(sc); 445} 446 447void 448rt2661_resume(void *xsc) 449{ 450 struct rt2661_softc *sc = xsc; 451 struct ifnet *ifp = sc->sc_ic.ic_ifp; 452 453 if (ifp->if_flags & IFF_UP) { 454 ifp->if_init(ifp->if_softc); 455 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 456 ifp->if_start(ifp); 457 } 458} 459 460static void 461rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 462{ 463 if (error != 0) 464 return; 465 466 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 467 468 *(bus_addr_t *)arg = segs[0].ds_addr; 469} 470 471static int 472rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 473 int count) 474{ 475 int i, error; 476 477 ring->count = count; 478 ring->queued = 0; 479 ring->cur = ring->next = ring->stat = 0; 480 481 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 482 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1, 483 count * RT2661_TX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); 484 if (error != 0) { 485 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 486 goto fail; 487 } 488 489 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 490 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 491 if (error != 0) { 492 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 493 goto fail; 494 } 495 496 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 497 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 498 0); 499 if (error != 0) { 500 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 501 goto fail; 502 } 503 504 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 505 M_NOWAIT | M_ZERO); 506 if (ring->data == NULL) { 507 device_printf(sc->sc_dev, "could not allocate soft data\n"); 508 error = ENOMEM; 509 goto fail; 510 } 511 512 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 513 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, RT2661_MAX_SCATTER, 514 MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 517 goto fail; 518 } 519 520 for (i = 0; i < count; i++) { 521 error = bus_dmamap_create(ring->data_dmat, 0, 522 &ring->data[i].map); 523 if (error != 0) { 524 device_printf(sc->sc_dev, "could not create DMA map\n"); 525 goto fail; 526 } 527 } 528 529 return 0; 530 531fail: rt2661_free_tx_ring(sc, ring); 532 return error; 533} 534 535static void 536rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 537{ 538 struct rt2661_tx_desc *desc; 539 struct rt2661_tx_data *data; 540 int i; 541 542 for (i = 0; i < ring->count; i++) { 543 desc = &ring->desc[i]; 544 data = &ring->data[i]; 545 546 if (data->m != NULL) { 547 bus_dmamap_sync(ring->data_dmat, data->map, 548 BUS_DMASYNC_POSTWRITE); 549 bus_dmamap_unload(ring->data_dmat, data->map); 550 m_freem(data->m); 551 data->m = NULL; 552 } 553 554 if (data->ni != NULL) { 555 ieee80211_free_node(data->ni); 556 data->ni = NULL; 557 } 558 559 desc->flags = 0; 560 } 561 562 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 563 564 ring->queued = 0; 565 ring->cur = ring->next = ring->stat = 0; 566} 567 568static void 569rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 570{ 571 struct rt2661_tx_data *data; 572 int i; 573 574 if (ring->desc != NULL) { 575 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 576 BUS_DMASYNC_POSTWRITE); 577 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 578 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 579 } 580 581 if (ring->desc_dmat != NULL) 582 bus_dma_tag_destroy(ring->desc_dmat); 583 584 if (ring->data != NULL) { 585 for (i = 0; i < ring->count; i++) { 586 data = &ring->data[i]; 587 588 if (data->m != NULL) { 589 bus_dmamap_sync(ring->data_dmat, data->map, 590 BUS_DMASYNC_POSTWRITE); 591 bus_dmamap_unload(ring->data_dmat, data->map); 592 m_freem(data->m); 593 } 594 595 if (data->ni != NULL) 596 ieee80211_free_node(data->ni); 597 598 if (data->map != NULL) 599 bus_dmamap_destroy(ring->data_dmat, data->map); 600 } 601 602 free(ring->data, M_DEVBUF); 603 } 604 605 if (ring->data_dmat != NULL) 606 bus_dma_tag_destroy(ring->data_dmat); 607} 608 609static int 610rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 611 int count) 612{ 613 struct rt2661_rx_desc *desc; 614 struct rt2661_rx_data *data; 615 bus_addr_t physaddr; 616 int i, error; 617 618 ring->count = count; 619 ring->cur = ring->next = 0; 620 621 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 622 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1, 623 count * RT2661_RX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); 624 if (error != 0) { 625 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 630 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 631 if (error != 0) { 632 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 633 goto fail; 634 } 635 636 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 637 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 638 0); 639 if (error != 0) { 640 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 641 goto fail; 642 } 643 644 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 645 M_NOWAIT | M_ZERO); 646 if (ring->data == NULL) { 647 device_printf(sc->sc_dev, "could not allocate soft data\n"); 648 error = ENOMEM; 649 goto fail; 650 } 651 652 /* 653 * Pre-allocate Rx buffers and populate Rx ring. 654 */ 655 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 656 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 657 NULL, &ring->data_dmat); 658 if (error != 0) { 659 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 660 goto fail; 661 } 662 663 for (i = 0; i < count; i++) { 664 desc = &sc->rxq.desc[i]; 665 data = &sc->rxq.data[i]; 666 667 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 668 if (error != 0) { 669 device_printf(sc->sc_dev, "could not create DMA map\n"); 670 goto fail; 671 } 672 673 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 674 if (data->m == NULL) { 675 device_printf(sc->sc_dev, 676 "could not allocate rx mbuf\n"); 677 error = ENOMEM; 678 goto fail; 679 } 680 681 error = bus_dmamap_load(ring->data_dmat, data->map, 682 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 683 &physaddr, 0); 684 if (error != 0) { 685 device_printf(sc->sc_dev, 686 "could not load rx buf DMA map"); 687 goto fail; 688 } 689 690 desc->flags = htole32(RT2661_RX_BUSY); 691 desc->physaddr = htole32(physaddr); 692 } 693 694 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 695 696 return 0; 697 698fail: rt2661_free_rx_ring(sc, ring); 699 return error; 700} 701 702static void 703rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 704{ 705 int i; 706 707 for (i = 0; i < ring->count; i++) 708 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 709 710 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 711 712 ring->cur = ring->next = 0; 713} 714 715static void 716rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 717{ 718 struct rt2661_rx_data *data; 719 int i; 720 721 if (ring->desc != NULL) { 722 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 723 BUS_DMASYNC_POSTWRITE); 724 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 725 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 726 } 727 728 if (ring->desc_dmat != NULL) 729 bus_dma_tag_destroy(ring->desc_dmat); 730 731 if (ring->data != NULL) { 732 for (i = 0; i < ring->count; i++) { 733 data = &ring->data[i]; 734 735 if (data->m != NULL) { 736 bus_dmamap_sync(ring->data_dmat, data->map, 737 BUS_DMASYNC_POSTREAD); 738 bus_dmamap_unload(ring->data_dmat, data->map); 739 m_freem(data->m); 740 } 741 742 if (data->map != NULL) 743 bus_dmamap_destroy(ring->data_dmat, data->map); 744 } 745 746 free(ring->data, M_DEVBUF); 747 } 748 749 if (ring->data_dmat != NULL) 750 bus_dma_tag_destroy(ring->data_dmat); 751} 752 753static struct ieee80211_node * 754rt2661_node_alloc(struct ieee80211_node_table *nt) 755{ 756 struct rt2661_node *rn; 757 758 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 759 M_NOWAIT | M_ZERO); 760 761 return (rn != NULL) ? &rn->ni : NULL; 762} 763 764static int 765rt2661_media_change(struct ifnet *ifp) 766{ 767 struct rt2661_softc *sc = ifp->if_softc; 768 int error; 769 770 error = ieee80211_media_change(ifp); 771 if (error != ENETRESET) 772 return error; 773 774 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 775 rt2661_init(sc); 776 777 return 0; 778} 779 780/* 781 * This function is called periodically (every 200ms) during scanning to 782 * switch from one channel to another. 783 */ 784static void 785rt2661_next_scan(void *arg) 786{ 787 struct rt2661_softc *sc = arg; 788 struct ieee80211com *ic = &sc->sc_ic; 789 790 if (ic->ic_state == IEEE80211_S_SCAN) 791 ieee80211_next_scan(ic); 792} 793 794/* 795 * This function is called for each node present in the node station table. 796 */ 797static void 798rt2661_iter_func(void *arg, struct ieee80211_node *ni) 799{ 800 struct rt2661_node *rn = (struct rt2661_node *)ni; 801 802 ral_rssadapt_updatestats(&rn->rssadapt); 803} 804 805/* 806 * This function is called periodically (every 100ms) in RUN state to update 807 * the rate adaptation statistics. 808 */ 809static void 810rt2661_update_rssadapt(void *arg) 811{ 812 struct rt2661_softc *sc = arg; 813 struct ieee80211com *ic = &sc->sc_ic; 814 815 RAL_LOCK(sc); 816 817 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 818 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_update_rssadapt, sc); 819 820 RAL_UNLOCK(sc); 821} 822 823static int 824rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 825{ 826 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 827 enum ieee80211_state ostate; 828 struct ieee80211_node *ni; 829 uint32_t tmp; 830 int error = 0; 831 832 ostate = ic->ic_state; 833 callout_stop(&sc->scan_ch); 834 835 switch (nstate) { 836 case IEEE80211_S_INIT: 837 callout_stop(&sc->rssadapt_ch); 838 839 if (ostate == IEEE80211_S_RUN) { 840 /* abort TSF synchronization */ 841 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 842 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 843 } 844 break; 845 846 case IEEE80211_S_SCAN: 847 rt2661_set_chan(sc, ic->ic_curchan); 848 callout_reset(&sc->scan_ch, (sc->dwelltime * hz) / 1000, 849 rt2661_next_scan, sc); 850 break; 851 852 case IEEE80211_S_AUTH: 853 case IEEE80211_S_ASSOC: 854 rt2661_set_chan(sc, ic->ic_curchan); 855 break; 856 857 case IEEE80211_S_RUN: 858 rt2661_set_chan(sc, ic->ic_curchan); 859 860 ni = ic->ic_bss; 861 862 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 863 rt2661_enable_mrr(sc); 864 rt2661_set_txpreamble(sc); 865 rt2661_set_basicrates(sc, &ni->ni_rates); 866 rt2661_set_bssid(sc, ni->ni_bssid); 867 } 868 869 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 870 ic->ic_opmode == IEEE80211_M_IBSS) { 871 if ((error = rt2661_prepare_beacon(sc)) != 0) 872 break; 873 } 874 875 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 876 callout_reset(&sc->rssadapt_ch, hz / 10, 877 rt2661_update_rssadapt, sc); 878 rt2661_enable_tsf_sync(sc); 879 } 880 break; 881 } 882 883 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 884} 885 886/* 887 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 888 * 93C66). 889 */ 890static uint16_t 891rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 892{ 893 uint32_t tmp; 894 uint16_t val; 895 int n; 896 897 /* clock C once before the first command */ 898 RT2661_EEPROM_CTL(sc, 0); 899 900 RT2661_EEPROM_CTL(sc, RT2661_S); 901 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 902 RT2661_EEPROM_CTL(sc, RT2661_S); 903 904 /* write start bit (1) */ 905 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 906 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 907 908 /* write READ opcode (10) */ 909 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 910 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 911 RT2661_EEPROM_CTL(sc, RT2661_S); 912 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 913 914 /* write address (A5-A0 or A7-A0) */ 915 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 916 for (; n >= 0; n--) { 917 RT2661_EEPROM_CTL(sc, RT2661_S | 918 (((addr >> n) & 1) << RT2661_SHIFT_D)); 919 RT2661_EEPROM_CTL(sc, RT2661_S | 920 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 921 } 922 923 RT2661_EEPROM_CTL(sc, RT2661_S); 924 925 /* read data Q15-Q0 */ 926 val = 0; 927 for (n = 15; n >= 0; n--) { 928 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 929 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 930 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 931 RT2661_EEPROM_CTL(sc, RT2661_S); 932 } 933 934 RT2661_EEPROM_CTL(sc, 0); 935 936 /* clear Chip Select and clock C */ 937 RT2661_EEPROM_CTL(sc, RT2661_S); 938 RT2661_EEPROM_CTL(sc, 0); 939 RT2661_EEPROM_CTL(sc, RT2661_C); 940 941 return val; 942} 943 944static void 945rt2661_tx_intr(struct rt2661_softc *sc) 946{ 947 struct ieee80211com *ic = &sc->sc_ic; 948 struct ifnet *ifp = ic->ic_ifp; 949 struct rt2661_tx_ring *txq; 950 struct rt2661_tx_data *data; 951 struct rt2661_node *rn; 952 uint32_t val; 953 int qid, retrycnt; 954 955 for (;;) { 956 val = RAL_READ(sc, RT2661_STA_CSR4); 957 if (!(val & RT2661_TX_STAT_VALID)) 958 break; 959 960 /* retrieve the queue in which this frame was sent */ 961 qid = RT2661_TX_QID(val); 962 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 963 964 /* retrieve rate control algorithm context */ 965 data = &txq->data[txq->stat]; 966 rn = (struct rt2661_node *)data->ni; 967 968 /* if no frame has been sent, ignore */ 969 if (rn == NULL) 970 continue; 971 972 switch (RT2661_TX_RESULT(val)) { 973 case RT2661_TX_SUCCESS: 974 retrycnt = RT2661_TX_RETRYCNT(val); 975 976 DPRINTFN(10, ("data frame sent successfully after " 977 "%d retries\n", retrycnt)); 978 if (retrycnt == 0 && data->id.id_node != NULL) { 979 ral_rssadapt_raise_rate(ic, &rn->rssadapt, 980 &data->id); 981 } 982 ifp->if_opackets++; 983 break; 984 985 case RT2661_TX_RETRY_FAIL: 986 DPRINTFN(9, ("sending data frame failed (too much " 987 "retries)\n")); 988 if (data->id.id_node != NULL) { 989 ral_rssadapt_lower_rate(ic, data->ni, 990 &rn->rssadapt, &data->id); 991 } 992 ifp->if_oerrors++; 993 break; 994 995 default: 996 /* other failure */ 997 device_printf(sc->sc_dev, 998 "sending data frame failed 0x%08x\n", val); 999 ifp->if_oerrors++; 1000 } 1001 1002 ieee80211_free_node(data->ni); 1003 data->ni = NULL; 1004 1005 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 1006 1007 txq->queued--; 1008 if (++txq->stat >= txq->count) /* faster than % count */ 1009 txq->stat = 0; 1010 } 1011 1012 sc->sc_tx_timer = 0; 1013 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1014 rt2661_start(ifp); 1015} 1016 1017static void 1018rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1019{ 1020 struct rt2661_tx_desc *desc; 1021 struct rt2661_tx_data *data; 1022 1023 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 1024 1025 for (;;) { 1026 desc = &txq->desc[txq->next]; 1027 data = &txq->data[txq->next]; 1028 1029 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1030 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1031 break; 1032 1033 bus_dmamap_sync(txq->data_dmat, data->map, 1034 BUS_DMASYNC_POSTWRITE); 1035 bus_dmamap_unload(txq->data_dmat, data->map); 1036 m_freem(data->m); 1037 data->m = NULL; 1038 /* node reference is released in rt2661_tx_intr() */ 1039 1040 /* descriptor is no longer valid */ 1041 desc->flags &= ~htole32(RT2661_TX_VALID); 1042 1043 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1044 1045 if (++txq->next >= txq->count) /* faster than % count */ 1046 txq->next = 0; 1047 } 1048 1049 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1050} 1051 1052static void 1053rt2661_rx_intr(struct rt2661_softc *sc) 1054{ 1055 struct ieee80211com *ic = &sc->sc_ic; 1056 struct ifnet *ifp = ic->ic_ifp; 1057 struct rt2661_rx_desc *desc; 1058 struct rt2661_rx_data *data; 1059 bus_addr_t physaddr; 1060 struct ieee80211_frame *wh; 1061 struct ieee80211_node *ni; 1062 struct rt2661_node *rn; 1063 struct mbuf *mnew, *m; 1064 int error; 1065 1066 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1067 BUS_DMASYNC_POSTREAD); 1068 1069 for (;;) { 1070 desc = &sc->rxq.desc[sc->rxq.cur]; 1071 data = &sc->rxq.data[sc->rxq.cur]; 1072 1073 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1074 break; 1075 1076 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1077 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1078 /* 1079 * This should not happen since we did not request 1080 * to receive those frames when we filled TXRX_CSR0. 1081 */ 1082 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1083 le32toh(desc->flags))); 1084 ifp->if_ierrors++; 1085 goto skip; 1086 } 1087 1088 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1089 ifp->if_ierrors++; 1090 goto skip; 1091 } 1092 1093 /* 1094 * Try to allocate a new mbuf for this ring element and load it 1095 * before processing the current mbuf. If the ring element 1096 * cannot be loaded, drop the received packet and reuse the old 1097 * mbuf. In the unlikely case that the old mbuf can't be 1098 * reloaded either, explicitly panic. 1099 */ 1100 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1101 if (mnew == NULL) { 1102 ifp->if_ierrors++; 1103 goto skip; 1104 } 1105 1106 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1107 BUS_DMASYNC_POSTREAD); 1108 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1109 1110 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1111 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1112 &physaddr, 0); 1113 if (error != 0) { 1114 m_freem(mnew); 1115 1116 /* try to reload the old mbuf */ 1117 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1118 mtod(data->m, void *), MCLBYTES, 1119 rt2661_dma_map_addr, &physaddr, 0); 1120 if (error != 0) { 1121 /* very unlikely that it will fail... */ 1122 panic("%s: could not load old rx mbuf", 1123 device_get_name(sc->sc_dev)); 1124 } 1125 ifp->if_ierrors++; 1126 goto skip; 1127 } 1128 1129 /* 1130 * New mbuf successfully loaded, update Rx ring and continue 1131 * processing. 1132 */ 1133 m = data->m; 1134 data->m = mnew; 1135 desc->physaddr = htole32(physaddr); 1136 1137 /* finalize mbuf */ 1138 m->m_pkthdr.rcvif = ifp; 1139 m->m_pkthdr.len = m->m_len = 1140 (le32toh(desc->flags) >> 16) & 0xfff; 1141 1142 if (bpf_peers_present(sc->sc_drvbpf)) { 1143 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1144 uint32_t tsf_lo, tsf_hi; 1145 1146 /* get timestamp (low and high 32 bits) */ 1147 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1148 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1149 1150 tap->wr_tsf = 1151 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1152 tap->wr_flags = 0; 1153 tap->wr_rate = rt2661_rxrate(desc); 1154 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1155 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1156 tap->wr_antsignal = desc->rssi; 1157 1158 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1159 } 1160 1161 wh = mtod(m, struct ieee80211_frame *); 1162 ni = ieee80211_find_rxnode(ic, 1163 (struct ieee80211_frame_min *)wh); 1164 1165 /* send the frame to the 802.11 layer */ 1166 ieee80211_input(ic, m, ni, desc->rssi, 0); 1167 1168 /* give rssi to the rate adatation algorithm */ 1169 rn = (struct rt2661_node *)ni; 1170 ral_rssadapt_input(ic, ni, &rn->rssadapt, 1171 rt2661_get_rssi(sc, desc->rssi)); 1172 1173 /* node is no longer needed */ 1174 ieee80211_free_node(ni); 1175 1176skip: desc->flags |= htole32(RT2661_RX_BUSY); 1177 1178 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1179 1180 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1181 } 1182 1183 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1184 BUS_DMASYNC_PREWRITE); 1185} 1186 1187/* ARGSUSED */ 1188static void 1189rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1190{ 1191 /* do nothing */ 1192} 1193 1194static void 1195rt2661_mcu_wakeup(struct rt2661_softc *sc) 1196{ 1197 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1198 1199 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1200 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1201 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1202 1203 /* send wakeup command to MCU */ 1204 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1205} 1206 1207static void 1208rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1209{ 1210 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1211 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1212} 1213 1214void 1215rt2661_intr(void *arg) 1216{ 1217 struct rt2661_softc *sc = arg; 1218 struct ifnet *ifp = sc->sc_ifp; 1219 uint32_t r1, r2; 1220 1221 RAL_LOCK(sc); 1222 1223 /* disable MAC and MCU interrupts */ 1224 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1225 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1226 1227 /* don't re-enable interrupts if we're shutting down */ 1228 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1229 RAL_UNLOCK(sc); 1230 return; 1231 } 1232 1233 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1234 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1235 1236 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1237 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1238 1239 if (r1 & RT2661_MGT_DONE) 1240 rt2661_tx_dma_intr(sc, &sc->mgtq); 1241 1242 if (r1 & RT2661_RX_DONE) 1243 rt2661_rx_intr(sc); 1244 1245 if (r1 & RT2661_TX0_DMA_DONE) 1246 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1247 1248 if (r1 & RT2661_TX1_DMA_DONE) 1249 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1250 1251 if (r1 & RT2661_TX2_DMA_DONE) 1252 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1253 1254 if (r1 & RT2661_TX3_DMA_DONE) 1255 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1256 1257 if (r1 & RT2661_TX_DONE) 1258 rt2661_tx_intr(sc); 1259 1260 if (r2 & RT2661_MCU_CMD_DONE) 1261 rt2661_mcu_cmd_intr(sc); 1262 1263 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1264 rt2661_mcu_beacon_expire(sc); 1265 1266 if (r2 & RT2661_MCU_WAKEUP) 1267 rt2661_mcu_wakeup(sc); 1268 1269 /* re-enable MAC and MCU interrupts */ 1270 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1271 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1272 1273 RAL_UNLOCK(sc); 1274} 1275 1276/* quickly determine if a given rate is CCK or OFDM */ 1277#define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1278 1279#define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1280#define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1281 1282#define RAL_SIFS 10 /* us */ 1283 1284/* 1285 * This function is only used by the Rx radiotap code. It returns the rate at 1286 * which a given frame was received. 1287 */ 1288static uint8_t 1289rt2661_rxrate(struct rt2661_rx_desc *desc) 1290{ 1291 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1292 /* reverse function of rt2661_plcp_signal */ 1293 switch (desc->rate & 0xf) { 1294 case 0xb: return 12; 1295 case 0xf: return 18; 1296 case 0xa: return 24; 1297 case 0xe: return 36; 1298 case 0x9: return 48; 1299 case 0xd: return 72; 1300 case 0x8: return 96; 1301 case 0xc: return 108; 1302 } 1303 } else { 1304 if (desc->rate == 10) 1305 return 2; 1306 if (desc->rate == 20) 1307 return 4; 1308 if (desc->rate == 55) 1309 return 11; 1310 if (desc->rate == 110) 1311 return 22; 1312 } 1313 return 2; /* should not get there */ 1314} 1315 1316/* 1317 * Return the expected ack rate for a frame transmitted at rate `rate'. 1318 * XXX: this should depend on the destination node basic rate set. 1319 */ 1320static int 1321rt2661_ack_rate(struct ieee80211com *ic, int rate) 1322{ 1323 switch (rate) { 1324 /* CCK rates */ 1325 case 2: 1326 return 2; 1327 case 4: 1328 case 11: 1329 case 22: 1330 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1331 1332 /* OFDM rates */ 1333 case 12: 1334 case 18: 1335 return 12; 1336 case 24: 1337 case 36: 1338 return 24; 1339 case 48: 1340 case 72: 1341 case 96: 1342 case 108: 1343 return 48; 1344 } 1345 1346 /* default to 1Mbps */ 1347 return 2; 1348} 1349 1350/* 1351 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1352 * The function automatically determines the operating mode depending on the 1353 * given rate. `flags' indicates whether short preamble is in use or not. 1354 */ 1355static uint16_t 1356rt2661_txtime(int len, int rate, uint32_t flags) 1357{ 1358 uint16_t txtime; 1359 1360 if (RAL_RATE_IS_OFDM(rate)) { 1361 /* IEEE Std 802.11a-1999, pp. 37 */ 1362 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1363 txtime = 16 + 4 + 4 * txtime + 6; 1364 } else { 1365 /* IEEE Std 802.11b-1999, pp. 28 */ 1366 txtime = (16 * len + rate - 1) / rate; 1367 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1368 txtime += 72 + 24; 1369 else 1370 txtime += 144 + 48; 1371 } 1372 1373 return txtime; 1374} 1375 1376static uint8_t 1377rt2661_plcp_signal(int rate) 1378{ 1379 switch (rate) { 1380 /* CCK rates (returned values are device-dependent) */ 1381 case 2: return 0x0; 1382 case 4: return 0x1; 1383 case 11: return 0x2; 1384 case 22: return 0x3; 1385 1386 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1387 case 12: return 0xb; 1388 case 18: return 0xf; 1389 case 24: return 0xa; 1390 case 36: return 0xe; 1391 case 48: return 0x9; 1392 case 72: return 0xd; 1393 case 96: return 0x8; 1394 case 108: return 0xc; 1395 1396 /* unsupported rates (should not get there) */ 1397 default: return 0xff; 1398 } 1399} 1400 1401static void 1402rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1403 uint32_t flags, uint16_t xflags, int len, int rate, 1404 const bus_dma_segment_t *segs, int nsegs, int ac) 1405{ 1406 struct ieee80211com *ic = &sc->sc_ic; 1407 uint16_t plcp_length; 1408 int i, remainder; 1409 1410 desc->flags = htole32(flags); 1411 desc->flags |= htole32(len << 16); 1412 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1413 1414 desc->xflags = htole16(xflags); 1415 desc->xflags |= htole16(nsegs << 13); 1416 1417 desc->wme = htole16( 1418 RT2661_QID(ac) | 1419 RT2661_AIFSN(2) | 1420 RT2661_LOGCWMIN(4) | 1421 RT2661_LOGCWMAX(10)); 1422 1423 /* 1424 * Remember in which queue this frame was sent. This field is driver 1425 * private data only. It will be made available by the NIC in STA_CSR4 1426 * on Tx interrupts. 1427 */ 1428 desc->qid = ac; 1429 1430 /* setup PLCP fields */ 1431 desc->plcp_signal = rt2661_plcp_signal(rate); 1432 desc->plcp_service = 4; 1433 1434 len += IEEE80211_CRC_LEN; 1435 if (RAL_RATE_IS_OFDM(rate)) { 1436 desc->flags |= htole32(RT2661_TX_OFDM); 1437 1438 plcp_length = len & 0xfff; 1439 desc->plcp_length_hi = plcp_length >> 6; 1440 desc->plcp_length_lo = plcp_length & 0x3f; 1441 } else { 1442 plcp_length = (16 * len + rate - 1) / rate; 1443 if (rate == 22) { 1444 remainder = (16 * len) % 22; 1445 if (remainder != 0 && remainder < 7) 1446 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1447 } 1448 desc->plcp_length_hi = plcp_length >> 8; 1449 desc->plcp_length_lo = plcp_length & 0xff; 1450 1451 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1452 desc->plcp_signal |= 0x08; 1453 } 1454 1455 /* RT2x61 supports scatter with up to 5 segments */ 1456 for (i = 0; i < nsegs; i++) { 1457 desc->addr[i] = htole32(segs[i].ds_addr); 1458 desc->len [i] = htole16(segs[i].ds_len); 1459 } 1460} 1461 1462static int 1463rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1464 struct ieee80211_node *ni) 1465{ 1466 struct ieee80211com *ic = &sc->sc_ic; 1467 struct rt2661_tx_desc *desc; 1468 struct rt2661_tx_data *data; 1469 struct ieee80211_frame *wh; 1470 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1471 uint16_t dur; 1472 uint32_t flags = 0; /* XXX HWSEQ */ 1473 int nsegs, rate, error; 1474 1475 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1476 data = &sc->mgtq.data[sc->mgtq.cur]; 1477 1478 /* send mgt frames at the lowest available rate */ 1479 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1480 1481 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1482 segs, &nsegs, 0); 1483 if (error != 0) { 1484 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1485 error); 1486 m_freem(m0); 1487 return error; 1488 } 1489 1490 if (bpf_peers_present(sc->sc_drvbpf)) { 1491 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1492 1493 tap->wt_flags = 0; 1494 tap->wt_rate = rate; 1495 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1496 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1497 1498 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1499 } 1500 1501 data->m = m0; 1502 data->ni = ni; 1503 1504 wh = mtod(m0, struct ieee80211_frame *); 1505 1506 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1507 flags |= RT2661_TX_NEED_ACK; 1508 1509 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1510 RAL_SIFS; 1511 *(uint16_t *)wh->i_dur = htole16(dur); 1512 1513 /* tell hardware to add timestamp in probe responses */ 1514 if ((wh->i_fc[0] & 1515 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1516 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1517 flags |= RT2661_TX_TIMESTAMP; 1518 } 1519 1520 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1521 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1522 1523 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1524 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1525 BUS_DMASYNC_PREWRITE); 1526 1527 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1528 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1529 1530 /* kick mgt */ 1531 sc->mgtq.queued++; 1532 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1533 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1534 1535 return 0; 1536} 1537 1538/* 1539 * Build a RTS control frame. 1540 */ 1541static struct mbuf * 1542rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1543 uint16_t dur) 1544{ 1545 struct ieee80211_frame_rts *rts; 1546 struct mbuf *m; 1547 1548 MGETHDR(m, M_DONTWAIT, MT_DATA); 1549 if (m == NULL) { 1550 sc->sc_ic.ic_stats.is_tx_nobuf++; 1551 device_printf(sc->sc_dev, "could not allocate RTS frame\n"); 1552 return NULL; 1553 } 1554 1555 rts = mtod(m, struct ieee80211_frame_rts *); 1556 1557 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1558 IEEE80211_FC0_SUBTYPE_RTS; 1559 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1560 *(uint16_t *)rts->i_dur = htole16(dur); 1561 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1562 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1563 1564 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1565 1566 return m; 1567} 1568 1569static int 1570rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1571 struct ieee80211_node *ni, int ac) 1572{ 1573 struct ieee80211com *ic = &sc->sc_ic; 1574 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1575 struct rt2661_tx_desc *desc; 1576 struct rt2661_tx_data *data; 1577 struct rt2661_node *rn; 1578 struct ieee80211_rateset *rs; 1579 struct ieee80211_frame *wh; 1580 struct ieee80211_key *k; 1581 const struct chanAccParams *cap; 1582 struct mbuf *mnew; 1583 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1584 uint16_t dur; 1585 uint32_t flags = 0; 1586 int error, nsegs, rate, noack = 0; 1587 1588 wh = mtod(m0, struct ieee80211_frame *); 1589 1590 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1591 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1592 rate = rs->rs_rates[ic->ic_fixed_rate]; 1593 } else { 1594 rs = &ni->ni_rates; 1595 rn = (struct rt2661_node *)ni; 1596 ni->ni_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, 1597 wh, m0->m_pkthdr.len, NULL, 0); 1598 rate = rs->rs_rates[ni->ni_txrate]; 1599 } 1600 rate &= IEEE80211_RATE_VAL; 1601 1602 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1603 cap = &ic->ic_wme.wme_chanParams; 1604 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1605 } 1606 1607 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1608 k = ieee80211_crypto_encap(ic, ni, m0); 1609 if (k == NULL) { 1610 m_freem(m0); 1611 return ENOBUFS; 1612 } 1613 1614 /* packet header may have moved, reset our local pointer */ 1615 wh = mtod(m0, struct ieee80211_frame *); 1616 } 1617 1618 /* 1619 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1620 * for directed frames only when the length of the MPDU is greater 1621 * than the length threshold indicated by [...]" ic_rtsthreshold. 1622 */ 1623 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1624 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1625 struct mbuf *m; 1626 uint16_t dur; 1627 int rtsrate, ackrate; 1628 1629 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1630 ackrate = rt2661_ack_rate(ic, rate); 1631 1632 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1633 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1634 /* XXX: noack (QoS)? */ 1635 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1636 3 * RAL_SIFS; 1637 1638 m = rt2661_get_rts(sc, wh, dur); 1639 1640 desc = &txq->desc[txq->cur]; 1641 data = &txq->data[txq->cur]; 1642 1643 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m, 1644 segs, &nsegs, 0); 1645 if (error != 0) { 1646 device_printf(sc->sc_dev, 1647 "could not map mbuf (error %d)\n", error); 1648 m_freem(m); 1649 m_freem(m0); 1650 return error; 1651 } 1652 1653 /* avoid multiple free() of the same node for each fragment */ 1654 ieee80211_ref_node(ni); 1655 1656 data->m = m; 1657 data->ni = ni; 1658 1659 /* RTS frames are not taken into account for rssadapt */ 1660 data->id.id_node = NULL; 1661 1662 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1663 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, segs, 1664 nsegs, ac); 1665 1666 bus_dmamap_sync(txq->data_dmat, data->map, 1667 BUS_DMASYNC_PREWRITE); 1668 1669 txq->queued++; 1670 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1671 1672 /* 1673 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1674 * asynchronous data frame shall be transmitted after the CTS 1675 * frame and a SIFS period. 1676 */ 1677 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1678 } 1679 1680 data = &txq->data[txq->cur]; 1681 desc = &txq->desc[txq->cur]; 1682 1683 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1684 &nsegs, 0); 1685 if (error != 0 && error != EFBIG) { 1686 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1687 error); 1688 m_freem(m0); 1689 return error; 1690 } 1691 if (error != 0) { 1692 mnew = m_defrag(m0, M_DONTWAIT); 1693 if (mnew == NULL) { 1694 device_printf(sc->sc_dev, 1695 "could not defragment mbuf\n"); 1696 m_freem(m0); 1697 return ENOBUFS; 1698 } 1699 m0 = mnew; 1700 1701 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1702 segs, &nsegs, 0); 1703 if (error != 0) { 1704 device_printf(sc->sc_dev, 1705 "could not map mbuf (error %d)\n", error); 1706 m_freem(m0); 1707 return error; 1708 } 1709 1710 /* packet header have moved, reset our local pointer */ 1711 wh = mtod(m0, struct ieee80211_frame *); 1712 } 1713 1714 if (bpf_peers_present(sc->sc_drvbpf)) { 1715 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1716 1717 tap->wt_flags = 0; 1718 tap->wt_rate = rate; 1719 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1720 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1721 1722 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1723 } 1724 1725 data->m = m0; 1726 data->ni = ni; 1727 1728 /* remember link conditions for rate adaptation algorithm */ 1729 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1730 data->id.id_len = m0->m_pkthdr.len; 1731 data->id.id_rateidx = ni->ni_txrate; 1732 data->id.id_node = ni; 1733 data->id.id_rssi = ni->ni_rssi; 1734 } else 1735 data->id.id_node = NULL; 1736 1737 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1738 flags |= RT2661_TX_NEED_ACK; 1739 1740 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1741 ic->ic_flags) + RAL_SIFS; 1742 *(uint16_t *)wh->i_dur = htole16(dur); 1743 } 1744 1745 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1746 nsegs, ac); 1747 1748 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1749 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1750 1751 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1752 m0->m_pkthdr.len, txq->cur, rate)); 1753 1754 /* kick Tx */ 1755 txq->queued++; 1756 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1757 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1758 1759 return 0; 1760} 1761 1762static void 1763rt2661_start(struct ifnet *ifp) 1764{ 1765 struct rt2661_softc *sc = ifp->if_softc; 1766 struct ieee80211com *ic = &sc->sc_ic; 1767 struct mbuf *m0; 1768 struct ether_header *eh; 1769 struct ieee80211_node *ni; 1770 int ac; 1771 1772 RAL_LOCK(sc); 1773 1774 /* prevent management frames from being sent if we're not ready */ 1775 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1776 RAL_UNLOCK(sc); 1777 return; 1778 } 1779 1780 for (;;) { 1781 IF_POLL(&ic->ic_mgtq, m0); 1782 if (m0 != NULL) { 1783 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1784 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1785 break; 1786 } 1787 IF_DEQUEUE(&ic->ic_mgtq, m0); 1788 1789 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1790 m0->m_pkthdr.rcvif = NULL; 1791 1792 if (bpf_peers_present(ic->ic_rawbpf)) 1793 bpf_mtap(ic->ic_rawbpf, m0); 1794 1795 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1796 break; 1797 1798 } else { 1799 if (ic->ic_state != IEEE80211_S_RUN) 1800 break; 1801 1802 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1803 if (m0 == NULL) 1804 break; 1805 1806 if (m0->m_len < sizeof (struct ether_header) && 1807 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1808 continue; 1809 1810 eh = mtod(m0, struct ether_header *); 1811 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1812 if (ni == NULL) { 1813 m_freem(m0); 1814 ifp->if_oerrors++; 1815 continue; 1816 } 1817 1818 /* classify mbuf so we can find which tx ring to use */ 1819 if (ieee80211_classify(ic, m0, ni) != 0) { 1820 m_freem(m0); 1821 ieee80211_free_node(ni); 1822 ifp->if_oerrors++; 1823 continue; 1824 } 1825 1826 /* no QoS encapsulation for EAPOL frames */ 1827 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1828 M_WME_GETAC(m0) : WME_AC_BE; 1829 1830 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1831 /* there is no place left in this ring */ 1832 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1833 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1834 break; 1835 } 1836 1837 BPF_MTAP(ifp, m0); 1838 1839 m0 = ieee80211_encap(ic, m0, ni); 1840 if (m0 == NULL) { 1841 ieee80211_free_node(ni); 1842 ifp->if_oerrors++; 1843 continue; 1844 } 1845 1846 if (bpf_peers_present(ic->ic_rawbpf)) 1847 bpf_mtap(ic->ic_rawbpf, m0); 1848 1849 if (rt2661_tx_data(sc, m0, ni, ac) != 0) { 1850 ieee80211_free_node(ni); 1851 ifp->if_oerrors++; 1852 break; 1853 } 1854 } 1855 1856 sc->sc_tx_timer = 5; 1857 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1858 } 1859 1860 RAL_UNLOCK(sc); 1861} 1862 1863static void 1864rt2661_watchdog(void *arg) 1865{ 1866 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1867 struct ieee80211com *ic = &sc->sc_ic; 1868 1869 if (sc->sc_tx_timer > 0) { 1870 if (--sc->sc_tx_timer == 0) { 1871 device_printf(sc->sc_dev, "device timeout\n"); 1872 rt2661_init(sc); 1873 sc->sc_ifp->if_oerrors++; 1874 return; 1875 } 1876 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1877 } 1878 1879 ieee80211_watchdog(ic); 1880} 1881 1882/* 1883 * This function allows for fast channel switching in monitor mode (used by 1884 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to 1885 * generate a new beacon frame. 1886 */ 1887static int 1888rt2661_reset(struct ifnet *ifp) 1889{ 1890 struct rt2661_softc *sc = ifp->if_softc; 1891 struct ieee80211com *ic = &sc->sc_ic; 1892 1893 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1894 return ENETRESET; 1895 1896 rt2661_set_chan(sc, ic->ic_curchan); 1897 1898 return 0; 1899} 1900 1901static int 1902rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1903{ 1904 struct rt2661_softc *sc = ifp->if_softc; 1905 struct ieee80211com *ic = &sc->sc_ic; 1906 int error = 0; 1907 1908 RAL_LOCK(sc); 1909 1910 switch (cmd) { 1911 case SIOCSIFFLAGS: 1912 if (ifp->if_flags & IFF_UP) { 1913 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1914 rt2661_update_promisc(sc); 1915 else 1916 rt2661_init(sc); 1917 } else { 1918 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1919 rt2661_stop(sc); 1920 } 1921 break; 1922 1923 default: 1924 error = ieee80211_ioctl(ic, cmd, data); 1925 } 1926 1927 if (error == ENETRESET) { 1928 if ((ifp->if_flags & IFF_UP) && 1929 (ifp->if_drv_flags & IFF_DRV_RUNNING) && 1930 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1931 rt2661_init(sc); 1932 error = 0; 1933 } 1934 1935 RAL_UNLOCK(sc); 1936 1937 return error; 1938} 1939 1940static void 1941rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1942{ 1943 uint32_t tmp; 1944 int ntries; 1945 1946 for (ntries = 0; ntries < 100; ntries++) { 1947 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1948 break; 1949 DELAY(1); 1950 } 1951 if (ntries == 100) { 1952 device_printf(sc->sc_dev, "could not write to BBP\n"); 1953 return; 1954 } 1955 1956 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1957 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1958 1959 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 1960} 1961 1962static uint8_t 1963rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1964{ 1965 uint32_t val; 1966 int ntries; 1967 1968 for (ntries = 0; ntries < 100; ntries++) { 1969 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1970 break; 1971 DELAY(1); 1972 } 1973 if (ntries == 100) { 1974 device_printf(sc->sc_dev, "could not read from BBP\n"); 1975 return 0; 1976 } 1977 1978 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1979 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1980 1981 for (ntries = 0; ntries < 100; ntries++) { 1982 val = RAL_READ(sc, RT2661_PHY_CSR3); 1983 if (!(val & RT2661_BBP_BUSY)) 1984 return val & 0xff; 1985 DELAY(1); 1986 } 1987 1988 device_printf(sc->sc_dev, "could not read from BBP\n"); 1989 return 0; 1990} 1991 1992static void 1993rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1994{ 1995 uint32_t tmp; 1996 int ntries; 1997 1998 for (ntries = 0; ntries < 100; ntries++) { 1999 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2000 break; 2001 DELAY(1); 2002 } 2003 if (ntries == 100) { 2004 device_printf(sc->sc_dev, "could not write to RF\n"); 2005 return; 2006 } 2007 2008 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2009 (reg & 3); 2010 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2011 2012 /* remember last written value in sc */ 2013 sc->rf_regs[reg] = val; 2014 2015 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2016} 2017 2018static int 2019rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2020{ 2021 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2022 return EIO; /* there is already a command pending */ 2023 2024 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2025 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2026 2027 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2028 2029 return 0; 2030} 2031 2032static void 2033rt2661_select_antenna(struct rt2661_softc *sc) 2034{ 2035 uint8_t bbp4, bbp77; 2036 uint32_t tmp; 2037 2038 bbp4 = rt2661_bbp_read(sc, 4); 2039 bbp77 = rt2661_bbp_read(sc, 77); 2040 2041 /* TBD */ 2042 2043 /* make sure Rx is disabled before switching antenna */ 2044 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2045 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2046 2047 rt2661_bbp_write(sc, 4, bbp4); 2048 rt2661_bbp_write(sc, 77, bbp77); 2049 2050 /* restore Rx filter */ 2051 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2052} 2053 2054/* 2055 * Enable multi-rate retries for frames sent at OFDM rates. 2056 * In 802.11b/g mode, allow fallback to CCK rates. 2057 */ 2058static void 2059rt2661_enable_mrr(struct rt2661_softc *sc) 2060{ 2061 struct ieee80211com *ic = &sc->sc_ic; 2062 uint32_t tmp; 2063 2064 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2065 2066 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2067 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2068 tmp |= RT2661_MRR_CCK_FALLBACK; 2069 tmp |= RT2661_MRR_ENABLED; 2070 2071 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2072} 2073 2074static void 2075rt2661_set_txpreamble(struct rt2661_softc *sc) 2076{ 2077 uint32_t tmp; 2078 2079 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2080 2081 tmp &= ~RT2661_SHORT_PREAMBLE; 2082 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2083 tmp |= RT2661_SHORT_PREAMBLE; 2084 2085 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2086} 2087 2088static void 2089rt2661_set_basicrates(struct rt2661_softc *sc, 2090 const struct ieee80211_rateset *rs) 2091{ 2092#define RV(r) ((r) & IEEE80211_RATE_VAL) 2093 uint32_t mask = 0; 2094 uint8_t rate; 2095 int i, j; 2096 2097 for (i = 0; i < rs->rs_nrates; i++) { 2098 rate = rs->rs_rates[i]; 2099 2100 if (!(rate & IEEE80211_RATE_BASIC)) 2101 continue; 2102 2103 /* 2104 * Find h/w rate index. We know it exists because the rate 2105 * set has already been negotiated. 2106 */ 2107 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2108 2109 mask |= 1 << j; 2110 } 2111 2112 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2113 2114 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2115#undef RV 2116} 2117 2118/* 2119 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2120 * driver. 2121 */ 2122static void 2123rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2124{ 2125 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2126 uint32_t tmp; 2127 2128 /* update all BBP registers that depend on the band */ 2129 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2130 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2131 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2132 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2133 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2134 } 2135 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2136 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2137 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2138 } 2139 2140 rt2661_bbp_write(sc, 17, bbp17); 2141 rt2661_bbp_write(sc, 96, bbp96); 2142 rt2661_bbp_write(sc, 104, bbp104); 2143 2144 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2145 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2146 rt2661_bbp_write(sc, 75, 0x80); 2147 rt2661_bbp_write(sc, 86, 0x80); 2148 rt2661_bbp_write(sc, 88, 0x80); 2149 } 2150 2151 rt2661_bbp_write(sc, 35, bbp35); 2152 rt2661_bbp_write(sc, 97, bbp97); 2153 rt2661_bbp_write(sc, 98, bbp98); 2154 2155 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2156 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2157 if (IEEE80211_IS_CHAN_2GHZ(c)) 2158 tmp |= RT2661_PA_PE_2GHZ; 2159 else 2160 tmp |= RT2661_PA_PE_5GHZ; 2161 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2162} 2163 2164static void 2165rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2166{ 2167 struct ieee80211com *ic = &sc->sc_ic; 2168 const struct rfprog *rfprog; 2169 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2170 int8_t power; 2171 u_int i, chan; 2172 2173 chan = ieee80211_chan2ieee(ic, c); 2174 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2175 return; 2176 2177 /* select the appropriate RF settings based on what EEPROM says */ 2178 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2179 2180 /* find the settings for this channel (we know it exists) */ 2181 for (i = 0; rfprog[i].chan != chan; i++); 2182 2183 power = sc->txpow[i]; 2184 if (power < 0) { 2185 bbp94 += power; 2186 power = 0; 2187 } else if (power > 31) { 2188 bbp94 += power - 31; 2189 power = 31; 2190 } 2191 2192 /* 2193 * If we are switching from the 2GHz band to the 5GHz band or 2194 * vice-versa, BBP registers need to be reprogrammed. 2195 */ 2196 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2197 rt2661_select_band(sc, c); 2198 rt2661_select_antenna(sc); 2199 } 2200 sc->sc_curchan = c; 2201 2202 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2203 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2204 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2205 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2206 2207 DELAY(200); 2208 2209 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2210 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2211 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2212 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2213 2214 DELAY(200); 2215 2216 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2217 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2218 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2219 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2220 2221 /* enable smart mode for MIMO-capable RFs */ 2222 bbp3 = rt2661_bbp_read(sc, 3); 2223 2224 bbp3 &= ~RT2661_SMART_MODE; 2225 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2226 bbp3 |= RT2661_SMART_MODE; 2227 2228 rt2661_bbp_write(sc, 3, bbp3); 2229 2230 if (bbp94 != RT2661_BBPR94_DEFAULT) 2231 rt2661_bbp_write(sc, 94, bbp94); 2232 2233 /* 5GHz radio needs a 1ms delay here */ 2234 if (IEEE80211_IS_CHAN_5GHZ(c)) 2235 DELAY(1000); 2236} 2237 2238static void 2239rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2240{ 2241 uint32_t tmp; 2242 2243 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2244 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2245 2246 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2247 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2248} 2249 2250static void 2251rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2252{ 2253 uint32_t tmp; 2254 2255 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2256 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2257 2258 tmp = addr[4] | addr[5] << 8; 2259 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2260} 2261 2262static void 2263rt2661_update_promisc(struct rt2661_softc *sc) 2264{ 2265 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2266 uint32_t tmp; 2267 2268 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2269 2270 tmp &= ~RT2661_DROP_NOT_TO_ME; 2271 if (!(ifp->if_flags & IFF_PROMISC)) 2272 tmp |= RT2661_DROP_NOT_TO_ME; 2273 2274 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2275 2276 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2277 "entering" : "leaving")); 2278} 2279 2280/* 2281 * Update QoS (802.11e) settings for each h/w Tx ring. 2282 */ 2283static int 2284rt2661_wme_update(struct ieee80211com *ic) 2285{ 2286 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2287 const struct wmeParams *wmep; 2288 2289 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2290 2291 /* XXX: not sure about shifts. */ 2292 /* XXX: the reference driver plays with AC_VI settings too. */ 2293 2294 /* update TxOp */ 2295 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2296 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2297 wmep[WME_AC_BK].wmep_txopLimit); 2298 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2299 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2300 wmep[WME_AC_VO].wmep_txopLimit); 2301 2302 /* update CWmin */ 2303 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2304 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2305 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2306 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2307 wmep[WME_AC_VO].wmep_logcwmin); 2308 2309 /* update CWmax */ 2310 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2311 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2312 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2313 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2314 wmep[WME_AC_VO].wmep_logcwmax); 2315 2316 /* update Aifsn */ 2317 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2318 wmep[WME_AC_BE].wmep_aifsn << 12 | 2319 wmep[WME_AC_BK].wmep_aifsn << 8 | 2320 wmep[WME_AC_VI].wmep_aifsn << 4 | 2321 wmep[WME_AC_VO].wmep_aifsn); 2322 2323 return 0; 2324} 2325 2326static void 2327rt2661_update_slot(struct ifnet *ifp) 2328{ 2329 struct rt2661_softc *sc = ifp->if_softc; 2330 struct ieee80211com *ic = &sc->sc_ic; 2331 uint8_t slottime; 2332 uint32_t tmp; 2333 2334 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2335 2336 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2337 tmp = (tmp & ~0xff) | slottime; 2338 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2339} 2340 2341static const char * 2342rt2661_get_rf(int rev) 2343{ 2344 switch (rev) { 2345 case RT2661_RF_5225: return "RT5225"; 2346 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2347 case RT2661_RF_2527: return "RT2527"; 2348 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2349 default: return "unknown"; 2350 } 2351} 2352 2353static void 2354rt2661_read_eeprom(struct rt2661_softc *sc) 2355{ 2356 struct ieee80211com *ic = &sc->sc_ic; 2357 uint16_t val; 2358 int i; 2359 2360 /* read MAC address */ 2361 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2362 ic->ic_myaddr[0] = val & 0xff; 2363 ic->ic_myaddr[1] = val >> 8; 2364 2365 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2366 ic->ic_myaddr[2] = val & 0xff; 2367 ic->ic_myaddr[3] = val >> 8; 2368 2369 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2370 ic->ic_myaddr[4] = val & 0xff; 2371 ic->ic_myaddr[5] = val >> 8; 2372 2373 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2374 /* XXX: test if different from 0xffff? */ 2375 sc->rf_rev = (val >> 11) & 0x1f; 2376 sc->hw_radio = (val >> 10) & 0x1; 2377 sc->rx_ant = (val >> 4) & 0x3; 2378 sc->tx_ant = (val >> 2) & 0x3; 2379 sc->nb_ant = val & 0x3; 2380 2381 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2382 2383 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2384 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2385 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2386 2387 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2388 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2389 2390 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2391 if ((val & 0xff) != 0xff) 2392 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2393 2394 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2395 if ((val & 0xff) != 0xff) 2396 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2397 2398 /* adjust RSSI correction for external low-noise amplifier */ 2399 if (sc->ext_2ghz_lna) 2400 sc->rssi_2ghz_corr -= 14; 2401 if (sc->ext_5ghz_lna) 2402 sc->rssi_5ghz_corr -= 14; 2403 2404 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2405 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2406 2407 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2408 if ((val >> 8) != 0xff) 2409 sc->rfprog = (val >> 8) & 0x3; 2410 if ((val & 0xff) != 0xff) 2411 sc->rffreq = val & 0xff; 2412 2413 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2414 2415 /* read Tx power for all a/b/g channels */ 2416 for (i = 0; i < 19; i++) { 2417 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2418 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2419 DPRINTF(("Channel=%d Tx power=%d\n", 2420 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2421 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2422 DPRINTF(("Channel=%d Tx power=%d\n", 2423 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2424 } 2425 2426 /* read vendor-specific BBP values */ 2427 for (i = 0; i < 16; i++) { 2428 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2429 if (val == 0 || val == 0xffff) 2430 continue; /* skip invalid entries */ 2431 sc->bbp_prom[i].reg = val >> 8; 2432 sc->bbp_prom[i].val = val & 0xff; 2433 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2434 sc->bbp_prom[i].val)); 2435 } 2436} 2437 2438static int 2439rt2661_bbp_init(struct rt2661_softc *sc) 2440{ 2441#define N(a) (sizeof (a) / sizeof ((a)[0])) 2442 int i, ntries; 2443 uint8_t val; 2444 2445 /* wait for BBP to be ready */ 2446 for (ntries = 0; ntries < 100; ntries++) { 2447 val = rt2661_bbp_read(sc, 0); 2448 if (val != 0 && val != 0xff) 2449 break; 2450 DELAY(100); 2451 } 2452 if (ntries == 100) { 2453 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2454 return EIO; 2455 } 2456 2457 /* initialize BBP registers to default values */ 2458 for (i = 0; i < N(rt2661_def_bbp); i++) { 2459 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2460 rt2661_def_bbp[i].val); 2461 } 2462 2463 /* write vendor-specific BBP values (from EEPROM) */ 2464 for (i = 0; i < 16; i++) { 2465 if (sc->bbp_prom[i].reg == 0) 2466 continue; 2467 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2468 } 2469 2470 return 0; 2471#undef N 2472} 2473 2474static void 2475rt2661_init(void *priv) 2476{ 2477#define N(a) (sizeof (a) / sizeof ((a)[0])) 2478 struct rt2661_softc *sc = priv; 2479 struct ieee80211com *ic = &sc->sc_ic; 2480 struct ifnet *ifp = ic->ic_ifp; 2481 uint32_t tmp, sta[3]; 2482 int i, ntries; 2483 2484 RAL_LOCK(sc); 2485 2486 rt2661_stop(sc); 2487 2488 /* initialize Tx rings */ 2489 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2490 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2491 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2492 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2493 2494 /* initialize Mgt ring */ 2495 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2496 2497 /* initialize Rx ring */ 2498 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2499 2500 /* initialize Tx rings sizes */ 2501 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2502 RT2661_TX_RING_COUNT << 24 | 2503 RT2661_TX_RING_COUNT << 16 | 2504 RT2661_TX_RING_COUNT << 8 | 2505 RT2661_TX_RING_COUNT); 2506 2507 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2508 RT2661_TX_DESC_WSIZE << 16 | 2509 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2510 RT2661_MGT_RING_COUNT); 2511 2512 /* initialize Rx rings */ 2513 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2514 RT2661_RX_DESC_BACK << 16 | 2515 RT2661_RX_DESC_WSIZE << 8 | 2516 RT2661_RX_RING_COUNT); 2517 2518 /* XXX: some magic here */ 2519 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2520 2521 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2522 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2523 2524 /* load base address of Rx ring */ 2525 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2526 2527 /* initialize MAC registers to default values */ 2528 for (i = 0; i < N(rt2661_def_mac); i++) 2529 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2530 2531 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2532 rt2661_set_macaddr(sc, ic->ic_myaddr); 2533 2534 /* set host ready */ 2535 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2536 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2537 2538 /* wait for BBP/RF to wakeup */ 2539 for (ntries = 0; ntries < 1000; ntries++) { 2540 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2541 break; 2542 DELAY(1000); 2543 } 2544 if (ntries == 1000) { 2545 printf("timeout waiting for BBP/RF to wakeup\n"); 2546 rt2661_stop(sc); 2547 RAL_UNLOCK(sc); 2548 return; 2549 } 2550 2551 if (rt2661_bbp_init(sc) != 0) { 2552 rt2661_stop(sc); 2553 RAL_UNLOCK(sc); 2554 return; 2555 } 2556 2557 /* select default channel */ 2558 sc->sc_curchan = ic->ic_curchan; 2559 rt2661_select_band(sc, sc->sc_curchan); 2560 rt2661_select_antenna(sc); 2561 rt2661_set_chan(sc, sc->sc_curchan); 2562 2563 /* update Rx filter */ 2564 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2565 2566 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2567 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2568 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2569 RT2661_DROP_ACKCTS; 2570 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2571 tmp |= RT2661_DROP_TODS; 2572 if (!(ifp->if_flags & IFF_PROMISC)) 2573 tmp |= RT2661_DROP_NOT_TO_ME; 2574 } 2575 2576 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2577 2578 /* clear STA registers */ 2579 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2580 2581 /* initialize ASIC */ 2582 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2583 2584 /* clear any pending interrupt */ 2585 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2586 2587 /* enable interrupts */ 2588 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2589 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2590 2591 /* kick Rx */ 2592 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2593 2594 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2595 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2596 2597 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2598 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2599 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2600 } else 2601 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2602 2603 RAL_UNLOCK(sc); 2604#undef N 2605} 2606 2607void 2608rt2661_stop(void *priv) 2609{ 2610 struct rt2661_softc *sc = priv; 2611 struct ieee80211com *ic = &sc->sc_ic; 2612 struct ifnet *ifp = ic->ic_ifp; 2613 uint32_t tmp; 2614 2615 sc->sc_tx_timer = 0; 2616 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2617 2618 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2619 2620 /* abort Tx (for all 5 Tx rings) */ 2621 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2622 2623 /* disable Rx (value remains after reset!) */ 2624 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2625 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2626 2627 /* reset ASIC */ 2628 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2629 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2630 2631 /* disable interrupts */ 2632 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2633 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2634 2635 /* clear any pending interrupt */ 2636 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2637 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2638 2639 /* reset Tx and Rx rings */ 2640 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2641 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2642 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2643 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2644 rt2661_reset_tx_ring(sc, &sc->mgtq); 2645 rt2661_reset_rx_ring(sc, &sc->rxq); 2646} 2647 2648static int 2649rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2650{ 2651 int ntries; 2652 2653 /* reset 8051 */ 2654 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2655 2656 /* cancel any pending Host to MCU command */ 2657 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2658 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2659 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2660 2661 /* write 8051's microcode */ 2662 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2663 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2664 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2665 2666 /* kick 8051's ass */ 2667 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2668 2669 /* wait for 8051 to initialize */ 2670 for (ntries = 0; ntries < 500; ntries++) { 2671 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2672 break; 2673 DELAY(100); 2674 } 2675 if (ntries == 500) { 2676 printf("timeout waiting for MCU to initialize\n"); 2677 return EIO; 2678 } 2679 return 0; 2680} 2681 2682#ifdef notyet 2683/* 2684 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2685 * false CCA count. This function is called periodically (every seconds) when 2686 * in the RUN state. Values taken from the reference driver. 2687 */ 2688static void 2689rt2661_rx_tune(struct rt2661_softc *sc) 2690{ 2691 uint8_t bbp17; 2692 uint16_t cca; 2693 int lo, hi, dbm; 2694 2695 /* 2696 * Tuning range depends on operating band and on the presence of an 2697 * external low-noise amplifier. 2698 */ 2699 lo = 0x20; 2700 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2701 lo += 0x08; 2702 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2703 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2704 lo += 0x10; 2705 hi = lo + 0x20; 2706 2707 /* retrieve false CCA count since last call (clear on read) */ 2708 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2709 2710 if (dbm >= -35) { 2711 bbp17 = 0x60; 2712 } else if (dbm >= -58) { 2713 bbp17 = hi; 2714 } else if (dbm >= -66) { 2715 bbp17 = lo + 0x10; 2716 } else if (dbm >= -74) { 2717 bbp17 = lo + 0x08; 2718 } else { 2719 /* RSSI < -74dBm, tune using false CCA count */ 2720 2721 bbp17 = sc->bbp17; /* current value */ 2722 2723 hi -= 2 * (-74 - dbm); 2724 if (hi < lo) 2725 hi = lo; 2726 2727 if (bbp17 > hi) { 2728 bbp17 = hi; 2729 2730 } else if (cca > 512) { 2731 if (++bbp17 > hi) 2732 bbp17 = hi; 2733 } else if (cca < 100) { 2734 if (--bbp17 < lo) 2735 bbp17 = lo; 2736 } 2737 } 2738 2739 if (bbp17 != sc->bbp17) { 2740 rt2661_bbp_write(sc, 17, bbp17); 2741 sc->bbp17 = bbp17; 2742 } 2743} 2744 2745/* 2746 * Enter/Leave radar detection mode. 2747 * This is for 802.11h additional regulatory domains. 2748 */ 2749static void 2750rt2661_radar_start(struct rt2661_softc *sc) 2751{ 2752 uint32_t tmp; 2753 2754 /* disable Rx */ 2755 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2756 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2757 2758 rt2661_bbp_write(sc, 82, 0x20); 2759 rt2661_bbp_write(sc, 83, 0x00); 2760 rt2661_bbp_write(sc, 84, 0x40); 2761 2762 /* save current BBP registers values */ 2763 sc->bbp18 = rt2661_bbp_read(sc, 18); 2764 sc->bbp21 = rt2661_bbp_read(sc, 21); 2765 sc->bbp22 = rt2661_bbp_read(sc, 22); 2766 sc->bbp16 = rt2661_bbp_read(sc, 16); 2767 sc->bbp17 = rt2661_bbp_read(sc, 17); 2768 sc->bbp64 = rt2661_bbp_read(sc, 64); 2769 2770 rt2661_bbp_write(sc, 18, 0xff); 2771 rt2661_bbp_write(sc, 21, 0x3f); 2772 rt2661_bbp_write(sc, 22, 0x3f); 2773 rt2661_bbp_write(sc, 16, 0xbd); 2774 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2775 rt2661_bbp_write(sc, 64, 0x21); 2776 2777 /* restore Rx filter */ 2778 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2779} 2780 2781static int 2782rt2661_radar_stop(struct rt2661_softc *sc) 2783{ 2784 uint8_t bbp66; 2785 2786 /* read radar detection result */ 2787 bbp66 = rt2661_bbp_read(sc, 66); 2788 2789 /* restore BBP registers values */ 2790 rt2661_bbp_write(sc, 16, sc->bbp16); 2791 rt2661_bbp_write(sc, 17, sc->bbp17); 2792 rt2661_bbp_write(sc, 18, sc->bbp18); 2793 rt2661_bbp_write(sc, 21, sc->bbp21); 2794 rt2661_bbp_write(sc, 22, sc->bbp22); 2795 rt2661_bbp_write(sc, 64, sc->bbp64); 2796 2797 return bbp66 == 1; 2798} 2799#endif 2800 2801static int 2802rt2661_prepare_beacon(struct rt2661_softc *sc) 2803{ 2804 struct ieee80211com *ic = &sc->sc_ic; 2805 struct ieee80211_beacon_offsets bo; 2806 struct rt2661_tx_desc desc; 2807 struct mbuf *m0; 2808 int rate; 2809 2810 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 2811 if (m0 == NULL) { 2812 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2813 return ENOBUFS; 2814 } 2815 2816 /* send beacons at the lowest available rate */ 2817 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 2818 2819 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2820 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2821 2822 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2823 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2824 2825 /* copy beacon header and payload into NIC memory */ 2826 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2827 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2828 2829 m_freem(m0); 2830 2831 return 0; 2832} 2833 2834/* 2835 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2836 * and HostAP operating modes. 2837 */ 2838static void 2839rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2840{ 2841 struct ieee80211com *ic = &sc->sc_ic; 2842 uint32_t tmp; 2843 2844 if (ic->ic_opmode != IEEE80211_M_STA) { 2845 /* 2846 * Change default 16ms TBTT adjustment to 8ms. 2847 * Must be done before enabling beacon generation. 2848 */ 2849 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2850 } 2851 2852 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2853 2854 /* set beacon interval (in 1/16ms unit) */ 2855 tmp |= ic->ic_bss->ni_intval * 16; 2856 2857 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2858 if (ic->ic_opmode == IEEE80211_M_STA) 2859 tmp |= RT2661_TSF_MODE(1); 2860 else 2861 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2862 2863 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2864} 2865 2866/* 2867 * Retrieve the "Received Signal Strength Indicator" from the raw values 2868 * contained in Rx descriptors. The computation depends on which band the 2869 * frame was received. Correction values taken from the reference driver. 2870 */ 2871static int 2872rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2873{ 2874 int lna, agc, rssi; 2875 2876 lna = (raw >> 5) & 0x3; 2877 agc = raw & 0x1f; 2878 2879 rssi = 2 * agc; 2880 2881 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2882 rssi += sc->rssi_2ghz_corr; 2883 2884 if (lna == 1) 2885 rssi -= 64; 2886 else if (lna == 2) 2887 rssi -= 74; 2888 else if (lna == 3) 2889 rssi -= 90; 2890 } else { 2891 rssi += sc->rssi_5ghz_corr; 2892 2893 if (lna == 1) 2894 rssi -= 64; 2895 else if (lna == 2) 2896 rssi -= 86; 2897 else if (lna == 3) 2898 rssi -= 100; 2899 } 2900 return rssi; 2901} 2902