1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/spad_layout.h 337517 2018-08-09 01:17:35Z davidcs $ 28 * 29 */ 30 31/**************************************************************************** 32 * Name: spad_layout.h 33 * 34 * Description: Global definitions 35 * 36 * Created: 01/09/2013 37 * 38 ****************************************************************************/ 39/* 40 * Spad Layout NVM CFG MCP public 41 *========================================================================================================== 42 * MCP_REG_SCRATCH REG_RD(MISC_REG_GEN_PURP_CR0) REG_RD(MISC_REG_SHARED_MEM_ADDR) 43 * +------------------+ +-------------------------+ +-------------------+ 44 * | Num Sections(4B)|Currently 4 | Num Sections(4B) | | Num Sections(4B)|Currently 6 45 * +------------------+ +-------------------------+ +-------------------+ 46 * | Offsize(Trace) |4B -+ +-- | Offset(NVM_CFG1) | | Offsize(drv_mb) | 47 * +-| Offsize(NVM_CFG) |4B | | | (Size is fixed) | | Offsize(mfw_mb) | 48 *+-|-| Offsize(Public) |4B | +-> +-------------------------+ | Offsize(global) | 49 *| | | Offsize(Private) |4B | | | | Offsize(path) | 50 *| | +------------------+ <--+ | nvm_cfg1_glob | | Offsize(port) | 51 *| | | | +-------------------------+ | Offsize(func) | 52 *| | | Trace | | nvm_cfg1_path 0 | +-------------------+ 53 *| +>+------------------+ | nvm_cfg1_path 1 | | drv_mb PF0/2/4..|8 Funcs of engine0 54 *| | | +-------------------------+ | drv_mb PF1/3/5..|8 Funcs of engine1 55 *| | NVM_CFG | | nvm_cfg1_port 0 | +-------------------+ 56 *+-> +------------------+ | .... | | mfw_mb PF0/2/4..|8 Funcs of engine0 57 * | | | nvm_cfg1_port 3 | | mfw_mb PF1/3/5..|8 Funcs of engine1 58 * | Public Data | +-------------------------+ +-------------------+ 59 * +------------------+ 8 Funcs of Engine 0| nvm_cfg1_func PF0/2/4/..| | | 60 * | | 8 Funcs of Engine 1| nvm_cfg1_func PF1/3/5/..| | public_global | 61 * | Private Data | +-------------------------+ +-------------------+ 62 * +------------------+ | public_path 0 | 63 * | Code | | public_path 1 | 64 * | Static Area | +-------------------+ 65 * +--- ---+ | public_port 0 | 66 * | Code | | .... | 67 * | PIM Area | | public_port 3 | 68 * +------------------+ +-------------------+ 69 * | public_func 0/2/4.|8 Funcs of engine0 70 * | public_func 1/3/5.|8 Funcs of engine1 71 * +-------------------+ 72*/ 73#ifndef SPAD_LAYOUT_H 74#define SPAD_LAYOUT_H 75 76#ifndef MDUMP_PARSE_TOOL 77 78#define PORT_0 0 79#define PORT_1 1 80#define PORT_2 2 81#define PORT_3 3 82 83#include "mcp_public.h" 84#include "mfw_hsi.h" 85#include "nvm_cfg.h" 86 87#ifdef MFW 88#include "mcp_private.h" 89#endif 90 91extern struct spad_layout g_spad; 92 93/* TBD - Consider renaming to MCP_STATIC_SPAD_SIZE, since the real size includes another 64kb */ 94#define MCP_SPAD_SIZE 0x00028000 /* 160 KB */ 95 96#define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE)) 97#endif /* MDUMP_PARSE_TOOL */ 98 99#define TO_OFFSIZE(_offset, _size) \ 100 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_OFFSET) | \ 101 (((u32)(_size) >> 2) << OFFSIZE_SIZE_OFFSET)) 102 103enum spad_sections { 104 SPAD_SECTION_TRACE, 105 SPAD_SECTION_NVM_CFG, 106 SPAD_SECTION_PUBLIC, 107 SPAD_SECTION_PRIVATE, 108 SPAD_SECTION_MAX /* Cannot be modified anymore since ROM relying on this size !! */ 109}; 110 111#ifndef MDUMP_PARSE_TOOL 112struct spad_layout { 113 struct nvm_cfg nvm_cfg; 114 struct mcp_public_data public_data; 115#ifdef MFW /* Drivers will not be compiled with this flag. */ 116 /* Linux should remove this appearance at all. */ 117 struct mcp_private_data private_data; 118#endif 119}; 120 121#endif /* MDUMP_PARSE_TOOL */ 122 123 124#define STRUCT_OFFSET(f) (STATIC_INIT_BASE + __builtin_offsetof(struct static_init, f)) 125 126/* This section is located at a fixed location in the beginning of the scratchpad, 127 * to ensure that the MCP trace is not run over during MFW upgrade. 128 * All the rest of data has a floating location which differs from version to version, 129 * and is pointed by the mcp_meta_data below. 130 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded with it 131 * from nvram in order to clear this portion. 132 */ 133 134struct static_init { 135 136 u32 num_sections; /* 0xe20000 */ 137 offsize_t sections[SPAD_SECTION_MAX]; /* 0xe20004 */ 138#define SECTION(_sec_) *((offsize_t*)(STRUCT_OFFSET(sections[_sec_]))) 139 140#ifdef SECURE_BOOT 141 u32 tim_sha256[8]; /* Used by E5 ROM. Do not relocate */ 142 u32 rom_status_code; /* Used by E5 ROM. Do not relocate */ 143 u32 secure_running_mfw; /* Instead of the one after the trace_buffer */ /* Used by E5 ROM. Do not relocate */ 144#define SECURE_RUNNING_MFW *((u32*)(STRUCT_OFFSET(secure_running_mfw))) 145#endif 146 147 struct mcp_trace trace; /* 0xe20014 */ 148 149#ifdef MFW 150#define MCP_TRACE_P ((struct mcp_trace*)(STRUCT_OFFSET(trace))) 151 u8 trace_buffer[MCP_TRACE_SIZE]; /* 0xe20030 */ 152#define MCP_TRACE_BUF ((u8*)(STRUCT_OFFSET(trace_buffer))) 153 /* running_mfw has the same definition as in nvm_map.h. 154 * This bit indicate both the running dir, and the running bundle. 155 * It is set once when the LIM is loaded. 156 */ 157 u32 running_mfw; /* 0xe20830 */ 158#define RUNNING_MFW *((u32*)(STRUCT_OFFSET(running_mfw))) 159 u32 build_time; /* 0xe20834 */ 160#define MFW_BUILD_TIME *((u32*)(STRUCT_OFFSET(build_time))) 161 u32 reset_type; /* 0xe20838 */ 162#define RESET_TYPE *((u32*)(STRUCT_OFFSET(reset_type))) 163 u32 mfw_secure_mode; /* 0xe2083c */ 164#define MFW_SECURE_MODE *((u32*)(STRUCT_OFFSET(mfw_secure_mode))) 165 u16 pme_status_pf_bitmap; /* 0xe20840 */ 166#define PME_STATUS_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_status_pf_bitmap))) 167 u16 pme_enable_pf_bitmap; 168#define PME_ENABLE_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_enable_pf_bitmap))) 169 u32 mim_nvm_addr; /* 0xe20844 */ 170 u32 mim_start_addr; /* 0xe20848 */ 171 u32 ah_pcie_link_params; /* 0xe20850 Stores PCIe link configuration at start, so they can be used later also for Hot-Reset, without the need to re-reading them from nvm cfg. */ 172#define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff) 173#define AH_PCIE_LINK_PARAMS_LINK_SPEED_OFFSET (0) 174#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00) 175#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_OFFSET (8) 176#define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000) 177#define AH_PCIE_LINK_PARAMS_ASPM_MODE_OFFSET (16) 178#define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000) 179#define AH_PCIE_LINK_PARAMS_ASPM_CAP_OFFSET (24) 180#define AH_PCIE_LINK_PARAMS *((u32*)(STRUCT_OFFSET(ah_pcie_link_params))) 181 182 u32 flags; /* 0xe20850 */ 183#define M_GLOB_FLAGS *((u32*)(STRUCT_OFFSET(flags))) 184#define FLAGS_VAUX_REQUIRED (1 << 0) 185#define FLAGS_WAIT_AVS_READY (1 << 1) 186#define FLAGS_FAILURE_ISSUED (1 << 2) 187#define FLAGS_FAILURE_DETECTED (1 << 3) 188#define FLAGS_VAUX (1 << 4) 189#define FLAGS_PERST_ASSERT_OCCURED (1 << 5) 190#define FLAGS_HOT_RESET_STEP2 (1 << 6) 191#define FLAGS_MSIX_SYNC_ALLOWED (1 << 7) 192#define FLAGS_PROGRAM_PCI_COMPLETED (1 << 8) 193#define FLAGS_SMBUS_AUX_MODE (1 << 9) 194#define FLAGS_PEND_SMBUS_VMAIN_TO_AUX (1 << 10) 195#define FLAGS_NVM_CFG_EFUSE_FAILURE (1 << 11) 196#define FLAGS_POWER_TRANSITION (1 << 12) 197#define FLAGS_MCTP_CHECK_PUMA_TIMEOUT (1 << 13) 198#define FLAGS_MCTP_TX_PLDM_UPDATE (1 << 14) 199#define FLAGS_MCTP_SENSOR_EVENT (1 << 15) 200#define FLAGS_PMBUS_ERROR (1 << 28) 201#define FLAGS_OS_DRV_LOADED (1 << 29) 202#define FLAGS_OVER_TEMP_OCCUR (1 << 30) 203#define FLAGS_FAN_FAIL_OCCUR (1 << 31) 204 u32 rsrv_persist[4]; /* Persist reserved for MFW upgrades */ /* 0xe20854 */ 205#endif /* MFW */ 206}; 207 208#ifndef MDUMP_PARSE_TOOL 209#define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x 210#define NVM_GLOB(x) NVM_CFG1(glob).x 211#define NVM_GLOB_VAL(n, m, o) ((NVM_GLOB(n) & m) >> o) 212#endif /* MDUMP_PARSE_TOOL */ 213 214#endif /* SPAD_LAYOUT_H */ 215