1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/nvm_map.h 337517 2018-08-09 01:17:35Z davidcs $ 28 * 29 */ 30 31 32/**************************************************************************** 33 * Name: nvm_map.h 34 * 35 * Description: Everest NVRAM map 36 * 37 ****************************************************************************/ 38 39#ifndef NVM_MAP_H 40#define NVM_MAP_H 41 42#define CRC_MAGIC_VALUE 0xDEBB20E3 43#define CRC32_POLYNOMIAL 0xEDB88320 44#define _KB(x) (x*1024) 45#define _MB(x) (_KB(x)*1024) 46#define NVM_CRC_SIZE (sizeof(u32)) 47enum nvm_sw_arbitrator { 48 NVM_SW_ARB_HOST, 49 NVM_SW_ARB_MCP, 50 NVM_SW_ARB_UART, 51 NVM_SW_ARB_RESERVED 52}; 53 54/**************************************************************************** 55 * Boot Strap Region * 56 ****************************************************************************/ 57struct legacy_bootstrap_region { 58 u32 magic_value; /* a pattern not likely to occur randomly */ 59#define NVM_MAGIC_VALUE 0x669955aa 60 u32 sram_start_addr; /* where to locate LIM code (byte addr) */ 61 u32 code_len; /* boot code length (in dwords) */ 62 u32 code_start_addr; /* location of code on media (media byte addr) */ 63 u32 crc; /* 32-bit CRC */ 64}; 65 66/**************************************************************************** 67 * Directories Region * 68 ****************************************************************************/ 69struct nvm_code_entry { 70 u32 image_type; /* Image type */ 71 u32 nvm_start_addr; /* NVM address of the image */ 72 u32 len; /* Include CRC */ 73 u32 sram_start_addr; /* Where to load the image on the scratchpad */ 74 u32 sram_run_addr; /* Relevant in case of MIM only */ 75}; 76 77enum nvm_image_type { 78 NVM_TYPE_TIM1 = 0x01, 79 NVM_TYPE_TIM2 = 0x02, 80 NVM_TYPE_MIM1 = 0x03, 81 NVM_TYPE_MIM2 = 0x04, 82 NVM_TYPE_MBA = 0x05, 83 NVM_TYPE_MODULES_PN = 0x06, 84 NVM_TYPE_VPD = 0x07, 85 NVM_TYPE_MFW_TRACE1 = 0x08, 86 NVM_TYPE_MFW_TRACE2 = 0x09, 87 NVM_TYPE_NVM_CFG1 = 0x0a, 88 NVM_TYPE_L2B = 0x0b, 89 NVM_TYPE_DIR1 = 0x0c, 90 NVM_TYPE_EAGLE_FW1 = 0x0d, 91 NVM_TYPE_FALCON_FW1 = 0x0e, 92 NVM_TYPE_PCIE_FW1 = 0x0f, 93 NVM_TYPE_HW_SET = 0x10, 94 NVM_TYPE_LIM = 0x11, 95 NVM_TYPE_AVS_FW1 = 0x12, 96 NVM_TYPE_DIR2 = 0x13, 97 NVM_TYPE_CCM = 0x14, 98 NVM_TYPE_EAGLE_FW2 = 0x15, 99 NVM_TYPE_FALCON_FW2 = 0x16, 100 NVM_TYPE_PCIE_FW2 = 0x17, 101 NVM_TYPE_AVS_FW2 = 0x18, 102 NVM_TYPE_INIT_HW = 0x19, 103 NVM_TYPE_DEFAULT_CFG= 0x1a, 104 NVM_TYPE_MDUMP = 0x1b, 105 NVM_TYPE_NVM_META = 0x1c, 106 NVM_TYPE_ISCSI_CFG = 0x1d, 107 NVM_TYPE_FCOE_CFG = 0x1f, 108 NVM_TYPE_ETH_PHY_FW1 = 0x20, 109 NVM_TYPE_ETH_PHY_FW2 = 0x21, 110 NVM_TYPE_BDN = 0x22, 111 NVM_TYPE_8485X_PHY_FW = 0x23, 112 NVM_TYPE_PUB_KEY = 0x24, 113 NVM_TYPE_RECOVERY = 0x25, 114 NVM_TYPE_PLDM = 0x26, 115 NVM_TYPE_UPK1 = 0x27, 116 NVM_TYPE_UPK2 = 0x28, 117 NVM_TYPE_MASTER_KC = 0x29, 118 NVM_TYPE_BACKUP_KC = 0x2a, 119 NVM_TYPE_ROM_TEST = 0xf0, 120 NVM_TYPE_MAX, 121}; 122 123#ifdef DEFINE_IMAGE_TABLE 124struct image_map { 125 char name[32]; 126 char option[32]; 127 u32 image_type; 128}; 129 130struct image_map g_image_table[] = { 131 {"TIM1", "-tim1", NVM_TYPE_TIM1}, 132 {"TIM2", "-tim2", NVM_TYPE_TIM2}, 133 {"MIM1", "-mim1", NVM_TYPE_MIM1}, 134 {"MIM2", "-mim2", NVM_TYPE_MIM2}, 135 {"MBA", "-mba", NVM_TYPE_MBA}, 136 {"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN}, 137 {"VPD", "-vpd", NVM_TYPE_VPD}, 138 {"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1}, 139 {"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2}, 140 {"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1}, 141 {"L2B", "-l2b", NVM_TYPE_L2B}, 142 {"DIR1", "-dir1", NVM_TYPE_DIR1}, 143 {"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1}, 144 {"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1}, 145 {"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1}, 146 {"HW_SET", "-hw_set", NVM_TYPE_HW_SET}, 147 {"LIM", "-lim", NVM_TYPE_LIM}, 148 {"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1}, 149 {"DIR2", "-dir2", NVM_TYPE_DIR2}, 150 {"CCM", "-ccm", NVM_TYPE_CCM}, 151 {"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2}, 152 {"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2}, 153 {"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2}, 154 {"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2}, 155 {"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW}, 156 {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG}, 157 {"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP}, 158 {"META", "-meta", NVM_TYPE_NVM_META}, 159 {"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG}, 160 {"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG}, 161 {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1}, 162 {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2}, 163 {"BDN", "-bdn", NVM_TYPE_BDN}, 164 {"PK", "-pk", NVM_TYPE_PUB_KEY}, 165 {"RECOVERY", "-recovery",NVM_TYPE_RECOVERY}, 166 {"PLDM", "-pldm", NVM_TYPE_PLDM}, 167 {"UPK1", "-upk1", NVM_TYPE_UPK1}, 168 {"UPK2", "-upk2", NVM_TYPE_UPK2}, 169 {"ROMTEST", "-romtest" ,NVM_TYPE_ROM_TEST}, 170 {"MASTER_KC", "-kc" ,NVM_TYPE_MASTER_KC}, 171 {"BACKUP_KC", "" ,NVM_TYPE_BACKUP_KC} 172}; 173 174#define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map)) 175 176#endif /* #ifdef DEFINE_IMAGE_TABLE */ 177#define MAX_NVM_DIR_ENTRIES 150 178/* Note: The has given 150 possible entries since anyway each file captures at least one page. */ 179 180struct nvm_dir_meta { 181 u32 dir_id; 182 u32 nvm_dir_addr; 183 u32 num_images; 184 u32 next_mfw_to_run; 185}; 186 187struct nvm_dir { 188 s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */ 189#define NVM_DIR_NEXT_MFW_MASK 0x00000001 190#define NVM_DIR_SEQ_MASK 0xfffffffe 191#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK) 192#define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \ 193 do { \ 194 _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \ 195 } while (0) 196#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK) 197 198 u32 num_images; 199 u32 rsrv; 200 struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */ 201}; 202#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE) 203 204struct nvm_vpd_image { 205 u32 format_revision; 206#define VPD_IMAGE_VERSION 1 207 208 /* This array length depends on the number of VPD fields */ 209 u8 vpd_data[1]; 210}; 211 212/**************************************************************************** 213 * NVRAM FULL MAP * 214 ****************************************************************************/ 215#define DIR_ID_1 (0) 216#define DIR_ID_2 (1) 217#define MAX_DIR_IDS (2) 218 219#define MFW_BUNDLE_1 (0) 220#define MFW_BUNDLE_2 (1) 221#define MAX_MFW_BUNDLES (2) 222 223#define FLASH_PAGE_SIZE 0x1000 224#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */ 225#define LEGACY_ASIC_MIM_MAX_SIZE (_KB(1200)) /* 1.2Mb - E4*/ 226#define NG_ASIC_MIM_MAX_SIZE (_MB(2)) /* 2Mb - E5 */ 227 228#define FPGA_MIM_MAX_SIZE (0x3E000) /* 250Kb */ 229 230/* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page. 231 * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it. 232 */ 233#define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE) 234#define LIM_OFFSET (NVM_OFFSET(lim_image)) 235#define NVM_RSV_SIZE (44) 236#define GET_MIM_MAX_SIZE(is_asic, is_e4) ((!is_asic) ? FPGA_MIM_MAX_SIZE : ((is_e4) ? LEGACY_ASIC_MIM_MAX_SIZE : NG_ASIC_MIM_MAX_SIZE)) 237#define GET_MIM_OFFSET(idx, is_asic, is_e4) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ?GET_MIM_MAX_SIZE(is_asic, is_e4) : 0)) 238#define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4) (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(is_asic, is_e4)*2) 239 240#define EMUL_NVM_FIXED_AREA_SIZE() (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(0, 0)) 241 242#define E5_MASTER_KEY_CHAIN_ADDR 0x1000 243#define E5_BACKUP_KEY_CHAIN_ADDR ((0x20000 << (REG_READ(0, MCP_REG_NVM_CFG4) & 0x7)) - 0x1000) 244 245union nvm_dir_union { 246 struct nvm_dir dir; 247 u8 page[FLASH_PAGE_SIZE]; 248}; 249 250/* E4 Address E5 Address 251 * +-------------------+ 0x000000 * +-------------------+ 0x000000 252 * | Bootstrap: | * | | 253 * | magic_number | * | | 254 * | sram_start_addr | * | | 255 * | code_len | * | | 256 * | code_start_addr | * | | 257 * | crc | * | | 258 * +-------------------+ 0x000014 * | | 259 * | rsrv | * | rsrv | 260 * +-------------------+ 0x000040 * +-------------------+ 0x001000 261 * | LIM | * | Master Key Chain | 262 * +-------------------+ 0x002000 * +-------------------+ 0x002000 263 * | Dir1 | * | Dir1 | 264 * +-------------------+ 0x003000 * +-------------------+ 0x003000 265 * | Dir2 | * | Dir2 | 266 * +-------------------+ 0x004000 * +-------------------+ 0x004000 267 * | MIM1 | * | MIM1 | 268 * +-------------------+ 0x130000 * +-------------------+ 0x130000 269 * | MIM2 | * | MIM2 | 270 * +-------------------+ 0x25C000 * +-------------------+ 0x25C000 271 * | Rest Images: | * | Rest Images: | 272 * | TIM1/2 | * | TIM1/2 | 273 * | MFW_TRACE1/2 | * | MFW_TRACE1/2 | 274 * | Eagle/Falcon FW | * | Eagle/Falcon FW | 275 * | PCIE/AVS FW | * | PCIE/AVS FW | 276 * | MBA/CCM/L2B | * | MBA/CCM/L2B | 277 * | VPD | * | VPD | 278 * | optic_modules | * +-------------------+ Flash end - 0x1000 279 * | ... | * | Backup Key Chain | 280 * +-------------------+ 0x400000 * +-------------------+ Flash end 281*/ 282struct nvm_image { 283/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 284 /* NVM Offset (size) */ 285 struct legacy_bootstrap_region bootstrap; /* 0x000000 (0x000014) */ 286 u8 rsrv[NVM_RSV_SIZE]; /* 0x000014 (0x00002c) */ 287 u8 lim_image[LIM_MAX_SIZE]; /* 0x000040 (0x001fc0) */ 288 union nvm_dir_union dir[MAX_MFW_BUNDLES]; /* 0x002000 (0x001000)x2 */ 289 /* MIM1_IMAGE 0x004000 (0x12c000) */ 290 /* MIM2_IMAGE 0x130000 (0x12c000) */ 291/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 292}; /* 0x134 */ 293 294#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f)))) 295 296 297struct hw_set_info { 298 u32 reg_type; 299#define GRC_REG_TYPE 1 300#define PHY_REG_TYPE 2 301#define PCI_REG_TYPE 4 302 303 u32 bank_num; 304 u32 pf_num; 305 u32 operation; 306#define READ_OP 1 307#define WRITE_OP 2 308#define RMW_SET_OP 3 309#define RMW_CLR_OP 4 310 311 u32 reg_addr; 312 u32 reg_data; 313 314 u32 reset_type; 315#define POR_RESET_TYPE (1 << 0) 316#define HARD_RESET_TYPE (1 << 1) 317#define CORE_RESET_TYPE (1 << 2) 318#define MCP_RESET_TYPE (1 << 3) 319#define PERSET_ASSERT (1 << 4) 320#define PERSET_DEASSERT (1 << 5) 321 322}; 323 324struct hw_set_image { 325 u32 format_version; 326#define HW_SET_IMAGE_VERSION 1 327 u32 no_hw_sets; 328 /* This array length depends on the no_hw_sets */ 329 struct hw_set_info hw_sets[1]; 330}; 331 332#endif //NVM_MAP_H 333