1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/ecore_hsi_init_tool.h 337517 2018-08-09 01:17:35Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs 32316485Sdavidcs#ifndef __ECORE_HSI_INIT_TOOL__ 33316485Sdavidcs#define __ECORE_HSI_INIT_TOOL__ 34316485Sdavidcs/**************************************/ 35316485Sdavidcs/* Init Tool HSI constants and macros */ 36316485Sdavidcs/**************************************/ 37316485Sdavidcs 38316485Sdavidcs/* Width of GRC address in bits (addresses are specified in dwords) */ 39316485Sdavidcs#define GRC_ADDR_BITS 23 40316485Sdavidcs#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 41316485Sdavidcs 42316485Sdavidcs/* indicates an init that should be applied to any phase ID */ 43316485Sdavidcs#define ANY_PHASE_ID 0xffff 44316485Sdavidcs 45316485Sdavidcs/* Max size in dwords of a zipped array */ 46316485Sdavidcs#define MAX_ZIPPED_SIZE 8192 47316485Sdavidcs 48316485Sdavidcs 49316485Sdavidcsenum chip_ids 50316485Sdavidcs{ 51316485Sdavidcs CHIP_BB, 52316485Sdavidcs CHIP_K2, 53316485Sdavidcs CHIP_E5, 54316485Sdavidcs MAX_CHIP_IDS 55316485Sdavidcs}; 56316485Sdavidcs 57316485Sdavidcs 58316485Sdavidcsenum init_modes 59316485Sdavidcs{ 60316485Sdavidcs MODE_BB_A0_DEPRECATED, 61316485Sdavidcs MODE_BB, 62316485Sdavidcs MODE_K2, 63316485Sdavidcs MODE_ASIC, 64316485Sdavidcs MODE_EMUL_REDUCED, 65316485Sdavidcs MODE_EMUL_FULL, 66316485Sdavidcs MODE_FPGA, 67316485Sdavidcs MODE_CHIPSIM, 68316485Sdavidcs MODE_SF, 69316485Sdavidcs MODE_MF_SD, 70316485Sdavidcs MODE_MF_SI, 71316485Sdavidcs MODE_PORTS_PER_ENG_1, 72316485Sdavidcs MODE_PORTS_PER_ENG_2, 73316485Sdavidcs MODE_PORTS_PER_ENG_4, 74316485Sdavidcs MODE_100G, 75316485Sdavidcs MODE_E5, 76316485Sdavidcs MAX_INIT_MODES 77316485Sdavidcs}; 78316485Sdavidcs 79316485Sdavidcs 80316485Sdavidcsenum init_phases 81316485Sdavidcs{ 82316485Sdavidcs PHASE_ENGINE, 83316485Sdavidcs PHASE_PORT, 84316485Sdavidcs PHASE_PF, 85316485Sdavidcs PHASE_VF, 86316485Sdavidcs PHASE_QM_PF, 87316485Sdavidcs MAX_INIT_PHASES 88316485Sdavidcs}; 89316485Sdavidcs 90316485Sdavidcs 91316485Sdavidcsenum init_split_types 92316485Sdavidcs{ 93316485Sdavidcs SPLIT_TYPE_NONE, 94316485Sdavidcs SPLIT_TYPE_PORT, 95316485Sdavidcs SPLIT_TYPE_PF, 96316485Sdavidcs SPLIT_TYPE_PORT_PF, 97316485Sdavidcs SPLIT_TYPE_VF, 98316485Sdavidcs MAX_INIT_SPLIT_TYPES 99316485Sdavidcs}; 100316485Sdavidcs 101316485Sdavidcs 102316485Sdavidcs/* 103316485Sdavidcs * Binary buffer header 104316485Sdavidcs */ 105316485Sdavidcsstruct bin_buffer_hdr 106316485Sdavidcs{ 107337517Sdavidcs u32 offset /* buffer offset in bytes from the beginning of the binary file */; 108337517Sdavidcs u32 length /* buffer length in bytes */; 109316485Sdavidcs}; 110316485Sdavidcs 111316485Sdavidcs 112316485Sdavidcs/* 113316485Sdavidcs * binary init buffer types 114316485Sdavidcs */ 115316485Sdavidcsenum bin_init_buffer_type 116316485Sdavidcs{ 117316485Sdavidcs BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */, 118316485Sdavidcs BIN_BUF_INIT_CMD /* init commands */, 119316485Sdavidcs BIN_BUF_INIT_VAL /* init data */, 120316485Sdavidcs BIN_BUF_INIT_MODE_TREE /* init modes tree */, 121316485Sdavidcs BIN_BUF_INIT_IRO /* internal RAM offsets */, 122316485Sdavidcs MAX_BIN_INIT_BUFFER_TYPE 123316485Sdavidcs}; 124316485Sdavidcs 125316485Sdavidcs 126316485Sdavidcs/* 127316485Sdavidcs * init array header: raw 128316485Sdavidcs */ 129316485Sdavidcsstruct init_array_raw_hdr 130316485Sdavidcs{ 131337517Sdavidcs u32 data; 132316485Sdavidcs#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 133316485Sdavidcs#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 134316485Sdavidcs#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 135316485Sdavidcs#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 136316485Sdavidcs}; 137316485Sdavidcs 138316485Sdavidcs/* 139316485Sdavidcs * init array header: standard 140316485Sdavidcs */ 141316485Sdavidcsstruct init_array_standard_hdr 142316485Sdavidcs{ 143337517Sdavidcs u32 data; 144316485Sdavidcs#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 145316485Sdavidcs#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 146316485Sdavidcs#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 147316485Sdavidcs#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 148316485Sdavidcs}; 149316485Sdavidcs 150316485Sdavidcs/* 151316485Sdavidcs * init array header: zipped 152316485Sdavidcs */ 153316485Sdavidcsstruct init_array_zipped_hdr 154316485Sdavidcs{ 155337517Sdavidcs u32 data; 156316485Sdavidcs#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 157316485Sdavidcs#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 158316485Sdavidcs#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 159316485Sdavidcs#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 160316485Sdavidcs}; 161316485Sdavidcs 162316485Sdavidcs/* 163316485Sdavidcs * init array header: pattern 164316485Sdavidcs */ 165316485Sdavidcsstruct init_array_pattern_hdr 166316485Sdavidcs{ 167337517Sdavidcs u32 data; 168316485Sdavidcs#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 169316485Sdavidcs#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 170316485Sdavidcs#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 171316485Sdavidcs#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 172316485Sdavidcs#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 173316485Sdavidcs#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 174316485Sdavidcs}; 175316485Sdavidcs 176316485Sdavidcs/* 177316485Sdavidcs * init array header union 178316485Sdavidcs */ 179316485Sdavidcsunion init_array_hdr 180316485Sdavidcs{ 181316485Sdavidcs struct init_array_raw_hdr raw /* raw init array header */; 182316485Sdavidcs struct init_array_standard_hdr standard /* standard init array header */; 183316485Sdavidcs struct init_array_zipped_hdr zipped /* zipped init array header */; 184316485Sdavidcs struct init_array_pattern_hdr pattern /* pattern init array header */; 185316485Sdavidcs}; 186316485Sdavidcs 187316485Sdavidcs 188316485Sdavidcs 189316485Sdavidcs 190316485Sdavidcs 191316485Sdavidcs/* 192316485Sdavidcs * init array types 193316485Sdavidcs */ 194316485Sdavidcsenum init_array_types 195316485Sdavidcs{ 196316485Sdavidcs INIT_ARR_STANDARD /* standard init array */, 197316485Sdavidcs INIT_ARR_ZIPPED /* zipped init array */, 198316485Sdavidcs INIT_ARR_PATTERN /* a repeated pattern */, 199316485Sdavidcs MAX_INIT_ARRAY_TYPES 200316485Sdavidcs}; 201316485Sdavidcs 202316485Sdavidcs 203316485Sdavidcs 204316485Sdavidcs/* 205316485Sdavidcs * init operation: callback 206316485Sdavidcs */ 207316485Sdavidcsstruct init_callback_op 208316485Sdavidcs{ 209337517Sdavidcs u32 op_data; 210316485Sdavidcs#define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 211316485Sdavidcs#define INIT_CALLBACK_OP_OP_SHIFT 0 212316485Sdavidcs#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 213316485Sdavidcs#define INIT_CALLBACK_OP_RESERVED_SHIFT 4 214337517Sdavidcs u16 callback_id /* Callback ID */; 215337517Sdavidcs u16 block_id /* Blocks ID */; 216316485Sdavidcs}; 217316485Sdavidcs 218316485Sdavidcs 219316485Sdavidcs/* 220316485Sdavidcs * init operation: delay 221316485Sdavidcs */ 222316485Sdavidcsstruct init_delay_op 223316485Sdavidcs{ 224337517Sdavidcs u32 op_data; 225316485Sdavidcs#define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 226316485Sdavidcs#define INIT_DELAY_OP_OP_SHIFT 0 227316485Sdavidcs#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 228316485Sdavidcs#define INIT_DELAY_OP_RESERVED_SHIFT 4 229337517Sdavidcs u32 delay /* delay in us */; 230316485Sdavidcs}; 231316485Sdavidcs 232316485Sdavidcs 233316485Sdavidcs/* 234316485Sdavidcs * init operation: if_mode 235316485Sdavidcs */ 236316485Sdavidcsstruct init_if_mode_op 237316485Sdavidcs{ 238337517Sdavidcs u32 op_data; 239316485Sdavidcs#define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 240316485Sdavidcs#define INIT_IF_MODE_OP_OP_SHIFT 0 241316485Sdavidcs#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 242316485Sdavidcs#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 243316485Sdavidcs#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 244316485Sdavidcs#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 245337517Sdavidcs u16 reserved2; 246337517Sdavidcs u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 247316485Sdavidcs}; 248316485Sdavidcs 249316485Sdavidcs 250316485Sdavidcs/* 251316485Sdavidcs * init operation: if_phase 252316485Sdavidcs */ 253316485Sdavidcsstruct init_if_phase_op 254316485Sdavidcs{ 255337517Sdavidcs u32 op_data; 256316485Sdavidcs#define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 257316485Sdavidcs#define INIT_IF_PHASE_OP_OP_SHIFT 0 258316485Sdavidcs#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 259316485Sdavidcs#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 260316485Sdavidcs#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 261316485Sdavidcs#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 262316485Sdavidcs#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 263316485Sdavidcs#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 264337517Sdavidcs u32 phase_data; 265316485Sdavidcs#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 266316485Sdavidcs#define INIT_IF_PHASE_OP_PHASE_SHIFT 0 267316485Sdavidcs#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 268316485Sdavidcs#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 269316485Sdavidcs#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 270316485Sdavidcs#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 271316485Sdavidcs}; 272316485Sdavidcs 273316485Sdavidcs 274316485Sdavidcs/* 275316485Sdavidcs * init mode operators 276316485Sdavidcs */ 277316485Sdavidcsenum init_mode_ops 278316485Sdavidcs{ 279316485Sdavidcs INIT_MODE_OP_NOT /* init mode not operator */, 280316485Sdavidcs INIT_MODE_OP_OR /* init mode or operator */, 281316485Sdavidcs INIT_MODE_OP_AND /* init mode and operator */, 282316485Sdavidcs MAX_INIT_MODE_OPS 283316485Sdavidcs}; 284316485Sdavidcs 285316485Sdavidcs 286316485Sdavidcs/* 287316485Sdavidcs * init operation: raw 288316485Sdavidcs */ 289316485Sdavidcsstruct init_raw_op 290316485Sdavidcs{ 291337517Sdavidcs u32 op_data; 292316485Sdavidcs#define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 293316485Sdavidcs#define INIT_RAW_OP_OP_SHIFT 0 294316485Sdavidcs#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 295316485Sdavidcs#define INIT_RAW_OP_PARAM1_SHIFT 4 296337517Sdavidcs u32 param2 /* Init param 2 */; 297316485Sdavidcs}; 298316485Sdavidcs 299316485Sdavidcs/* 300316485Sdavidcs * init array params 301316485Sdavidcs */ 302316485Sdavidcsstruct init_op_array_params 303316485Sdavidcs{ 304337517Sdavidcs u16 size /* array size in dwords */; 305337517Sdavidcs u16 offset /* array start offset in dwords */; 306316485Sdavidcs}; 307316485Sdavidcs 308316485Sdavidcs/* 309316485Sdavidcs * Write init operation arguments 310316485Sdavidcs */ 311316485Sdavidcsunion init_write_args 312316485Sdavidcs{ 313337517Sdavidcs u32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 314337517Sdavidcs u32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 315337517Sdavidcs u32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 316316485Sdavidcs struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 317316485Sdavidcs}; 318316485Sdavidcs 319316485Sdavidcs/* 320316485Sdavidcs * init operation: write 321316485Sdavidcs */ 322316485Sdavidcsstruct init_write_op 323316485Sdavidcs{ 324337517Sdavidcs u32 data; 325316485Sdavidcs#define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 326316485Sdavidcs#define INIT_WRITE_OP_OP_SHIFT 0 327316485Sdavidcs#define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 328316485Sdavidcs#define INIT_WRITE_OP_SOURCE_SHIFT 4 329316485Sdavidcs#define INIT_WRITE_OP_RESERVED_MASK 0x1 330316485Sdavidcs#define INIT_WRITE_OP_RESERVED_SHIFT 7 331316485Sdavidcs#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 332316485Sdavidcs#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 333316485Sdavidcs#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 334316485Sdavidcs#define INIT_WRITE_OP_ADDRESS_SHIFT 9 335316485Sdavidcs union init_write_args args /* Write init operation arguments */; 336316485Sdavidcs}; 337316485Sdavidcs 338316485Sdavidcs/* 339316485Sdavidcs * init operation: read 340316485Sdavidcs */ 341316485Sdavidcsstruct init_read_op 342316485Sdavidcs{ 343337517Sdavidcs u32 op_data; 344316485Sdavidcs#define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 345316485Sdavidcs#define INIT_READ_OP_OP_SHIFT 0 346316485Sdavidcs#define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 347316485Sdavidcs#define INIT_READ_OP_POLL_TYPE_SHIFT 4 348316485Sdavidcs#define INIT_READ_OP_RESERVED_MASK 0x1 349316485Sdavidcs#define INIT_READ_OP_RESERVED_SHIFT 8 350316485Sdavidcs#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 351316485Sdavidcs#define INIT_READ_OP_ADDRESS_SHIFT 9 352337517Sdavidcs u32 expected_val /* expected polling value, used only when polling is done */; 353316485Sdavidcs}; 354316485Sdavidcs 355316485Sdavidcs/* 356316485Sdavidcs * Init operations union 357316485Sdavidcs */ 358316485Sdavidcsunion init_op 359316485Sdavidcs{ 360316485Sdavidcs struct init_raw_op raw /* raw init operation */; 361316485Sdavidcs struct init_write_op write /* write init operation */; 362316485Sdavidcs struct init_read_op read /* read init operation */; 363316485Sdavidcs struct init_if_mode_op if_mode /* if_mode init operation */; 364316485Sdavidcs struct init_if_phase_op if_phase /* if_phase init operation */; 365316485Sdavidcs struct init_callback_op callback /* callback init operation */; 366316485Sdavidcs struct init_delay_op delay /* delay init operation */; 367316485Sdavidcs}; 368316485Sdavidcs 369316485Sdavidcs 370316485Sdavidcs 371316485Sdavidcs/* 372316485Sdavidcs * Init command operation types 373316485Sdavidcs */ 374316485Sdavidcsenum init_op_types 375316485Sdavidcs{ 376316485Sdavidcs INIT_OP_READ /* GRC read init command */, 377316485Sdavidcs INIT_OP_WRITE /* GRC write init command */, 378316485Sdavidcs INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 379316485Sdavidcs INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 380316485Sdavidcs INIT_OP_DELAY /* delay init command */, 381316485Sdavidcs INIT_OP_CALLBACK /* callback init command */, 382316485Sdavidcs MAX_INIT_OP_TYPES 383316485Sdavidcs}; 384316485Sdavidcs 385316485Sdavidcs 386316485Sdavidcs/* 387316485Sdavidcs * init polling types 388316485Sdavidcs */ 389316485Sdavidcsenum init_poll_types 390316485Sdavidcs{ 391316485Sdavidcs INIT_POLL_NONE /* No polling */, 392316485Sdavidcs INIT_POLL_EQ /* init value is included in the init command */, 393316485Sdavidcs INIT_POLL_OR /* init value is all zeros */, 394316485Sdavidcs INIT_POLL_AND /* init value is an array of values */, 395316485Sdavidcs MAX_INIT_POLL_TYPES 396316485Sdavidcs}; 397316485Sdavidcs 398316485Sdavidcs 399316485Sdavidcs 400316485Sdavidcs 401316485Sdavidcs/* 402316485Sdavidcs * init source types 403316485Sdavidcs */ 404316485Sdavidcsenum init_source_types 405316485Sdavidcs{ 406316485Sdavidcs INIT_SRC_INLINE /* init value is included in the init command */, 407316485Sdavidcs INIT_SRC_ZEROS /* init value is all zeros */, 408316485Sdavidcs INIT_SRC_ARRAY /* init value is an array of values */, 409316485Sdavidcs INIT_SRC_RUNTIME /* init value is provided during runtime */, 410316485Sdavidcs MAX_INIT_SOURCE_TYPES 411316485Sdavidcs}; 412316485Sdavidcs 413316485Sdavidcs 414316485Sdavidcs 415316485Sdavidcs 416316485Sdavidcs/* 417316485Sdavidcs * Internal RAM Offsets macro data 418316485Sdavidcs */ 419316485Sdavidcsstruct iro 420316485Sdavidcs{ 421337517Sdavidcs u32 base /* RAM field offset */; 422337517Sdavidcs u16 m1 /* multiplier 1 */; 423337517Sdavidcs u16 m2 /* multiplier 2 */; 424337517Sdavidcs u16 m3 /* multiplier 3 */; 425337517Sdavidcs u16 size /* RAM field size */; 426316485Sdavidcs}; 427316485Sdavidcs 428316485Sdavidcs#endif /* __ECORE_HSI_INIT_TOOL__ */ 429