1/*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 *  Redistribution and use in source and binary forms, with or without
6 *  modification, are permitted provided that the following conditions
7 *  are met:
8 *
9 *  1. Redistributions of source code must retain the above copyright
10 *     notice, this list of conditions and the following disclaimer.
11 *  2. Redistributions in binary form must reproduce the above copyright
12 *     notice, this list of conditions and the following disclaimer in the
13 *     documentation and/or other materials provided with the distribution.
14 *
15 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 *  POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/ecore_hsi_init_tool.h 337517 2018-08-09 01:17:35Z davidcs $
28 *
29 */
30
31
32#ifndef __ECORE_HSI_INIT_TOOL__
33#define __ECORE_HSI_INIT_TOOL__
34/**************************************/
35/* Init Tool HSI constants and macros */
36/**************************************/
37
38/* Width of GRC address in bits (addresses are specified in dwords) */
39#define GRC_ADDR_BITS			23
40#define MAX_GRC_ADDR			((1 << GRC_ADDR_BITS) - 1)
41
42/* indicates an init that should be applied to any phase ID */
43#define ANY_PHASE_ID			0xffff
44
45/* Max size in dwords of a zipped array */
46#define MAX_ZIPPED_SIZE			8192
47
48
49enum chip_ids
50{
51	CHIP_BB,
52	CHIP_K2,
53	CHIP_E5,
54	MAX_CHIP_IDS
55};
56
57
58enum init_modes
59{
60	MODE_BB_A0_DEPRECATED,
61	MODE_BB,
62	MODE_K2,
63	MODE_ASIC,
64	MODE_EMUL_REDUCED,
65	MODE_EMUL_FULL,
66	MODE_FPGA,
67	MODE_CHIPSIM,
68	MODE_SF,
69	MODE_MF_SD,
70	MODE_MF_SI,
71	MODE_PORTS_PER_ENG_1,
72	MODE_PORTS_PER_ENG_2,
73	MODE_PORTS_PER_ENG_4,
74	MODE_100G,
75	MODE_E5,
76	MAX_INIT_MODES
77};
78
79
80enum init_phases
81{
82	PHASE_ENGINE,
83	PHASE_PORT,
84	PHASE_PF,
85	PHASE_VF,
86	PHASE_QM_PF,
87	MAX_INIT_PHASES
88};
89
90
91enum init_split_types
92{
93	SPLIT_TYPE_NONE,
94	SPLIT_TYPE_PORT,
95	SPLIT_TYPE_PF,
96	SPLIT_TYPE_PORT_PF,
97	SPLIT_TYPE_VF,
98	MAX_INIT_SPLIT_TYPES
99};
100
101
102/*
103 * Binary buffer header
104 */
105struct bin_buffer_hdr
106{
107	u32 offset /* buffer offset in bytes from the beginning of the binary file */;
108	u32 length /* buffer length in bytes */;
109};
110
111
112/*
113 * binary init buffer types
114 */
115enum bin_init_buffer_type
116{
117	BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
118	BIN_BUF_INIT_CMD /* init commands */,
119	BIN_BUF_INIT_VAL /* init data */,
120	BIN_BUF_INIT_MODE_TREE /* init modes tree */,
121	BIN_BUF_INIT_IRO /* internal RAM offsets */,
122	MAX_BIN_INIT_BUFFER_TYPE
123};
124
125
126/*
127 * init array header: raw
128 */
129struct init_array_raw_hdr
130{
131	u32 data;
132#define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF /* Init array type, from init_array_types enum */
133#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
134#define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF /* init array params */
135#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
136};
137
138/*
139 * init array header: standard
140 */
141struct init_array_standard_hdr
142{
143	u32 data;
144#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK  0xF /* Init array type, from init_array_types enum */
145#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
146#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK  0xFFFFFFF /* Init array size (in dwords) */
147#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
148};
149
150/*
151 * init array header: zipped
152 */
153struct init_array_zipped_hdr
154{
155	u32 data;
156#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF /* Init array type, from init_array_types enum */
157#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
158#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF /* Init array zipped size (in bytes) */
159#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
160};
161
162/*
163 * init array header: pattern
164 */
165struct init_array_pattern_hdr
166{
167	u32 data;
168#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK          0xF /* Init array type, from init_array_types enum */
169#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT         0
170#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK  0xF /* pattern size in dword */
171#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
172#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK   0xFFFFFF /* pattern repetitions */
173#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT  8
174};
175
176/*
177 * init array header union
178 */
179union init_array_hdr
180{
181	struct init_array_raw_hdr raw /* raw init array header */;
182	struct init_array_standard_hdr standard /* standard init array header */;
183	struct init_array_zipped_hdr zipped /* zipped init array header */;
184	struct init_array_pattern_hdr pattern /* pattern init array header */;
185};
186
187
188
189
190
191/*
192 * init array types
193 */
194enum init_array_types
195{
196	INIT_ARR_STANDARD /* standard init array */,
197	INIT_ARR_ZIPPED /* zipped init array */,
198	INIT_ARR_PATTERN /* a repeated pattern */,
199	MAX_INIT_ARRAY_TYPES
200};
201
202
203
204/*
205 * init operation: callback
206 */
207struct init_callback_op
208{
209	u32 op_data;
210#define INIT_CALLBACK_OP_OP_MASK        0xF /* Init operation, from init_op_types enum */
211#define INIT_CALLBACK_OP_OP_SHIFT       0
212#define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
213#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
214	u16 callback_id /* Callback ID */;
215	u16 block_id /* Blocks ID */;
216};
217
218
219/*
220 * init operation: delay
221 */
222struct init_delay_op
223{
224	u32 op_data;
225#define INIT_DELAY_OP_OP_MASK        0xF /* Init operation, from init_op_types enum */
226#define INIT_DELAY_OP_OP_SHIFT       0
227#define INIT_DELAY_OP_RESERVED_MASK  0xFFFFFFF
228#define INIT_DELAY_OP_RESERVED_SHIFT 4
229	u32 delay /* delay in us */;
230};
231
232
233/*
234 * init operation: if_mode
235 */
236struct init_if_mode_op
237{
238	u32 op_data;
239#define INIT_IF_MODE_OP_OP_MASK          0xF /* Init operation, from init_op_types enum */
240#define INIT_IF_MODE_OP_OP_SHIFT         0
241#define INIT_IF_MODE_OP_RESERVED1_MASK   0xFFF
242#define INIT_IF_MODE_OP_RESERVED1_SHIFT  4
243#define INIT_IF_MODE_OP_CMD_OFFSET_MASK  0xFFFF /* Commands to skip if the modes dont match */
244#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
245	u16 reserved2;
246	u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */;
247};
248
249
250/*
251 * init operation: if_phase
252 */
253struct init_if_phase_op
254{
255	u32 op_data;
256#define INIT_IF_PHASE_OP_OP_MASK           0xF /* Init operation, from init_op_types enum */
257#define INIT_IF_PHASE_OP_OP_SHIFT          0
258#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK  0x1 /* Indicates if DMAE is enabled in this phase */
259#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
260#define INIT_IF_PHASE_OP_RESERVED1_MASK    0x7FF
261#define INIT_IF_PHASE_OP_RESERVED1_SHIFT   5
262#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK   0xFFFF /* Commands to skip if the phases dont match */
263#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT  16
264	u32 phase_data;
265#define INIT_IF_PHASE_OP_PHASE_MASK        0xFF /* Init phase */
266#define INIT_IF_PHASE_OP_PHASE_SHIFT       0
267#define INIT_IF_PHASE_OP_RESERVED2_MASK    0xFF
268#define INIT_IF_PHASE_OP_RESERVED2_SHIFT   8
269#define INIT_IF_PHASE_OP_PHASE_ID_MASK     0xFFFF /* Init phase ID */
270#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT    16
271};
272
273
274/*
275 * init mode operators
276 */
277enum init_mode_ops
278{
279	INIT_MODE_OP_NOT /* init mode not operator */,
280	INIT_MODE_OP_OR /* init mode or operator */,
281	INIT_MODE_OP_AND /* init mode and operator */,
282	MAX_INIT_MODE_OPS
283};
284
285
286/*
287 * init operation: raw
288 */
289struct init_raw_op
290{
291	u32 op_data;
292#define INIT_RAW_OP_OP_MASK      0xF /* Init operation, from init_op_types enum */
293#define INIT_RAW_OP_OP_SHIFT     0
294#define INIT_RAW_OP_PARAM1_MASK  0xFFFFFFF /* init param 1 */
295#define INIT_RAW_OP_PARAM1_SHIFT 4
296	u32 param2 /* Init param 2 */;
297};
298
299/*
300 * init array params
301 */
302struct init_op_array_params
303{
304	u16 size /* array size in dwords */;
305	u16 offset /* array start offset in dwords */;
306};
307
308/*
309 * Write init operation arguments
310 */
311union init_write_args
312{
313	u32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */;
314	u32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */;
315	u32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */;
316	struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */;
317};
318
319/*
320 * init operation: write
321 */
322struct init_write_op
323{
324	u32 data;
325#define INIT_WRITE_OP_OP_MASK        0xF /* init operation, from init_op_types enum */
326#define INIT_WRITE_OP_OP_SHIFT       0
327#define INIT_WRITE_OP_SOURCE_MASK    0x7 /* init source type, taken from init_source_types enum */
328#define INIT_WRITE_OP_SOURCE_SHIFT   4
329#define INIT_WRITE_OP_RESERVED_MASK  0x1
330#define INIT_WRITE_OP_RESERVED_SHIFT 7
331#define INIT_WRITE_OP_WIDE_BUS_MASK  0x1 /* indicates if the register is wide-bus */
332#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
333#define INIT_WRITE_OP_ADDRESS_MASK   0x7FFFFF /* internal (absolute) GRC address, in dwords */
334#define INIT_WRITE_OP_ADDRESS_SHIFT  9
335	union init_write_args args /* Write init operation arguments */;
336};
337
338/*
339 * init operation: read
340 */
341struct init_read_op
342{
343	u32 op_data;
344#define INIT_READ_OP_OP_MASK         0xF /* init operation, from init_op_types enum */
345#define INIT_READ_OP_OP_SHIFT        0
346#define INIT_READ_OP_POLL_TYPE_MASK  0xF /* polling type, from init_poll_types enum */
347#define INIT_READ_OP_POLL_TYPE_SHIFT 4
348#define INIT_READ_OP_RESERVED_MASK   0x1
349#define INIT_READ_OP_RESERVED_SHIFT  8
350#define INIT_READ_OP_ADDRESS_MASK    0x7FFFFF /* internal (absolute) GRC address, in dwords */
351#define INIT_READ_OP_ADDRESS_SHIFT   9
352	u32 expected_val /* expected polling value, used only when polling is done */;
353};
354
355/*
356 * Init operations union
357 */
358union init_op
359{
360	struct init_raw_op raw /* raw init operation */;
361	struct init_write_op write /* write init operation */;
362	struct init_read_op read /* read init operation */;
363	struct init_if_mode_op if_mode /* if_mode init operation */;
364	struct init_if_phase_op if_phase /* if_phase init operation */;
365	struct init_callback_op callback /* callback init operation */;
366	struct init_delay_op delay /* delay init operation */;
367};
368
369
370
371/*
372 * Init command operation types
373 */
374enum init_op_types
375{
376	INIT_OP_READ /* GRC read init command */,
377	INIT_OP_WRITE /* GRC write init command */,
378	INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */,
379	INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */,
380	INIT_OP_DELAY /* delay init command */,
381	INIT_OP_CALLBACK /* callback init command */,
382	MAX_INIT_OP_TYPES
383};
384
385
386/*
387 * init polling types
388 */
389enum init_poll_types
390{
391	INIT_POLL_NONE /* No polling */,
392	INIT_POLL_EQ /* init value is included in the init command */,
393	INIT_POLL_OR /* init value is all zeros */,
394	INIT_POLL_AND /* init value is an array of values */,
395	MAX_INIT_POLL_TYPES
396};
397
398
399
400
401/*
402 * init source types
403 */
404enum init_source_types
405{
406	INIT_SRC_INLINE /* init value is included in the init command */,
407	INIT_SRC_ZEROS /* init value is all zeros */,
408	INIT_SRC_ARRAY /* init value is an array of values */,
409	INIT_SRC_RUNTIME /* init value is provided during runtime */,
410	MAX_INIT_SOURCE_TYPES
411};
412
413
414
415
416/*
417 * Internal RAM Offsets macro data
418 */
419struct iro
420{
421	u32 base /* RAM field offset */;
422	u16 m1 /* multiplier 1 */;
423	u16 m2 /* multiplier 2 */;
424	u16 m3 /* multiplier 3 */;
425	u16 size /* RAM field size */;
426};
427
428#endif /* __ECORE_HSI_INIT_TOOL__ */
429