1/*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30/* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/kernel.h> 38#include <sys/bus.h> 39#include <sys/sysctl.h> 40 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44 45#include <dev/ic/ns16550.h> 46 47#include <dev/pci/pcireg.h> 48#include <dev/pci/pcivar.h> 49 50#include <dev/puc/puc_bus.h> 51#include <dev/puc/puc_cfg.h> 52#include <dev/puc/puc_bfe.h> 53 54static puc_config_f puc_config_advantech; 55static puc_config_f puc_config_amc; 56static puc_config_f puc_config_diva; 57static puc_config_f puc_config_exar; 58static puc_config_f puc_config_exar_pcie; 59static puc_config_f puc_config_icbook; 60static puc_config_f puc_config_moxa; 61static puc_config_f puc_config_oxford_pci954; 62static puc_config_f puc_config_oxford_pcie; 63static puc_config_f puc_config_quatech; 64static puc_config_f puc_config_syba; 65static puc_config_f puc_config_siig; 66static puc_config_f puc_config_sunix; 67static puc_config_f puc_config_timedia; 68static puc_config_f puc_config_titan; 69 70const struct puc_cfg puc_pci_devices[] = { 71 { 0x0009, 0x7168, 0xffff, 0, 72 "Sunix SUN1889", 73 DEFAULT_RCLK * 8, 74 PUC_PORT_2S, 0x10, 0, 8, 75 }, 76 77 { 0x103c, 0x1048, 0x103c, 0x1049, 78 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 79 DEFAULT_RCLK, 80 PUC_PORT_3S, 0x10, 0, -1, 81 .config_function = puc_config_diva 82 }, 83 84 { 0x103c, 0x1048, 0x103c, 0x104a, 85 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 86 DEFAULT_RCLK, 87 PUC_PORT_2S, 0x10, 0, -1, 88 .config_function = puc_config_diva 89 }, 90 91 { 0x103c, 0x1048, 0x103c, 0x104b, 92 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 93 DEFAULT_RCLK, 94 PUC_PORT_4S, 0x10, 0, -1, 95 .config_function = puc_config_diva 96 }, 97 98 { 0x103c, 0x1048, 0x103c, 0x1223, 99 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 100 DEFAULT_RCLK, 101 PUC_PORT_3S, 0x10, 0, -1, 102 .config_function = puc_config_diva 103 }, 104 105 { 0x103c, 0x1048, 0x103c, 0x1226, 106 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 107 DEFAULT_RCLK, 108 PUC_PORT_3S, 0x10, 0, -1, 109 .config_function = puc_config_diva 110 }, 111 112 { 0x103c, 0x1048, 0x103c, 0x1282, 113 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 114 DEFAULT_RCLK, 115 PUC_PORT_3S, 0x10, 0, -1, 116 .config_function = puc_config_diva 117 }, 118 119 { 0x10b5, 0x1076, 0x10b5, 0x1076, 120 "VScom PCI-800", 121 DEFAULT_RCLK * 8, 122 PUC_PORT_8S, 0x18, 0, 8, 123 }, 124 125 { 0x10b5, 0x1077, 0x10b5, 0x1077, 126 "VScom PCI-400", 127 DEFAULT_RCLK * 8, 128 PUC_PORT_4S, 0x18, 0, 8, 129 }, 130 131 { 0x10b5, 0x1103, 0x10b5, 0x1103, 132 "VScom PCI-200", 133 DEFAULT_RCLK * 8, 134 PUC_PORT_2S, 0x18, 4, 0, 135 }, 136 137 /* 138 * Boca Research Turbo Serial 658 (8 serial port) card. 139 * Appears to be the same as Chase Research PLC PCI-FAST8 140 * and Perle PCI-FAST8 Multi-Port serial cards. 141 */ 142 { 0x10b5, 0x9050, 0x12e0, 0x0021, 143 "Boca Research Turbo Serial 658", 144 DEFAULT_RCLK * 4, 145 PUC_PORT_8S, 0x18, 0, 8, 146 }, 147 148 { 0x10b5, 0x9050, 0x12e0, 0x0031, 149 "Boca Research Turbo Serial 654", 150 DEFAULT_RCLK * 4, 151 PUC_PORT_4S, 0x18, 0, 8, 152 }, 153 154 /* 155 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 156 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 157 * into the subsystem fields, and claims that it's a 158 * network/misc (0x02/0x80) device. 159 */ 160 { 0x10b5, 0x9050, 0xd84d, 0x6808, 161 "Dolphin Peripherals 4035", 162 DEFAULT_RCLK, 163 PUC_PORT_2S, 0x18, 4, 0, 164 }, 165 166 /* 167 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 168 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 169 * into the subsystem fields, and claims that it's a 170 * network/misc (0x02/0x80) device. 171 */ 172 { 0x10b5, 0x9050, 0xd84d, 0x6810, 173 "Dolphin Peripherals 4014", 174 0, 175 PUC_PORT_2P, 0x20, 4, 0, 176 }, 177 178 { 0x10e8, 0x818e, 0xffff, 0, 179 "Applied Micro Circuits 8 Port UART", 180 DEFAULT_RCLK, 181 PUC_PORT_8S, 0x14, -1, -1, 182 .config_function = puc_config_amc 183 }, 184 185 /* 186 * The following members of the Digi International Neo series are 187 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV. 188 * Accordingly, the PCIe versions of these cards incorporate a PLX 189 * PCIe-PCI-bridge. 190 */ 191 192 { 0x114f, 0x00b0, 0xffff, 0, 193 "Digi Neo PCI 4 Port", 194 DEFAULT_RCLK * 8, 195 PUC_PORT_4S, 0x10, 0, -1, 196 .config_function = puc_config_exar 197 }, 198 199 { 0x114f, 0x00b1, 0xffff, 0, 200 "Digi Neo PCI 8 Port", 201 DEFAULT_RCLK * 8, 202 PUC_PORT_8S, 0x10, 0, -1, 203 .config_function = puc_config_exar 204 }, 205 206 { 0x114f, 0x00f0, 0xffff, 0, 207 "Digi Neo PCIe 8 Port", 208 DEFAULT_RCLK * 8, 209 PUC_PORT_8S, 0x10, 0, -1, 210 .config_function = puc_config_exar 211 }, 212 213 { 0x114f, 0x00f1, 0xffff, 0, 214 "Digi Neo PCIe 4 Port", 215 DEFAULT_RCLK * 8, 216 PUC_PORT_4S, 0x10, 0, -1, 217 .config_function = puc_config_exar 218 }, 219 220 { 0x114f, 0x00f2, 0xffff, 0, 221 "Digi Neo PCIe 4 Port RJ45", 222 DEFAULT_RCLK * 8, 223 PUC_PORT_4S, 0x10, 0, -1, 224 .config_function = puc_config_exar 225 }, 226 227 { 0x114f, 0x00f3, 0xffff, 0, 228 "Digi Neo PCIe 8 Port RJ45", 229 DEFAULT_RCLK * 8, 230 PUC_PORT_8S, 0x10, 0, -1, 231 .config_function = puc_config_exar 232 }, 233 234 { 0x11fe, 0x8010, 0xffff, 0, 235 "Comtrol RocketPort 550/8 RJ11 part A", 236 DEFAULT_RCLK * 4, 237 PUC_PORT_4S, 0x10, 0, 8, 238 }, 239 240 { 0x11fe, 0x8011, 0xffff, 0, 241 "Comtrol RocketPort 550/8 RJ11 part B", 242 DEFAULT_RCLK * 4, 243 PUC_PORT_4S, 0x10, 0, 8, 244 }, 245 246 { 0x11fe, 0x8012, 0xffff, 0, 247 "Comtrol RocketPort 550/8 Octa part A", 248 DEFAULT_RCLK * 4, 249 PUC_PORT_4S, 0x10, 0, 8, 250 }, 251 252 { 0x11fe, 0x8013, 0xffff, 0, 253 "Comtrol RocketPort 550/8 Octa part B", 254 DEFAULT_RCLK * 4, 255 PUC_PORT_4S, 0x10, 0, 8, 256 }, 257 258 { 0x11fe, 0x8014, 0xffff, 0, 259 "Comtrol RocketPort 550/4 RJ45", 260 DEFAULT_RCLK * 4, 261 PUC_PORT_4S, 0x10, 0, 8, 262 }, 263 264 { 0x11fe, 0x8015, 0xffff, 0, 265 "Comtrol RocketPort 550/Quad", 266 DEFAULT_RCLK * 4, 267 PUC_PORT_4S, 0x10, 0, 8, 268 }, 269 270 { 0x11fe, 0x8016, 0xffff, 0, 271 "Comtrol RocketPort 550/16 part A", 272 DEFAULT_RCLK * 4, 273 PUC_PORT_4S, 0x10, 0, 8, 274 }, 275 276 { 0x11fe, 0x8017, 0xffff, 0, 277 "Comtrol RocketPort 550/16 part B", 278 DEFAULT_RCLK * 4, 279 PUC_PORT_12S, 0x10, 0, 8, 280 }, 281 282 { 0x11fe, 0x8018, 0xffff, 0, 283 "Comtrol RocketPort 550/8 part A", 284 DEFAULT_RCLK * 4, 285 PUC_PORT_4S, 0x10, 0, 8, 286 }, 287 288 { 0x11fe, 0x8019, 0xffff, 0, 289 "Comtrol RocketPort 550/8 part B", 290 DEFAULT_RCLK * 4, 291 PUC_PORT_4S, 0x10, 0, 8, 292 }, 293 294 /* 295 * IBM SurePOS 300 Series (481033H) serial ports 296 * Details can be found on the IBM RSS websites 297 */ 298 299 { 0x1014, 0x0297, 0xffff, 0, 300 "IBM SurePOS 300 Series (481033H) serial ports", 301 DEFAULT_RCLK, 302 PUC_PORT_4S, 0x10, 4, 0 303 }, 304 305 /* 306 * SIIG Boards. 307 * 308 * SIIG provides documentation for their boards at: 309 * <URL:http://www.siig.com/downloads.asp> 310 */ 311 312 { 0x131f, 0x1010, 0xffff, 0, 313 "SIIG Cyber I/O PCI 16C550 (10x family)", 314 DEFAULT_RCLK, 315 PUC_PORT_1S1P, 0x18, 4, 0, 316 }, 317 318 { 0x131f, 0x1011, 0xffff, 0, 319 "SIIG Cyber I/O PCI 16C650 (10x family)", 320 DEFAULT_RCLK, 321 PUC_PORT_1S1P, 0x18, 4, 0, 322 }, 323 324 { 0x131f, 0x1012, 0xffff, 0, 325 "SIIG Cyber I/O PCI 16C850 (10x family)", 326 DEFAULT_RCLK, 327 PUC_PORT_1S1P, 0x18, 4, 0, 328 }, 329 330 { 0x131f, 0x1021, 0xffff, 0, 331 "SIIG Cyber Parallel Dual PCI (10x family)", 332 0, 333 PUC_PORT_2P, 0x18, 8, 0, 334 }, 335 336 { 0x131f, 0x1030, 0xffff, 0, 337 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 338 DEFAULT_RCLK, 339 PUC_PORT_2S, 0x18, 4, 0, 340 }, 341 342 { 0x131f, 0x1031, 0xffff, 0, 343 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 344 DEFAULT_RCLK, 345 PUC_PORT_2S, 0x18, 4, 0, 346 }, 347 348 { 0x131f, 0x1032, 0xffff, 0, 349 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 350 DEFAULT_RCLK, 351 PUC_PORT_2S, 0x18, 4, 0, 352 }, 353 354 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 355 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 356 DEFAULT_RCLK, 357 PUC_PORT_2S1P, 0x18, 4, 0, 358 }, 359 360 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 361 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 362 DEFAULT_RCLK, 363 PUC_PORT_2S1P, 0x18, 4, 0, 364 }, 365 366 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 367 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 368 DEFAULT_RCLK, 369 PUC_PORT_2S1P, 0x18, 4, 0, 370 }, 371 372 { 0x131f, 0x1050, 0xffff, 0, 373 "SIIG Cyber 4S PCI 16C550 (10x family)", 374 DEFAULT_RCLK, 375 PUC_PORT_4S, 0x18, 4, 0, 376 }, 377 378 { 0x131f, 0x1051, 0xffff, 0, 379 "SIIG Cyber 4S PCI 16C650 (10x family)", 380 DEFAULT_RCLK, 381 PUC_PORT_4S, 0x18, 4, 0, 382 }, 383 384 { 0x131f, 0x1052, 0xffff, 0, 385 "SIIG Cyber 4S PCI 16C850 (10x family)", 386 DEFAULT_RCLK, 387 PUC_PORT_4S, 0x18, 4, 0, 388 }, 389 390 { 0x131f, 0x2010, 0xffff, 0, 391 "SIIG Cyber I/O PCI 16C550 (20x family)", 392 DEFAULT_RCLK, 393 PUC_PORT_1S1P, 0x10, 4, 0, 394 }, 395 396 { 0x131f, 0x2011, 0xffff, 0, 397 "SIIG Cyber I/O PCI 16C650 (20x family)", 398 DEFAULT_RCLK, 399 PUC_PORT_1S1P, 0x10, 4, 0, 400 }, 401 402 { 0x131f, 0x2012, 0xffff, 0, 403 "SIIG Cyber I/O PCI 16C850 (20x family)", 404 DEFAULT_RCLK, 405 PUC_PORT_1S1P, 0x10, 4, 0, 406 }, 407 408 { 0x131f, 0x2021, 0xffff, 0, 409 "SIIG Cyber Parallel Dual PCI (20x family)", 410 0, 411 PUC_PORT_2P, 0x10, 8, 0, 412 }, 413 414 { 0x131f, 0x2030, 0xffff, 0, 415 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 416 DEFAULT_RCLK, 417 PUC_PORT_2S, 0x10, 4, 0, 418 }, 419 420 { 0x131f, 0x2031, 0xffff, 0, 421 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 422 DEFAULT_RCLK, 423 PUC_PORT_2S, 0x10, 4, 0, 424 }, 425 426 { 0x131f, 0x2032, 0xffff, 0, 427 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 428 DEFAULT_RCLK, 429 PUC_PORT_2S, 0x10, 4, 0, 430 }, 431 432 { 0x131f, 0x2040, 0xffff, 0, 433 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 434 DEFAULT_RCLK, 435 PUC_PORT_1S2P, 0x10, -1, 0, 436 .config_function = puc_config_siig 437 }, 438 439 { 0x131f, 0x2041, 0xffff, 0, 440 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 441 DEFAULT_RCLK, 442 PUC_PORT_1S2P, 0x10, -1, 0, 443 .config_function = puc_config_siig 444 }, 445 446 { 0x131f, 0x2042, 0xffff, 0, 447 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 448 DEFAULT_RCLK, 449 PUC_PORT_1S2P, 0x10, -1, 0, 450 .config_function = puc_config_siig 451 }, 452 453 { 0x131f, 0x2050, 0xffff, 0, 454 "SIIG Cyber 4S PCI 16C550 (20x family)", 455 DEFAULT_RCLK, 456 PUC_PORT_4S, 0x10, 4, 0, 457 }, 458 459 { 0x131f, 0x2051, 0xffff, 0, 460 "SIIG Cyber 4S PCI 16C650 (20x family)", 461 DEFAULT_RCLK, 462 PUC_PORT_4S, 0x10, 4, 0, 463 }, 464 465 { 0x131f, 0x2052, 0xffff, 0, 466 "SIIG Cyber 4S PCI 16C850 (20x family)", 467 DEFAULT_RCLK, 468 PUC_PORT_4S, 0x10, 4, 0, 469 }, 470 471 { 0x131f, 0x2060, 0xffff, 0, 472 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 473 DEFAULT_RCLK, 474 PUC_PORT_2S1P, 0x10, 4, 0, 475 }, 476 477 { 0x131f, 0x2061, 0xffff, 0, 478 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 479 DEFAULT_RCLK, 480 PUC_PORT_2S1P, 0x10, 4, 0, 481 }, 482 483 { 0x131f, 0x2062, 0xffff, 0, 484 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 485 DEFAULT_RCLK, 486 PUC_PORT_2S1P, 0x10, 4, 0, 487 }, 488 489 { 0x131f, 0x2081, 0xffff, 0, 490 "SIIG PS8000 8S PCI 16C650 (20x family)", 491 DEFAULT_RCLK, 492 PUC_PORT_8S, 0x10, -1, -1, 493 .config_function = puc_config_siig 494 }, 495 496 { 0x135c, 0x0010, 0xffff, 0, 497 "Quatech QSC-100", 498 -3, /* max 8x clock rate */ 499 PUC_PORT_4S, 0x14, 0, 8, 500 .config_function = puc_config_quatech 501 }, 502 503 { 0x135c, 0x0020, 0xffff, 0, 504 "Quatech DSC-100", 505 -1, /* max 2x clock rate */ 506 PUC_PORT_2S, 0x14, 0, 8, 507 .config_function = puc_config_quatech 508 }, 509 510 { 0x135c, 0x0030, 0xffff, 0, 511 "Quatech DSC-200/300", 512 -1, /* max 2x clock rate */ 513 PUC_PORT_2S, 0x14, 0, 8, 514 .config_function = puc_config_quatech 515 }, 516 517 { 0x135c, 0x0040, 0xffff, 0, 518 "Quatech QSC-200/300", 519 -3, /* max 8x clock rate */ 520 PUC_PORT_4S, 0x14, 0, 8, 521 .config_function = puc_config_quatech 522 }, 523 524 { 0x135c, 0x0050, 0xffff, 0, 525 "Quatech ESC-100D", 526 -3, /* max 8x clock rate */ 527 PUC_PORT_8S, 0x14, 0, 8, 528 .config_function = puc_config_quatech 529 }, 530 531 { 0x135c, 0x0060, 0xffff, 0, 532 "Quatech ESC-100M", 533 -3, /* max 8x clock rate */ 534 PUC_PORT_8S, 0x14, 0, 8, 535 .config_function = puc_config_quatech 536 }, 537 538 { 0x135c, 0x0170, 0xffff, 0, 539 "Quatech QSCLP-100", 540 -1, /* max 2x clock rate */ 541 PUC_PORT_4S, 0x18, 0, 8, 542 .config_function = puc_config_quatech 543 }, 544 545 { 0x135c, 0x0180, 0xffff, 0, 546 "Quatech DSCLP-100", 547 -1, /* max 3x clock rate */ 548 PUC_PORT_2S, 0x18, 0, 8, 549 .config_function = puc_config_quatech 550 }, 551 552 { 0x135c, 0x01b0, 0xffff, 0, 553 "Quatech DSCLP-200/300", 554 -1, /* max 2x clock rate */ 555 PUC_PORT_2S, 0x18, 0, 8, 556 .config_function = puc_config_quatech 557 }, 558 559 { 0x135c, 0x01e0, 0xffff, 0, 560 "Quatech ESCLP-100", 561 -3, /* max 8x clock rate */ 562 PUC_PORT_8S, 0x10, 0, 8, 563 .config_function = puc_config_quatech 564 }, 565 566 { 0x1393, 0x1024, 0xffff, 0, 567 "Moxa Technologies, Smartio CP-102E/PCIe", 568 DEFAULT_RCLK * 8, 569 PUC_PORT_2S, 0x14, 0, -1, 570 .config_function = puc_config_moxa 571 }, 572 573 { 0x1393, 0x1025, 0xffff, 0, 574 "Moxa Technologies, Smartio CP-102EL/PCIe", 575 DEFAULT_RCLK * 8, 576 PUC_PORT_2S, 0x14, 0, -1, 577 .config_function = puc_config_moxa 578 }, 579 580 { 0x1393, 0x1040, 0xffff, 0, 581 "Moxa Technologies, Smartio C104H/PCI", 582 DEFAULT_RCLK * 8, 583 PUC_PORT_4S, 0x18, 0, 8, 584 }, 585 586 { 0x1393, 0x1041, 0xffff, 0, 587 "Moxa Technologies, Smartio CP-104UL/PCI", 588 DEFAULT_RCLK * 8, 589 PUC_PORT_4S, 0x18, 0, 8, 590 }, 591 592 { 0x1393, 0x1042, 0xffff, 0, 593 "Moxa Technologies, Smartio CP-104JU/PCI", 594 DEFAULT_RCLK * 8, 595 PUC_PORT_4S, 0x18, 0, 8, 596 }, 597 598 { 0x1393, 0x1043, 0xffff, 0, 599 "Moxa Technologies, Smartio CP-104EL/PCIe", 600 DEFAULT_RCLK * 8, 601 PUC_PORT_4S, 0x18, 0, 8, 602 }, 603 604 { 0x1393, 0x1045, 0xffff, 0, 605 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 606 DEFAULT_RCLK * 8, 607 PUC_PORT_4S, 0x14, 0, -1, 608 .config_function = puc_config_moxa 609 }, 610 611 { 0x1393, 0x1120, 0xffff, 0, 612 "Moxa Technologies, CP-112UL", 613 DEFAULT_RCLK * 8, 614 PUC_PORT_2S, 0x18, 0, 8, 615 }, 616 617 { 0x1393, 0x1141, 0xffff, 0, 618 "Moxa Technologies, Industio CP-114", 619 DEFAULT_RCLK * 8, 620 PUC_PORT_4S, 0x18, 0, 8, 621 }, 622 623 { 0x1393, 0x1144, 0xffff, 0, 624 "Moxa Technologies, Smartio CP-114EL/PCIe", 625 DEFAULT_RCLK * 8, 626 PUC_PORT_4S, 0x14, 0, -1, 627 .config_function = puc_config_moxa 628 }, 629 630 { 0x1393, 0x1182, 0xffff, 0, 631 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 632 DEFAULT_RCLK * 8, 633 PUC_PORT_8S, 0x14, 0, -1, 634 .config_function = puc_config_moxa 635 }, 636 637 { 0x1393, 0x1680, 0xffff, 0, 638 "Moxa Technologies, C168H/PCI", 639 DEFAULT_RCLK * 8, 640 PUC_PORT_8S, 0x18, 0, 8, 641 }, 642 643 { 0x1393, 0x1681, 0xffff, 0, 644 "Moxa Technologies, C168U/PCI", 645 DEFAULT_RCLK * 8, 646 PUC_PORT_8S, 0x18, 0, 8, 647 }, 648 649 { 0x1393, 0x1682, 0xffff, 0, 650 "Moxa Technologies, CP-168EL/PCIe", 651 DEFAULT_RCLK * 8, 652 PUC_PORT_8S, 0x18, 0, 8, 653 }, 654 655 { 0x1393, 0x1683, 0xffff, 0, 656 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 657 DEFAULT_RCLK * 8, 658 PUC_PORT_8S, 0x14, 0, -1, 659 .config_function = puc_config_moxa 660 }, 661 662 { 0x13a8, 0x0152, 0xffff, 0, 663 "Exar XR17C/D152", 664 DEFAULT_RCLK * 8, 665 PUC_PORT_2S, 0x10, 0, -1, 666 .config_function = puc_config_exar 667 }, 668 669 { 0x13a8, 0x0154, 0xffff, 0, 670 "Exar XR17C154", 671 DEFAULT_RCLK * 8, 672 PUC_PORT_4S, 0x10, 0, -1, 673 .config_function = puc_config_exar 674 }, 675 676 { 0x13a8, 0x0158, 0xffff, 0, 677 "Exar XR17C158", 678 DEFAULT_RCLK * 8, 679 PUC_PORT_8S, 0x10, 0, -1, 680 .config_function = puc_config_exar 681 }, 682 683 { 0x13a8, 0x0258, 0xffff, 0, 684 "Exar XR17V258IV", 685 DEFAULT_RCLK * 8, 686 PUC_PORT_8S, 0x10, 0, -1, 687 .config_function = puc_config_exar 688 }, 689 690 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 691 { 0x13a8, 0x0358, 0xffff, 0, 692 "Exar XR17V358", 693 125000000, 694 PUC_PORT_8S, 0x10, 0, -1, 695 .config_function = puc_config_exar_pcie 696 }, 697 698 /* 699 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford 700 * Semiconductor OXuPCI954. Note these boards have a hardware bug in 701 * that they drive the RS-422/485 transmitters after power-on until a 702 * driver initalizes the UARTs. 703 */ 704 { 0x13fe, 0x1600, 0x1602, 0x0002, 705 "Advantech PCI-1602 Rev. A", 706 DEFAULT_RCLK * 8, 707 PUC_PORT_2S, 0x10, 0, 8, 708 .config_function = puc_config_advantech 709 }, 710 711 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */ 712 { 0x13fe, 0xa102, 0x13fe, 0xa102, 713 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)", 714 DEFAULT_RCLK * 8, 715 PUC_PORT_2S, 0x10, 4, 0, 716 .config_function = puc_config_advantech 717 }, 718 719 { 0x1407, 0x0100, 0xffff, 0, 720 "Lava Computers Dual Serial", 721 DEFAULT_RCLK, 722 PUC_PORT_2S, 0x10, 4, 0, 723 }, 724 725 { 0x1407, 0x0101, 0xffff, 0, 726 "Lava Computers Quatro A", 727 DEFAULT_RCLK, 728 PUC_PORT_2S, 0x10, 4, 0, 729 }, 730 731 { 0x1407, 0x0102, 0xffff, 0, 732 "Lava Computers Quatro B", 733 DEFAULT_RCLK, 734 PUC_PORT_2S, 0x10, 4, 0, 735 }, 736 737 { 0x1407, 0x0120, 0xffff, 0, 738 "Lava Computers Quattro-PCI A", 739 DEFAULT_RCLK, 740 PUC_PORT_2S, 0x10, 4, 0, 741 }, 742 743 { 0x1407, 0x0121, 0xffff, 0, 744 "Lava Computers Quattro-PCI B", 745 DEFAULT_RCLK, 746 PUC_PORT_2S, 0x10, 4, 0, 747 }, 748 749 { 0x1407, 0x0180, 0xffff, 0, 750 "Lava Computers Octo A", 751 DEFAULT_RCLK, 752 PUC_PORT_4S, 0x10, 4, 0, 753 }, 754 755 { 0x1407, 0x0181, 0xffff, 0, 756 "Lava Computers Octo B", 757 DEFAULT_RCLK, 758 PUC_PORT_4S, 0x10, 4, 0, 759 }, 760 761 { 0x1409, 0x7268, 0xffff, 0, 762 "Sunix SUN1888", 763 0, 764 PUC_PORT_2P, 0x10, 0, 8, 765 }, 766 767 { 0x1409, 0x7168, 0xffff, 0, 768 NULL, 769 DEFAULT_RCLK * 8, 770 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 771 .config_function = puc_config_timedia 772 }, 773 774 /* 775 * Boards with an Oxford Semiconductor chip. 776 * 777 * Oxford Semiconductor provides documentation for their chip at: 778 * <URL:http://www.plxtech.com/products/uart/> 779 * 780 * As sold by Kouwell <URL:http://www.kouwell.com/>. 781 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 782 */ 783 { 784 0x1415, 0x9501, 0x10fc, 0xc070, 785 "I-O DATA RSA-PCI2/R", 786 DEFAULT_RCLK * 8, 787 PUC_PORT_2S, 0x10, 0, 8, 788 }, 789 790 { 0x1415, 0x9501, 0x131f, 0x2050, 791 "SIIG Cyber 4 PCI 16550", 792 DEFAULT_RCLK * 10, 793 PUC_PORT_4S, 0x10, 0, 8, 794 }, 795 796 { 0x1415, 0x9501, 0x131f, 0x2051, 797 "SIIG Cyber 4S PCI 16C650 (20x family)", 798 DEFAULT_RCLK * 10, 799 PUC_PORT_4S, 0x10, 0, 8, 800 }, 801 802 { 0x1415, 0x9501, 0x131f, 0x2052, 803 "SIIG Quartet Serial 850", 804 DEFAULT_RCLK * 10, 805 PUC_PORT_4S, 0x10, 0, 8, 806 }, 807 808 { 0x1415, 0x9501, 0x14db, 0x2150, 809 "Kuroutoshikou SERIAL4P-LPPCI2", 810 DEFAULT_RCLK * 10, 811 PUC_PORT_4S, 0x10, 0, 8, 812 }, 813 814 { 0x1415, 0x9501, 0xffff, 0, 815 "Oxford Semiconductor OX16PCI954 UARTs", 816 0, 817 PUC_PORT_4S, 0x10, 0, 8, 818 .config_function = puc_config_oxford_pci954 819 }, 820 821 { 0x1415, 0x950a, 0x131f, 0x2030, 822 "SIIG Cyber 2S PCIe", 823 DEFAULT_RCLK * 10, 824 PUC_PORT_2S, 0x10, 0, 8, 825 }, 826 827 { 0x1415, 0x950a, 0x131f, 0x2032, 828 "SIIG Cyber Serial Dual PCI 16C850", 829 DEFAULT_RCLK * 10, 830 PUC_PORT_4S, 0x10, 0, 8, 831 }, 832 833 { 0x1415, 0x950a, 0x131f, 0x2061, 834 "SIIG Cyber 2SP1 PCIe", 835 DEFAULT_RCLK * 10, 836 PUC_PORT_2S, 0x10, 0, 8, 837 }, 838 839 { 0x1415, 0x950a, 0xffff, 0, 840 "Oxford Semiconductor OX16PCI954 UARTs", 841 DEFAULT_RCLK, 842 PUC_PORT_4S, 0x10, 0, 8, 843 }, 844 845 { 0x1415, 0x9511, 0xffff, 0, 846 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 847 DEFAULT_RCLK, 848 PUC_PORT_4S, 0x10, 0, 8, 849 }, 850 851 { 0x1415, 0x9521, 0xffff, 0, 852 "Oxford Semiconductor OX16PCI952 UARTs", 853 DEFAULT_RCLK, 854 PUC_PORT_2S, 0x10, 4, 0, 855 }, 856 857 { 0x1415, 0x9538, 0xffff, 0, 858 "Oxford Semiconductor OX16PCI958 UARTs", 859 DEFAULT_RCLK, 860 PUC_PORT_8S, 0x18, 0, 8, 861 }, 862 863 /* 864 * Perle boards use Oxford Semiconductor chips, but they store the 865 * Oxford Semiconductor device ID as a subvendor device ID and use 866 * their own device IDs. 867 */ 868 869 { 0x155f, 0x0331, 0xffff, 0, 870 "Perle Ultraport4 Express", 871 DEFAULT_RCLK * 8, 872 PUC_PORT_4S, 0x10, 0, 8, 873 }, 874 875 { 0x155f, 0xB012, 0xffff, 0, 876 "Perle Speed2 LE", 877 DEFAULT_RCLK * 8, 878 PUC_PORT_2S, 0x10, 0, 8, 879 }, 880 881 { 0x155f, 0xB022, 0xffff, 0, 882 "Perle Speed2 LE", 883 DEFAULT_RCLK * 8, 884 PUC_PORT_2S, 0x10, 0, 8, 885 }, 886 887 { 0x155f, 0xB004, 0xffff, 0, 888 "Perle Speed4 LE", 889 DEFAULT_RCLK * 8, 890 PUC_PORT_4S, 0x10, 0, 8, 891 }, 892 893 { 0x155f, 0xB008, 0xffff, 0, 894 "Perle Speed8 LE", 895 DEFAULT_RCLK * 8, 896 PUC_PORT_8S, 0x10, 0, 8, 897 }, 898 899 900 /* 901 * Oxford Semiconductor PCI Express Expresso family 902 * 903 * Found in many 'native' PCI Express serial boards such as: 904 * 905 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 906 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 907 * 908 * Lindy 51189 (4 port) 909 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 910 * 911 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 912 * <URL:http://www.startech.com> 913 */ 914 915 { 0x1415, 0xc11b, 0xffff, 0, 916 "Oxford Semiconductor OXPCIe952 1S1P", 917 DEFAULT_RCLK * 0x22, 918 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 919 .config_function = puc_config_oxford_pcie 920 }, 921 922 { 0x1415, 0xc138, 0xffff, 0, 923 "Oxford Semiconductor OXPCIe952 UARTs", 924 DEFAULT_RCLK * 0x22, 925 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 926 .config_function = puc_config_oxford_pcie 927 }, 928 929 { 0x1415, 0xc158, 0xffff, 0, 930 "Oxford Semiconductor OXPCIe952 UARTs", 931 DEFAULT_RCLK * 0x22, 932 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 933 .config_function = puc_config_oxford_pcie 934 }, 935 936 { 0x1415, 0xc15d, 0xffff, 0, 937 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 938 DEFAULT_RCLK * 0x22, 939 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 940 .config_function = puc_config_oxford_pcie 941 }, 942 943 { 0x1415, 0xc208, 0xffff, 0, 944 "Oxford Semiconductor OXPCIe954 UARTs", 945 DEFAULT_RCLK * 0x22, 946 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 947 .config_function = puc_config_oxford_pcie 948 }, 949 950 { 0x1415, 0xc20d, 0xffff, 0, 951 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 952 DEFAULT_RCLK * 0x22, 953 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 954 .config_function = puc_config_oxford_pcie 955 }, 956 957 { 0x1415, 0xc308, 0xffff, 0, 958 "Oxford Semiconductor OXPCIe958 UARTs", 959 DEFAULT_RCLK * 0x22, 960 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 961 .config_function = puc_config_oxford_pcie 962 }, 963 964 { 0x1415, 0xc30d, 0xffff, 0, 965 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 966 DEFAULT_RCLK * 0x22, 967 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 968 .config_function = puc_config_oxford_pcie 969 }, 970 971 { 0x14d2, 0x8010, 0xffff, 0, 972 "VScom PCI-100L", 973 DEFAULT_RCLK * 8, 974 PUC_PORT_1S, 0x14, 0, 0, 975 }, 976 977 { 0x14d2, 0x8020, 0xffff, 0, 978 "VScom PCI-200L", 979 DEFAULT_RCLK * 8, 980 PUC_PORT_2S, 0x14, 4, 0, 981 }, 982 983 { 0x14d2, 0x8028, 0xffff, 0, 984 "VScom 200Li", 985 DEFAULT_RCLK, 986 PUC_PORT_2S, 0x20, 0, 8, 987 }, 988 989 /* 990 * VScom (Titan?) PCI-800L. More modern variant of the 991 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 992 * two of them obviously implemented as macro cells in 993 * the ASIC. This causes the weird port access pattern 994 * below, where two of the IO port ranges each access 995 * one of the ASIC UARTs, and a block of IO addresses 996 * access the external UARTs. 997 */ 998 { 0x14d2, 0x8080, 0xffff, 0, 999 "Titan VScom PCI-800L", 1000 DEFAULT_RCLK * 8, 1001 PUC_PORT_8S, 0x14, -1, -1, 1002 .config_function = puc_config_titan 1003 }, 1004 1005 /* 1006 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 1007 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 1008 * device ID 3 and PCI device 1 device ID 4. 1009 */ 1010 { 0x14d2, 0xa003, 0xffff, 0, 1011 "Titan PCI-800H", 1012 DEFAULT_RCLK * 8, 1013 PUC_PORT_4S, 0x10, 0, 8, 1014 }, 1015 1016 { 0x14d2, 0xa004, 0xffff, 0, 1017 "Titan PCI-800H", 1018 DEFAULT_RCLK * 8, 1019 PUC_PORT_4S, 0x10, 0, 8, 1020 }, 1021 1022 { 0x14d2, 0xa005, 0xffff, 0, 1023 "Titan PCI-200H", 1024 DEFAULT_RCLK * 8, 1025 PUC_PORT_2S, 0x10, 0, 8, 1026 }, 1027 1028 { 0x14d2, 0xe020, 0xffff, 0, 1029 "Titan VScom PCI-200HV2", 1030 DEFAULT_RCLK * 8, 1031 PUC_PORT_2S, 0x10, 4, 0, 1032 }, 1033 1034 { 0x14d2, 0xa007, 0xffff, 0, 1035 "Titan VScom PCIex-800H", 1036 DEFAULT_RCLK * 8, 1037 PUC_PORT_4S, 0x10, 0, 8, 1038 }, 1039 1040 { 0x14d2, 0xa008, 0xffff, 0, 1041 "Titan VScom PCIex-800H", 1042 DEFAULT_RCLK * 8, 1043 PUC_PORT_4S, 0x10, 0, 8, 1044 }, 1045 1046 { 0x14db, 0x2130, 0xffff, 0, 1047 "Avlab Technology, PCI IO 2S", 1048 DEFAULT_RCLK, 1049 PUC_PORT_2S, 0x10, 4, 0, 1050 }, 1051 1052 { 0x14db, 0x2150, 0xffff, 0, 1053 "Avlab Low Profile PCI 4 Serial", 1054 DEFAULT_RCLK, 1055 PUC_PORT_4S, 0x10, 4, 0, 1056 }, 1057 1058 { 0x14db, 0x2152, 0xffff, 0, 1059 "Avlab Low Profile PCI 4 Serial", 1060 DEFAULT_RCLK, 1061 PUC_PORT_4S, 0x10, 4, 0, 1062 }, 1063 1064 { 0x1592, 0x0781, 0xffff, 0, 1065 "Syba Tech Ltd. PCI-4S2P-550-ECP", 1066 DEFAULT_RCLK, 1067 PUC_PORT_4S1P, 0x10, 0, -1, 1068 .config_function = puc_config_syba 1069 }, 1070 1071 { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 1072 "Sunix SER5xxxx 2-port serial", 1073 DEFAULT_RCLK * 8, 1074 PUC_PORT_2S, 0x10, 0, 8, 1075 }, 1076 1077 { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 1078 "Sunix SER5xxxx 4-port serial", 1079 DEFAULT_RCLK * 8, 1080 PUC_PORT_4S, 0x10, 0, 8, 1081 }, 1082 1083 { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1084 "Sunix SER5xxxx 8-port serial", 1085 DEFAULT_RCLK * 8, 1086 PUC_PORT_8S, -1, -1, -1, 1087 .config_function = puc_config_sunix 1088 }, 1089 1090 { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1091 "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1092 DEFAULT_RCLK * 8, 1093 PUC_PORT_1S1P, -1, -1, -1, 1094 .config_function = puc_config_sunix 1095 }, 1096 1097 { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1098 "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1099 DEFAULT_RCLK * 8, 1100 PUC_PORT_2S1P, -1, -1, -1, 1101 .config_function = puc_config_sunix 1102 }, 1103 1104 { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1105 "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1106 DEFAULT_RCLK * 8, 1107 PUC_PORT_4S1P, -1, -1, -1, 1108 .config_function = puc_config_sunix 1109 }, 1110 1111 { 0x5372, 0x6872, 0xffff, 0, 1112 "Feasso PCI FPP-02 2S1P", 1113 DEFAULT_RCLK, 1114 PUC_PORT_2S1P, 0x10, 4, 0, 1115 }, 1116 1117 { 0x5372, 0x6873, 0xffff, 0, 1118 "Sun 1040 PCI Quad Serial", 1119 DEFAULT_RCLK, 1120 PUC_PORT_4S, 0x10, 4, 0, 1121 }, 1122 1123 { 0x6666, 0x0001, 0xffff, 0, 1124 "Decision Computer Inc, PCCOM 4-port serial", 1125 DEFAULT_RCLK, 1126 PUC_PORT_4S, 0x1c, 0, 8, 1127 }, 1128 1129 { 0x6666, 0x0002, 0xffff, 0, 1130 "Decision Computer Inc, PCCOM 8-port serial", 1131 DEFAULT_RCLK, 1132 PUC_PORT_8S, 0x1c, 0, 8, 1133 }, 1134 1135 { 0x6666, 0x0004, 0xffff, 0, 1136 "PCCOM dual port RS232/422/485", 1137 DEFAULT_RCLK, 1138 PUC_PORT_2S, 0x1c, 0, 8, 1139 }, 1140 1141 { 0x9710, 0x9815, 0xffff, 0, 1142 "NetMos NM9815 Dual 1284 Printer port", 1143 0, 1144 PUC_PORT_2P, 0x10, 8, 0, 1145 }, 1146 1147 /* 1148 * This is more specific than the generic NM9835 entry, and is placed 1149 * here to _prevent_ puc(4) from claiming this single port card. 1150 * 1151 * uart(4) will claim this device. 1152 */ 1153 { 0x9710, 0x9835, 0x1000, 1, 1154 "NetMos NM9835 based 1-port serial", 1155 DEFAULT_RCLK, 1156 PUC_PORT_1S, 0x10, 4, 0, 1157 }, 1158 1159 { 0x9710, 0x9835, 0x1000, 2, 1160 "NetMos NM9835 based 2-port serial", 1161 DEFAULT_RCLK, 1162 PUC_PORT_2S, 0x10, 4, 0, 1163 }, 1164 1165 { 0x9710, 0x9835, 0xffff, 0, 1166 "NetMos NM9835 Dual UART and 1284 Printer port", 1167 DEFAULT_RCLK, 1168 PUC_PORT_2S1P, 0x10, 4, 0, 1169 }, 1170 1171 { 0x9710, 0x9845, 0x1000, 0x0006, 1172 "NetMos NM9845 6 Port UART", 1173 DEFAULT_RCLK, 1174 PUC_PORT_6S, 0x10, 4, 0, 1175 }, 1176 1177 { 0x9710, 0x9845, 0xffff, 0, 1178 "NetMos NM9845 Quad UART and 1284 Printer port", 1179 DEFAULT_RCLK, 1180 PUC_PORT_4S1P, 0x10, 4, 0, 1181 }, 1182 1183 { 0x9710, 0x9865, 0xa000, 0x3002, 1184 "NetMos NM9865 Dual UART", 1185 DEFAULT_RCLK, 1186 PUC_PORT_2S, 0x10, 4, 0, 1187 }, 1188 1189 { 0x9710, 0x9865, 0xa000, 0x3003, 1190 "NetMos NM9865 Triple UART", 1191 DEFAULT_RCLK, 1192 PUC_PORT_3S, 0x10, 4, 0, 1193 }, 1194 1195 { 0x9710, 0x9865, 0xa000, 0x3004, 1196 "NetMos NM9865 Quad UART", 1197 DEFAULT_RCLK, 1198 PUC_PORT_4S, 0x10, 4, 0, 1199 }, 1200 1201 { 0x9710, 0x9865, 0xa000, 0x3011, 1202 "NetMos NM9865 Single UART and 1284 Printer port", 1203 DEFAULT_RCLK, 1204 PUC_PORT_1S1P, 0x10, 4, 0, 1205 }, 1206 1207 { 0x9710, 0x9865, 0xa000, 0x3012, 1208 "NetMos NM9865 Dual UART and 1284 Printer port", 1209 DEFAULT_RCLK, 1210 PUC_PORT_2S1P, 0x10, 4, 0, 1211 }, 1212 1213 { 0x9710, 0x9865, 0xa000, 0x3020, 1214 "NetMos NM9865 Dual 1284 Printer port", 1215 DEFAULT_RCLK, 1216 PUC_PORT_2P, 0x10, 4, 0, 1217 }, 1218 1219 { 0xb00c, 0x021c, 0xffff, 0, 1220 "IC Book Labs Gunboat x4 Lite", 1221 DEFAULT_RCLK, 1222 PUC_PORT_4S, 0x10, 0, 8, 1223 .config_function = puc_config_icbook 1224 }, 1225 1226 { 0xb00c, 0x031c, 0xffff, 0, 1227 "IC Book Labs Gunboat x4 Pro", 1228 DEFAULT_RCLK, 1229 PUC_PORT_4S, 0x10, 0, 8, 1230 .config_function = puc_config_icbook 1231 }, 1232 1233 { 0xb00c, 0x041c, 0xffff, 0, 1234 "IC Book Labs Ironclad x8 Lite", 1235 DEFAULT_RCLK, 1236 PUC_PORT_8S, 0x10, 0, 8, 1237 .config_function = puc_config_icbook 1238 }, 1239 1240 { 0xb00c, 0x051c, 0xffff, 0, 1241 "IC Book Labs Ironclad x8 Pro", 1242 DEFAULT_RCLK, 1243 PUC_PORT_8S, 0x10, 0, 8, 1244 .config_function = puc_config_icbook 1245 }, 1246 1247 { 0xb00c, 0x081c, 0xffff, 0, 1248 "IC Book Labs Dreadnought x16 Pro", 1249 DEFAULT_RCLK * 8, 1250 PUC_PORT_16S, 0x10, 0, 8, 1251 .config_function = puc_config_icbook 1252 }, 1253 1254 { 0xb00c, 0x091c, 0xffff, 0, 1255 "IC Book Labs Dreadnought x16 Lite", 1256 DEFAULT_RCLK, 1257 PUC_PORT_16S, 0x10, 0, 8, 1258 .config_function = puc_config_icbook 1259 }, 1260 1261 { 0xb00c, 0x0a1c, 0xffff, 0, 1262 "IC Book Labs Gunboat x2 Low Profile", 1263 DEFAULT_RCLK, 1264 PUC_PORT_2S, 0x10, 0, 8, 1265 }, 1266 1267 { 0xb00c, 0x0b1c, 0xffff, 0, 1268 "IC Book Labs Gunboat x4 Low Profile", 1269 DEFAULT_RCLK, 1270 PUC_PORT_4S, 0x10, 0, 8, 1271 .config_function = puc_config_icbook 1272 }, 1273 1274 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1275}; 1276 1277static int 1278puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1279 intptr_t *res __unused) 1280{ 1281 const struct puc_cfg *cfg; 1282 struct resource *cres; 1283 struct puc_bar *bar; 1284 device_t cdev, dev; 1285 bus_size_t off; 1286 int base, crtype, fixed, high, i, oxpcie; 1287 uint8_t acr, func, mask; 1288 1289 if (cmd != PUC_CFG_SETUP) 1290 return (ENXIO); 1291 1292 base = fixed = oxpcie = 0; 1293 crtype = SYS_RES_IOPORT; 1294 acr = mask = 0x0; 1295 func = high = 1; 1296 off = 0x60; 1297 1298 cfg = sc->sc_cfg; 1299 switch (cfg->subvendor) { 1300 case 0x13fe: 1301 switch (cfg->device) { 1302 case 0xa102: 1303 high = 0; 1304 break; 1305 default: 1306 break; 1307 } 1308 default: 1309 break; 1310 } 1311 if (fixed == 1) 1312 goto setup; 1313 1314 dev = sc->sc_dev; 1315 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1316 pci_get_slot(dev), func); 1317 if (cdev == NULL) { 1318 device_printf(dev, "could not find config function\n"); 1319 return (ENXIO); 1320 } 1321 1322 i = PCIR_BAR(0); 1323 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE); 1324 if (cres == NULL) { 1325 device_printf(dev, "could not allocate config resource\n"); 1326 return (ENXIO); 1327 } 1328 1329 if (oxpcie == 0) { 1330 mask = bus_read_1(cres, off); 1331 if (pci_get_function(dev) == 1) 1332 base = 4; 1333 } 1334 1335 setup: 1336 for (i = 0; i < sc->sc_nports; ++i) { 1337 device_printf(dev, "port %d: ", i); 1338 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid); 1339 if (bar == NULL) { 1340 printf("could not get BAR\n"); 1341 continue; 1342 } 1343 1344 if (fixed == 0) { 1345 if ((mask & (1 << (base + i))) == 0) { 1346 acr = 0; 1347 printf("RS-232\n"); 1348 } else { 1349 acr = (high == 1 ? 0x18 : 0x10); 1350 printf("RS-422/RS-485, active-%s auto-DTR\n", 1351 high == 1 ? "high" : "low"); 1352 } 1353 } 1354 1355 bus_write_1(bar->b_res, REG_SPR, REG_ACR); 1356 bus_write_1(bar->b_res, REG_ICR, acr); 1357 } 1358 1359 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres); 1360 return (0); 1361} 1362 1363static int 1364puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port, 1365 intptr_t *res) 1366{ 1367 1368 switch (cmd) { 1369 case PUC_CFG_GET_OFS: 1370 *res = 8 * (port & 1); 1371 return (0); 1372 case PUC_CFG_GET_RID: 1373 *res = 0x14 + (port >> 1) * 4; 1374 return (0); 1375 default: 1376 break; 1377 } 1378 return (ENXIO); 1379} 1380 1381static int 1382puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1383 intptr_t *res) 1384{ 1385 const struct puc_cfg *cfg = sc->sc_cfg; 1386 1387 if (cmd == PUC_CFG_GET_OFS) { 1388 if (cfg->subdevice == 0x1282) /* Everest SP */ 1389 port <<= 1; 1390 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1391 port = (port == 3) ? 4 : port; 1392 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1393 return (0); 1394 } 1395 return (ENXIO); 1396} 1397 1398static int 1399puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1400 int port, intptr_t *res) 1401{ 1402 1403 if (cmd == PUC_CFG_GET_OFS) { 1404 *res = port * 0x200; 1405 return (0); 1406 } 1407 return (ENXIO); 1408} 1409 1410static int 1411puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1412 int port, intptr_t *res) 1413{ 1414 1415 if (cmd == PUC_CFG_GET_OFS) { 1416 *res = port * 0x400; 1417 return (0); 1418 } 1419 return (ENXIO); 1420} 1421 1422static int 1423puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1424 int port __unused, intptr_t *res) 1425{ 1426 1427 if (cmd == PUC_CFG_GET_ILR) { 1428 *res = PUC_ILR_DIGI; 1429 return (0); 1430 } 1431 return (ENXIO); 1432} 1433 1434static int 1435puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1436 intptr_t *res) 1437{ 1438 const struct puc_cfg *cfg = sc->sc_cfg; 1439 1440 if (cmd == PUC_CFG_GET_OFS) { 1441 if (port == 3 && (cfg->device == 0x1045 || 1442 cfg->device == 0x1144)) 1443 port = 7; 1444 *res = port * 0x200; 1445 1446 return 0; 1447 } 1448 return (ENXIO); 1449} 1450 1451static int 1452puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1453 int port __unused, intptr_t *res) 1454{ 1455 const struct puc_cfg *cfg = sc->sc_cfg; 1456 struct puc_bar *bar; 1457 uint8_t v0, v1; 1458 1459 switch (cmd) { 1460 case PUC_CFG_SETUP: 1461 /* 1462 * Check if the scratchpad register is enabled or if the 1463 * interrupt status and options registers are active. 1464 */ 1465 bar = puc_get_bar(sc, cfg->rid); 1466 if (bar == NULL) 1467 return (ENXIO); 1468 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); 1469 bus_write_1(bar->b_res, REG_SPR, 0); 1470 v0 = bus_read_1(bar->b_res, REG_SPR); 1471 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); 1472 v1 = bus_read_1(bar->b_res, REG_SPR); 1473 bus_write_1(bar->b_res, REG_LCR, 0); 1474 sc->sc_cfg_data = (v0 << 8) | v1; 1475 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1476 /* 1477 * The SPR register echoed the two values written 1478 * by us. This means that the SPAD jumper is set. 1479 */ 1480 device_printf(sc->sc_dev, "warning: extra features " 1481 "not usable -- SPAD compatibility enabled\n"); 1482 return (0); 1483 } 1484 if (v0 != 0) { 1485 /* 1486 * The first value doesn't match. This can only mean 1487 * that the SPAD jumper is not set and that a non- 1488 * standard fixed clock multiplier jumper is set. 1489 */ 1490 if (bootverbose) 1491 device_printf(sc->sc_dev, "fixed clock rate " 1492 "multiplier of %d\n", 1 << v0); 1493 if (v0 < -cfg->clock) 1494 device_printf(sc->sc_dev, "warning: " 1495 "suboptimal fixed clock rate multiplier " 1496 "setting\n"); 1497 return (0); 1498 } 1499 /* 1500 * The first value matched, but the second didn't. We know 1501 * that the SPAD jumper is not set. We also know that the 1502 * clock rate multiplier is software controlled *and* that 1503 * we just programmed it to the maximum allowed. 1504 */ 1505 if (bootverbose) 1506 device_printf(sc->sc_dev, "clock rate multiplier of " 1507 "%d selected\n", 1 << -cfg->clock); 1508 return (0); 1509 case PUC_CFG_GET_CLOCK: 1510 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1511 v1 = sc->sc_cfg_data & 0xff; 1512 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1513 /* 1514 * XXX With the SPAD jumper applied, there's no 1515 * easy way of knowing if there's also a clock 1516 * rate multiplier jumper installed. Let's hope 1517 * not ... 1518 */ 1519 *res = DEFAULT_RCLK; 1520 } else if (v0 == 0) { 1521 /* 1522 * No clock rate multiplier jumper installed, 1523 * so we programmed the board with the maximum 1524 * multiplier allowed as given to us in the 1525 * clock field of the config record (negated). 1526 */ 1527 *res = DEFAULT_RCLK << -cfg->clock; 1528 } else 1529 *res = DEFAULT_RCLK << v0; 1530 return (0); 1531 case PUC_CFG_GET_ILR: 1532 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1533 v1 = sc->sc_cfg_data & 0xff; 1534 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? 1535 PUC_ILR_NONE : PUC_ILR_QUATECH; 1536 return (0); 1537 default: 1538 break; 1539 } 1540 return (ENXIO); 1541} 1542 1543static int 1544puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1545 intptr_t *res) 1546{ 1547 static int base[] = { 0x251, 0x3f0, 0 }; 1548 const struct puc_cfg *cfg = sc->sc_cfg; 1549 struct puc_bar *bar; 1550 int efir, idx, ofs; 1551 uint8_t v; 1552 1553 switch (cmd) { 1554 case PUC_CFG_SETUP: 1555 bar = puc_get_bar(sc, cfg->rid); 1556 if (bar == NULL) 1557 return (ENXIO); 1558 1559 /* configure both W83877TFs */ 1560 bus_write_1(bar->b_res, 0x250, 0x89); 1561 bus_write_1(bar->b_res, 0x3f0, 0x87); 1562 bus_write_1(bar->b_res, 0x3f0, 0x87); 1563 idx = 0; 1564 while (base[idx] != 0) { 1565 efir = base[idx]; 1566 bus_write_1(bar->b_res, efir, 0x09); 1567 v = bus_read_1(bar->b_res, efir + 1); 1568 if ((v & 0x0f) != 0x0c) 1569 return (ENXIO); 1570 bus_write_1(bar->b_res, efir, 0x16); 1571 v = bus_read_1(bar->b_res, efir + 1); 1572 bus_write_1(bar->b_res, efir, 0x16); 1573 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1574 bus_write_1(bar->b_res, efir, 0x16); 1575 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1576 ofs = base[idx] & 0x300; 1577 bus_write_1(bar->b_res, efir, 0x23); 1578 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1579 bus_write_1(bar->b_res, efir, 0x24); 1580 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1581 bus_write_1(bar->b_res, efir, 0x25); 1582 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1583 bus_write_1(bar->b_res, efir, 0x17); 1584 bus_write_1(bar->b_res, efir + 1, 0x03); 1585 bus_write_1(bar->b_res, efir, 0x28); 1586 bus_write_1(bar->b_res, efir + 1, 0x43); 1587 idx++; 1588 } 1589 bus_write_1(bar->b_res, 0x250, 0xaa); 1590 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1591 return (0); 1592 case PUC_CFG_GET_OFS: 1593 switch (port) { 1594 case 0: 1595 *res = 0x2f8; 1596 return (0); 1597 case 1: 1598 *res = 0x2e8; 1599 return (0); 1600 case 2: 1601 *res = 0x3f8; 1602 return (0); 1603 case 3: 1604 *res = 0x3e8; 1605 return (0); 1606 case 4: 1607 *res = 0x278; 1608 return (0); 1609 } 1610 break; 1611 default: 1612 break; 1613 } 1614 return (ENXIO); 1615} 1616 1617static int 1618puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1619 intptr_t *res) 1620{ 1621 const struct puc_cfg *cfg = sc->sc_cfg; 1622 1623 switch (cmd) { 1624 case PUC_CFG_GET_OFS: 1625 if (cfg->ports == PUC_PORT_8S) { 1626 *res = (port > 4) ? 8 * (port - 4) : 0; 1627 return (0); 1628 } 1629 break; 1630 case PUC_CFG_GET_RID: 1631 if (cfg->ports == PUC_PORT_8S) { 1632 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1633 return (0); 1634 } 1635 if (cfg->ports == PUC_PORT_2S1P) { 1636 switch (port) { 1637 case 0: *res = 0x10; return (0); 1638 case 1: *res = 0x14; return (0); 1639 case 2: *res = 0x1c; return (0); 1640 } 1641 } 1642 break; 1643 default: 1644 break; 1645 } 1646 return (ENXIO); 1647} 1648 1649static int 1650puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1651 intptr_t *res) 1652{ 1653 static const uint16_t dual[] = { 1654 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1655 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1656 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1657 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1658 0xD079, 0 1659 }; 1660 static const uint16_t quad[] = { 1661 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1662 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1663 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1664 0xB157, 0 1665 }; 1666 static const uint16_t octa[] = { 1667 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1668 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1669 }; 1670 static const struct { 1671 int ports; 1672 const uint16_t *ids; 1673 } subdevs[] = { 1674 { 2, dual }, 1675 { 4, quad }, 1676 { 8, octa }, 1677 { 0, NULL } 1678 }; 1679 static char desc[64]; 1680 int dev, id; 1681 uint16_t subdev; 1682 1683 switch (cmd) { 1684 case PUC_CFG_GET_CLOCK: 1685 if (port < 2) 1686 *res = DEFAULT_RCLK * 8; 1687 else 1688 *res = DEFAULT_RCLK; 1689 return (0); 1690 case PUC_CFG_GET_DESC: 1691 snprintf(desc, sizeof(desc), 1692 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1693 *res = (intptr_t)desc; 1694 return (0); 1695 case PUC_CFG_GET_NPORTS: 1696 subdev = pci_get_subdevice(sc->sc_dev); 1697 dev = 0; 1698 while (subdevs[dev].ports != 0) { 1699 id = 0; 1700 while (subdevs[dev].ids[id] != 0) { 1701 if (subdev == subdevs[dev].ids[id]) { 1702 sc->sc_cfg_data = subdevs[dev].ports; 1703 *res = sc->sc_cfg_data; 1704 return (0); 1705 } 1706 id++; 1707 } 1708 dev++; 1709 } 1710 return (ENXIO); 1711 case PUC_CFG_GET_OFS: 1712 *res = (port == 1 || port == 3) ? 8 : 0; 1713 return (0); 1714 case PUC_CFG_GET_RID: 1715 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1716 return (0); 1717 case PUC_CFG_GET_TYPE: 1718 *res = PUC_TYPE_SERIAL; 1719 return (0); 1720 default: 1721 break; 1722 } 1723 return (ENXIO); 1724} 1725 1726static int 1727puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1728 int port __unused, intptr_t *res) 1729{ 1730 1731 switch (cmd) { 1732 case PUC_CFG_GET_CLOCK: 1733 /* 1734 * OXu16PCI954 use a 14.7456 MHz clock by default while 1735 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 1736 */ 1737 if (pci_get_revid(sc->sc_dev) == 1) 1738 *res = DEFAULT_RCLK * 8; 1739 else 1740 *res = DEFAULT_RCLK; 1741 return (0); 1742 default: 1743 break; 1744 } 1745 return (ENXIO); 1746} 1747 1748static int 1749puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1750 intptr_t *res) 1751{ 1752 const struct puc_cfg *cfg = sc->sc_cfg; 1753 int idx; 1754 struct puc_bar *bar; 1755 uint8_t value; 1756 1757 switch (cmd) { 1758 case PUC_CFG_SETUP: 1759 device_printf(sc->sc_dev, "%d UARTs detected\n", 1760 sc->sc_nports); 1761 1762 /* Set UARTs to enhanced mode */ 1763 bar = puc_get_bar(sc, cfg->rid); 1764 if (bar == NULL) 1765 return (ENXIO); 1766 for (idx = 0; idx < sc->sc_nports; idx++) { 1767 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1768 0x92); 1769 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1770 value | 0x10); 1771 } 1772 return (0); 1773 case PUC_CFG_GET_LEN: 1774 *res = 0x200; 1775 return (0); 1776 case PUC_CFG_GET_NPORTS: 1777 /* 1778 * Check if we are being called from puc_bfe_attach() 1779 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1780 * puc_get_bar(), so we return a value of 16. This has 1781 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC, 1782 * sc->sc_cfg_data will not contain the true number of 1783 * ports in PUC_CFG_GET_DESC, but we are not implementing 1784 * that call for this device family anyway. 1785 * 1786 * The check is for initialization of sc->sc_bar[idx], 1787 * which is only done in puc_bfe_attach(). 1788 */ 1789 idx = 0; 1790 do { 1791 if (sc->sc_bar[idx++].b_rid != -1) { 1792 sc->sc_cfg_data = 16; 1793 *res = sc->sc_cfg_data; 1794 return (0); 1795 } 1796 } while (idx < PUC_PCI_BARS); 1797 1798 bar = puc_get_bar(sc, cfg->rid); 1799 if (bar == NULL) 1800 return (ENXIO); 1801 1802 value = bus_read_1(bar->b_res, 0x04); 1803 if (value == 0) 1804 return (ENXIO); 1805 1806 sc->sc_cfg_data = value; 1807 *res = sc->sc_cfg_data; 1808 return (0); 1809 case PUC_CFG_GET_OFS: 1810 *res = 0x1000 + (port << 9); 1811 return (0); 1812 case PUC_CFG_GET_TYPE: 1813 *res = PUC_TYPE_SERIAL; 1814 return (0); 1815 default: 1816 break; 1817 } 1818 return (ENXIO); 1819} 1820 1821static int 1822puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1823 intptr_t *res) 1824{ 1825 int error; 1826 1827 switch (cmd) { 1828 case PUC_CFG_GET_OFS: 1829 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1830 if (error != 0) 1831 return (error); 1832 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 1833 return (0); 1834 case PUC_CFG_GET_RID: 1835 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1836 if (error != 0) 1837 return (error); 1838 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 1839 return (0); 1840 default: 1841 break; 1842 } 1843 return (ENXIO); 1844} 1845 1846static int 1847puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1848 int port, intptr_t *res) 1849{ 1850 1851 switch (cmd) { 1852 case PUC_CFG_GET_OFS: 1853 *res = (port < 3) ? 0 : (port - 2) << 3; 1854 return (0); 1855 case PUC_CFG_GET_RID: 1856 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1857 return (0); 1858 default: 1859 break; 1860 } 1861 return (ENXIO); 1862} 1863