1/*******************************************************************************
2*Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved.
3*
4*Redistribution and use in source and binary forms, with or without modification, are permitted provided
5*that the following conditions are met:
6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
7*following disclaimer.
8*2. Redistributions in binary form must reproduce the above copyright notice,
9*this list of conditions and the following disclaimer in the documentation and/or other materials provided
10*with the distribution.
11*
12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
20*
21* $FreeBSD$
22*
23********************************************************************************/
24/*******************************************************************************/
25
26/*! \file samacro.h
27 *  \brief The file defines macros used in LL sTSDK
28 */
29
30/*******************************************************************************/
31
32#ifndef __SAMACRO_H__
33#define __SAMACRO_H__
34
35#if defined(SALLSDK_DEBUG)
36#define MPI_IBQ_IOMB_LOG_ENABLE
37#define MPI_OBQ_IOMB_LOG_ENABLE
38#endif
39
40/*! \def MIN(a,b)
41* \brief MIN macro
42*
43* use to find MIN of two values
44*/
45#ifndef MIN
46#define MIN(a,b) ((a) < (b) ? (a) : (b))
47#endif
48
49/*! \def MAX(a,b)
50* \brief MAX macro
51*
52* use to find MAX of two values
53*/
54#ifndef MAX
55#define MAX(a,b) ((a) < (b) ? (b) : (a))
56#endif
57
58/*************************************************************************************************
59 *                      define Phy status macros                                                 *
60 *************************************************************************************************/
61/*! \def PHY_STATUS_SET(pPhy, value)
62* \brief PHY_STATUS_SET macro
63*
64* use to set phy status
65*/
66#define PHY_STATUS_SET(pPhy, value)  ((pPhy)->status = (((pPhy)->status & 0xFFFF0000) | (value)))
67
68/*! \def PHY_STATUS_CHECK(pPhy, value)
69* \brief PHY_STATUS_CHECK macro
70*
71* use to check phy status
72*/
73#define PHY_STATUS_CHECK(pPhy, value)  ( ((pPhy)->status & 0x0000FFFF) == (value) )
74
75
76/************************************************************************************
77 *                        define CBUFFER operation macros                           *
78 ************************************************************************************/
79/*! \def AGSAMEM_ELEMENT_READ(pMem, index)
80* \brief AGSAMEM_ELEMENT_READ macro
81*
82* use to read an element of a memory array
83*/
84#define AGSAMEM_ELEMENT_READ(pMem, index) (((bit8 *)(pMem)->virtPtr) + (pMem)->singleElementLength * (index))
85
86/************************************************************************************
87 *                        define Chip ID macro                                      *
88 ************************************************************************************/
89
90#define SA_TREAT_SFC_AS_SPC
91
92#ifdef SA_TREAT_SFC_AS_SPC
93#define SA_SFC_AS_SPC 1
94#define SA_SFC_AS_SPCV 0
95#else /* TREAT_SFC_AS_SPCv */
96#define SA_SFC_AS_SPC 0
97#define SA_SFC_AS_SPCV 1
98#endif /* SA_TREAT_SFC_AS_SPC */
99
100#define IS_SDKDATA(agr) (((agr)->sdkData != agNULL ) ? 1 : 0) /* returns true if sdkdata is available */
101
102#define smIsCfgSpcREV_A(agr)    (8  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */
103#define smIsCfgSpcREV_B(agr)    (4  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */
104#define smIsCfgSpcREV_C(agr)    (5  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */
105
106#define smIsCfgVREV_A(agr)    (4  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */
107#define smIsCfgVREV_B(agr)    (5  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */
108#define smIsCfgVREV_C(agr)    (6  ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */
109
110#define smIsCfg8001(agr)   (VEN_DEV_SPC   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPC */
111#define smIsCfg8081(agr)   (VEN_DEV_HIL   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000 ) ? 1 : 0) /* returns true config space read is Hialeah */
112
113#define smIsCfg_V8025(agr) (VEN_DEV_SFC   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SFC  */
114
115#define smIsCfg_V8008(agr) (VEN_DEV_SPCV  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
116#define smIsCfg_V8009(agr) (VEN_DEV_SPCVE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
117#define smIsCfg_V8018(agr) (VEN_DEV_SPCVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
118#define smIsCfg_V8019(agr) (VEN_DEV_SPCVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000)  ? 1 : 0) /* returns true config space read is SPCv */
119
120#define smIsCfg_V8088(agr) (VEN_DEV_ADAPVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */
121#define smIsCfg_V8089(agr) (VEN_DEV_ADAPVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */
122
123#define smIsCfg_V8070(agr) (VEN_DEV_SPC12V  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
124#define smIsCfg_V8071(agr) (VEN_DEV_SPC12VE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
125#define smIsCfg_V8072(agr) (VEN_DEV_SPC12VP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
126#define smIsCfg_V8073(agr) (VEN_DEV_SPC12VEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
127
128#define smIsCfg_V8074(agr) (VEN_DEV_SPC12ADP   == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
129#define smIsCfg_V8075(agr) (VEN_DEV_SPC12ADPE  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
130#define smIsCfg_V8076(agr) (VEN_DEV_SPC12ADPP  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
131#define smIsCfg_V8077(agr) (VEN_DEV_SPC12ADPEP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
132#define smIsCfg_V8006(agr) (VEN_DEV_SPC12SATA  == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */
133#define smIsCfg_V9015(agr) (VEN_DEV_9015 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
134#define smIsCfg_V9060(agr) (VEN_DEV_9060 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */
135
136#define smIsCfg_SPC_ANY(agr) ((smIsCfg8001((agr))    == 1) ? 1 : \
137                              (smIsCfg8081((agr))    == 1) ? 1 : \
138                              (smIsCfg_V8025((agr)) == 1) ? SA_SFC_AS_SPC : 0)
139
140#define smIS_SPCV8008(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCV )  ? 1 : 0) : smIsCfg_V8008((agr)))
141#define smIS_SPCV8009(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVE)  ? 1 : 0) : smIsCfg_V8009((agr)))
142#define smIS_SPCV8018(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVP)  ? 1 : 0) : smIsCfg_V8018((agr)))
143#define smIS_SPCV8019(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVEP) ? 1 : 0) : smIsCfg_V8019((agr)))
144#define smIS_ADAP8088(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVP) ? 1 : 0) : smIsCfg_V8088((agr)))
145#define smIS_ADAP8089(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVEP)? 1 : 0): smIsCfg_V8089((agr)))
146
147#define smIS_SPCV8070(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12V ) ? 1 : 0) : smIsCfg_V8070((agr)))
148#define smIS_SPCV8071(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VE) ? 1 : 0) : smIsCfg_V8071((agr)))
149#define smIS_SPCV8072(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VP) ? 1 : 0) : smIsCfg_V8072((agr)))
150#define smIS_SPCV8073(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VEP)? 1 : 0) : smIsCfg_V8073((agr)))
151
152#define smIS_SPCV8074(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADP ) ? 1 : 0) : smIsCfg_V8074((agr)))
153#define smIS_SPCV8075(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPE) ? 1 : 0) : smIsCfg_V8075((agr)))
154#define smIS_SPCV8076(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPP) ? 1 : 0) : smIsCfg_V8076((agr)))
155#define smIS_SPCV8077(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPEP)? 1 : 0) : smIsCfg_V8077((agr)))
156#define smIS_SPCV8006(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12SATA) ? 1 : 0) : smIsCfg_V8006((agr)))
157#define smIS_SPCV9015(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9015)    ? 1 : 0) : smIsCfg_V9015((agr)))
158#define smIS_SPCV9060(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9060)    ? 1 : 0) : smIsCfg_V9060((agr)))
159
160#define smIS_SPCV8025(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC  ) ? 1 : 0) : smIsCfg_V8025((agr)))
161
162#define smIS_SFC(agr)      (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC  ) ? 1 : 0) : smIsCfg_V8025((agr)))
163#define smIS_spc8001(agr)  (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC  ) ? 1 : 0) : smIsCfg8001((agr)))
164#define smIS_spc8081(agr)  (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_HIL  ) ? 1 : 0) : smIsCfg8081((agr)))
165
166
167
168#define smIS_SFC_AS_SPC(agr) ((smIS_SFC((agr)) == 1) ? SA_SFC_AS_SPC : 0 )
169
170#define smIS_SFC_AS_V(agr)   ((smIS_SFC((agr)) == 1 )? SA_SFC_AS_SPCV : 0 )
171
172/* Use 64 bit interrupts for SPCv, before getting saroot. Once saroot available only use 64bit when needed */
173#define smIS64bInt(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->Use64bit) ? 1 : 0)  : smIS_SPCV(agr))
174
175#define WHATTABLE(agr)                                                         \
176(                                                                               \
177IS_SDKDATA((agr)) ?                                                               \
178  (smIS_SPC((agr))  ? &SPCTable[0]  : (smIS_SPCV((agr)) ? &SPC_V_Table[0] : agNULL ) )  \
179:                                                                               \
180  (smIsCfg_SPC_ANY((agr)) ? &SPCTable[0] : (smIsCfg_V_ANY((agr)) ? &SPC_V_Table[0] : agNULL ) ) \
181) \
182
183#if defined(SALLSDK_DEBUG)
184/*
185* for debugging purposes.
186*/
187extern bit32 gLLDebugLevel;
188
189#define SA_DBG0(format) ossaLogDebugString(gLLDebugLevel, 0, format)
190#define SA_DBG1(format) ossaLogDebugString(gLLDebugLevel, 1, format)
191#define SA_DBG2(format) ossaLogDebugString(gLLDebugLevel, 2, format)
192#define SA_DBG3(format) ossaLogDebugString(gLLDebugLevel, 3, format)
193#define SA_DBG4(format) ossaLogDebugString(gLLDebugLevel, 4, format)
194#define SA_DBG5(format) ossaLogDebugString(gLLDebugLevel, 5, format)
195#define SA_DBG6(format) ossaLogDebugString(gLLDebugLevel, 6, format)
196
197#else
198
199#define SA_DBG0(format)
200#define SA_DBG1(format)
201#define SA_DBG2(format)
202#define SA_DBG3(format)
203#define SA_DBG4(format)
204#define SA_DBG5(format)
205#define SA_DBG6(format)
206
207#endif
208
209#define SA_ASSERT OS_ASSERT
210
211typedef enum siPrintType_e
212{
213  SA_8,
214  SA_16,
215  SA_32
216} siPrintType;
217
218#if defined(SALLSDK_DEBUG)
219#define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength) siPrintBuffer(lDebugLevel,lWidth,pHeader,pBuffer,lLength)
220#else
221#define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength)
222#endif
223
224#ifdef SALLSDK_DEBUG
225
226#define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody) siDumpSSPStartIu(agDevHandle,agRequestType,agRequestBody)
227
228#else
229
230#define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody)
231
232#endif
233
234#ifdef MPI_DEBUG_TRACE_ENABLE
235#define MPI_DEBUG_TRACE_ENTER_LOCK  ossaSingleThreadedEnter(agRoot, LL_IOMB_TRACE_LOCK);
236#define MPI_DEBUG_TRACE_LEAVE_LOCK  ossaSingleThreadedLeave(agRoot, LL_IOMB_TRACE_LOCK);
237
238#define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count) \
239  MPI_DEBUG_TRACE_ENTER_LOCK \
240 mpiTraceAdd( (queue), (pici),(ib), (iomb), (count)); \
241  MPI_DEBUG_TRACE_LEAVE_LOCK
242#else
243#define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count)
244#endif /* MPI_DEBUG_TRACE_ENABLE */
245
246#ifdef MPI_IBQ_IOMB_LOG_ENABLE
247#define MPI_IBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \
248do \
249{ \
250  bit32 i; \
251  SA_DBG3(("\n")); \
252  SA_DBG3(("mpiMsgProduce: IBQ %d\n", (qNumber))); \
253  for (i = 0; i < msgLength/16; i++) \
254  { \
255    SA_DBG3(("Inb: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \
256           *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \
257           *((bit32 *)msgHeader+(i*4)+3))); \
258  } \
259} while(0)
260#endif
261#ifdef MPI_OBQ_IOMB_LOG_ENABLE
262#define MPI_OBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \
263do \
264{ \
265  bit32 i; \
266  SA_DBG3(("\n")); \
267  SA_DBG3(("mpiMsgConsume: OBQ %d\n", qNumber)); \
268  for (i = 0; i < msgLength/16; i++) \
269  { \
270    SA_DBG3(("Out: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \
271           *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \
272           *((bit32 *)msgHeader+(i*4)+3))); \
273  } \
274} while(0)
275#endif
276
277
278/************************************************************************************
279 *                        Wait X Second                                             *
280 ************************************************************************************/
281
282#define WAIT_SECONDS(x) ((x) * 1000 * 1000 )
283#define ONE_HUNDRED_MILLISECS (100 * 1000)   /* 100,000 microseconds  */
284
285#define WAIT_INCREMENT_DEFAULT  1000
286#define WAIT_INCREMENT  (IS_SDKDATA(agRoot) ? ( ((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs ) : WAIT_INCREMENT_DEFAULT )
287// (((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs)
288
289
290#define MAKE_MODULO(a,b)  (((a) % (b)) ? ((a) - ((a) % (b))) : (a))
291
292
293#define HDA_STEP_2  1
294#define HDA_STEP_3  1
295#define HDA_STEP_4  1
296#define HDA_STEP_5  1
297#define HDA_STEP_6  1
298#define HDA_STEP_7  1
299#define HDA_STEP_8  1
300
301#endif /* __SAMACRO_H__ */
302