1/******************************************************************************* 2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3* 4*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5*that the following conditions are met: 6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7*following disclaimer. 8*2. Redistributions in binary form must reproduce the above copyright notice, 9*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10*with the distribution. 11* 12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 21********************************************************************************/ 22/*******************************************************************************/ 23/*! \file sainit.c 24 * \brief The file implements the functions to initialize the LL layer 25 * 26 */ 27/******************************************************************************/ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/pms/RefTisa/sallsdk/spc/sainit.c 315221 2017-03-14 02:06:03Z pfg $"); 30#include <dev/pms/config.h> 31 32#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h> 33#ifdef SA_ENABLE_TRACE_FUNCTIONS 34#ifdef siTraceFileID 35#undef siTraceFileID 36#endif 37#define siTraceFileID 'F' 38#endif 39 40bit32 gLLDebugLevel = 3; 41 42#if defined(SALLSDK_DEBUG) 43bit32 gLLDebugLevelSet = 0; // block reinitialize from updating 44bit32 gLLLogFuncDebugLevel = 0; 45bit32 gLLSoftResetCounter = 0; 46#endif 47 48bit32 gPollForMissingInt; 49 50#ifdef FW_EVT_LOG_TST 51void *eventLogAddress = NULL; 52#endif 53 54extern bit32 gWait_3; 55extern bit32 gWait_2; 56bit32 gFPGA_TEST = 0; // If set unblock fpga functions 57 58/******************************************************************************/ 59/*! \brief Get the memory and lock requirement from LL layer 60 * 61 * Get the memory and lock requirement from LL layer 62 * 63 * \param agRoot Handles for this instance of SAS/SATA hardware 64 * \param swConfig Pointer to the software configuration 65 * \param memoryRequirement Point to the data structure that holds the different 66 * chunks of memory that are required 67 * \param usecsPerTick micro-seconds per tick for the LL layer 68 * \param maxNumLocks maximum number of locks for the LL layer 69 * 70 * \return -void- 71 * 72 */ 73/*******************************************************************************/ 74GLOBAL void saGetRequirements( 75 agsaRoot_t *agRoot, 76 agsaSwConfig_t *swConfig, 77 agsaMemoryRequirement_t *memoryRequirement, 78 bit32 *usecsPerTick, 79 bit32 *maxNumLocks 80 ) 81{ 82 bit32 memoryReqCount = 0; 83 bit32 i; 84 static mpiConfig_t mpiConfig; 85 static mpiMemReq_t mpiMemoryRequirement; 86 87 88 /* sanity check */ 89 SA_ASSERT((agNULL != swConfig), ""); 90 SA_ASSERT((agNULL != memoryRequirement), ""); 91 SA_ASSERT((agNULL != usecsPerTick), ""); 92 SA_ASSERT((agNULL != maxNumLocks), ""); 93 94 si_memset(&mpiMemoryRequirement, 0, sizeof(mpiMemReq_t)); 95 si_memset(&mpiConfig, 0, sizeof(mpiConfig_t)); 96 97 SA_DBG1(("saGetRequirements:agRoot %p swConfig %p memoryRequirement %p usecsPerTick %p maxNumLocks %p\n",agRoot, swConfig,memoryRequirement,usecsPerTick,maxNumLocks)); 98 SA_DBG1(("saGetRequirements: usecsPerTick 0x%x (%d)\n",*usecsPerTick,*usecsPerTick)); 99 100 /* Get Resource Requirements for SPC MPI */ 101 /* Set the default/specified requirements swConfig from TD layer */ 102 siConfiguration(agRoot, &mpiConfig, agNULL, swConfig); 103 mpiRequirementsGet(&mpiConfig, &mpiMemoryRequirement); 104 105 /* memory requirement for saRoot, CACHE memory */ 106 memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength = sizeof(agsaLLRoot_t); 107 memoryRequirement->agMemory[LLROOT_MEM_INDEX].numElements = 1; 108 memoryRequirement->agMemory[LLROOT_MEM_INDEX].totalLength = sizeof(agsaLLRoot_t); 109 memoryRequirement->agMemory[LLROOT_MEM_INDEX].alignment = sizeof(void *); 110 memoryRequirement->agMemory[LLROOT_MEM_INDEX].type = AGSA_CACHED_MEM; 111 memoryReqCount ++; 112 113 SA_DBG1(("saGetRequirements: agMemory[LLROOT_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 114 memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength, 115 memoryRequirement->agMemory[LLROOT_MEM_INDEX].totalLength, 116 memoryRequirement->agMemory[LLROOT_MEM_INDEX].alignment, 117 memoryRequirement->agMemory[LLROOT_MEM_INDEX].type )); 118 119 /* memory requirement for Device Links, CACHE memory */ 120 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].singleElementLength = sizeof(agsaDeviceDesc_t); 121 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].numElements = swConfig->numDevHandles; 122 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].totalLength = sizeof(agsaDeviceDesc_t) 123 * swConfig->numDevHandles; 124 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].alignment = sizeof(void *); 125 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].type = AGSA_CACHED_MEM; 126 memoryReqCount ++; 127 SA_DBG1(("saGetRequirements: agMemory[DEVICELINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 128 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].singleElementLength, 129 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].totalLength, 130 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].alignment, 131 memoryRequirement->agMemory[DEVICELINK_MEM_INDEX].type )); 132 133 /* memory requirement for IORequest Links, CACHE memory */ 134 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].singleElementLength = sizeof(agsaIORequestDesc_t); 135 /* 136 Add SA_RESERVED_REQUEST_COUNT to guarantee quality of service 137 */ 138 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].numElements = swConfig->maxActiveIOs + SA_RESERVED_REQUEST_COUNT; 139 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].totalLength = sizeof(agsaIORequestDesc_t) * 140 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].numElements; 141 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].alignment = sizeof(void *); 142 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].type = AGSA_CACHED_MEM; 143 memoryReqCount ++; 144 145 SA_DBG1(("saGetRequirements: agMemory[IOREQLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 146 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].singleElementLength, 147 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].totalLength, 148 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].alignment, 149 memoryRequirement->agMemory[IOREQLINK_MEM_INDEX].type )); 150 151 /* memory requirement for Timer Links, CACHE memory */ 152 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].singleElementLength = sizeof(agsaTimerDesc_t); 153 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].numElements = NUM_TIMERS; 154 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].totalLength = sizeof(agsaTimerDesc_t) * NUM_TIMERS; 155 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].alignment = sizeof(void *); 156 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].type = AGSA_CACHED_MEM; 157 memoryReqCount ++; 158 SA_DBG1(("saGetRequirements: agMemory[TIMERLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 159 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].singleElementLength, 160 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].totalLength, 161 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].alignment, 162 memoryRequirement->agMemory[TIMERLINK_MEM_INDEX].type )); 163 164#ifdef SA_ENABLE_TRACE_FUNCTIONS 165 166 /* memory requirement for LL trace memory */ 167 memoryRequirement->agMemory[LL_FUNCTION_TRACE].singleElementLength = 1; 168 memoryRequirement->agMemory[LL_FUNCTION_TRACE].numElements = swConfig->TraceBufferSize; 169 memoryRequirement->agMemory[LL_FUNCTION_TRACE].totalLength = swConfig->TraceBufferSize; 170 memoryRequirement->agMemory[LL_FUNCTION_TRACE].alignment = sizeof(void *); 171 memoryRequirement->agMemory[LL_FUNCTION_TRACE].type = AGSA_CACHED_MEM; 172 memoryReqCount ++; 173 174 SA_DBG1(("saGetRequirements: agMemory[LL_FUNCTION_TRACE] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 175 memoryRequirement->agMemory[LL_FUNCTION_TRACE].singleElementLength, 176 memoryRequirement->agMemory[LL_FUNCTION_TRACE].totalLength, 177 memoryRequirement->agMemory[LL_FUNCTION_TRACE].alignment, 178 memoryRequirement->agMemory[LL_FUNCTION_TRACE].type )); 179 180#endif /* END SA_ENABLE_TRACE_FUNCTIONS */ 181 182#ifdef FAST_IO_TEST 183 { 184 agsaMem_t *agMemory = memoryRequirement->agMemory; 185 186 /* memory requirement for Super IO CACHE memory */ 187 agMemory[LL_FAST_IO].singleElementLength = sizeof(saFastRequest_t); 188 agMemory[LL_FAST_IO].numElements = LL_FAST_IO_SIZE; 189 agMemory[LL_FAST_IO].totalLength = LL_FAST_IO_SIZE * 190 agMemory[LL_FAST_IO].singleElementLength; 191 agMemory[LL_FAST_IO].alignment = sizeof(void*); 192 agMemory[LL_FAST_IO].type = AGSA_CACHED_MEM; 193 memoryReqCount ++; 194 195 SA_DBG1(("saGetRequirements: agMemory[LL_FAST_IO] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 196 memoryRequirement->agMemory[LL_FAST_IO].singleElementLength, 197 memoryRequirement->agMemory[LL_FAST_IO].totalLength, 198 memoryRequirement->agMemory[LL_FAST_IO].alignment, 199 memoryRequirement->agMemory[LL_FAST_IO].type )); 200 201 } 202#endif 203 204#ifdef SA_ENABLE_HDA_FUNCTIONS 205 { 206 agsaMem_t *agMemory = memoryRequirement->agMemory; 207 208 /* memory requirement for HDA FW image */ 209 agMemory[HDA_DMA_BUFFER].singleElementLength = (1024 * 1024); /* must be greater than size of aap1 fw image */ 210 agMemory[HDA_DMA_BUFFER].numElements = 1; 211 agMemory[HDA_DMA_BUFFER].totalLength = agMemory[HDA_DMA_BUFFER].numElements * 212 agMemory[HDA_DMA_BUFFER].singleElementLength; 213 agMemory[HDA_DMA_BUFFER].alignment = 32; 214 agMemory[HDA_DMA_BUFFER].type = AGSA_DMA_MEM; 215 memoryReqCount ++; 216 SA_DBG1(("saGetRequirements: agMemory[HDA_DMA_BUFFER] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 217 memoryRequirement->agMemory[HDA_DMA_BUFFER].singleElementLength, 218 memoryRequirement->agMemory[HDA_DMA_BUFFER].totalLength, 219 memoryRequirement->agMemory[HDA_DMA_BUFFER].alignment, 220 memoryRequirement->agMemory[HDA_DMA_BUFFER].type )); 221 } 222#endif /* SA_ENABLE_HDA_FUNCTIONS */ 223 224 /* memory requirement for MPI MSGU layer, DMA memory */ 225 for ( i = 0; i < mpiMemoryRequirement.count; i ++ ) 226 { 227 memoryRequirement->agMemory[memoryReqCount].singleElementLength = mpiMemoryRequirement.region[i].elementSize; 228 memoryRequirement->agMemory[memoryReqCount].numElements = mpiMemoryRequirement.region[i].numElements; 229 memoryRequirement->agMemory[memoryReqCount].totalLength = mpiMemoryRequirement.region[i].totalLength; 230 memoryRequirement->agMemory[memoryReqCount].alignment = mpiMemoryRequirement.region[i].alignment; 231 memoryRequirement->agMemory[memoryReqCount].type = mpiMemoryRequirement.region[i].type; 232 SA_DBG1(("saGetRequirements:MPI agMemory[%d] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n", 233 memoryReqCount, 234 memoryRequirement->agMemory[memoryReqCount].singleElementLength, 235 memoryRequirement->agMemory[memoryReqCount].totalLength, 236 memoryRequirement->agMemory[memoryReqCount].alignment, 237 memoryRequirement->agMemory[memoryReqCount].type )); 238 memoryReqCount ++; 239 } 240 241 242 /* requirement for locks */ 243 if (swConfig->param3 == agNULL) 244 { 245 *maxNumLocks = (LL_IOREQ_IBQ_LOCK + AGSA_MAX_INBOUND_Q ); 246 SA_DBG1(("saGetRequirements: param3 == agNULL maxNumLocks %d\n", *maxNumLocks )); 247 } 248 else 249 { 250 agsaQueueConfig_t *queueConfig; 251 queueConfig = (agsaQueueConfig_t *)swConfig->param3; 252 *maxNumLocks = (LL_IOREQ_IBQ_LOCK_PARM + queueConfig->numInboundQueues ); 253 SA_DBG1(("saGetRequirements: maxNumLocks %d\n", *maxNumLocks )); 254 } 255 256 257 /* setup the time tick */ 258 *usecsPerTick = SA_USECS_PER_TICK; 259 260 SA_ASSERT(memoryReqCount < AGSA_NUM_MEM_CHUNKS, "saGetRequirements: Exceed max number of memory place holder"); 261 262 /* set up memory requirement count */ 263 memoryRequirement->count = memoryReqCount; 264 265 swConfig->legacyInt_X = 1; 266 swConfig->max_MSI_InterruptVectors = 32; 267 swConfig->max_MSIX_InterruptVectors = 64;//16; 268 269 SA_DBG1(("saGetRequirements: swConfig->stallUsec %d\n",swConfig->stallUsec )); 270 271#ifdef SA_CONFIG_MDFD_REGISTRY 272 SA_DBG1(("saGetRequirements: swConfig->disableMDF %d\n",swConfig->disableMDF)); 273#endif /*SA_CONFIG_MDFD_REGISTRY*/ 274 /*SA_DBG1(("saGetRequirements: swConfig->enableDIF %d\n",swConfig->enableDIF ));*/ 275 /*SA_DBG1(("saGetRequirements: swConfig->enableEncryption %d\n",swConfig->enableEncryption ));*/ 276#ifdef SA_ENABLE_HDA_FUNCTIONS 277 swConfig->hostDirectAccessSupport = 1; 278 swConfig->hostDirectAccessMode = 0; 279#else 280 swConfig->hostDirectAccessSupport = 0; 281 swConfig->hostDirectAccessMode = 0; 282#endif 283 284} 285 286/******************************************************************************/ 287/*! \brief Initialize the Hardware 288 * 289 * Initialize the Hardware 290 * 291 * \param agRoot Handles for this instance of SAS/SATA hardware 292 * \param memoryAllocated Point to the data structure that holds the different 293 chunks of memory that are required 294 * \param hwConfig Pointer to the hardware configuration 295 * \param swConfig Pointer to the software configuration 296 * \param usecsPerTick micro-seconds per tick for the LL layer 297 * 298 * \return If initialization is successful 299 * - \e AGSA_RC_SUCCESS initialization is successful 300 * - \e AGSA_RC_FAILURE initialization is not successful 301 */ 302/*******************************************************************************/ 303GLOBAL bit32 saInitialize( 304 agsaRoot_t *agRoot, 305 agsaMemoryRequirement_t *memoryAllocated, 306 agsaHwConfig_t *hwConfig, 307 agsaSwConfig_t *swConfig, 308 bit32 usecsPerTick 309 ) 310{ 311 agsaLLRoot_t *saRoot; 312 agsaDeviceDesc_t *pDeviceDesc; 313 agsaIORequestDesc_t *pRequestDesc; 314 agsaTimerDesc_t *pTimerDesc; 315 agsaPort_t *pPort; 316 agsaPortMap_t *pPortMap; 317 agsaDeviceMap_t *pDeviceMap; 318 agsaIOMap_t *pIOMap; 319 bit32 maxNumIODevices; 320 bit32 i, j; 321 static mpiMemReq_t mpiMemoryAllocated; 322 bit32 Tried_NO_HDA = agFALSE; 323 bit32 Double_Reset_HDA = agFALSE; 324 bit32 ret = AGSA_RC_SUCCESS; 325#ifdef FAST_IO_TEST 326 void *fr; /* saFastRequest_t */ 327 bit32 size; 328 bit32 alignment; 329#endif 330 331 /* sanity check */ 332 SA_ASSERT((agNULL != agRoot), ""); 333 SA_ASSERT((agNULL != memoryAllocated), ""); 334 SA_ASSERT((agNULL != hwConfig), ""); 335 SA_ASSERT((agNULL != swConfig), ""); 336 SA_ASSERT((LLROOT_MEM_INDEX < memoryAllocated->count), ""); 337 SA_ASSERT((DEVICELINK_MEM_INDEX < memoryAllocated->count), ""); 338 SA_ASSERT((IOREQLINK_MEM_INDEX < memoryAllocated->count), ""); 339 SA_ASSERT((TIMERLINK_MEM_INDEX < memoryAllocated->count), ""); 340 341 si_memset(&mpiMemoryAllocated, 0, sizeof(mpiMemReq_t)); 342 343 si_macro_check(agRoot); 344 345 SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n", WAIT_INCREMENT )); 346 SA_DBG1(("saInitialize: usecsPerTick %d\n", usecsPerTick )); 347 if(! smIS_SPC(agRoot)) 348 { 349 if(! smIS_SPCV(agRoot)) 350 { 351 SA_DBG1(("saInitialize: ossaHwRegReadConfig32 ID reads as %08X\n", ossaHwRegReadConfig32(agRoot,0 ) )); 352 SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCV, VEN_DEV_SPCVE)); 353 SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCVP, VEN_DEV_SPCVEP)); 354 SA_DBG1(("saInitialize: expect %08X or %08X\n", VEN_DEV_ADAPVEP, VEN_DEV_ADAPVP)); 355 return AGSA_RC_FAILURE; 356 } 357 } 358 359 if( smIS_SPC(agRoot) && smIS_SPCV(agRoot)) 360 { 361 SA_DBG1(("saInitialize: Macro error !smIS_SPC %d smIS_SPCv %d smIS_SFC %d\n",smIS_SPC(agRoot),smIS_SPCV(agRoot), smIS_SFC(agRoot) )); 362 return AGSA_RC_FAILURE; 363 } 364 365 /* Check the memory allocated */ 366 for ( i = 0; i < memoryAllocated->count; i ++ ) 367 { 368 /* If memory allocation failed */ 369 if (memoryAllocated->agMemory[i].singleElementLength && 370 memoryAllocated->agMemory[i].numElements) 371 { 372 if ( (0 != memoryAllocated->agMemory[i].numElements) 373 && (0 == memoryAllocated->agMemory[i].totalLength) ) 374 { 375 /* return failure */ 376 SA_DBG1(("saInitialize:AGSA_RC_FAILURE Memory[%d] singleElementLength = 0x%x numElements = 0x%x NOT allocated\n", 377 i, 378 memoryAllocated->agMemory[i].singleElementLength, 379 memoryAllocated->agMemory[i].numElements)); 380 ret = AGSA_RC_FAILURE; 381 return ret; 382 } 383 else 384 { 385 SA_DBG1(("saInitialize: Memory[%d] singleElementLength = 0x%x numElements = 0x%x allocated %p\n", 386 i, 387 memoryAllocated->agMemory[i].singleElementLength, 388 memoryAllocated->agMemory[i].numElements, 389 memoryAllocated->agMemory[i].virtPtr)); 390 } 391 } 392 } 393 394 /* Get the saRoot memory address */ 395 saRoot = (agsaLLRoot_t *) (memoryAllocated->agMemory[LLROOT_MEM_INDEX].virtPtr); 396 SA_ASSERT((agNULL != saRoot), "saRoot"); 397 if(agNULL == saRoot) 398 { 399 SA_DBG1(("saInitialize:AGSA_RC_FAILURE saRoot\n")); 400 return AGSA_RC_FAILURE; 401 } 402 403 agRoot->sdkData = (void *) saRoot; 404 405 SA_DBG1(("saInitialize: saRoot %p\n",saRoot)); 406 407 if ( (memoryAllocated != &saRoot->memoryAllocated) || 408 (hwConfig != &saRoot->hwConfig) || 409 (swConfig != &saRoot->swConfig) ) 410 { 411 agsaMemoryRequirement_t *memA = &saRoot->memoryAllocated; 412 agsaHwConfig_t *hwC = &saRoot->hwConfig; 413 agsaSwConfig_t *swC = &saRoot->swConfig; 414 415 /* Copy data here */ 416 417 *memA = *memoryAllocated; 418 *hwC = *hwConfig; 419 *swC = *swConfig; 420 } 421 422 423#if defined(SALLSDK_DEBUG) 424 if(gLLDebugLevelSet == 0) 425 { 426 gLLDebugLevelSet = 1; 427 gLLDebugLevel = swConfig->sallDebugLevel & 0xF; 428 SA_DBG1(("saInitialize: gLLDebugLevel %x\n",gLLDebugLevel)); 429 } 430#endif /* SALLSDK_DEBUG */ 431 432#ifdef SA_ENABLE_TRACE_FUNCTIONS 433 434 saRoot->TraceBufferLength = memoryAllocated->agMemory[LL_FUNCTION_TRACE].totalLength; 435 saRoot->TraceBuffer = memoryAllocated->agMemory[LL_FUNCTION_TRACE].virtPtr; 436 437 siEnableTracing ( agRoot ); 438/* 439*/ 440 441#endif /* SA_ENABLE_TRACE_FUNCTIONS */ 442 443#ifdef FAST_IO_TEST 444 { 445 agsaMem_t *agMemory = memoryAllocated->agMemory; 446 447 /* memory requirement for Super IO CACHE memory */ 448 size = sizeof(saRoot->freeFastReq) / sizeof(saRoot->freeFastReq[0]); 449 450 SA_ASSERT(size == agMemory[LL_FAST_IO].numElements, ""); 451 SA_ASSERT(agMemory[LL_FAST_IO].virtPtr, ""); 452 SA_ASSERT((agMemory[LL_FAST_IO].singleElementLength == 453 sizeof(saFastRequest_t)) && 454 (agMemory[LL_FAST_IO].numElements == LL_FAST_IO_SIZE) && 455 (agMemory[LL_FAST_IO].totalLength == agMemory[LL_FAST_IO].numElements * 456 agMemory[LL_FAST_IO].singleElementLength), ""); 457 458 for (i = 0, alignment = agMemory[LL_FAST_IO].alignment, 459 fr = agMemory[LL_FAST_IO].virtPtr; 460 i < size; i++, 461 fr = (void*)((bitptr)fr + (bitptr)(((bit32)sizeof(saFastRequest_t) + 462 alignment - 1) & ~(alignment - 1)))) 463 { 464 saRoot->freeFastReq[i] = fr; 465 } 466 saRoot->freeFastIdx = size; 467 } 468#endif /* FAST_IO_TEST*/ 469 470 smTraceFuncEnter(hpDBG_VERY_LOUD, "m1"); 471 472 SA_DBG1(("saInitialize: swConfig->PortRecoveryResetTimer %x\n",swConfig->PortRecoveryResetTimer )); 473 474 SA_DBG1(("saInitialize: hwDEVICE_ID_VENDID 0x%08x\n", ossaHwRegReadConfig32(agRoot,0))); 475 SA_DBG1(("saInitialize: CFGSTAT CFGCMD 0x%08x\n", ossaHwRegReadConfig32(agRoot,4))); 476 SA_DBG1(("saInitialize: CLSCODE REVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,8))); 477 SA_DBG1(("saInitialize: BIST DT HDRTYPE LATTIM CLSIZE 0x%08x\n", ossaHwRegReadConfig32(agRoot,12))); 478 SA_DBG1(("saInitialize: hwSVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,44))); 479 480 481#ifdef SA_ENABLE_PCI_TRIGGER 482 483 SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER a 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger)); 484 485 if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_INIT_TEST ) 486 { 487 SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger)); 488 saRoot->swConfig.PCI_trigger &= ~PCI_TRIGGER_INIT_TEST; 489 siPCITriger(agRoot); 490 } 491#endif /* SA_ENABLE_PCI_TRIGGER */ 492 493 494 saRoot->ChipId = (ossaHwRegReadConfig32(agRoot,0) & 0xFFFF0000); 495 496 SA_DBG1(("saInitialize: saRoot->ChipId 0x%08x\n", saRoot->ChipId)); 497 siUpdateBarOffsetTable(agRoot,saRoot->ChipId); 498 499 if(saRoot->ChipId == VEN_DEV_SPC) 500 { 501 if(! smIS_SPC(agRoot)) 502 { 503 SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" )); 504 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m1"); 505 return AGSA_RC_FAILURE; 506 } 507 508 SA_DBG1(("saInitialize: SPC \n" )); 509 } 510 else if(saRoot->ChipId == VEN_DEV_HIL ) 511 { 512 SA_DBG1(("saInitialize: SPC HIL\n" )); 513 if(! smIS_SPC(agRoot)) 514 { 515 SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" )); 516 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m1"); 517 return AGSA_RC_FAILURE; 518 } 519 } 520 else if(saRoot->ChipId == VEN_DEV_SPCV) 521 { 522 SA_DBG1(("saInitialize: SPC V\n" )); 523 if(! smIS_SPCV(agRoot)) 524 { 525 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 526 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m1"); 527 return AGSA_RC_FAILURE; 528 } 529 } 530 else if(saRoot->ChipId == VEN_DEV_SPCVE) 531 { 532 SA_DBG1(("saInitialize: SPC VE\n" )); 533 if(! smIS_SPCV(agRoot)) 534 { 535 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 536 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m1"); 537 return AGSA_RC_FAILURE; 538 } 539 } 540 else if(saRoot->ChipId == VEN_DEV_SPCVP) 541 { 542 SA_DBG1(("saInitialize: SPC VP\n" )); 543 if(! smIS_SPCV(agRoot)) 544 { 545 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 546 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m1"); 547 return AGSA_RC_FAILURE; 548 } 549 } 550 else if(saRoot->ChipId == VEN_DEV_SPCVEP) 551 { 552 SA_DBG1(("saInitialize: SPC VEP\n" )); 553 if(! smIS_SPCV(agRoot)) 554 { 555 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 556 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m1"); 557 return AGSA_RC_FAILURE; 558 } 559 } 560 else if(saRoot->ChipId == VEN_DEV_ADAPVP) 561 { 562 SA_DBG1(("saInitialize: Adaptec 8088\n" )); 563 } 564 else if(saRoot->ChipId == VEN_DEV_ADAPVEP) 565 { 566 SA_DBG1(("saInitialize: Adaptec 8089\n" )); 567 } 568 else if(saRoot->ChipId == VEN_DEV_SPC12V) 569 { 570 SA_DBG1(("saInitialize: SPC 12V\n" )); 571 if(! smIS_SPCV(agRoot)) 572 { 573 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 574 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m1"); 575 return AGSA_RC_FAILURE; 576 } 577 } 578 else if(saRoot->ChipId == VEN_DEV_SPC12VE) 579 { 580 SA_DBG1(("saInitialize: SPC 12VE\n" )); 581 if(! smIS_SPCV(agRoot)) 582 { 583 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 584 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m1"); 585 return AGSA_RC_FAILURE; 586 } 587 } 588 else if(saRoot->ChipId == VEN_DEV_SPC12VP) 589 { 590 SA_DBG1(("saInitialize: SPC 12VP\n" )); 591 if(! smIS_SPCV(agRoot)) 592 { 593 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 594 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m1"); 595 return AGSA_RC_FAILURE; 596 } 597 } 598 else if(saRoot->ChipId == VEN_DEV_SPC12VEP) 599 { 600 SA_DBG1(("saInitialize: SPC 12VEP\n" )); 601 if(! smIS_SPCV(agRoot)) 602 { 603 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 604 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m1"); 605 return AGSA_RC_FAILURE; 606 } 607 } 608 else if(saRoot->ChipId == VEN_DEV_SPC12ADP) 609 { 610 SA_DBG1(("saInitialize: SPC 12ADP\n" )); 611 if(! smIS_SPCV(agRoot)) 612 { 613 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 614 smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "m1"); 615 return AGSA_RC_FAILURE; 616 } 617 } 618 else if(saRoot->ChipId == VEN_DEV_SPC12ADPE) 619 { 620 SA_DBG1(("saInitialize: SPC 12ADPE\n" )); 621 if(! smIS_SPCV(agRoot)) 622 { 623 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 624 smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "m1"); 625 return AGSA_RC_FAILURE; 626 } 627 } 628 else if(saRoot->ChipId == VEN_DEV_SPC12ADPP) 629 { 630 SA_DBG1(("saInitialize: SPC 12ADPP\n" )); 631 if(! smIS_SPCV(agRoot)) 632 { 633 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 634 smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "m1"); 635 return AGSA_RC_FAILURE; 636 } 637 } 638 else if(saRoot->ChipId == VEN_DEV_SPC12ADPEP) 639 { 640 SA_DBG1(("saInitialize: SPC 12ADPEP\n" )); 641 if(! smIS_SPCV(agRoot)) 642 { 643 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 644 smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "m1"); 645 return AGSA_RC_FAILURE; 646 } 647 } 648 else if(saRoot->ChipId == VEN_DEV_SPC12SATA) 649 { 650 SA_DBG1(("saInitialize: SPC12SATA\n" )); 651 if(! smIS_SPCV(agRoot)) 652 { 653 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 654 smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "m1"); 655 return AGSA_RC_FAILURE; 656 } 657 } 658 else if(saRoot->ChipId == VEN_DEV_9015) 659 { 660 SA_DBG1(("saInitialize: SPC 12V FPGA\n" )); 661 if(! smIS_SPCV(agRoot)) 662 { 663 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 664 smTraceFuncExit(hpDBG_VERY_LOUD, 'p', "m1"); 665 return AGSA_RC_FAILURE; 666 } 667 } 668 else if(saRoot->ChipId == VEN_DEV_9060) 669 { 670 SA_DBG1(("saInitialize: SPC 12V FPGA B\n" )); 671 if(! smIS_SPCV(agRoot)) 672 { 673 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" )); 674 smTraceFuncExit(hpDBG_VERY_LOUD, 'q', "m1"); 675 return AGSA_RC_FAILURE; 676 } 677 } 678 else if(saRoot->ChipId == VEN_DEV_SFC) 679 { 680 SA_DBG1(("saInitialize: SFC \n" )); 681 } 682 else 683 { 684 SA_DBG1(("saInitialize saRoot->ChipId %8X expect %8X or %8X\n", saRoot->ChipId,VEN_DEV_SPC, VEN_DEV_SPCV)); 685 SA_ASSERT(0, "ChipId"); 686 smTraceFuncExit(hpDBG_VERY_LOUD, 'r', "m1"); 687 return AGSA_RC_FAILURE; 688 } 689 690 if( smIS_SPC(agRoot)) 691 { 692 SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgSpcREV_A(agRoot),smIsCfgSpcREV_B(agRoot),smIsCfgSpcREV_C(agRoot))); 693 } 694 else 695 { 696 SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgVREV_A(agRoot),smIsCfgVREV_B(agRoot),smIsCfgVREV_C(agRoot))); 697 } 698 699 if( smIS_SPC(agRoot)) 700 { 701 SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,128), 702 ((ossaHwRegReadConfig32(agRoot,128) & 0x000F0000) >> 16), 703 ((ossaHwRegReadConfig32(agRoot,128) & 0x0FF00000) >> 20) )); 704 } 705 else 706 { 707 SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,208), 708 ((ossaHwRegReadConfig32(agRoot,208) & 0x000F0000) >> 16), 709 ((ossaHwRegReadConfig32(agRoot,208) & 0x0FF00000) >> 20) )); 710 } 711 712 SA_DBG1(("saInitialize: V_SoftResetRegister %08X\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ))); 713 714/* 715 SA_DBG1(("saInitialize:TOP_BOOT_STRAP STRAP_BIT %X\n", ossaHwRegReadExt(agRoot, PCIBAR1, 0) )); 716 717 SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_DEVICE_ID), SPC_TOP_DEVICE_ID)); 718 SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", siHalRegReadExt( agRoot, GEN_SPC_REG_TOP_DEVICE_ID,SPC_REG_TOP_DEVICE_ID ) , SPC_TOP_DEVICE_ID)); 719 720 SA_DBG1(("SPC_REG_TOP_BOOT_STRAP %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_BOOT_STRAP), SPC_TOP_BOOT_STRAP)); 721 722 SA_DBG1(("swConfig->numSASDevHandles =%d\n", swConfig->numDevHandles)); 723*/ 724 smTrace(hpDBG_VERY_LOUD,"29",swConfig->numDevHandles); 725 /* TP:29 swConfig->numDevHandles */ 726 727 /* Setup Device link */ 728 /* Save the information of allocated device Link memory */ 729 saRoot->deviceLinkMem = memoryAllocated->agMemory[DEVICELINK_MEM_INDEX]; 730 if(agNULL == saRoot->deviceLinkMem.virtPtr) 731 { 732 SA_ASSERT(0, "deviceLinkMem"); 733 smTraceFuncExit(hpDBG_VERY_LOUD, 'q', "m1"); 734 return AGSA_RC_FAILURE; 735 } 736 737 si_memset(saRoot->deviceLinkMem.virtPtr, 0, saRoot->deviceLinkMem.totalLength); 738 SA_DBG2(("saInitialize: [%d] saRoot->deviceLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 739 DEVICELINK_MEM_INDEX, 740 saRoot->deviceLinkMem.virtPtr, 741 saRoot->deviceLinkMem.phyAddrLower, 742 saRoot->deviceLinkMem.numElements, 743 saRoot->deviceLinkMem.totalLength, 744 saRoot->deviceLinkMem.type)); 745 746 maxNumIODevices = swConfig->numDevHandles; 747 SA_DBG2(("saInitialize: maxNumIODevices=%d, swConfig->numDevHandles=%d \n", 748 maxNumIODevices, 749 swConfig->numDevHandles)); 750 751#ifdef SA_ENABLE_PCI_TRIGGER 752 SA_DBG1(("saInitialize: swConfig->PCI_trigger= 0x%x\n", swConfig->PCI_trigger)); 753#endif /* SA_ENABLE_PCI_TRIGGER */ 754 755 /* Setup free IO Devices link list */ 756 saLlistInitialize(&(saRoot->freeDevicesList)); 757 for ( i = 0; i < (bit32) maxNumIODevices; i ++ ) 758 { 759 /* get the pointer to the device descriptor */ 760 pDeviceDesc = (agsaDeviceDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->deviceLinkMem), i); 761 /* Initialize device descriptor */ 762 saLlinkInitialize(&(pDeviceDesc->linkNode)); 763 764 pDeviceDesc->initiatorDevHandle.osData = agNULL; 765 pDeviceDesc->initiatorDevHandle.sdkData = agNULL; 766 pDeviceDesc->targetDevHandle.osData = agNULL; 767 pDeviceDesc->targetDevHandle.sdkData = agNULL; 768 pDeviceDesc->deviceType = SAS_SATA_UNKNOWN_DEVICE; 769 pDeviceDesc->pPort = agNULL; 770 pDeviceDesc->DeviceMapIndex = 0; 771 772 saLlistInitialize(&(pDeviceDesc->pendingIORequests)); 773 774 /* Add the device descriptor to the free IO device link list */ 775 saLlistAdd(&(saRoot->freeDevicesList), &(pDeviceDesc->linkNode)); 776 } 777 778 /* Setup IO Request link */ 779 /* Save the information of allocated IO Request Link memory */ 780 saRoot->IORequestMem = memoryAllocated->agMemory[IOREQLINK_MEM_INDEX]; 781 si_memset(saRoot->IORequestMem.virtPtr, 0, saRoot->IORequestMem.totalLength); 782 783 SA_DBG2(("saInitialize: [%d] saRoot->IORequestMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 784 IOREQLINK_MEM_INDEX, 785 saRoot->IORequestMem.virtPtr, 786 saRoot->IORequestMem.phyAddrLower, 787 saRoot->IORequestMem.numElements, 788 saRoot->IORequestMem.totalLength, 789 saRoot->IORequestMem.type)); 790 791 /* Setup free IO Request link list */ 792 saLlistIOInitialize(&(saRoot->freeIORequests)); 793 saLlistIOInitialize(&(saRoot->freeReservedRequests)); 794 for ( i = 0; i < swConfig->maxActiveIOs; i ++ ) 795 { 796 /* get the pointer to the request descriptor */ 797 pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), i); 798 /* Initialize request descriptor */ 799 saLlinkInitialize(&(pRequestDesc->linkNode)); 800 801 pRequestDesc->valid = agFALSE; 802 pRequestDesc->requestType = AGSA_REQ_TYPE_UNKNOWN; 803 pRequestDesc->pIORequestContext = agNULL; 804 pRequestDesc->HTag = i; 805 pRequestDesc->pDevice = agNULL; 806 pRequestDesc->pPort = agNULL; 807 808 /* Add the request descriptor to the free Reserved Request link list */ 809 /* SMP request must get service so reserve one request when first SMP completes */ 810 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 811 { 812 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequestDesc->linkNode)); 813 } 814 else 815 { 816 /* Add the request descriptor to the free IO Request link list */ 817 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequestDesc->linkNode)); 818 } 819 820 } 821 822 /* Setup timer link */ 823 /* Save the information of allocated timer Link memory */ 824 saRoot->timerLinkMem = memoryAllocated->agMemory[TIMERLINK_MEM_INDEX]; 825 si_memset(saRoot->timerLinkMem.virtPtr, 0, saRoot->timerLinkMem.totalLength); 826 SA_DBG2(("saInitialize: [%d] saRoot->timerLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 827 TIMERLINK_MEM_INDEX, 828 saRoot->timerLinkMem.virtPtr, 829 saRoot->timerLinkMem.phyAddrLower, 830 saRoot->timerLinkMem.numElements, 831 saRoot->timerLinkMem.totalLength, 832 saRoot->timerLinkMem.type )); 833 834 /* Setup free timer link list */ 835 saLlistInitialize(&(saRoot->freeTimers)); 836 for ( i = 0; i < NUM_TIMERS; i ++ ) 837 { 838 /* get the pointer to the timer descriptor */ 839 pTimerDesc = (agsaTimerDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->timerLinkMem), i); 840 /* Initialize timer descriptor */ 841 saLlinkInitialize(&(pTimerDesc->linkNode)); 842 843 pTimerDesc->valid = agFALSE; 844 pTimerDesc->timeoutTick = 0; 845 pTimerDesc->pfnTimeout = agNULL; 846 pTimerDesc->Event = 0; 847 pTimerDesc->pParm = agNULL; 848 849 /* Add the timer descriptor to the free timer link list */ 850 saLlistAdd(&(saRoot->freeTimers), &(pTimerDesc->linkNode)); 851 } 852 /* Setup valid timer link list */ 853 saLlistInitialize(&(saRoot->validTimers)); 854 855 /* Setup Phys */ 856 /* Setup PhyCount */ 857 saRoot->phyCount = (bit8) hwConfig->phyCount; 858 /* Init Phy data structure */ 859 for ( i = 0; i < saRoot->phyCount; i ++ ) 860 { 861 saRoot->phys[i].pPort = agNULL; 862 saRoot->phys[i].phyId = (bit8) i; 863 864 /* setup phy status is PHY_STOPPED */ 865 PHY_STATUS_SET(&(saRoot->phys[i]), PHY_STOPPED); 866 } 867 868 /* Setup Ports */ 869 /* Setup PortCount */ 870 saRoot->portCount = saRoot->phyCount; 871 /* Setup free port link list */ 872 saLlistInitialize(&(saRoot->freePorts)); 873 for ( i = 0; i < saRoot->portCount; i ++ ) 874 { 875 /* get the pointer to the port */ 876 pPort = &(saRoot->ports[i]); 877 /* Initialize port */ 878 saLlinkInitialize(&(pPort->linkNode)); 879 880 pPort->portContext.osData = agNULL; 881 pPort->portContext.sdkData = pPort; 882 pPort->portId = 0; 883 pPort->portIdx = (bit8) i; 884 pPort->status = PORT_NORMAL; 885 886 for ( j = 0; j < saRoot->phyCount; j ++ ) 887 { 888 pPort->phyMap[j] = agFALSE; 889 } 890 891 saLlistInitialize(&(pPort->listSASATADevices)); 892 893 /* Add the port to the free port link list */ 894 saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode)); 895 } 896 /* Setup valid port link list */ 897 saLlistInitialize(&(saRoot->validPorts)); 898 899 /* Init sysIntsActive - default is interrupt enable */ 900 saRoot->sysIntsActive = agFALSE; 901 902 /* setup timer tick granunarity */ 903 saRoot->usecsPerTick = usecsPerTick; 904 905 /* setup smallest timer increment for stall */ 906 saRoot->minStallusecs = swConfig->stallUsec; 907 908 SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n" ,WAIT_INCREMENT )); 909 if (0 == WAIT_INCREMENT) 910 { 911 saRoot->minStallusecs = WAIT_INCREMENT_DEFAULT; 912 } 913 914 /* initialize LL timer tick */ 915 saRoot->timeTick = 0; 916 917 /* initialize device (de)registration callback fns */ 918 saRoot->DeviceRegistrationCB = agNULL; 919 saRoot->DeviceDeregistrationCB = agNULL; 920 921 /* Initialize the PortMap for port context */ 922 for ( i = 0; i < saRoot->portCount; i ++ ) 923 { 924 pPortMap = &(saRoot->PortMap[i]); 925 926 pPortMap->PortContext = agNULL; 927 pPortMap->PortID = PORT_MARK_OFF; 928 pPortMap->PortStatus = PORT_NORMAL; 929 saRoot->autoDeregDeviceflag[i] = 0; 930 } 931 932 /* Initialize the DeviceMap for device handle */ 933 for ( i = 0; i < MAX_IO_DEVICE_ENTRIES; i ++ ) 934 { 935 pDeviceMap = &(saRoot->DeviceMap[i]); 936 937 pDeviceMap->DeviceHandle = agNULL; 938 pDeviceMap->DeviceIdFromFW = i; 939 } 940 941 /* Initialize the IOMap for IOrequest */ 942 for ( i = 0; i < MAX_ACTIVE_IO_REQUESTS; i ++ ) 943 { 944 pIOMap = &(saRoot->IOMap[i]); 945 946 pIOMap->IORequest = agNULL; 947 pIOMap->Tag = MARK_OFF; 948 } 949 950 /* setup mpi configuration */ 951 if (!swConfig->param3) 952 { 953 /* default configuration */ 954 siConfiguration(agRoot, &saRoot->mpiConfig, hwConfig, swConfig); 955 } 956 else 957 { 958 /* get from TD layer and save it */ 959 agsaQueueConfig_t *dCFG = &saRoot->QueueConfig; 960 agsaQueueConfig_t *sCFG = (agsaQueueConfig_t *)swConfig->param3; 961 962 if (dCFG != sCFG) 963 { 964 *dCFG = *sCFG; 965 966 if ((hwConfig->hwInterruptCoalescingTimer) || (hwConfig->hwInterruptCoalescingControl)) 967 { 968 for ( i = 0; i < sCFG->numOutboundQueues; i ++ ) 969 { 970 /* disable FW assisted coalescing */ 971 sCFG->outboundQueues[i].interruptDelay = 0; 972 sCFG->outboundQueues[i].interruptCount = 0; 973 } 974 975 if(smIS_SPC(agRoot)) 976 { 977 if (hwConfig->hwInterruptCoalescingTimer == 0) 978 { 979 hwConfig->hwInterruptCoalescingTimer = 1; 980 SA_DBG1(("saInitialize:InterruptCoalescingTimer should not be zero. Force to 1\n")); 981 } 982 } 983 } 984 ret = siConfiguration(agRoot, &saRoot->mpiConfig, hwConfig, swConfig); 985 if (AGSA_RC_FAILURE == ret) 986 { 987 SA_DBG1(("saInitialize failure queue number=%d\n", saRoot->QueueConfig.numInboundQueues)); 988 agRoot->sdkData = agNULL; 989 smTraceFuncExit(hpDBG_VERY_LOUD, 'r', "m1"); 990 return ret; 991 } 992 } 993 } 994 995 996 saRoot->swConfig.param3 = &saRoot->QueueConfig; 997 998 mpiMemoryAllocated.count = memoryAllocated->count - MPI_MEM_INDEX; 999 for ( i = 0; i < mpiMemoryAllocated.count; i ++ ) 1000 { 1001 mpiMemoryAllocated.region[i].virtPtr = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].virtPtr; 1002 mpiMemoryAllocated.region[i].appHandle = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].osHandle; 1003 mpiMemoryAllocated.region[i].physAddrUpper = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrUpper; 1004 mpiMemoryAllocated.region[i].physAddrLower = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrLower; 1005 mpiMemoryAllocated.region[i].totalLength = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].totalLength; 1006 mpiMemoryAllocated.region[i].numElements = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].numElements; 1007 mpiMemoryAllocated.region[i].elementSize = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].singleElementLength; 1008 mpiMemoryAllocated.region[i].alignment = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].alignment; 1009 mpiMemoryAllocated.region[i].type = memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].type; 1010 SA_DBG2(("saInitialize: memoryAllocated->agMemory[%d] VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 1011 (MPI_IBQ_OBQ_INDEX + i), 1012 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].virtPtr, 1013 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].phyAddrLower, 1014 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].numElements, 1015 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].totalLength, 1016 memoryAllocated->agMemory[MPI_IBQ_OBQ_INDEX + i].type)); 1017 1018 /* set to zeros */ 1019 SA_DBG1(("saInitialize: Zero memory region %d virt %p allocated %d\n", 1020 i,mpiMemoryAllocated.region[i].virtPtr, mpiMemoryAllocated.region[i].totalLength)); 1021 si_memset(mpiMemoryAllocated.region[i].virtPtr , 0,mpiMemoryAllocated.region[i].totalLength); 1022 1023 } 1024 1025 if ((!swConfig->max_MSI_InterruptVectors) && 1026 (!swConfig->max_MSIX_InterruptVectors) && 1027 (!swConfig->legacyInt_X)) 1028 { 1029 /* polling mode */ 1030 SA_DBG1(("saInitialize: configured as polling mode\n")); 1031 } 1032 else 1033 { 1034 1035 SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %d\n",swConfig->max_MSI_InterruptVectors)); 1036 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %d\n",swConfig->max_MSIX_InterruptVectors)); 1037 1038 if ((swConfig->legacyInt_X > 1) || (swConfig->max_MSI_InterruptVectors > 32) || 1039 (swConfig->max_MSIX_InterruptVectors > 64)) 1040 { 1041 /* error */ 1042 agRoot->sdkData = agNULL; 1043 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors A\n")); 1044 smTraceFuncExit(hpDBG_VERY_LOUD, 's', "m1"); 1045 return AGSA_RC_FAILURE; 1046 } 1047 if ((swConfig->legacyInt_X) && (swConfig->max_MSI_InterruptVectors)) 1048 { 1049 /* error */ 1050 agRoot->sdkData = agNULL; 1051 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors B\n")); 1052 smTraceFuncExit(hpDBG_VERY_LOUD, 't', "m1"); 1053 return AGSA_RC_FAILURE; 1054 } 1055 else if ((swConfig->legacyInt_X) && (swConfig->max_MSIX_InterruptVectors)) 1056 { 1057 /* error */ 1058 agRoot->sdkData = agNULL; 1059 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors C\n")); 1060 smTraceFuncExit(hpDBG_VERY_LOUD, 'u', "m1"); 1061 return AGSA_RC_FAILURE; 1062 } 1063 else if ((swConfig->max_MSI_InterruptVectors) && (swConfig->max_MSIX_InterruptVectors)) 1064 { 1065 /* error */ 1066 agRoot->sdkData = agNULL; 1067 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors D\n")); 1068 smTraceFuncExit(hpDBG_VERY_LOUD, 'v', "m1"); 1069 return AGSA_RC_FAILURE; 1070 } 1071 } 1072 1073 /* This section sets common interrupt for Legacy(IRQ) and MSI and MSIX types */ 1074 if(smIS_SPC(agRoot)) 1075 { 1076 SA_DBG1(("saInitialize: SPC interrupts\n" )); 1077 1078 if (swConfig->legacyInt_X) 1079 { 1080 saRoot->OurInterrupt = siOurLegacyInterrupt; /* Called in ISR*/ 1081 saRoot->DisableInterrupts = siDisableLegacyInterrupts; /* Called in ISR*/ 1082 saRoot->ReEnableInterrupts = siReenableLegacyInterrupts;/* Called in Delayed Int handler*/ 1083 } 1084 else if (swConfig->max_MSIX_InterruptVectors) 1085 { 1086 saRoot->OurInterrupt = siOurMSIXInterrupt; 1087 saRoot->DisableInterrupts = siDisableMSIXInterrupts; 1088 saRoot->ReEnableInterrupts = siReenableMSIXInterrupts; 1089 } 1090 else if (swConfig->max_MSI_InterruptVectors) 1091 { 1092 saRoot->OurInterrupt = siOurMSIInterrupt; 1093 saRoot->DisableInterrupts = siDisableMSIInterrupts; 1094 saRoot->ReEnableInterrupts = siReenableMSIInterrupts; 1095 } 1096 else 1097 { 1098 /* polling mode */ 1099 saRoot->OurInterrupt = siOurLegacyInterrupt; /* Called in ISR*/ 1100 saRoot->DisableInterrupts = siDisableLegacyInterrupts; /* Called in ISR*/ 1101 saRoot->ReEnableInterrupts = siReenableLegacyInterrupts;/* Called in Delayed Int handler*/ 1102 } 1103 } 1104 else 1105 { 1106 SA_DBG1(("saInitialize: SPC V interrupts\n" )); 1107 if (swConfig->legacyInt_X ) 1108 { 1109 SA_DBG1(("saInitialize: SPC V legacyInt_X\n" )); 1110 saRoot->OurInterrupt = siOurLegacy_V_Interrupt; /* Called in ISR*/ 1111 saRoot->DisableInterrupts = siDisableLegacy_V_Interrupts; /* Called in ISR*/ 1112 saRoot->ReEnableInterrupts = siReenableLegacy_V_Interrupts;/* Called in Delayed Int handler*/ 1113 } 1114 else if (swConfig->max_MSIX_InterruptVectors) 1115 { 1116 SA_DBG1(("saInitialize: SPC V max_MSIX_InterruptVectors %X\n", swConfig->max_MSIX_InterruptVectors)); 1117 saRoot->OurInterrupt = siOurMSIX_V_Interrupt; /* */ 1118 saRoot->DisableInterrupts = siDisableMSIX_V_Interrupts; 1119 saRoot->ReEnableInterrupts = siReenableMSIX_V_Interrupts; 1120 } 1121 else if (swConfig->max_MSI_InterruptVectors) 1122 { 1123 SA_DBG1(("saInitialize: SPC V max_MSI_InterruptVectors\n" )); 1124 saRoot->OurInterrupt = siOurMSIX_V_Interrupt; /* */ 1125 saRoot->DisableInterrupts = siDisableMSIX_V_Interrupts; 1126 saRoot->ReEnableInterrupts = siReenableMSIX_V_Interrupts; 1127 } 1128 else 1129 { 1130 /* polling mode */ 1131 SA_DBG1(("saInitialize: SPC V polling mode\n" )); 1132 saRoot->OurInterrupt = siOurLegacy_V_Interrupt; /* Called in ISR*/ 1133 saRoot->DisableInterrupts = siDisableLegacy_V_Interrupts; /* Called in ISR*/ 1134 saRoot->ReEnableInterrupts = siReenableLegacy_V_Interrupts;/* Called in Delayed Int handler*/ 1135 } 1136 SA_DBG1(("saInitialize: SPC V\n" )); 1137 } 1138 1139 saRoot->Use64bit = (saRoot->QueueConfig.numOutboundQueues > 32 ) ? 1 : 0; 1140 if( smIS64bInt(agRoot)) 1141 { 1142 SA_DBG1(("saInitialize: Use 64 bits for interrupts %d %d\n" ,saRoot->Use64bit, saRoot->QueueConfig.numOutboundQueues )); 1143 } 1144 else 1145 { 1146 SA_DBG1(("saInitialize: Use 32 bits for interrupts %d %d\n",saRoot->Use64bit , saRoot->QueueConfig.numOutboundQueues )); 1147 } 1148 1149#ifdef SA_LL_IBQ_PROTECT 1150 SA_DBG1(("saInitialize: Inbound locking defined since LL_IOREQ_IBQ0_LOCK %d\n",LL_IOREQ_IBQ0_LOCK)); 1151#endif /* SA_LL_IBQ_PROTECT */ 1152 1153 /* Disable interrupt */ 1154 saRoot->DisableInterrupts(agRoot, 0); 1155 SA_DBG1(("saInitialize: DisableInterrupts sysIntsActive %X\n" ,saRoot->sysIntsActive)); 1156 1157#ifdef SA_FW_TEST_BUNCH_STARTS 1158 saRoot->BunchStarts_Enable = FALSE; 1159 saRoot->BunchStarts_Threshold = 5; 1160 saRoot->BunchStarts_Pending = 0; 1161 saRoot->BunchStarts_TimeoutTicks = 10; // N x 100 ms 1162#endif /* SA_FW_TEST_BUNCH_STARTS */ 1163 1164 /* clear the interrupt vector bitmap */ 1165 for ( i = 0; i < MAX_NUM_VECTOR; i ++ ) 1166 { 1167 saRoot->interruptVecIndexBitMap[i] = 0; 1168 saRoot->interruptVecIndexBitMap1[i] = 0; 1169 } 1170 1171#if defined(SALLSDK_DEBUG) 1172 smTrace(hpDBG_VERY_LOUD,"2Y",0); 1173 /* TP:2Y SCRATCH_PAD */ 1174 1175 SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0))); 1176 SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 1177 SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2))); 1178 SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); 1179#endif /* SALLSDK_DEBUG */ 1180 1181 if(smIS_SPCV(agRoot)) 1182 { 1183 bit32 ScratchPad1 =0; 1184 bit32 ScratchPad3 =0; 1185 1186 ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register); 1187 ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register); 1188 if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK) 1189 { 1190 if(((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_DIS_ERR ) || 1191 ((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_ENA_ERR ) ) 1192 { 1193 SA_DBG1(("saInitialize:Warning Encryption Issue SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); 1194 } 1195 } 1196 } 1197 1198 if( smIS_SPC(agRoot)) 1199 { 1200#ifdef SA_ENABLE_HDA_FUNCTIONS 1201 TryWithHDA_ON: 1202 Double_Reset_HDA = TRUE; 1203 1204 if (swConfig->hostDirectAccessSupport) 1205 { 1206 if (AGSA_RC_FAILURE == siHDAMode(agRoot, swConfig->hostDirectAccessMode, (agsaFwImg_t *)swConfig->param4)) 1207 { 1208 SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode\n")); 1209 agRoot->sdkData = agNULL; 1210 smTraceFuncExit(hpDBG_VERY_LOUD, 'w', "m1"); 1211 return AGSA_RC_FAILURE; 1212 } 1213 else 1214 { 1215 SA_DBG1(("saInitialize:1 Going to HDA mode HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1216 if(Double_Reset_HDA == agFALSE) 1217 { 1218 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1219 SA_DBG1(("saInitialize: Double_Reset_HDA HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1220 Double_Reset_HDA = TRUE; 1221 goto TryWithHDA_ON; 1222 } 1223 } 1224 } 1225 else 1226 { 1227 /* check FW is running */ 1228 if (BOOTTLOADERHDA_IDLE == (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS)) 1229 { 1230 /* HDA mode */ 1231 SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n")); 1232 if(Tried_NO_HDA != agTRUE ) 1233 { 1234 1235 Tried_NO_HDA = TRUE; 1236 swConfig->hostDirectAccessSupport = 1; 1237 swConfig->hostDirectAccessMode = 1; 1238 siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1239 SA_DBG1(("saInitialize: 2 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1240 goto TryWithHDA_ON; 1241 } 1242 else 1243 { 1244 SA_DBG1(("saInitialize: could not start HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1245 smTraceFuncExit(hpDBG_VERY_LOUD, 'x', "m1"); 1246 1247 return AGSA_RC_FAILURE; 1248 } 1249 smTraceFuncExit(hpDBG_VERY_LOUD, 'y', "m1"); 1250 return AGSA_RC_FAILURE; 1251 } 1252 } 1253#else /* SA_ENABLE_HDA_FUNCTIONS */ 1254 /* check FW is running */ 1255 if (BOOTTLOADERHDA_IDLE == (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS) ) 1256 { 1257 /* HDA mode */ 1258 SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n")); 1259 smTraceFuncExit(hpDBG_VERY_LOUD, 'z', "m1"); 1260 return AGSA_RC_FAILURE; 1261 } 1262#endif /* SA_ENABLE_HDA_FUNCTIONS */ 1263 } 1264 else 1265 { 1266 SA_DBG1(("saInitialize: SPCv swConfig->hostDirectAccessMode %d swConfig->hostDirectAccessSupport %d\n",swConfig->hostDirectAccessMode,swConfig->hostDirectAccessSupport)); 1267 if (swConfig->hostDirectAccessSupport) 1268 { 1269 bit32 hda_status; 1270 bit32 soft_reset_status = AGSA_RC_SUCCESS; 1271 1272 SA_DBG1(("saInitialize: SPCv load HDA\n")); 1273 1274 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 1275 1276 SA_DBG1(("saInitialize: hda_status 0x%x\n",hda_status)); 1277 1278 siScratchDump(agRoot); 1279 1280 if( swConfig->hostDirectAccessMode == 0) 1281 { 1282 soft_reset_status = siSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1283 if(soft_reset_status != AGSA_RC_SUCCESS) 1284 { 1285 agRoot->sdkData = agNULL; 1286 SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status\n")); 1287 1288 smTraceFuncExit(hpDBG_VERY_LOUD, 'A', "m1"); 1289 return AGSA_RC_FAILURE; 1290 } 1291 } 1292 1293 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) 1294 { 1295 SA_DBG1(("saInitialize: hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status)); 1296 soft_reset_status = siSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1297 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 1298 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) 1299 { 1300 SA_DBG1(("saInitialize: 2 reset hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status)); 1301 } 1302 } 1303 if(soft_reset_status != AGSA_RC_SUCCESS) 1304 { 1305 agRoot->sdkData = agNULL; 1306 SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status A\n")); 1307 smTraceFuncExit(hpDBG_VERY_LOUD, 'B', "m1"); 1308 return AGSA_RC_FAILURE; 1309 } 1310 1311#ifdef SA_ENABLE_HDA_FUNCTIONS 1312 if (AGSA_RC_FAILURE == siHDAMode_V(agRoot, swConfig->hostDirectAccessMode, (agsaFwImg_t *)swConfig->param4)) 1313 { 1314 SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode_V\n")); 1315 1316 siChipResetV(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1317 agRoot->sdkData = agNULL; 1318 smTraceFuncExit(hpDBG_VERY_LOUD, 'C', "m1"); 1319 return AGSA_RC_FAILURE; 1320 } 1321#endif /* SA_ENABLE_HDA_FUNCTIONS */ 1322 1323 } 1324 else 1325 { 1326 SA_DBG1(("saInitialize: SPCv normal\n")); 1327 } 1328 1329 } 1330 1331 /* copy the table to the LL layer */ 1332 si_memcpy(&saRoot->mpiConfig.phyAnalogConfig, &hwConfig->phyAnalogConfig, sizeof(agsaPhyAnalogSetupTable_t)); 1333 1334#ifdef SALL_API_TEST 1335 /* Initialize the LL IO counter */ 1336 si_memset(&saRoot->LLCounters, 0, sizeof(agsaIOCountInfo_t)); 1337#endif 1338 1339 si_memset(&saRoot->IoErrorCount, 0, sizeof(agsaIOErrorEventStats_t)); 1340 si_memset(&saRoot->IoEventCount, 0, sizeof(agsaIOErrorEventStats_t)); 1341 if(smIS_SPC(agRoot)) 1342 { 1343 if( smIS_spc8081(agRoot)) 1344 { 1345 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_GSM_SM_BASE)) 1346 { 1347 SA_DBG1(("saInitialize: siBar4Shift FAILED ******************************************\n")); 1348 } 1349 } 1350 siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 1351 } 1352 if(smIS_SPCV(agRoot)) 1353 { 1354 SA_DBG1(("saInitialize: saRoot->ChipId == VEN_DEV_SPCV\n")); 1355 siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); 1356 } 1357 1358 /* MPI Initialization */ 1359 ret = mpiInitialize(agRoot, &mpiMemoryAllocated, &saRoot->mpiConfig); 1360 SA_DBG1(("saInitialize: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", saRoot->ControllerInfo.maxPendingIO,saRoot->swConfig.maxActiveIOs )); 1361 1362#ifdef SA_ENABLE_HDA_FUNCTIONS 1363 if( ret == AGSA_RC_FAILURE && Tried_NO_HDA == agFALSE && smIS_SPC(agRoot)) 1364 { /* FW not flashed */ 1365 Tried_NO_HDA=agTRUE; 1366 swConfig->hostDirectAccessSupport = 1; 1367 swConfig->hostDirectAccessMode = 1; 1368 siSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 1369 SA_DBG1(("saInitialize: 3 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET))); 1370 goto TryWithHDA_ON; 1371 } 1372 1373#endif /* SA_ENABLE_HDA_FUNCTIONS */ 1374 1375 if( ret == AGSA_RC_FAILURE) 1376 { 1377 SA_DBG1(("saInitialize: AGSA_RC_FAILURE mpiInitialize\n")); 1378 SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_0_Register))); 1379 SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_1_Register))); 1380 SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_2_Register))); 1381 SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_3_Register))); 1382 1383 if(saRoot->swConfig.fatalErrorInterruptEnable) 1384 { 1385 ossaDisableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); 1386 } 1387 1388 agRoot->sdkData = agNULL; 1389 smTraceFuncExit(hpDBG_VERY_LOUD, 'D', "m1"); 1390 return ret; 1391 } 1392 1393 /* setup hardware interrupt coalescing control and timer registers */ 1394 if(smIS_SPCV(agRoot)) 1395 { 1396 SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingTimer\n" )); 1397 SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingControl\n" )); 1398 } 1399 else 1400 { 1401 ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICTIMER,hwConfig->hwInterruptCoalescingTimer ); 1402 ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ICCONTROL, hwConfig->hwInterruptCoalescingControl); 1403 } 1404 1405 1406 SA_DBG1(("saInitialize: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable)); 1407 1408 SA_DBG1(("saInitialize: saRoot->swConfig.fatalErrorInterruptVector %X\n",saRoot->swConfig.fatalErrorInterruptVector)); 1409 SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %X\n",swConfig->max_MSI_InterruptVectors)); 1410 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors)); 1411 SA_DBG1(("saInitialize: swConfig->legacyInt_X %X\n",swConfig->legacyInt_X)); 1412 SA_DBG1(("saInitialize: swConfig->hostDirectAccessSupport %X\n",swConfig->hostDirectAccessSupport)); 1413 SA_DBG1(("saInitialize: swConfig->hostDirectAccessMode %X\n",swConfig->hostDirectAccessMode)); 1414 1415#ifdef SA_CONFIG_MDFD_REGISTRY 1416 SA_DBG1(("saInitialize: swConfig->disableMDF %X\n",swConfig->disableMDF)); 1417#endif /*SA_CONFIG_MDFD_REGISTRY*/ 1418 /*SA_DBG1(("saInitialize: swConfig->enableDIF %X\n",swConfig->enableDIF));*/ 1419 /*SA_DBG1(("saInitialize: swConfig->enableEncryption %X\n",swConfig->enableEncryption));*/ 1420 1421 1422 /* log message if failure */ 1423 if (AGSA_RC_FAILURE == ret) 1424 { 1425 SA_DBG1(("saInitialize:AGSA_RC_FAILURE mpiInitialize\n")); 1426 /* Assign chip status */ 1427 saRoot->chipStatus = CHIP_FATAL_ERROR; 1428 } 1429 else 1430 { 1431 /* Assign chip status */ 1432 saRoot->chipStatus = CHIP_NORMAL; 1433#ifdef SA_FW_TIMER_READS_STATUS 1434 siTimerAdd(agRoot,SA_FW_TIMER_READS_STATUS_INTERVAL, siReadControllerStatus,0,agNULL ); 1435#endif /* SA_FW_TIMER_READS_STATUS */ 1436 } 1437 1438 1439 if( ret == AGSA_RC_SUCCESS || ret == AGSA_RC_VERSION_UNTESTED) 1440 { 1441 if(gPollForMissingInt) 1442 { 1443 mpiOCQueue_t *circularQ; 1444 SA_DBG1(("saInitialize: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); 1445 1446 circularQ = &saRoot->outboundQueue[0]; 1447 OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 1448 SA_DBG1(("saInitialize: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx)); 1449 } 1450 } 1451 1452 /* If fatal error interrupt enable we need checking it during the interrupt */ 1453 SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptEnable %d\n",saRoot->swConfig.fatalErrorInterruptEnable)); 1454 SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptVector %d\n",saRoot->swConfig.fatalErrorInterruptVector)); 1455 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors)); 1456 1457 if(saRoot->swConfig.fatalErrorInterruptEnable) 1458 { 1459 1460 SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n", 1461 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1462 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1463 SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n", 1464 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1465 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1466 1467 ossaReenableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); 1468 1469 SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n", 1470 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1471 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1472 SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n", 1473 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1474 ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1475 } 1476 1477 1478 SA_DBG1(("saInitialize: siDumpActiveIORequests\n")); 1479 siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs); 1480 1481 smTraceFuncExit(hpDBG_VERY_LOUD, 'E', "m1"); 1482 /* return */ 1483 return ret; 1484} 1485 1486 1487 1488#ifdef SA_FW_TIMER_READS_STATUS 1489 1490bit32 siReadControllerStatus( 1491 agsaRoot_t *agRoot, 1492 bit32 Event, 1493 void * pParm 1494 ) 1495{ 1496 bit32 to_ret =0; 1497 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1498 mpiReadGSTable(agRoot, &saRoot->mpiGSTable); 1499 1500 if(smIS_SPCV_2_IOP(agRoot)) 1501 { 1502 if(saRoot->Iop1Tcnt_last == saRoot->mpiGSTable.Iop1Tcnt ) 1503 SA_DBG2(("siReadControllerStatus: Iop1 %d STUCK\n", saRoot->mpiGSTable.Iop1Tcnt)); 1504 } 1505 1506 if( saRoot->MsguTcnt_last == saRoot->mpiGSTable.MsguTcnt || saRoot->IopTcnt_last == saRoot->mpiGSTable.IopTcnt ) 1507 { 1508 SA_DBG1(("siReadControllerStatus: Msgu %d Iop %d\n",saRoot->mpiGSTable.MsguTcnt, saRoot->mpiGSTable.IopTcnt)); 1509 saFatalInterruptHandler(agRoot, saRoot->swConfig.fatalErrorInterruptVector ); 1510 } 1511 SA_DBG2(("siReadControllerStatus: Msgu %d Iop %d\n",saRoot->mpiGSTable.MsguTcnt, saRoot->mpiGSTable.IopTcnt)); 1512 1513 saRoot->MsguTcnt_last = saRoot->mpiGSTable.MsguTcnt; 1514 saRoot->IopTcnt_last = saRoot->mpiGSTable.IopTcnt; 1515 saRoot->Iop1Tcnt_last = saRoot->mpiGSTable.Iop1Tcnt; 1516 1517 1518 if(gPollForMissingInt) 1519 { 1520 mpiOCQueue_t *circularQ; 1521 SA_DBG4(("siReadControllerStatus: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); 1522 1523 circularQ = &saRoot->outboundQueue[0]; 1524 OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 1525 if(circularQ->producerIdx != circularQ->consumerIdx) 1526 { 1527 SA_DBG1(("siReadControllerStatus: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive)); 1528 SA_DBG1(("siReadControllerStatus: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx)); 1529 1530 SA_DBG1(("siReadControllerStatus:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1531 SA_DBG1(("siReadControllerStatus:MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 1532 ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, 0xFFFFFFFF ); 1533 1534 } 1535 } 1536 1537 siTimerAdd(agRoot,SA_FW_TIMER_READS_STATUS_INTERVAL, siReadControllerStatus,Event,pParm ); 1538 1539 return(to_ret); 1540} 1541 1542#endif /* SA_FW_TIMER_READS_STATUS */ 1543 1544/******************************************************************************/ 1545/*! \brief Routine to do SPC configuration with default or specified values 1546 * 1547 * Set up configuration table in LL Layer 1548 * 1549 * \param agRoot handles for this instance of SAS/SATA hardware 1550 * \param mpiConfig MPI Configuration 1551 * \param swConfig Pointer to the software configuration 1552 * 1553 * \return -void- 1554 */ 1555/*******************************************************************************/ 1556GLOBAL bit32 siConfiguration( 1557 agsaRoot_t *agRoot, 1558 mpiConfig_t *mpiConfig, 1559 agsaHwConfig_t *hwConfig, 1560 agsaSwConfig_t *swConfig 1561 ) 1562{ 1563 agsaQueueConfig_t *queueConfig; 1564 bit32 intOption, enable64 = 0; 1565 bit8 i; 1566 1567 1568 /* sanity check */ 1569 SA_ASSERT( (agNULL != agRoot), ""); 1570 1571 smTraceFuncEnter(hpDBG_VERY_LOUD,"m2"); 1572 1573 si_memset(mpiConfig, 0, sizeof(mpiConfig_t)); 1574 SA_DBG1(("siConfiguration: si_memset mpiConfig\n")); 1575 1576#if defined(SALLSDK_DEBUG) 1577 sidump_swConfig(swConfig); 1578#endif 1579 mpiConfig->mainConfig.custset = swConfig->FWConfig; 1580 1581 SA_DBG1(("siConfiguration:custset %8X %8X\n",mpiConfig->mainConfig.custset,swConfig->FWConfig)); 1582 1583 if (swConfig->param3 == agNULL) 1584 { 1585 SA_DBG1(("siConfiguration: swConfig->param3 == agNULL\n")); 1586 /* initialize the mpiConfig */ 1587 /* We configure the Host main part of configuration table */ 1588 mpiConfig->mainConfig.iQNPPD_HPPD_GEvent = 0; 1589 mpiConfig->mainConfig.outboundHWEventPID0_3 = 0; 1590 mpiConfig->mainConfig.outboundHWEventPID4_7 = 0; 1591 mpiConfig->mainConfig.outboundNCQEventPID0_3 = 0; 1592 mpiConfig->mainConfig.outboundNCQEventPID4_7 = 0; 1593 mpiConfig->mainConfig.outboundTargetITNexusEventPID0_3 = 0; 1594 mpiConfig->mainConfig.outboundTargetITNexusEventPID4_7 = 0; 1595 mpiConfig->mainConfig.outboundTargetSSPEventPID0_3 = 0; 1596 mpiConfig->mainConfig.outboundTargetSSPEventPID4_7 = 0; 1597 1598 mpiConfig->mainConfig.ioAbortDelay = 0; 1599 1600 mpiConfig->mainConfig.upperEventLogAddress = 0; 1601 mpiConfig->mainConfig.lowerEventLogAddress = 0; 1602 mpiConfig->mainConfig.eventLogSize = MPI_LOGSIZE; 1603 mpiConfig->mainConfig.eventLogOption = 0; 1604 mpiConfig->mainConfig.upperIOPeventLogAddress = 0; 1605 mpiConfig->mainConfig.lowerIOPeventLogAddress = 0; 1606 mpiConfig->mainConfig.IOPeventLogSize = MPI_LOGSIZE; 1607 mpiConfig->mainConfig.IOPeventLogOption = 0; 1608 mpiConfig->mainConfig.FatalErrorInterrupt = 0; 1609 1610 /* save the default value */ 1611 mpiConfig->numInboundQueues = AGSA_MAX_INBOUND_Q; 1612 mpiConfig->numOutboundQueues = AGSA_MAX_OUTBOUND_Q; 1613 mpiConfig->maxNumInboundQueues = AGSA_MAX_INBOUND_Q; 1614 mpiConfig->maxNumOutboundQueues = AGSA_MAX_OUTBOUND_Q; 1615 1616 /* configure inbound queues */ 1617 for ( i = 0; i < AGSA_MAX_INBOUND_Q; i ++ ) 1618 { 1619 mpiConfig->inboundQueues[i].numElements = INBOUND_DEPTH_SIZE; 1620 mpiConfig->inboundQueues[i].elementSize = IOMB_SIZE64; 1621 mpiConfig->inboundQueues[i].priority = MPI_QUEUE_NORMAL; 1622 } 1623 1624 /* configure outbound queues */ 1625 for ( i = 0; i < AGSA_MAX_OUTBOUND_Q; i ++ ) 1626 { 1627 mpiConfig->outboundQueues[i].numElements = OUTBOUND_DEPTH_SIZE; 1628 mpiConfig->outboundQueues[i].elementSize = IOMB_SIZE64; 1629 mpiConfig->outboundQueues[i].interruptVector = 0; 1630 mpiConfig->outboundQueues[i].interruptDelay = 0; 1631 mpiConfig->outboundQueues[i].interruptThreshold = 0; 1632 /* always enable OQ interrupt */ 1633 mpiConfig->outboundQueues[i].interruptEnable = 1; 1634 } 1635 } 1636 else 1637 { /* Parm3 is not null */ 1638 queueConfig = (agsaQueueConfig_t *)swConfig->param3; 1639 1640#if defined(SALLSDK_DEBUG) 1641 sidump_Q_config( queueConfig ); 1642#endif 1643 1644 SA_DBG1(("siConfiguration: swConfig->param3 == %p\n",queueConfig)); 1645 1646 if ((queueConfig->numInboundQueues > AGSA_MAX_INBOUND_Q) || 1647 (queueConfig->numOutboundQueues > AGSA_MAX_OUTBOUND_Q)) 1648 { 1649 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m2"); 1650 SA_DBG1(("siConfiguration:AGSA_RC_FAILURE MAX_Q\n")); 1651 1652 return AGSA_RC_FAILURE; 1653 } 1654 1655 if ((queueConfig->numInboundQueues == 0 || 1656 queueConfig->numOutboundQueues == 0 )) 1657 { 1658 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m2"); 1659 SA_DBG1(("siConfiguration:AGSA_RC_FAILURE NO_Q\n")); 1660 return AGSA_RC_FAILURE; 1661 } 1662 mpiConfig->mainConfig.eventLogSize = swConfig->sizefEventLog1 * KBYTES; 1663 mpiConfig->mainConfig.eventLogOption = swConfig->eventLog1Option; 1664 mpiConfig->mainConfig.IOPeventLogSize = swConfig->sizefEventLog2 * KBYTES; 1665 mpiConfig->mainConfig.IOPeventLogOption = swConfig->eventLog2Option; 1666 1667 if ((queueConfig->numInboundQueues > IQ_NUM_32) || (queueConfig->numOutboundQueues > OQ_NUM_32)) 1668 { 1669 enable64 = 1; 1670 } 1671 1672 if (agNULL == hwConfig) 1673 { 1674 intOption = 0; 1675 } 1676 else 1677 { 1678 1679#if defined(SALLSDK_DEBUG) 1680 sidump_hwConfig(hwConfig); 1681#endif 1682 1683 1684 if(smIS_SPCV(agRoot)) 1685 { 1686 intOption = 0; 1687 } 1688 else 1689 { 1690 intOption = hwConfig->intReassertionOption & INT_OPTION; 1691 } 1692 1693 } 1694 1695 /* Enable SGPIO */ 1696 swConfig->sgpioSupportEnable = 1; 1697 1698 /* set bit for normal priority or high priority path */ 1699 /* set fatal error interrupt enable and vector */ 1700 /* set Interrupt Reassertion enable and 64 IQ/OQ enable */ 1701 mpiConfig->mainConfig.FatalErrorInterrupt = 1702 (swConfig->fatalErrorInterruptEnable) /* bit 0*/ | 1703 (hwConfig == agNULL ? 0: (hwConfig->hwOption & HW_CFG_PICI_EFFECTIVE_ADDRESS ? (0x1 << SHIFT1): 0))| 1704 (swConfig->sgpioSupportEnable ? (0x1 << SHIFT2): 0) | 1705 /* compile option SA_ENABLE_POISION_TLP */(SA_PTNFE_POISION_TLP << SHIFT3) | 1706#ifdef SA_CONFIG_MDFD_REGISTRY 1707 (swConfig->disableMDF ? (0x1 << SHIFT4): 0) | 1708#else 1709 /* compile option SA_DISABLE_MDFD */ (SA_MDFD_MULTI_DATA_FETCH << SHIFT4) | 1710#endif /*SA_CONFIG_MDFD_REGISTRY*/ 1711 /* compile option SA_DISABLE_OB_COAL */(SA_OUTBOUND_COALESCE << SHIFT5) | 1712 /* compile option SA_ENABLE_ARBTE */(SA_ARBTE << SHIFT6) | 1713 ((swConfig->fatalErrorInterruptVector & FATAL_ERROR_INT_BITS) << SHIFT8) | 1714 (enable64 << SHIFT16) | 1715 (intOption << SHIFT17); 1716 1717 1718 SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable)); 1719 SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptVector %X\n",swConfig->fatalErrorInterruptVector)); 1720 1721 1722 1723 /* initialize the mpiConfig */ 1724 /* We configure the Host main part of configuration table */ 1725 mpiConfig->mainConfig.outboundTargetITNexusEventPID0_3 = 0; 1726 mpiConfig->mainConfig.outboundTargetITNexusEventPID4_7 = 0; 1727 mpiConfig->mainConfig.outboundTargetSSPEventPID0_3 = 0; 1728 mpiConfig->mainConfig.outboundTargetSSPEventPID4_7 = 0; 1729 mpiConfig->mainConfig.ioAbortDelay = 0; 1730 mpiConfig->mainConfig.PortRecoveryTimerPortResetTimer = swConfig->PortRecoveryResetTimer; 1731 1732 /* get parameter from queueConfig */ 1733 mpiConfig->mainConfig.iQNPPD_HPPD_GEvent = queueConfig->iqNormalPriorityProcessingDepth | 1734 (queueConfig->iqHighPriorityProcessingDepth << SHIFT8) | 1735 (queueConfig->generalEventQueue << SHIFT16) | 1736 (queueConfig->tgtDeviceRemovedEventQueue << SHIFT24); 1737 1738 mpiConfig->mainConfig.outboundHWEventPID0_3 = queueConfig->sasHwEventQueue[0] | 1739 (queueConfig->sasHwEventQueue[1] << SHIFT8) | 1740 (queueConfig->sasHwEventQueue[2] << SHIFT16) | 1741 (queueConfig->sasHwEventQueue[3] << SHIFT24); 1742 mpiConfig->mainConfig.outboundHWEventPID4_7 = queueConfig->sasHwEventQueue[4] | 1743 (queueConfig->sasHwEventQueue[5] << SHIFT8) | 1744 (queueConfig->sasHwEventQueue[6] << SHIFT16) | 1745 (queueConfig->sasHwEventQueue[7] << SHIFT24); 1746 mpiConfig->mainConfig.outboundNCQEventPID0_3 = queueConfig->sataNCQErrorEventQueue[0] | 1747 (queueConfig->sataNCQErrorEventQueue[1] << SHIFT8) | 1748 (queueConfig->sataNCQErrorEventQueue[2] << SHIFT16) | 1749 (queueConfig->sataNCQErrorEventQueue[3] << SHIFT24); 1750 mpiConfig->mainConfig.outboundNCQEventPID4_7 = queueConfig->sataNCQErrorEventQueue[4] | 1751 (queueConfig->sataNCQErrorEventQueue[5] << SHIFT8) | 1752 (queueConfig->sataNCQErrorEventQueue[6] << SHIFT16) | 1753 (queueConfig->sataNCQErrorEventQueue[7] << SHIFT24); 1754 /* save it */ 1755 mpiConfig->numInboundQueues = queueConfig->numInboundQueues; 1756 mpiConfig->numOutboundQueues = queueConfig->numOutboundQueues; 1757 mpiConfig->queueOption = queueConfig->queueOption; 1758 1759 SA_DBG2(("siConfiguration: numInboundQueues=%d numOutboundQueues=%d\n", 1760 queueConfig->numInboundQueues, 1761 queueConfig->numOutboundQueues)); 1762 1763 /* configure inbound queues */ 1764 /* We configure the size of queue based on swConfig */ 1765 for( i = 0; i < queueConfig->numInboundQueues; i ++ ) 1766 { 1767 mpiConfig->inboundQueues[i].numElements = (bit16)queueConfig->inboundQueues[i].elementCount; 1768 mpiConfig->inboundQueues[i].elementSize = (bit16)queueConfig->inboundQueues[i].elementSize;; 1769 mpiConfig->inboundQueues[i].priority = queueConfig->inboundQueues[i].priority; 1770 1771 SA_DBG2(("siConfiguration: IBQ%d:elementCount=%d elementSize=%d priority=%d Total Size 0x%X\n", 1772 i, 1773 queueConfig->inboundQueues[i].elementCount, 1774 queueConfig->inboundQueues[i].elementSize, 1775 queueConfig->inboundQueues[i].priority, 1776 queueConfig->inboundQueues[i].elementCount * queueConfig->inboundQueues[i].elementSize )); 1777 } 1778 1779 /* configura outbound queues */ 1780 /* We configure the size of queue based on swConfig */ 1781 for( i = 0; i < queueConfig->numOutboundQueues; i ++ ) 1782 { 1783 mpiConfig->outboundQueues[i].numElements = (bit16)queueConfig->outboundQueues[i].elementCount; 1784 mpiConfig->outboundQueues[i].elementSize = (bit16)queueConfig->outboundQueues[i].elementSize; 1785 mpiConfig->outboundQueues[i].interruptVector = (bit8)queueConfig->outboundQueues[i].interruptVectorIndex; 1786 mpiConfig->outboundQueues[i].interruptDelay = (bit16)queueConfig->outboundQueues[i].interruptDelay; 1787 mpiConfig->outboundQueues[i].interruptThreshold = (bit8)queueConfig->outboundQueues[i].interruptCount; 1788 mpiConfig->outboundQueues[i].interruptEnable = (bit32)queueConfig->outboundQueues[i].interruptEnable; 1789 1790 SA_DBG2(("siConfiguration: OBQ%d:elementCount=%d elementSize=%d interruptCount=%d interruptEnable=%d\n", 1791 i, 1792 queueConfig->outboundQueues[i].elementCount, 1793 queueConfig->outboundQueues[i].elementSize, 1794 queueConfig->outboundQueues[i].interruptCount, 1795 queueConfig->outboundQueues[i].interruptEnable)); 1796 } 1797 } 1798 1799 SA_DBG1(("siConfiguration:mpiConfig->mainConfig.FatalErrorInterrupt 0x%X\n",mpiConfig->mainConfig.FatalErrorInterrupt)); 1800 SA_DBG1(("siConfiguration:swConfig->fatalErrorInterruptVector 0x%X\n",swConfig->fatalErrorInterruptVector)); 1801 SA_DBG1(("siConfiguration:enable64 0x%X\n",enable64)); 1802 SA_DBG1(("siConfiguration:PortRecoveryResetTimer 0x%X\n",swConfig->PortRecoveryResetTimer)); 1803 1804 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m2"); 1805 1806 /* return */ 1807 return AGSA_RC_SUCCESS; 1808} 1809 1810#ifdef FW_EVT_LOG_TST 1811void saLogDump(agsaRoot_t *agRoot, 1812 U32 *eventLogSize, 1813 U32 **eventLogAddress_) 1814{ 1815 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1816 //mpiConfig_t *mpiConfig = &saRoot->mpiConfig; 1817 mpiHostLLConfigDescriptor_t *mpiConfig = &saRoot->mainConfigTable; 1818 1819 *eventLogAddress_ = (U32*)eventLogAddress; 1820 *eventLogSize = (U32)mpiConfig->eventLogSize; 1821} 1822#endif 1823 1824/*******************************************************************************/ 1825/** \fn mpiInitialize(agsaRoot *agRoot, mpiMemReq_t* memoryAllocated, mpiConfig_t* config) 1826 * \brief Initializes the MPI Message Unit 1827 * \param agRoot Pointer to a data structure containing LL layer context handles 1828 * \param memoryAllocated Data structure that holds the different chunks of memory that are allocated 1829 * \param config MPI configuration 1830 * 1831 * This function is called to initialize SPC_HOST_MPI internal data structures and the SPC hardware. 1832 * This function is competed synch->ronously (there is no callback) 1833 * 1834 * Return: 1835 * AGSA_RC_SUCCESS if initialization succeeded. 1836 * AGSA_RC_FAILURE if initialization failed. 1837 */ 1838/*******************************************************************************/ 1839GLOBAL bit32 mpiInitialize(agsaRoot_t *agRoot, 1840 mpiMemReq_t* memoryAllocated, 1841 mpiConfig_t* config) 1842{ 1843 static spc_configMainDescriptor_t mainCfg; /* main part of MPI configuration */ 1844 static spc_inboundQueueDescriptor_t inQueueCfg; /* Inbound queue HW configuration structure */ 1845 static spc_outboundQueueDescriptor_t outQueueCfg; /* Outbound queue HW configuration structure */ 1846 bit16 qIdx, i, indexoffset; /* Queue index */ 1847 bit16 mIdx = 0; /* Memory region index */ 1848 bit32 MSGUCfgTblDWIdx, GSTLenMPIS; 1849 bit32 MSGUCfgTblBase, ret = AGSA_RC_SUCCESS; 1850 bit32 value, togglevalue; 1851 bit32 saveOffset; 1852 bit32 inboundoffset, outboundoffset; 1853 bit8 pcibar; 1854 bit16 maxinbound = AGSA_MAX_INBOUND_Q; 1855 bit16 maxoutbound = AGSA_MAX_OUTBOUND_Q; 1856 bit32 OB_CIPCIBar; 1857 bit32 IB_PIPCIBar; 1858 bit32 max_wait_time; 1859 bit32 max_wait_count; 1860 bit32 memOffset; 1861 agsaLLRoot_t *saRoot; 1862 mpiICQueue_t *circularIQ = agNULL; 1863 mpiOCQueue_t *circularOQ; 1864 1865 bit32 mpiUnInitFailed = 0; 1866 bit32 mpiStartToggleFailed = 0; 1867 1868 1869#if defined(SALLSDK_DEBUG) 1870 bit8 phycount = AGSA_MAX_VALID_PHYS; 1871#endif /* SALLSDK_DEBUG */ 1872 1873 SA_DBG1(("mpiInitialize: Entering\n")); 1874 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 1875 SA_ASSERT(NULL != memoryAllocated, "memoryAllocated argument cannot be null"); 1876 SA_ASSERT(NULL != config, "config argument cannot be null"); 1877 SA_ASSERT(0 == (sizeof(spc_inboundQueueDescriptor_t) % 4), "spc_inboundQueueDescriptor_t type size has to be divisible by 4"); 1878 1879 saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1880 1881 si_memset(&mainCfg,0,sizeof(spc_configMainDescriptor_t)); 1882 si_memset(&inQueueCfg,0,sizeof(spc_inboundQueueDescriptor_t)); 1883 si_memset(&outQueueCfg,0,sizeof(spc_outboundQueueDescriptor_t)); 1884 1885 SA_ASSERT((agNULL !=saRoot ), ""); 1886 if(saRoot == agNULL) 1887 { 1888 SA_DBG1(("mpiInitialize: saRoot == agNULL\n")); 1889 return(AGSA_RC_FAILURE); 1890 } 1891 smTraceFuncEnter(hpDBG_VERY_LOUD,"m3"); 1892 1893 /*Shift BAR 4 for SPC HAILEAH*/ 1894 if(smIS_SPC(agRoot)) 1895 { 1896 if( smIS_HIL(agRoot)) 1897 { 1898 if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_GSM_SM_BASE)) 1899 { 1900 SA_DBG1(("mpiInitialize: siBar4Shift FAILED ******************************************\n")); 1901 return AGSA_RC_FAILURE; 1902 } 1903 } 1904 } 1905 1906 /* Wait for the SPC Configuration Table to be ready */ 1907 ret = mpiWaitForConfigTable(agRoot, &mainCfg); 1908 if (AGSA_RC_FAILURE == ret) 1909 { 1910 /* return error if MPI Configuration Table not ready */ 1911 SA_DBG1(("mpiInitialize: mpiWaitForConfigTable FAILED ******************************************\n")); 1912 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m3"); 1913 return ret; 1914 } 1915 1916 /* read scratch pad0 to get PCI BAR and offset of configuration table */ 1917 MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 1918 /* get PCI BAR */ 1919 MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 1920 /* get pci Bar index */ 1921 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); 1922 1923 SA_DBG1(("mpiInitialize: MSGUCfgTblBase = 0x%x\n", MSGUCfgTblBase)); 1924#if defined(SALLSDK_DEBUG) 1925 /* get Phy count from configuration table */ 1926 phycount = (bit8)((mainCfg.ContrlCapFlag & PHY_COUNT_BITS) >> SHIFT19); 1927 1928 SA_DBG1(("mpiInitialize: Number of PHYs = 0x%x\n", phycount)); 1929 1930 smTrace(hpDBG_VERY_LOUD,"70",phycount); 1931 /* TP:70 phycount */ 1932#endif /* SALLSDK_DEBUG */ 1933 1934 /* get High Priority IQ support flag */ 1935 if (mainCfg.ContrlCapFlag & HP_SUPPORT_BIT) 1936 { 1937 SA_DBG1(("mpiInitialize: High Priority IQ support from SPC\n")); 1938 } 1939 /* get Interrupt Coalescing Support flag */ 1940 if (mainCfg.ContrlCapFlag & INT_COL_BIT) 1941 { 1942 SA_DBG1(("mpiInitialize: Interrupt Coalescing support from SPC\n")); 1943 } 1944 1945 /* get configured the number of inbound/outbound queues */ 1946 if (memoryAllocated->count == TOTAL_MPI_MEM_CHUNKS) 1947 { 1948 config->maxNumInboundQueues = AGSA_MAX_INBOUND_Q; 1949 config->maxNumOutboundQueues = AGSA_MAX_OUTBOUND_Q; 1950 } 1951 else 1952 { 1953 config->maxNumInboundQueues = config->numInboundQueues; 1954 config->maxNumOutboundQueues = config->numOutboundQueues; 1955 maxinbound = config->numInboundQueues; 1956 maxoutbound = config->numOutboundQueues; 1957 } 1958 1959 SA_DBG1(("mpiInitialize: Number of IQ %d\n", maxinbound)); 1960 SA_DBG1(("mpiInitialize: Number of OQ %d\n", maxoutbound)); 1961 1962 /* get inbound queue offset */ 1963 inboundoffset = mainCfg.inboundQueueOffset; 1964 /* get outbound queue offset */ 1965 outboundoffset = mainCfg.outboundQueueOffset; 1966 1967 if(smIS_SPCV(agRoot)) 1968 { 1969 SA_DBG2(("mpiInitialize: Offset of IQ %d\n", (inboundoffset & 0xFF000000) >> 24)); 1970 SA_DBG2(("mpiInitialize: Offset of OQ %d\n", (outboundoffset & 0xFF000000) >> 24)); 1971 inboundoffset &= 0x00FFFFFF; 1972 outboundoffset &= 0x00FFFFFF; 1973 } 1974 /* get offset of the configuration table */ 1975 MSGUCfgTblDWIdx = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 1976 MSGUCfgTblDWIdx = MSGUCfgTblDWIdx & SCRATCH_PAD0_OFFSET_MASK; 1977 1978 saveOffset = MSGUCfgTblDWIdx; 1979 1980 /* Checks if the configuration memory region size is the same as the mpiConfigMain */ 1981 if(memoryAllocated->region[mIdx].totalLength != sizeof(bit8) * config->mainConfig.eventLogSize) 1982 { 1983 SA_DBG1(("ERROR: The memory region [%d] 0x%X != 0x%X does not have the size of the MSGU event log ******************************************\n", 1984 mIdx,memoryAllocated->region[mIdx].totalLength,config->mainConfig.eventLogSize)); 1985 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m3"); 1986 return AGSA_RC_FAILURE; 1987 } 1988 1989 mainCfg.iQNPPD_HPPD_GEvent = config->mainConfig.iQNPPD_HPPD_GEvent; 1990 1991 if(smIS_SPCV(agRoot)) 1992 { 1993 mainCfg.outboundHWEventPID0_3 = 0; 1994 mainCfg.outboundHWEventPID4_7 = 0; 1995 mainCfg.outboundNCQEventPID0_3 = 0; 1996 mainCfg.outboundNCQEventPID4_7 = 0; 1997 mainCfg.outboundTargetITNexusEventPID0_3 = 0; 1998 mainCfg.outboundTargetITNexusEventPID4_7 = 0; 1999 mainCfg.outboundTargetSSPEventPID0_3 = 0; 2000 mainCfg.outboundTargetSSPEventPID4_7 = 0; 2001 mainCfg.ioAbortDelay = 0; /* SPCV reserved */ 2002 mainCfg.custset = 0; 2003 mainCfg.portRecoveryResetTimer = config->mainConfig.PortRecoveryTimerPortResetTimer; 2004 SA_DBG1(("mpiInitialize:custset V %8X\n",mainCfg.custset)); 2005 SA_DBG1(("mpiInitialize:portRecoveryResetTimer V %8X\n",mainCfg.portRecoveryResetTimer)); 2006 2007 mainCfg.interruptReassertionDelay = saRoot->hwConfig.intReassertionOption; 2008 SA_DBG1(("mpiInitialize:interruptReassertionDelay V %8X\n", mainCfg.interruptReassertionDelay)); 2009 2010 2011 } 2012 else 2013 { 2014 mainCfg.outboundHWEventPID0_3 = config->mainConfig.outboundHWEventPID0_3; 2015 mainCfg.outboundHWEventPID4_7 = config->mainConfig.outboundHWEventPID4_7; 2016 mainCfg.outboundNCQEventPID0_3 = config->mainConfig.outboundNCQEventPID0_3; 2017 mainCfg.outboundNCQEventPID4_7 = config->mainConfig.outboundNCQEventPID4_7; 2018 mainCfg.outboundTargetITNexusEventPID0_3 = config->mainConfig.outboundTargetITNexusEventPID0_3; 2019 mainCfg.outboundTargetITNexusEventPID4_7 = config->mainConfig.outboundTargetITNexusEventPID4_7; 2020 mainCfg.outboundTargetSSPEventPID0_3 = config->mainConfig.outboundTargetSSPEventPID0_3; 2021 mainCfg.outboundTargetSSPEventPID4_7 = config->mainConfig.outboundTargetSSPEventPID4_7; 2022 mainCfg.ioAbortDelay = config->mainConfig.ioAbortDelay; 2023 mainCfg.custset = config->mainConfig.custset; 2024 2025 SA_DBG1(("mpiInitialize:custset spc %8X\n",mainCfg.custset)); 2026 2027 } 2028#ifdef FW_EVT_LOG_TST 2029 eventLogAddress = memoryAllocated->region[mIdx].virtPtr; 2030#endif 2031 mainCfg.upperEventLogAddress = memoryAllocated->region[mIdx].physAddrUpper; 2032 mainCfg.lowerEventLogAddress = memoryAllocated->region[mIdx].physAddrLower; 2033 mainCfg.eventLogSize = config->mainConfig.eventLogSize; 2034 mainCfg.eventLogOption = config->mainConfig.eventLogOption; 2035 2036 mIdx++; 2037 2038 /* Checks if the configuration memory region size is the same as the mpiConfigMain */ 2039 if(memoryAllocated->region[mIdx].totalLength != sizeof(bit8) * config->mainConfig.IOPeventLogSize) 2040 { 2041 SA_DBG1(("ERROR: The memory region does not have the size of the IOP event log\n")); 2042 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m3"); 2043 return AGSA_RC_FAILURE; 2044 } 2045 2046 mainCfg.upperIOPeventLogAddress = memoryAllocated->region[mIdx].physAddrUpper; 2047 mainCfg.lowerIOPeventLogAddress = memoryAllocated->region[mIdx].physAddrLower; 2048 mainCfg.IOPeventLogSize = config->mainConfig.IOPeventLogSize; 2049 mainCfg.IOPeventLogOption = config->mainConfig.IOPeventLogOption; 2050 mainCfg.FatalErrorInterrupt = config->mainConfig.FatalErrorInterrupt; 2051 2052 SA_DBG1(("mpiInitialize: iQNPPD_HPPD_GEvent 0x%x\n", mainCfg.iQNPPD_HPPD_GEvent)); 2053 if(smIS_SPCV(agRoot)) 2054 { 2055 } 2056 else 2057 { 2058 SA_DBG3(("mpiInitialize: outboundHWEventPID0_3 0x%x\n", mainCfg.outboundHWEventPID0_3)); 2059 SA_DBG3(("mpiInitialize: outboundHWEventPID4_7 0x%x\n", mainCfg.outboundHWEventPID4_7)); 2060 SA_DBG3(("mpiInitialize: outboundNCQEventPID0_3 0x%x\n", mainCfg.outboundNCQEventPID0_3)); 2061 SA_DBG3(("mpiInitialize: outboundNCQEventPID4_7 0x%x\n", mainCfg.outboundNCQEventPID4_7)); 2062 SA_DBG3(("mpiInitialize: outboundTargetITNexusEventPID0_3 0x%x\n", mainCfg.outboundTargetITNexusEventPID0_3)); 2063 SA_DBG3(("mpiInitialize: outboundTargetITNexusEventPID4_7 0x%x\n", mainCfg.outboundTargetITNexusEventPID4_7)); 2064 SA_DBG3(("mpiInitialize: outboundTargetSSPEventPID0_3 0x%x\n", mainCfg.outboundTargetSSPEventPID0_3)); 2065 SA_DBG3(("mpiInitialize: outboundTargetSSPEventPID4_7 0x%x\n", mainCfg.outboundTargetSSPEventPID4_7)); 2066 } 2067 2068 SA_DBG3(("mpiInitialize: upperEventLogAddress 0x%x\n", mainCfg.upperEventLogAddress)); 2069 SA_DBG3(("mpiInitialize: lowerEventLogAddress 0x%x\n", mainCfg.lowerEventLogAddress)); 2070 SA_DBG3(("mpiInitialize: eventLogSize 0x%x\n", mainCfg.eventLogSize)); 2071 SA_DBG3(("mpiInitialize: eventLogOption 0x%x\n", mainCfg.eventLogOption)); 2072#ifdef FW_EVT_LOG_TST 2073 SA_DBG3(("mpiInitialize: eventLogAddress 0x%p\n", eventLogAddress)); 2074#endif 2075 SA_DBG3(("mpiInitialize: upperIOPLogAddress 0x%x\n", mainCfg.upperIOPeventLogAddress)); 2076 SA_DBG3(("mpiInitialize: lowerIOPLogAddress 0x%x\n", mainCfg.lowerIOPeventLogAddress)); 2077 SA_DBG3(("mpiInitialize: IOPeventLogSize 0x%x\n", mainCfg.IOPeventLogSize)); 2078 SA_DBG3(("mpiInitialize: IOPeventLogOption 0x%x\n", mainCfg.IOPeventLogOption)); 2079 SA_DBG3(("mpiInitialize: FatalErrorInterrupt 0x%x\n", mainCfg.FatalErrorInterrupt)); 2080 SA_DBG3(("mpiInitialize: HDAModeFlags 0x%x\n", mainCfg.HDAModeFlags)); 2081 SA_DBG3(("mpiInitialize: analogSetupTblOffset 0x%08x\n", mainCfg.analogSetupTblOffset)); 2082 2083 saRoot->mainConfigTable.iQNPPD_HPPD_GEvent = mainCfg.iQNPPD_HPPD_GEvent; 2084 2085 if(smIS_SPCV(agRoot)) 2086 { 2087 /* SPCV - reserved fields */ 2088 saRoot->mainConfigTable.outboundHWEventPID0_3 = 0; 2089 saRoot->mainConfigTable.outboundHWEventPID4_7 = 0; 2090 saRoot->mainConfigTable.outboundNCQEventPID0_3 = 0; 2091 saRoot->mainConfigTable.outboundNCQEventPID4_7 = 0; 2092 saRoot->mainConfigTable.outboundTargetITNexusEventPID0_3 = 0; 2093 saRoot->mainConfigTable.outboundTargetITNexusEventPID4_7 = 0; 2094 saRoot->mainConfigTable.outboundTargetSSPEventPID0_3 = 0; 2095 saRoot->mainConfigTable.outboundTargetSSPEventPID4_7 = 0; 2096 saRoot->mainConfigTable.ioAbortDelay = 0; 2097 saRoot->mainConfigTable.custset = 0; 2098 2099 } 2100 else 2101 { 2102 saRoot->mainConfigTable.outboundHWEventPID0_3 = mainCfg.outboundHWEventPID0_3; 2103 saRoot->mainConfigTable.outboundHWEventPID4_7 = mainCfg.outboundHWEventPID4_7; 2104 saRoot->mainConfigTable.outboundNCQEventPID0_3 = mainCfg.outboundNCQEventPID0_3; 2105 saRoot->mainConfigTable.outboundNCQEventPID4_7 = mainCfg.outboundNCQEventPID4_7; 2106 saRoot->mainConfigTable.outboundTargetITNexusEventPID0_3 = mainCfg.outboundTargetITNexusEventPID0_3; 2107 saRoot->mainConfigTable.outboundTargetITNexusEventPID4_7 = mainCfg.outboundTargetITNexusEventPID4_7; 2108 saRoot->mainConfigTable.outboundTargetSSPEventPID0_3 = mainCfg.outboundTargetSSPEventPID0_3; 2109 saRoot->mainConfigTable.outboundTargetSSPEventPID4_7 = mainCfg.outboundTargetSSPEventPID4_7; 2110 saRoot->mainConfigTable.ioAbortDelay = mainCfg.ioAbortDelay; 2111 saRoot->mainConfigTable.custset = mainCfg.custset; 2112 2113 } 2114 2115 saRoot->mainConfigTable.upperEventLogAddress = mainCfg.upperEventLogAddress; 2116 saRoot->mainConfigTable.lowerEventLogAddress = mainCfg.lowerEventLogAddress; 2117 saRoot->mainConfigTable.eventLogSize = mainCfg.eventLogSize; 2118 saRoot->mainConfigTable.eventLogOption = mainCfg.eventLogOption; 2119 saRoot->mainConfigTable.upperIOPeventLogAddress = mainCfg.upperIOPeventLogAddress; 2120 saRoot->mainConfigTable.lowerIOPeventLogAddress = mainCfg.lowerIOPeventLogAddress; 2121 saRoot->mainConfigTable.IOPeventLogSize = mainCfg.IOPeventLogSize; 2122 saRoot->mainConfigTable.IOPeventLogOption = mainCfg.IOPeventLogOption; 2123 saRoot->mainConfigTable.FatalErrorInterrupt = mainCfg.FatalErrorInterrupt; 2124 2125 2126 if(smIS_SPCV(agRoot)) 2127 { 2128 ;/* SPCV - reserved fields */ 2129 } 2130 else 2131 { 2132 saRoot->mainConfigTable.HDAModeFlags = mainCfg.HDAModeFlags; 2133 } 2134 2135 saRoot->mainConfigTable.analogSetupTblOffset = mainCfg.analogSetupTblOffset; 2136 2137 smTrace(hpDBG_VERY_LOUD,"71",mIdx); 2138 /* TP:71 71 mIdx */ 2139 2140 2141 2142 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IQNPPD_HPPD_OFFSET), 2143 mainCfg.iQNPPD_HPPD_GEvent); 2144 2145 SA_DBG3(("mpiInitialize: Offset 0x%08x mainCfg.iQNPPD_HPPD_GEvent 0x%x\n", (bit32)(MSGUCfgTblDWIdx + MAIN_IQNPPD_HPPD_OFFSET), mainCfg.iQNPPD_HPPD_GEvent)); 2146 2147 if(smIS_SPC6V(agRoot)) 2148 { 2149 if(smIsCfgVREV_B(agRoot)) 2150 { 2151 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2152 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); 2153 2154 SA_DBG1(("mpiInitialize:SPCV - MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE\n" )); 2155 } 2156 if(smIsCfgVREV_C(agRoot)) 2157 { 2158 SA_DBG1(("mpiInitialize:SPCV - END_TO_END_CRC On\n" )); 2159 } 2160 SA_DBG3(("mpiInitialize:SPCV - rest reserved field \n" )); 2161 ;/* SPCV - reserved field */ 2162 } 2163 else if(smIS_SPC(agRoot)) 2164 { 2165 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_HW_EVENT_PID03_OFFSET), 2166 mainCfg.outboundHWEventPID0_3); 2167 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_HW_EVENT_PID47_OFFSET), 2168 mainCfg.outboundHWEventPID4_7); 2169 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_NCQ_EVENT_PID03_OFFSET), 2170 mainCfg.outboundNCQEventPID0_3); 2171 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_NCQ_EVENT_PID47_OFFSET), 2172 mainCfg.outboundNCQEventPID4_7); 2173 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_TITNX_EVENT_PID03_OFFSET), 2174 mainCfg.outboundTargetITNexusEventPID0_3); 2175 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_TITNX_EVENT_PID47_OFFSET), 2176 mainCfg.outboundTargetITNexusEventPID4_7); 2177 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_SSP_EVENT_PID03_OFFSET), 2178 mainCfg.outboundTargetSSPEventPID0_3); 2179 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_OB_SSP_EVENT_PID47_OFFSET), 2180 mainCfg.outboundTargetSSPEventPID4_7); 2181 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_CUSTOMER_SETTING), 2182 mainCfg.custset); 2183 }else 2184 { 2185 if(smIsCfgVREV_A(agRoot)) 2186 { 2187 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2188 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); /* */ 2189 SA_DBG1(("mpiInitialize:SPCV12G - offset MAIN_IO_ABORT_DELAY 0x%x value MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x%x\n",MAIN_IO_ABORT_DELAY ,MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE)); 2190 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC OFF for rev A %d\n",smIsCfgVREV_A(agRoot) )); 2191 } 2192 else if(smIsCfgVREV_B(agRoot)) 2193 { 2194 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC ON rev B %d ****************************\n",smIsCfgVREV_B(agRoot) )); 2195 /*ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2196 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); 2197 */ 2198 } 2199 else if(smIsCfgVREV_C(agRoot)) 2200 { 2201 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC on rev C %d\n",smIsCfgVREV_C(agRoot) )); 2202 } 2203 else 2204 { 2205 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IO_ABORT_DELAY), 2206 MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE); 2207 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC Off unknown rev 0x%x\n", ossaHwRegReadConfig32((agRoot), 8 ))); 2208 } 2209 } 2210 2211 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI), mainCfg.upperEventLogAddress); 2212 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO), mainCfg.lowerEventLogAddress); 2213 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE), mainCfg.eventLogSize); 2214 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION), mainCfg.eventLogOption); 2215 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI), mainCfg.upperIOPeventLogAddress); 2216 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO), mainCfg.lowerIOPeventLogAddress); 2217 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE), mainCfg.IOPeventLogSize); 2218 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION), mainCfg.IOPeventLogOption); 2219 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT), mainCfg.FatalErrorInterrupt); 2220 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD), mainCfg.portRecoveryResetTimer); 2221 2222 SA_DBG3(("mpiInitialize: Offset 0x%08x upperEventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI), mainCfg.upperEventLogAddress )); 2223 SA_DBG3(("mpiInitialize: Offset 0x%08x lowerEventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO), mainCfg.lowerEventLogAddress )); 2224 SA_DBG3(("mpiInitialize: Offset 0x%08x eventLogSize 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE), mainCfg.eventLogSize )); 2225 SA_DBG3(("mpiInitialize: Offset 0x%08x eventLogOption 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION), mainCfg.eventLogOption )); 2226 SA_DBG3(("mpiInitialize: Offset 0x%08x upperIOPeventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI), mainCfg.upperIOPeventLogAddress )); 2227 SA_DBG3(("mpiInitialize: Offset 0x%08x lowerIOPeventLogAddress 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO), mainCfg.lowerIOPeventLogAddress )); 2228 SA_DBG3(("mpiInitialize: Offset 0x%08x IOPeventLogSize 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE), mainCfg.IOPeventLogSize )); 2229 SA_DBG3(("mpiInitialize: Offset 0x%08x IOPeventLogOption 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION), mainCfg.IOPeventLogOption )); 2230 SA_DBG3(("mpiInitialize: Offset 0x%08x FatalErrorInterrupt 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT), mainCfg.FatalErrorInterrupt )); 2231 SA_DBG3(("mpiInitialize: Offset 0x%08x PortRecoveryResetTimer 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD), mainCfg.portRecoveryResetTimer )); 2232 2233 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED), mainCfg.interruptReassertionDelay); 2234 SA_DBG3(("mpiInitialize: Offset 0x%08x InterruptReassertionDelay 0x%x\n",(bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED), mainCfg.interruptReassertionDelay )); 2235 2236 mIdx++; 2237 2238 /* skip the ci and pi memory region */ 2239 mIdx++; 2240 mIdx++; 2241 2242 smTrace(hpDBG_VERY_LOUD,"72",mIdx); 2243 /* TP:72 mIdx */ 2244 smTrace(hpDBG_VERY_LOUD,"Bc",maxinbound); 2245 /* TP:Bc maxinbound */ 2246 smTrace(hpDBG_VERY_LOUD,"Bd",pcibar); 2247 /* TP:Bd pcibar */ 2248 2249 /* index offset */ 2250 indexoffset = 0; 2251 memOffset = 0; 2252 2253 /* Memory regions for the inbound queues */ 2254 for(qIdx = 0; qIdx < maxinbound; qIdx++) 2255 { 2256 /* point back to the begin then plus offset to next queue */ 2257 smTrace(hpDBG_VERY_LOUD,"Bd",pcibar); 2258 /* TP:Bd pcibar */ 2259 MSGUCfgTblDWIdx = saveOffset; 2260 MSGUCfgTblDWIdx += inboundoffset; 2261 MSGUCfgTblDWIdx += (sizeof(spc_inboundQueueDescriptor_t) * qIdx); 2262 SA_DBG1(("mpiInitialize: A saveOffset 0x%x MSGUCfgTblDWIdx 0x%x\n",saveOffset ,MSGUCfgTblDWIdx)); 2263 2264 /* if the MPI configuration says that this queue is disabled ... */ 2265 if(0 == config->inboundQueues[qIdx].numElements) 2266 { 2267 /* ... Clears the configuration table for this queue */ 2268 2269 inQueueCfg.elementPriSizeCount= 0; 2270 inQueueCfg.upperBaseAddress = 0; 2271 inQueueCfg.lowerBaseAddress = 0; 2272 inQueueCfg.ciUpperBaseAddress = 0; 2273 inQueueCfg.ciLowerBaseAddress = 0; 2274 /* skip inQueueCfg.PIPCIBar (PM8000 write access) */ 2275 /* skip inQueueCfg.PIOffset (PM8000 write access) */ 2276 2277 /* Update the inbound configuration table in SPC GSM */ 2278 mpiUpdateIBQueueCfgTable(agRoot, &inQueueCfg, MSGUCfgTblDWIdx, pcibar); 2279 } 2280 2281 /* If the queue is enabled, then ... */ 2282 else 2283 { 2284 bit32 memSize = config->inboundQueues[qIdx].numElements * config->inboundQueues[qIdx].elementSize; 2285 bit32 remainder = memSize & 127; 2286 2287 /* Calculate the size of this queue padded to 128 bytes */ 2288 if (remainder > 0) 2289 { 2290 memSize += (128 - remainder); 2291 } 2292 2293 /* ... first checks that the memory region has the right size */ 2294 if( (memoryAllocated->region[mIdx].totalLength - memOffset < memSize) || 2295 (NULL == memoryAllocated->region[mIdx].virtPtr) || 2296 (0 == memoryAllocated->region[mIdx].totalLength)) 2297 { 2298 SA_DBG1(("mpiInitialize: ERROR The memory region does not have the right size for this inbound queue")); 2299 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m3"); 2300 return AGSA_RC_FAILURE; 2301 } 2302 else 2303 { 2304 /* Then, using the MPI configuration argument, initializes the corresponding element on the saRoot */ 2305 saRoot->inboundQueue[qIdx].numElements = config->inboundQueues[qIdx].numElements; 2306 saRoot->inboundQueue[qIdx].elementSize = config->inboundQueues[qIdx].elementSize; 2307 saRoot->inboundQueue[qIdx].priority = config->inboundQueues[qIdx].priority; 2308 si_memcpy(&saRoot->inboundQueue[qIdx].memoryRegion, &memoryAllocated->region[mIdx], sizeof(mpiMem_t)); 2309 saRoot->inboundQueue[qIdx].memoryRegion.virtPtr = 2310 (bit8 *)saRoot->inboundQueue[qIdx].memoryRegion.virtPtr + memOffset; 2311 saRoot->inboundQueue[qIdx].memoryRegion.physAddrLower += memOffset; 2312 saRoot->inboundQueue[qIdx].memoryRegion.elementSize = memSize; 2313 saRoot->inboundQueue[qIdx].memoryRegion.totalLength = memSize; 2314 saRoot->inboundQueue[qIdx].memoryRegion.numElements = 1; 2315 2316 /* Initialize the local copy of PIs, CIs */ 2317 SA_DBG1(("mpiInitialize: queue %d PI CI zero\n",qIdx)); 2318 saRoot->inboundQueue[qIdx].producerIdx = 0; 2319 saRoot->inboundQueue[qIdx].consumerIdx = 0; 2320 saRoot->inboundQueue[qIdx].agRoot = agRoot; 2321 2322 /* MPI memory region for inbound CIs are 2 */ 2323 saRoot->inboundQueue[qIdx].ciPointer = (((bit8 *)(memoryAllocated->region[MPI_CI_INDEX].virtPtr)) + qIdx * 4); 2324 /* ... and in the local structure we will use to copy to the HW configuration table */ 2325 2326 /* CI base address */ 2327 inQueueCfg.elementPriSizeCount= config->inboundQueues[qIdx].numElements | 2328 (config->inboundQueues[qIdx].elementSize << SHIFT16) | 2329 (config->inboundQueues[qIdx].priority << SHIFT30); 2330 inQueueCfg.upperBaseAddress = saRoot->inboundQueue[qIdx].memoryRegion.physAddrUpper; 2331 inQueueCfg.lowerBaseAddress = saRoot->inboundQueue[qIdx].memoryRegion.physAddrLower; 2332 inQueueCfg.ciUpperBaseAddress = memoryAllocated->region[MPI_CI_INDEX].physAddrUpper; 2333 inQueueCfg.ciLowerBaseAddress = memoryAllocated->region[MPI_CI_INDEX].physAddrLower + qIdx * 4; 2334 2335 /* write the configured data of inbound queue to SPC GSM */ 2336 mpiUpdateIBQueueCfgTable(agRoot, &inQueueCfg, MSGUCfgTblDWIdx, pcibar); 2337 /* get inbound PI PCI Bar and Offset */ 2338 /* get the PI PCI Bar offset and convert it to logical BAR */ 2339 IB_PIPCIBar = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR)); 2340 saRoot->inboundQueue[qIdx].PIPCIBar = mpiGetPCIBarIndex(agRoot, IB_PIPCIBar); 2341 saRoot->inboundQueue[qIdx].PIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR_OFFSET)); 2342 saRoot->inboundQueue[qIdx].qNumber = qIdx; 2343 2344 memOffset += memSize; 2345 2346 if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || 2347 (qIdx == (maxinbound - 1))) 2348 { 2349 mIdx++; 2350 indexoffset += MAX_QUEUE_EACH_MEM; 2351 memOffset = 0; 2352 } 2353 2354 } /* else for memeory ok */ 2355 } /* queue enable */ 2356 } /* loop for inbound queue */ 2357 2358 smTrace(hpDBG_VERY_LOUD,"73",0); 2359 /* TP:73 outbound queues */ 2360 2361 /* index offset */ 2362 indexoffset = 0; 2363 memOffset = 0; 2364 /* Let's process the memory regions for the outbound queues */ 2365 for(qIdx = 0; qIdx < maxoutbound; qIdx++) 2366 { 2367 /* point back to the begin then plus offset to next queue */ 2368 MSGUCfgTblDWIdx = saveOffset; 2369 MSGUCfgTblDWIdx += outboundoffset; 2370 MSGUCfgTblDWIdx += (sizeof(spc_outboundQueueDescriptor_t) * qIdx); 2371 2372 /* if the MPI configuration says that this queue is disabled ... */ 2373 if(0 == config->outboundQueues[qIdx].numElements) 2374 { 2375 /* ... Clears the configuration table for this queue */ 2376 outQueueCfg.upperBaseAddress = 0; 2377 outQueueCfg.lowerBaseAddress = 0; 2378 outQueueCfg.piUpperBaseAddress = 0; 2379 outQueueCfg.piLowerBaseAddress = 0; 2380 /* skip outQueueCfg.CIPCIBar = 0; read access only */ 2381 /* skip outQueueCfg.CIOffset = 0; read access only */ 2382 outQueueCfg.elementSizeCount = 0; 2383 outQueueCfg.interruptVecCntDelay = 0; 2384 2385 /* Updated the configuration table in SPC GSM */ 2386 mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar); 2387 } 2388 2389 /* If the outbound queue is enabled, then ... */ 2390 else 2391 { 2392 bit32 memSize = config->outboundQueues[qIdx].numElements * config->outboundQueues[qIdx].elementSize; 2393 bit32 remainder = memSize & 127; 2394 2395 /* Calculate the size of this queue padded to 128 bytes */ 2396 if (remainder > 0) 2397 { 2398 memSize += (128 - remainder); 2399 } 2400 2401 /* ... first checks that the memory region has the right size */ 2402 if((memoryAllocated->region[mIdx].totalLength - memOffset < memSize) || 2403 (NULL == memoryAllocated->region[mIdx].virtPtr) || 2404 (0 == memoryAllocated->region[mIdx].totalLength)) 2405 { 2406 SA_DBG1(("ERROR: The memory region does not have the right size for this outbound queue")); 2407 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m3"); 2408 return AGSA_RC_FAILURE; 2409 } 2410 else 2411 { 2412 /* Then, using the MPI configuration argument, initializes the corresponding element on the MPI context ... */ 2413 saRoot->outboundQueue[qIdx].numElements = config->outboundQueues[qIdx].numElements; 2414 saRoot->outboundQueue[qIdx].elementSize = config->outboundQueues[qIdx].elementSize; 2415 si_memcpy(&saRoot->outboundQueue[qIdx].memoryRegion, &memoryAllocated->region[mIdx], sizeof(mpiMem_t)); 2416 saRoot->outboundQueue[qIdx].memoryRegion.virtPtr = 2417 (bit8 *)saRoot->outboundQueue[qIdx].memoryRegion.virtPtr + memOffset; 2418 saRoot->outboundQueue[qIdx].memoryRegion.physAddrLower += memOffset; 2419 saRoot->outboundQueue[qIdx].memoryRegion.elementSize = memSize; 2420 saRoot->outboundQueue[qIdx].memoryRegion.totalLength = memSize; 2421 saRoot->outboundQueue[qIdx].memoryRegion.numElements = 1; 2422 saRoot->outboundQueue[qIdx].producerIdx = 0; 2423 saRoot->outboundQueue[qIdx].consumerIdx = 0; 2424 saRoot->outboundQueue[qIdx].agRoot = agRoot; 2425 2426 /* MPI memory region for outbound PIs are 3 */ 2427 saRoot->outboundQueue[qIdx].piPointer = (((bit8 *)(memoryAllocated->region[MPI_CI_INDEX + 1].virtPtr))+ qIdx * 4); 2428 /* ... and in the local structure we will use to copy to the HW configuration table */ 2429 outQueueCfg.upperBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrUpper; 2430 outQueueCfg.lowerBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrLower; 2431 2432 /* PI base address */ 2433 outQueueCfg.piUpperBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrUpper; 2434 outQueueCfg.piLowerBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrLower + qIdx * 4; 2435 outQueueCfg.elementSizeCount = config->outboundQueues[qIdx].numElements | 2436 (config->outboundQueues[qIdx].elementSize << SHIFT16); 2437 2438 /* enable/disable interrupt - use saSystemInterruptsActive() API */ 2439 /* instead of ossaHwRegWrite(agRoot, MSGU_ODMR, 0); */ 2440 /* Outbound Doorbell Auto disable */ 2441 /* LL does not use ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_ODAR, 0xffffffff); */ 2442 if (config->outboundQueues[qIdx].interruptEnable) 2443 { 2444 /* enable interrupt flag bit30 of outbound table */ 2445 outQueueCfg.elementSizeCount |= OB_PROPERTY_INT_ENABLE; 2446 } 2447 if(smIS_SPCV(agRoot)) 2448 { 2449 outQueueCfg.interruptVecCntDelay = ((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24); 2450 } 2451 else 2452 { 2453 outQueueCfg.interruptVecCntDelay = (config->outboundQueues[qIdx].interruptDelay & INT_DELAY_BITS) | 2454 ((config->outboundQueues[qIdx].interruptThreshold & INT_THR_BITS ) << SHIFT16) | 2455 ((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24); 2456 } 2457 2458 /* create a VectorIndex Bit Map */ 2459 if (qIdx < OQ_NUM_32) 2460 { 2461 saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector] |= (1 << qIdx); 2462 SA_DBG2(("mpiInitialize:below 32 saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector] 0x%08x\n",saRoot->interruptVecIndexBitMap[config->outboundQueues[qIdx].interruptVector])); 2463 } 2464 else 2465 { 2466 saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector] |= (1 << (qIdx - OQ_NUM_32)); 2467 SA_DBG2(("mpiInitialize:Above 32 saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector] 0x%08x\n",saRoot->interruptVecIndexBitMap1[config->outboundQueues[qIdx].interruptVector])); 2468 } 2469 /* Update the outbound configuration table */ 2470 mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar); 2471 2472 /* read the CI PCIBar offset and convert it to logical bar */ 2473 OB_CIPCIBar = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_CIPCI_BAR)); 2474 saRoot->outboundQueue[qIdx].CIPCIBar = mpiGetPCIBarIndex(agRoot, OB_CIPCIBar); 2475 saRoot->outboundQueue[qIdx].CIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_CIPCI_BAR_OFFSET)); 2476 saRoot->outboundQueue[qIdx].DIntTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + OB_DYNAMIC_COALES_OFFSET)); 2477 saRoot->outboundQueue[qIdx].qNumber = qIdx; 2478 2479 memOffset += memSize; 2480 2481 if ((0 == ((qIdx + 1) % MAX_QUEUE_EACH_MEM)) || 2482 (qIdx == (maxoutbound - 1))) 2483 { 2484 mIdx++; 2485 indexoffset += MAX_QUEUE_EACH_MEM; 2486 memOffset =0; 2487 } 2488 } 2489 } 2490 } 2491 2492 /* calculate number of vectors */ 2493 saRoot->numInterruptVectors = 0; 2494 for (qIdx = 0; qIdx < MAX_NUM_VECTOR; qIdx++) 2495 { 2496 if ((saRoot->interruptVecIndexBitMap[qIdx]) || (saRoot->interruptVecIndexBitMap1[qIdx])) 2497 { 2498 (saRoot->numInterruptVectors)++; 2499 } 2500 } 2501 2502 SA_DBG2(("mpiInitialize:(saRoot->numInterruptVectors) 0x%x\n",(saRoot->numInterruptVectors))); 2503 2504 if(smIS_SPCV(agRoot)) 2505 { 2506 /* setup interrupt vector table */ 2507 mpiWrIntVecTable(agRoot,config); 2508 } 2509 2510 if(smIS_SPCV(agRoot)) 2511 { 2512 mpiWrAnalogSetupTable(agRoot,config); 2513 } 2514 2515 /* setup phy analog registers */ 2516 mpiWriteCALAll(agRoot, &config->phyAnalogConfig); 2517 2518 { 2519 bit32 pcibar = 0; 2520 bit32 TableOffset; 2521 pcibar = siGetPciBar(agRoot); 2522 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2523 TableOffset &= SCRATCH_PAD0_OFFSET_MASK; 2524 SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ))); 2525 2526 SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture"); 2527 2528 SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE 0x%08X\n", 0)); 2529 SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_GST_OFFSET) & 0xFFFF ))); 2530 SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_IBQ_OFFSET) & 0xFFFF))); 2531 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_OBQ_OFFSET) & 0xFFFF))); 2532 SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_ANALOG_SETUP_OFFSET) & 0xFFFF ))); 2533 SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_INT_VEC_TABLE_OFFSET) & 0xFFFF))); 2534 SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET) & 0xFFFF))); 2535 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_MOQFOT_MOQFOES) & 0xFFFF))); 2536 2537 } 2538 2539 if(agNULL != saRoot->swConfig.mpiContextTable ) 2540 { 2541 agsaMPIContext_t * context = (agsaMPIContext_t * )saRoot->swConfig.mpiContextTable; 2542 bit32 length = saRoot->swConfig.mpiContextTablelen; 2543 bit32 pcibar = 0; 2544 bit32 TableOffset; 2545 pcibar = siGetPciBar(agRoot); 2546 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2547 TableOffset &= SCRATCH_PAD0_OFFSET_MASK; 2548 SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ))); 2549 2550 SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture"); 2551 if ( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) != 0x53434D50)) 2552 { 2553 SA_DBG1(("mpiInitialize: TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50)); 2554 } 2555 2556 if(context ) 2557 { 2558 SA_DBG1(("mpiInitialize: MPITableType 0x%x context->offset 0x%x context->value 0x%x\n",context->MPITableType,context->offset,context->value)); 2559 while( length != 0) 2560 { 2561 switch(context->MPITableType) 2562 { 2563 2564 bit32 OffsetInMain; 2565 case AGSA_MPI_MAIN_CONFIGURATION_TABLE: 2566 SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE %d 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset, context->offset, context->value)); 2567 OffsetInMain = TableOffset; 2568 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4) , context->value); 2569 break; 2570 case AGSA_MPI_GENERAL_STATUS_TABLE: 2571 SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType ,TableOffset+MAIN_GST_OFFSET, context->offset, context->value )); 2572 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_GST_OFFSET ) & 0xFFFF) + TableOffset; 2573 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2574 break; 2575 case AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE: 2576 SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_IBQ_OFFSET, context->offset, context->value)); 2577 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_IBQ_OFFSET ) & 0xFFFF) + TableOffset; 2578 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2579 break; 2580 case AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE: 2581 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_OBQ_OFFSET, context->offset, context->value)); 2582 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_OBQ_OFFSET ) & 0xFFFF) + TableOffset; 2583 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2584 break; 2585 case AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE: 2586 SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_ANALOG_SETUP_OFFSET, context->offset, context->value)); 2587 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+ MAIN_ANALOG_SETUP_OFFSET) & 0xFFFF) + TableOffset; 2588 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2589 break; 2590 case AGSA_MPI_INTERRUPT_VECTOR_TABLE: 2591 SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_INT_VEC_TABLE_OFFSET, context->offset, context->value)); 2592 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+ MAIN_INT_VEC_TABLE_OFFSET) & 0xFFFF) + TableOffset; 2593 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2594 break; 2595 case AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE: 2596 SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET, context->offset, context->value)); 2597 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET ) & 0xFFFF) + TableOffset; 2598 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2599 break; 2600 case AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE: 2601 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_MOQFOT_MOQFOES, context->offset, context->value)); 2602 OffsetInMain = (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_MOQFOT_MOQFOES ) & 0xFFFF) + TableOffset; 2603 ossaHwRegWriteExt(agRoot, pcibar, OffsetInMain + (context->offset * 4), context->value); 2604 break; 2605 default: 2606 SA_DBG1(("mpiInitialize: error MPITableType unknown %d offset 0x%x value 0x%x\n",context->MPITableType, context->offset, context->value)); 2607 break; 2608 } 2609 if(smIS_SPC12V(agRoot)) 2610 { 2611 if (saRoot->ControllerInfo.fwInterfaceRev > 0x301 ) 2612 { 2613 SA_DBG1(("mpiInitialize: MAIN_AWT_MIDRANGE 0x%08X\n", 2614 ossaHwRegReadExt(agRoot, pcibar, TableOffset + MAIN_AWT_MIDRANGE) 2615 )); 2616 } 2617 } 2618 if(length >= sizeof(agsaMPIContext_t)) 2619 { 2620 length -= sizeof(agsaMPIContext_t); 2621 context++; 2622 2623 } 2624 else 2625 { 2626 length = 0; 2627 } 2628 } 2629 2630 } 2631 2632 SA_DBG1(("mpiInitialize: context %p saRoot->swConfig.mpiContextTable %p %d\n",context,saRoot->swConfig.mpiContextTable,context == saRoot->swConfig.mpiContextTable ? 1 : 0)); 2633 2634 if ( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) != 0x53434D50)) 2635 { 2636 SA_DBG1(("mpiInitialize:TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50)); 2637 } 2638 2639 SA_ASSERT( (ossaHwRegReadExt(agRoot, pcibar, TableOffset ) == 0x53434D50), "Config table signiture After"); 2640 } 2641 /* At this point the Message Unit configuration table is set up. Now we need to ring the doorbell */ 2642 togglevalue = 0; 2643 2644 smTrace(hpDBG_VERY_LOUD,"74", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET )); 2645 /* TP:74 Doorbell */ 2646 2647 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the table is updated */ 2648 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 2649 2650 if(siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET ) & SPC_MSGU_CFG_TABLE_UPDATE) 2651 { 2652 SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE (0x%X) \n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET))); 2653 } 2654 else 2655 { 2656 SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE not set (0x%X)\n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET))); 2657 ossaStallThread(agRoot, WAIT_INCREMENT); 2658 } 2659 2660 smTrace(hpDBG_VERY_LOUD,"A5", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET )); 2661 /* TP:A5 Doorbell */ 2662 2663/* 2664// ossaHwRegWrite(agRoot, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 2665 MSGU_WRITE_IDR(SPC_MSGU_CFG_TABLE_UPDATE); 2666*/ 2667 2668 2669 /* wait until Inbound DoorBell Clear Register toggled */ 2670WaitLonger: 2671 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 2672 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 2673 do 2674 { 2675 ossaStallThread(agRoot, WAIT_INCREMENT); 2676 value = MSGU_READ_IDR; 2677 value &= SPC_MSGU_CFG_TABLE_UPDATE; 2678 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 2679 2680 smTrace(hpDBG_VERY_LOUD,"80", max_wait_count); 2681 /* TP:80 TP max_wait_count */ 2682 if (!max_wait_count && mpiStartToggleFailed < 5 ) 2683 { 2684 SA_DBG1(("mpiInitialize: mpiStartToggleFailed count %d\n", mpiStartToggleFailed)); 2685 mpiStartToggleFailed++; 2686 goto WaitLonger; 2687 } 2688 2689 if (!max_wait_count ) 2690 { 2691 2692 SA_DBG1(("mpiInitialize: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 2693 MSGUCfgTblDWIdx = saveOffset; 2694 GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)MSGUCfgTblDWIdx + (bit32)(mainCfg.GSTOffset + GST_GSTLEN_MPIS_OFFSET)); 2695 SA_DBG1(("mpiInitialize: MPI State = 0x%x\n", GSTLenMPIS)); 2696 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m3"); 2697 return AGSA_RC_FAILURE; 2698 } 2699 smTrace(hpDBG_VERY_LOUD,"81", mpiStartToggleFailed ); 2700 /* TP:81 TP */ 2701 2702 /* check the MPI-State for initialization */ 2703 MSGUCfgTblDWIdx = saveOffset; 2704 GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)MSGUCfgTblDWIdx + (bit32)(mainCfg.GSTOffset + GST_GSTLEN_MPIS_OFFSET)); 2705 if ( (GST_MPI_STATE_UNINIT == (GSTLenMPIS & GST_MPI_STATE_MASK)) && ( mpiUnInitFailed < 5 ) ) 2706 { 2707 SA_DBG1(("mpiInitialize: MPI State = 0x%x mpiUnInitFailed count %d\n", GSTLenMPIS & GST_MPI_STATE_MASK,mpiUnInitFailed)); 2708 ossaStallThread(agRoot, (20 * 1000)); 2709 2710 mpiUnInitFailed++; 2711 goto WaitLonger; 2712 } 2713 2714 if (GST_MPI_STATE_INIT != (GSTLenMPIS & GST_MPI_STATE_MASK)) 2715 { 2716 SA_DBG1(("mpiInitialize: Error Not GST_MPI_STATE_INIT MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK)); 2717 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m3"); 2718 return AGSA_RC_FAILURE; 2719 } 2720 smTrace(hpDBG_VERY_LOUD,"82", 0); 2721 /* TP:82 TP */ 2722 2723 /* check MPI Initialization error */ 2724 GSTLenMPIS = GSTLenMPIS >> SHIFT16; 2725 if (0x0000 != GSTLenMPIS) 2726 { 2727 SA_DBG1(("mpiInitialize: MPI Error = 0x%x\n", GSTLenMPIS)); 2728 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m3"); 2729 return AGSA_RC_FAILURE; 2730 } 2731 smTrace(hpDBG_VERY_LOUD,"83", 0); 2732 /* TP:83 TP */ 2733 2734 /* reread IQ PI offset from SPC if IQ/OQ > 32 */ 2735 if ((maxinbound > IQ_NUM_32) || (maxoutbound > OQ_NUM_32)) 2736 { 2737 for(qIdx = 0; qIdx < maxinbound; qIdx++) 2738 { 2739 /* point back to the begin then plus offset to next queue */ 2740 MSGUCfgTblDWIdx = saveOffset; 2741 MSGUCfgTblDWIdx += inboundoffset; 2742 MSGUCfgTblDWIdx += (sizeof(spc_inboundQueueDescriptor_t) * qIdx); 2743 saRoot->inboundQueue[qIdx].PIPCIOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + IB_PIPCI_BAR_OFFSET)); 2744 } 2745 } 2746 smTrace(hpDBG_VERY_LOUD,"84", 0); 2747 /* TP:84 TP */ 2748 2749 /* at least one inbound queue and one outbound queue enabled */ 2750 if ((0 == config->inboundQueues[0].numElements) || (0 == config->outboundQueues[0].numElements)) 2751 { 2752 SA_DBG1(("mpiInitialize: Error,IQ0 or OQ0 have to enable\n")); 2753 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m3"); 2754 return AGSA_RC_FAILURE; 2755 } 2756 smTrace(hpDBG_VERY_LOUD,"85", 0); 2757 /* TP:85 TP */ 2758 2759 /* clean the inbound queues */ 2760 for (i = 0; i < config->numInboundQueues; i ++) 2761 { 2762 if(0 != config->inboundQueues[i].numElements) 2763 { 2764 circularIQ = &saRoot->inboundQueue[i]; 2765 si_memset(circularIQ->memoryRegion.virtPtr, 0, circularIQ->memoryRegion.totalLength); 2766 si_memset(saRoot->inboundQueue[i].ciPointer, 0, sizeof(bit32)); 2767 2768 if(smIS_SPCV(agRoot)) 2769 { 2770 ossaHwRegWriteExt(circularIQ->agRoot, circularIQ->PIPCIBar, circularIQ->PIPCIOffset, 0); 2771 SA_DBG1(("mpiInitialize: SPC V writes IQ %2d offset 0x%x\n",i ,circularIQ->PIPCIOffset)); 2772 } 2773 } 2774 } 2775 smTrace(hpDBG_VERY_LOUD,"86", 0); 2776 /* TP:86 TP */ 2777 2778 /* clean the outbound queues */ 2779 for (i = 0; i < config->numOutboundQueues; i ++) 2780 { 2781 if(0 != config->outboundQueues[i].numElements) 2782 { 2783 circularOQ = &saRoot->outboundQueue[i]; 2784 si_memset(circularOQ->memoryRegion.virtPtr, 0, circularOQ->memoryRegion.totalLength); 2785 si_memset(saRoot->outboundQueue[i].piPointer, 0, sizeof(bit32)); 2786 if(smIS_SPCV(agRoot)) 2787 { 2788 ossaHwRegWriteExt(circularOQ->agRoot, circularOQ->CIPCIBar, circularOQ->CIPCIOffset, 0); 2789 SA_DBG2(("mpiInitialize: SPC V writes OQ %2d offset 0x%x\n",i ,circularOQ->CIPCIOffset)); 2790 } 2791 2792 } 2793 } 2794 2795 2796 smTrace(hpDBG_VERY_LOUD,"75",0); 2797 /* TP:75 AAP1 IOP */ 2798 2799 /* read back AAP1 and IOP event log address and size */ 2800 MSGUCfgTblDWIdx = saveOffset; 2801 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_HI)); 2802 saRoot->mainConfigTable.upperEventLogAddress = value; 2803 SA_DBG1(("mpiInitialize: upperEventLogAddress 0x%x\n", value)); 2804 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_ADDR_LO)); 2805 saRoot->mainConfigTable.lowerEventLogAddress = value; 2806 SA_DBG1(("mpiInitialize: lowerEventLogAddress 0x%x\n", value)); 2807 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_BUFF_SIZE)); 2808 saRoot->mainConfigTable.eventLogSize = value; 2809 SA_DBG1(("mpiInitialize: eventLogSize 0x%x\n", value)); 2810 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_EVENT_LOG_OPTION)); 2811 saRoot->mainConfigTable.eventLogOption = value; 2812 SA_DBG1(("mpiInitialize: eventLogOption 0x%x\n", value)); 2813 SA_DBG1(("mpiInitialize: EventLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperEventLogAddress,saRoot->mainConfigTable.lowerEventLogAddress,saRoot->mainConfigTable.eventLogSize/4 )); 2814 2815 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_HI)); 2816 saRoot->mainConfigTable.upperIOPeventLogAddress = value; 2817 SA_DBG1(("mpiInitialize: upperIOPLogAddress 0x%x\n", value)); 2818 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_ADDR_LO)); 2819 saRoot->mainConfigTable.lowerIOPeventLogAddress = value; 2820 SA_DBG1(("mpiInitialize: lowerIOPLogAddress 0x%x\n", value)); 2821 SA_DBG1(("mpiInitialize: IOPLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperIOPeventLogAddress,saRoot->mainConfigTable.lowerIOPeventLogAddress,saRoot->mainConfigTable.IOPeventLogSize/4 )); 2822 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_BUFF_SIZE)); 2823 saRoot->mainConfigTable.IOPeventLogSize = value; 2824 SA_DBG1(("mpiInitialize: IOPeventLogSize 0x%x\n", value)); 2825 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IOP_EVENT_LOG_OPTION)); 2826 saRoot->mainConfigTable.IOPeventLogOption = value; 2827 SA_DBG1(("mpiInitialize: IOPeventLogOption 0x%x\n", value)); 2828 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_INTERRUPT)); 2829 2830#ifdef SA_PRINTOUT_IN_WINDBG 2831#ifndef DBG 2832 DbgPrint("mpiInitialize: EventLog (%d) dd /p %08X`%08X L %x\n", 2833 saRoot->mainConfigTable.eventLogOption, 2834 saRoot->mainConfigTable.upperEventLogAddress, 2835 saRoot->mainConfigTable.lowerEventLogAddress, 2836 saRoot->mainConfigTable.eventLogSize/4 ); 2837 DbgPrint("mpiInitialize: IOPLog (%d) dd /p %08X`%08X L %x\n", 2838 saRoot->mainConfigTable.IOPeventLogOption, 2839 saRoot->mainConfigTable.upperIOPeventLogAddress, 2840 saRoot->mainConfigTable.lowerIOPeventLogAddress, 2841 saRoot->mainConfigTable.IOPeventLogSize/4 ); 2842#endif /* DBG */ 2843#endif /* SA_PRINTOUT_IN_WINDBG */ 2844 2845 saRoot->mainConfigTable.FatalErrorInterrupt = value; 2846 smTrace(hpDBG_VERY_LOUD,"76",value); 2847 /* TP:76 FatalErrorInterrupt */ 2848 2849 SA_DBG1(("mpiInitialize: hwConfig->hwOption %X\n", saRoot->hwConfig.hwOption )); 2850 2851 SA_DBG1(("mpiInitialize: FatalErrorInterrupt 0x%x\n", value)); 2852 2853 /* read back Register Dump offset and length */ 2854 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_OFFSET)); 2855 saRoot->mainConfigTable.FatalErrorDumpOffset0 = value; 2856 SA_DBG1(("mpiInitialize: FatalErrorDumpOffset0 0x%x\n", value)); 2857 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_LENGTH)); 2858 saRoot->mainConfigTable.FatalErrorDumpLength0 = value; 2859 SA_DBG1(("mpiInitialize: FatalErrorDumpLength0 0x%x\n", value)); 2860 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_OFFSET)); 2861 saRoot->mainConfigTable.FatalErrorDumpOffset1 = value; 2862 SA_DBG1(("mpiInitialize: FatalErrorDumpOffset1 0x%x\n", value)); 2863 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_LENGTH)); 2864 saRoot->mainConfigTable.FatalErrorDumpLength1 = value; 2865 SA_DBG1(("mpiInitialize: FatalErrorDumpLength1 0x%x\n", value)); 2866 2867 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_PRECTD_PRESETD)); 2868 saRoot->mainConfigTable.PortRecoveryTimerPortResetTimer = value; 2869 2870 SA_DBG1(("mpiInitialize: PortRecoveryTimerPortResetTimer 0x%x\n", value)); 2871 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(MSGUCfgTblDWIdx + MAIN_IRAD_RESERVED)); 2872 saRoot->mainConfigTable.InterruptReassertionDelay = value; 2873 2874 SA_DBG1(("mpiInitialize: InterruptReassertionDelay 0x%x\n", value)); 2875 2876 2877 if(smIS_SPCV(agRoot)) 2878 { 2879 bit32 sp1; 2880 sp1= ossaHwRegRead(agRoot,V_Scratchpad_1_Register ); 2881 if(SCRATCH_PAD1_V_ERROR_STATE(sp1)) 2882 { 2883 SA_DBG1(("mpiInitialize: SCRATCH_PAD1_V_ERROR_STAT 0x%x\n",sp1 )); 2884 ret = AGSA_RC_FAILURE; 2885 } 2886 2887 } 2888 2889 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m3"); 2890 return ret; 2891} 2892 2893/*******************************************************************************/ 2894/** \fn mpiWaitForConfigTable(agsaRoot_t *agRoot, spc_configMainDescriptor_t *config) 2895 * \brief Reading and Writing the Configuration Table 2896 * \param agsaRoot Pointer to a data structure containing LL layer context handles 2897 * \param config Pointer to Configuration Table 2898 * 2899 * Return: 2900 * AGSA_RC_SUCCESS if read the configuration table from SPC sucessful 2901 * AGSA_RC_FAILURE if read the configuration table from SPC failed 2902 */ 2903/*******************************************************************************/ 2904GLOBAL bit32 mpiWaitForConfigTable(agsaRoot_t *agRoot, 2905 spc_configMainDescriptor_t *config) 2906{ 2907 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2908 bit32 MSGUCfgTblBase, ret = AGSA_RC_SUCCESS; 2909 bit32 CfgTblDWIdx; 2910 bit32 value, value1; 2911 bit32 max_wait_time; 2912 bit32 max_wait_count; 2913 bit32 Signature, ExpSignature; 2914 bit8 pcibar; 2915 2916 SA_DBG2(("mpiWaitForConfigTable: Entering\n")); 2917 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 2918 2919 smTraceFuncEnter(hpDBG_VERY_LOUD,"m4"); 2920 2921 2922 /* check error state */ 2923 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); 2924 value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 2925 2926 if( smIS_SPC(agRoot) ) 2927 { 2928 SA_DBG1(("mpiWaitForConfigTable: Waiting for SPC FW becoming ready.P1 0x%X P2 0x%X\n",value,value1)); 2929 2930 /* check AAP error */ 2931 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) 2932 { 2933 /* error state */ 2934 SA_DBG1(("mpiWaitForConfigTable: AAP error state and code 0x%x, ScratchPad2=0x%x\n", value, value1)); 2935#if defined(SALLSDK_DEBUG) 2936 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2937 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 2938#endif 2939 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m4"); 2940 return AGSA_RC_FAILURE; 2941 } 2942 2943 /* check IOP error */ 2944 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) 2945 { 2946 /* error state */ 2947 SA_DBG1(("mpiWaitForConfigTable: IOP error state and code 0x%x, ScratchPad1=0x%x\n", value1, value)); 2948#if defined(SALLSDK_DEBUG) 2949 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2950 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 2951#endif 2952 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m4"); 2953 return AGSA_RC_FAILURE; 2954 } 2955 2956 /* bit 4-31 of scratch pad1 should be zeros if it is not in error state */ 2957#ifdef DONT_DO /* */ 2958 if (value & SCRATCH_PAD1_STATE_MASK) 2959 { 2960 /* error case */ 2961 SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad1 0x%x\n", value)); 2962 SA_DBG1(("mpiWaitForConfigTable: ScratchPad0 AAP error code 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2963#if defined(SALLSDK_DEBUG) 2964 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_0))); 2965 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 2966#endif 2967 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m4"); 2968 return AGSA_RC_FAILURE; 2969 } 2970 2971 /* bit 4-31 of scratch pad2 should be zeros if it is not in error state */ 2972 if (value1 & SCRATCH_PAD2_STATE_MASK) 2973 { 2974 /* error case */ 2975 SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad2 0x%x\n", value1)); 2976 SA_DBG1(("mpiWaitForConfigTable: ScratchPad3 IOP error code 0x%x\n",siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3) )); 2977#if defined(SALLSDK_DEBUG) 2978 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 2979 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1))); 2980#endif 2981 smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "m4"); 2982 2983 return AGSA_RC_FAILURE; 2984 } 2985#endif /* DONT_DO */ 2986 2987 /* checking the fw and IOP in ready state */ 2988 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec timeout */ 2989 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 2990 /* wait until scratch pad 1 and 2 registers in ready state */ 2991 do 2992 { 2993 ossaStallThread(agRoot, WAIT_INCREMENT); 2994 value =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RDY; 2995 value1 =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_RDY; 2996 if(smIS_SPCV(agRoot)) 2997 { 2998 SA_DBG1(("mpiWaitForConfigTable:VEN_DEV_SPCV force SCRATCH_PAD2 RDY 1 %08X 2 %08X\n" ,value,value1)); 2999 value1 =3; 3000 } 3001 3002 if ((max_wait_count -= WAIT_INCREMENT) == 0) 3003 { 3004 SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); 3005 break; 3006 } 3007 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 3008 3009 if (!max_wait_count) 3010 { 3011 SA_DBG1(("mpiWaitForConfigTable: timeout failure\n")); 3012#if defined(SALLSDK_DEBUG) 3013 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 3014 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 3015#endif 3016 smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "m4"); 3017 return AGSA_RC_FAILURE; 3018 } 3019 3020 }else 3021 { 3022 3023 if(((value & SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM ) == SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM)) 3024 { 3025 SA_DBG1(("mpiWaitForConfigTable: HDA mode set in SEEPROM SP1 0x%X\n",value)); 3026 } 3027 if(((value & SCRATCH_PAD1_V_READY) != SCRATCH_PAD1_V_READY) || 3028 (value == 0xffffffff)) 3029 { 3030 SA_DBG1(("mpiWaitForConfigTable: Waiting for _V_ FW becoming ready.P1 0x%X P2 0x%X\n",value,value1)); 3031 3032 /* checking the fw and IOP in ready state */ 3033 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec timeout */ 3034 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 3035 /* wait until scratch pad 1 and 2 registers in ready state */ 3036 do 3037 { 3038 ossaStallThread(agRoot, WAIT_INCREMENT); 3039 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); 3040 value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 3041 3042 if ((max_wait_count -= WAIT_INCREMENT) == 0) 3043 { 3044 SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); 3045 return AGSA_RC_FAILURE; 3046 } 3047 } while (((value & SCRATCH_PAD1_V_READY) != SCRATCH_PAD1_V_READY) || 3048 (value == 0xffffffff)); 3049 } 3050 } 3051 3052 3053 SA_DBG1(("mpiWaitForConfigTable: FW Ready, SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1)); 3054 3055 /* read scratch pad0 to get PCI BAR and offset of configuration table */ 3056 MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 3057 /* get offset */ 3058 CfgTblDWIdx = MSGUCfgTblBase & SCRATCH_PAD0_OFFSET_MASK; 3059 /* get PCI BAR */ 3060 MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 3061 3062 if(smIS_SPC(agRoot)) 3063 { 3064 if( smIS_spc8081(agRoot)) 3065 { 3066 if (BAR4 != MSGUCfgTblBase) 3067 { 3068 SA_DBG1(("mpiWaitForConfigTable: smIS_spc8081 PCI BAR is not BAR4, bar=0x%x - failure\n", MSGUCfgTblBase)); 3069 smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "m4"); 3070 return AGSA_RC_FAILURE; 3071 } 3072 } 3073 else 3074 { 3075 if (BAR5 != MSGUCfgTblBase) 3076 { 3077 SA_DBG1(("mpiWaitForConfigTable: PCI BAR is not BAR5, bar=0x%x - failure\n", MSGUCfgTblBase)); 3078 smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "m4"); 3079 return AGSA_RC_FAILURE; 3080 } 3081 } 3082 } 3083 3084 /* convert the PCI BAR to logical bar number */ 3085 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); 3086 3087 /* read signature from the configuration table */ 3088 Signature = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx); 3089 3090 /* Error return if the signature is not "PMCS" */ 3091 ExpSignature = ('P') | ('M' << SHIFT8) | ('C' << SHIFT16) | ('S' << SHIFT24); 3092 3093 if (Signature != ExpSignature) 3094 { 3095 SA_DBG1(("mpiWaitForConfigTable: Signature value = 0x%x\n", Signature)); 3096 smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "m4"); 3097 return AGSA_RC_FAILURE; 3098 } 3099 3100 /* save Signature */ 3101 si_memcpy(&config->Signature, &Signature, sizeof(Signature)); 3102 3103 /* read Interface Revsion from the configuration table */ 3104 config->InterfaceRev = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INTERFACE_REVISION); 3105 3106 /* read FW Revsion from the configuration table */ 3107 config->FWRevision = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FW_REVISION); 3108 3109 /* read Max Outstanding IO from the configuration table */ 3110 config->MaxOutstandingIO = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_OUTSTANDING_IO_OFFSET); 3111 3112 /* read Max SGL and Max Devices from the configuration table */ 3113 config->MDevMaxSGL = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_MAX_SGL_OFFSET); 3114 3115 /* read Controller Cap Flags from the configuration table */ 3116 config->ContrlCapFlag = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_CNTRL_CAP_OFFSET); 3117 3118 /* read GST Table Offset from the configuration table */ 3119 config->GSTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_GST_OFFSET); 3120 3121 /* read Inbound Queue Offset from the configuration table */ 3122 config->inboundQueueOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_IBQ_OFFSET); 3123 3124 /* read Outbound Queue Offset from the configuration table */ 3125 config->outboundQueueOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_OBQ_OFFSET); 3126 3127 3128 if(smIS_SPCV(agRoot)) 3129 { 3130 ;/* SPCV - reserved field */ 3131 } 3132 else 3133 { 3134 /* read HDA Flags from the configuration table */ 3135 config->HDAModeFlags = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_HDA_FLAGS_OFFSET); 3136 } 3137 3138 /* read analog Setting offset from the configuration table */ 3139 config->analogSetupTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ANALOG_SETUP_OFFSET); 3140 3141 if(smIS_SPCV(agRoot)) 3142 { 3143 ;/* SPCV - reserved field */ 3144 /* read interrupt vector table offset */ 3145 config->InterruptVecTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INT_VEC_TABLE_OFFSET); 3146 /* read phy attribute table offset */ 3147 config->phyAttributeTblOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_PHY_ATTRIBUTE_OFFSET); 3148 SA_DBG1(("mpiWaitForConfigTable: INT Vector Tble Offset = 0x%x\n", config->InterruptVecTblOffset)); 3149 SA_DBG1(("mpiWaitForConfigTable: Phy Attribute Tble Offset = 0x%x\n", config->phyAttributeTblOffset)); 3150 } 3151 else 3152 { 3153 ;/* SPC - Not used */ 3154 } 3155 3156 /* read Error Dump Offset and Length */ 3157 config->FatalErrorDumpOffset0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_OFFSET); 3158 config->FatalErrorDumpLength0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP0_LENGTH); 3159 config->FatalErrorDumpOffset1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_OFFSET); 3160 config->FatalErrorDumpLength1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_FATAL_ERROR_RDUMP1_LENGTH); 3161 3162 SA_DBG1(("mpiWaitForConfigTable: Interface Revision value = 0x%08x\n", config->InterfaceRev)); 3163 SA_DBG1(("mpiWaitForConfigTable: FW Revision value = 0x%08x\n", config->FWRevision)); 3164 3165 if(smIS_SPC(agRoot)) 3166 { 3167 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n", STSDK_LL_SPC_VERSION)); 3168 } 3169 if(smIS_SPC6V(agRoot)) 3170 { 3171 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_VERSION )); 3172 } 3173 if(smIS_SPC12V(agRoot)) 3174 { 3175 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_12G_VERSION )); 3176 } 3177 3178 SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO value = 0x%08x\n", config->MaxOutstandingIO)); 3179 SA_DBG1(("mpiWaitForConfigTable: MDevMaxSGL value = 0x%08x\n", config->MDevMaxSGL)); 3180 SA_DBG1(("mpiWaitForConfigTable: ContrlCapFlag value = 0x%08x\n", config->ContrlCapFlag)); 3181 SA_DBG1(("mpiWaitForConfigTable: GSTOffset value = 0x%08x\n", config->GSTOffset)); 3182 SA_DBG1(("mpiWaitForConfigTable: inboundQueueOffset value = 0x%08x\n", config->inboundQueueOffset)); 3183 SA_DBG1(("mpiWaitForConfigTable: outboundQueueOffset value = 0x%08x\n", config->outboundQueueOffset)); 3184 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset0 value = 0x%08x\n", config->FatalErrorDumpOffset0)); 3185 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength0 value = 0x%08x\n", config->FatalErrorDumpLength0)); 3186 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset1 value = 0x%08x\n", config->FatalErrorDumpOffset1)); 3187 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength1 value = 0x%08x\n", config->FatalErrorDumpLength1)); 3188 3189 3190 SA_DBG1(("mpiWaitForConfigTable: HDAModeFlags value = 0x%08x\n", config->HDAModeFlags)); 3191 SA_DBG1(("mpiWaitForConfigTable: analogSetupTblOffset value = 0x%08x\n", config->analogSetupTblOffset)); 3192 3193 /* check interface version */ 3194 3195 if(smIS_SPC6V(agRoot)) 3196 { 3197 if (config->InterfaceRev != STSDK_LL_INTERFACE_VERSION) 3198 { 3199 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); 3200 ret = AGSA_RC_VERSION_UNTESTED; 3201 if ((config->InterfaceRev & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK) != (STSDK_LL_INTERFACE_VERSION & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK)) 3202 { 3203 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); 3204 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3205 smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "m4"); 3206 return ret; 3207 } 3208 } 3209 } 3210 else if(smIS_SPC12V(agRoot)) 3211 { 3212 if (config->InterfaceRev != STSDK_LL_12G_INTERFACE_VERSION) 3213 { 3214 SA_DBG1(("mpiWaitForConfigTable: 12g V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev)); 3215 ret = AGSA_RC_VERSION_UNTESTED; 3216 if ((config->InterfaceRev & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK) != (STSDK_LL_12G_INTERFACE_VERSION & STSDK_LL_INTERFACE_VERSION_IGNORE_MASK)) 3217 { 3218 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev)); 3219 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3220 ret = AGSA_RC_VERSION_UNTESTED; 3221 smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "m4"); 3222 return ret; 3223 } 3224 } 3225 } 3226 else 3227 { 3228 if (config->InterfaceRev != STSDK_LL_OLD_INTERFACE_VERSION) 3229 { 3230 SA_DBG1(("mpiWaitForConfigTable: SPC sTSDK interface ver. 0x%08x not compatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev)); 3231 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3232 smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "m4"); 3233 return ret; 3234 } 3235 3236 } 3237 3238 3239 /* Check FW versions */ 3240 if(smIS_SPC6V(agRoot)) 3241 { 3242 SA_DBG1(("mpiWaitForConfigTable:6 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_VERSION, config->FWRevision)); 3243 /* check FW and LL sTSDK version */ 3244 if (config->FWRevision != MATCHING_V_FW_VERSION ) 3245 { 3246 if (config->FWRevision > MATCHING_V_FW_VERSION) 3247 { 3248 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision)); 3249 ret = AGSA_RC_VERSION_UNTESTED; 3250 } 3251 3252 else if (config->FWRevision < MIN_FW_SPCVE_VERSION_SUPPORTED) 3253 { 3254 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision)); 3255 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3256 smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "m4"); 3257 return ret; 3258 } 3259 else 3260 { 3261 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_VERSION , config->FWRevision)); 3262 ret = AGSA_RC_VERSION_UNTESTED; 3263 } 3264 } 3265 }else if(smIS_SPC12V(agRoot)) 3266 { 3267 SA_DBG1(("mpiWaitForConfigTable:12 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_12G_VERSION, config->FWRevision)); 3268 /* check FW and LL sTSDK version */ 3269 if (config->FWRevision != MATCHING_12G_V_FW_VERSION ) 3270 { 3271 if (config->FWRevision > MATCHING_12G_V_FW_VERSION) 3272 { 3273 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision)); 3274 ret = AGSA_RC_VERSION_UNTESTED; 3275 } 3276 3277 else if (config->FWRevision < MIN_FW_12G_SPCVE_VERSION_SUPPORTED) 3278 { 3279 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision)); 3280 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3281 smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "m4"); 3282 return ret; 3283 } 3284 else 3285 { 3286 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_12G_VERSION , config->FWRevision)); 3287 ret = AGSA_RC_VERSION_UNTESTED; 3288 } 3289 } 3290 } 3291 else 3292 { 3293 if (config->FWRevision != MATCHING_SPC_FW_VERSION ) 3294 { 3295 if (config->FWRevision > MATCHING_SPC_FW_VERSION) 3296 { 3297 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision)); 3298 ret = AGSA_RC_VERSION_UNTESTED; 3299 } 3300 else if (config->FWRevision < MIN_FW_SPC_VERSION_SUPPORTED) 3301 { 3302 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision)); 3303 ret = AGSA_RC_VERSION_INCOMPATIBLE; 3304 smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "m4"); 3305 return ret; 3306 } 3307 else 3308 { 3309 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_SPC_VERSION , config->FWRevision)); 3310 ret = AGSA_RC_VERSION_UNTESTED; 3311 } 3312 } 3313 } 3314 SA_DBG1(("mpiWaitForConfigTable: ILA version 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN) )); 3315 3316 3317 if(smIS_SPC12V(agRoot)) 3318 { 3319 if (config->InterfaceRev > 0x301 ) 3320 { 3321 SA_DBG1(("mpiWaitForConfigTable: MAIN_INACTIVE_ILA_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INACTIVE_ILA_REVSION) )); 3322 SA_DBG1(("mpiWaitForConfigTable: MAIN_SEEPROM_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_SEEPROM_REVSION) )); 3323 } 3324 } 3325 3326 if(smIS_SPC12V(agRoot)) 3327 { 3328 if (config->InterfaceRev > 0x301 ) 3329 { 3330 SA_DBG1(("mpiWaitForConfigTable: MAIN_AWT_MIDRANGE 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_AWT_MIDRANGE) )); 3331 } 3332 } 3333 3334 3335 if(smIS_SFC(agRoot)) 3336 { 3337 /* always success for SFC*/ 3338 ret = AGSA_RC_SUCCESS; 3339 } 3340 3341 if (agNULL != saRoot) 3342 { 3343 /* save the information */ 3344 saRoot->ControllerInfo.signature = Signature; 3345 saRoot->ControllerInfo.fwInterfaceRev = config->InterfaceRev; 3346 3347 if(smIS_SPCV(agRoot)) 3348 { 3349 saRoot->ControllerInfo.hwRevision = (ossaHwRegReadConfig32(agRoot,8) & 0xFF); 3350 SA_DBG1(("mpiWaitForConfigTable: hwRevision 0x%x\n",saRoot->ControllerInfo.hwRevision )); 3351 } 3352 else 3353 { 3354 saRoot->ControllerInfo.hwRevision = SPC_READ_DEV_REV; 3355 } 3356 3357 saRoot->ControllerInfo.fwRevision = config->FWRevision; 3358 saRoot->ControllerInfo.ilaRevision = config->ilaRevision; 3359 saRoot->ControllerInfo.maxPendingIO = config->MaxOutstandingIO; 3360 saRoot->ControllerInfo.maxSgElements = config->MDevMaxSGL & 0xFFFF; 3361 saRoot->ControllerInfo.maxDevices = (config->MDevMaxSGL & MAX_DEV_BITS) >> SHIFT16; 3362 saRoot->ControllerInfo.queueSupport = config->ContrlCapFlag & Q_SUPPORT_BITS; 3363 saRoot->ControllerInfo.phyCount = (bit8)((config->ContrlCapFlag & PHY_COUNT_BITS) >> SHIFT19); 3364 saRoot->ControllerInfo.sasSpecsSupport = (config->ContrlCapFlag & SAS_SPEC_BITS) >> SHIFT25; 3365 SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", config->MaxOutstandingIO,saRoot->swConfig.maxActiveIOs )); 3366 3367 if(smIS_SPCV(agRoot)) 3368 { 3369 ;/* SPCV - reserved field */ 3370 } 3371 else 3372 { 3373 saRoot->ControllerInfo.controllerSetting = (bit8)config->HDAModeFlags; 3374 } 3375 3376 saRoot->ControllerInfo.sdkInterfaceRev = STSDK_LL_INTERFACE_VERSION; 3377 saRoot->ControllerInfo.sdkRevision = STSDK_LL_VERSION; 3378 saRoot->mainConfigTable.regDumpPCIBAR = pcibar; 3379 saRoot->mainConfigTable.FatalErrorDumpOffset0 = config->FatalErrorDumpOffset0; 3380 saRoot->mainConfigTable.FatalErrorDumpLength0 = config->FatalErrorDumpLength0; 3381 saRoot->mainConfigTable.FatalErrorDumpOffset1 = config->FatalErrorDumpOffset1; 3382 saRoot->mainConfigTable.FatalErrorDumpLength1 = config->FatalErrorDumpLength1; 3383 3384 if(smIS_SPCV(agRoot)) 3385 { 3386 ;/* SPCV - reserved field */ 3387 } 3388 else 3389 { 3390 saRoot->mainConfigTable.HDAModeFlags = config->HDAModeFlags; 3391 } 3392 3393 saRoot->mainConfigTable.analogSetupTblOffset = config->analogSetupTblOffset; 3394 3395 if(smIS_SPCV(agRoot)) 3396 { 3397 saRoot->mainConfigTable.InterruptVecTblOffset = config->InterruptVecTblOffset; 3398 saRoot->mainConfigTable.phyAttributeTblOffset = config->phyAttributeTblOffset; 3399 saRoot->mainConfigTable.PortRecoveryTimerPortResetTimer = config->portRecoveryResetTimer; 3400 } 3401 3402 SA_DBG1(("mpiWaitForConfigTable: Signature = 0x%x\n", Signature)); 3403 SA_DBG1(("mpiWaitForConfigTable: hwRevision = 0x%x\n", saRoot->ControllerInfo.hwRevision)); 3404 SA_DBG1(("mpiWaitForConfigTable: FW Revision = 0x%x\n", config->FWRevision)); 3405 SA_DBG1(("mpiWaitForConfigTable: Max Sgl = 0x%x\n", saRoot->ControllerInfo.maxSgElements)); 3406 SA_DBG1(("mpiWaitForConfigTable: Max Device = 0x%x\n", saRoot->ControllerInfo.maxDevices)); 3407 SA_DBG1(("mpiWaitForConfigTable: Queue Support = 0x%x\n", saRoot->ControllerInfo.queueSupport)); 3408 SA_DBG1(("mpiWaitForConfigTable: Phy Count = 0x%x\n", saRoot->ControllerInfo.phyCount)); 3409 SA_DBG1(("mpiWaitForConfigTable: sas Specs Support = 0x%x\n", saRoot->ControllerInfo.sasSpecsSupport)); 3410 3411 } 3412 3413 3414 if(ret != AGSA_RC_SUCCESS ) 3415 { 3416 SA_DBG1(("mpiWaitForConfigTable: return 0x%x not AGSA_RC_SUCCESS warning!\n", ret)); 3417 } 3418 3419 3420 smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "m4"); 3421 return ret; 3422} 3423 3424/*******************************************************************************/ 3425/** \fn mpiUnInitConfigTable(agsaRoot_t *agRoot, spc_configMainDescriptor_t *config) 3426 * \brief UnInitialization Configuration Table 3427 * \param agsaRoot Pointer to a data structure containing LL layer context handles 3428 * 3429 * Return: 3430 * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful 3431 * AGSA_RC_FAILURE if Un-initialize the configuration table failed 3432 */ 3433/*******************************************************************************/ 3434GLOBAL bit32 mpiUnInitConfigTable(agsaRoot_t *agRoot) 3435{ 3436 bit32 MSGUCfgTblBase; 3437 bit32 CfgTblDWIdx, GSTOffset, GSTLenMPIS; 3438 bit32 value, togglevalue; 3439 bit32 max_wait_time; 3440 bit32 max_wait_count; 3441 bit8 pcibar; 3442 3443 smTraceFuncEnter(hpDBG_VERY_LOUD,"m7"); 3444 SA_DBG1(("mpiUnInitConfigTable: agRoot %p\n",agRoot)); 3445 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 3446 3447 togglevalue = 0; 3448 3449 /* read scratch pad0 to get PCI BAR and offset of configuration table */ 3450 MSGUCfgTblBase =siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 3451 3452 if(MSGUCfgTblBase == 0xFFFFFFFF) 3453 { 3454 SA_DBG1(("mpiUnInitConfigTable: MSGUCfgTblBase = 0x%x AGSA_RC_FAILURE\n",MSGUCfgTblBase)); 3455 return AGSA_RC_FAILURE; 3456 } 3457 3458 /* get offset */ 3459 CfgTblDWIdx = MSGUCfgTblBase & SCRATCH_PAD0_OFFSET_MASK; 3460 /* get PCI BAR */ 3461 MSGUCfgTblBase = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 3462 3463 /* convert the PCI BAR to logical bar number */ 3464 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, MSGUCfgTblBase); 3465 3466 /* Write bit 1 to Inbound DoorBell Register */ 3467 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 3468 3469 /* wait until Inbound DoorBell Clear Register toggled */ 3470 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 3471 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 3472 do 3473 { 3474 ossaStallThread(agRoot, WAIT_INCREMENT); 3475 value = MSGU_READ_IDR; 3476 value &= SPC_MSGU_CFG_TABLE_RESET; 3477 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 3478 3479 if (!max_wait_count) 3480 { 3481 SA_DBG1(("mpiUnInitConfigTable: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 3482 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m7"); 3483 3484 if(smIS_SPC(agRoot) ) 3485 { 3486 return AGSA_RC_FAILURE; 3487 } 3488 3489 } 3490 3491 /* check the MPI-State for termination in progress */ 3492 /* wait until Inbound DoorBell Clear Register toggled */ 3493 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 3494 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 3495 GSTOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_GST_OFFSET); 3496 do 3497 { 3498 ossaStallThread(agRoot, WAIT_INCREMENT); 3499 3500 if(GSTOffset == 0xFFFFFFFF) 3501 { 3502 SA_DBG1(("mpiUnInitConfigTable:AGSA_RC_FAILURE GSTOffset = 0x%x\n",GSTOffset)); 3503 return AGSA_RC_FAILURE; 3504 } 3505 3506 GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + (bit32)(GSTOffset + GST_GSTLEN_MPIS_OFFSET)); 3507 if (GST_MPI_STATE_UNINIT == (GSTLenMPIS & GST_MPI_STATE_MASK)) 3508 { 3509 break; 3510 } 3511 } while (max_wait_count -= WAIT_INCREMENT); 3512 3513 if (!max_wait_count) 3514 { 3515 SA_DBG1(("mpiUnInitConfigTable: TIMEOUT, MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK)); 3516#if defined(SALLSDK_DEBUG) 3517 3518 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0))); 3519 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 3520 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2))); 3521 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3))); 3522#endif 3523 3524 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "m7"); 3525 return AGSA_RC_FAILURE; 3526 } 3527 3528 smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "m7"); 3529 return AGSA_RC_SUCCESS; 3530} 3531 3532/*******************************************************************************/ 3533/** \fn void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, spc_inboundQueueDescriptor_t *outQueueCfg, 3534 * bit32 QueueTableOffset,bit8 pcibar) 3535 * \brief Writing to the inbound queue of the Configuration Table 3536 * \param agsaRoot Pointer to a data structure containing both application and LL layer context handles 3537 * \param outQueueCfg Pointer to inbuond configuration area 3538 * \param QueueTableOffset Queue configuration table offset 3539 * \param pcibar PCI BAR 3540 * 3541 * Return: 3542 * None 3543 */ 3544/*******************************************************************************/ 3545GLOBAL void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, 3546 spc_inboundQueueDescriptor_t *inQueueCfg, 3547 bit32 QueueTableOffset, 3548 bit8 pcibar) 3549{ 3550 smTraceFuncEnter(hpDBG_VERY_LOUD,"m5"); 3551 3552 smTrace(hpDBG_VERY_LOUD,"Ba",QueueTableOffset); 3553 /* TP:Ba QueueTableOffset */ 3554 smTrace(hpDBG_VERY_LOUD,"Bb",pcibar); 3555 /* TP:Bb pcibar */ 3556 3557 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_PROPERITY_OFFSET), inQueueCfg->elementPriSizeCount); 3558 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_BASE_ADDR_HI_OFFSET), inQueueCfg->upperBaseAddress); 3559 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_BASE_ADDR_LO_OFFSET), inQueueCfg->lowerBaseAddress); 3560 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_CI_BASE_ADDR_HI_OFFSET), inQueueCfg->ciUpperBaseAddress); 3561 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + IB_CI_BASE_ADDR_LO_OFFSET), inQueueCfg->ciLowerBaseAddress); 3562 3563 3564 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x elementPriSizeCount 0x%x\n",(bit32)(QueueTableOffset + IB_PROPERITY_OFFSET), inQueueCfg->elementPriSizeCount)); 3565 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x upperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_BASE_ADDR_HI_OFFSET), inQueueCfg->upperBaseAddress)); 3566 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x lowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_BASE_ADDR_LO_OFFSET), inQueueCfg->lowerBaseAddress)); 3567 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x ciUpperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_CI_BASE_ADDR_HI_OFFSET), inQueueCfg->ciUpperBaseAddress)); 3568 SA_DBG3(("mpiUpdateIBQueueCfgTable: Offset 0x%08x ciLowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + IB_CI_BASE_ADDR_LO_OFFSET), inQueueCfg->ciLowerBaseAddress)); 3569 3570 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m5"); 3571} 3572 3573/*******************************************************************************/ 3574/** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg, 3575 * bit32 QueueTableOffset,bit8 pcibar) 3576 * \brief Writing to the inbound queue of the Configuration Table 3577 * \param agsaRoot Pointer to a data structure containing both application 3578 * and LL layer context handles 3579 * \param outQueueCfg Pointer to outbuond configuration area 3580 * \param QueueTableOffset Queue configuration table offset 3581 * \param pcibar PCI BAR 3582 * 3583 * Return: 3584 * None 3585 */ 3586/*******************************************************************************/ 3587GLOBAL void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, 3588 spc_outboundQueueDescriptor_t *outQueueCfg, 3589 bit32 QueueTableOffset, 3590 bit8 pcibar) 3591{ 3592 3593 smTraceFuncEnter(hpDBG_VERY_LOUD,"m8"); 3594 3595 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount); 3596 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress); 3597 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress); 3598 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress); 3599 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress); 3600 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay); 3601 3602 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x elementSizeCount 0x%x\n",(bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount)); 3603 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x upperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress)); 3604 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x lowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress)); 3605 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piUpperBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress)); 3606 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piLowerBaseAddress 0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress)); 3607 SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x interruptVecCntDelay 0x%x\n",(bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay)); 3608 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m8"); 3609} 3610 3611 3612 3613/*******************************************************************************/ 3614/** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg, 3615 * bit32 QueueTableOffset,bit8 pcibar) 3616 * \brief Writing to the inbound queue of the Configuration Table 3617 * \param agsaRoot Pointer to a data structure containing both application 3618 * and LL layer context handles 3619 * \param outQueueCfg Pointer to outbuond configuration area 3620 * \param QueueTableOffset Queue configuration table offset 3621 * \param pcibar PCI BAR 3622 * 3623 * Return: 3624 * None 3625 */ 3626/*******************************************************************************/ 3627GLOBAL void mpiUpdateFatalErrorTable(agsaRoot_t *agRoot, 3628 bit32 FerrTableOffset, 3629 bit32 lowerBaseAddress, 3630 bit32 upperBaseAddress, 3631 bit32 length, 3632 bit8 pcibar) 3633{ 3634 3635 smTraceFuncEnter(hpDBG_VERY_LOUD,"2U"); 3636 3637 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LO_OFFSET), lowerBaseAddress); 3638 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HI_OFFSET), upperBaseAddress); 3639 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LENGTH), length); 3640 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HANDSHAKE), 0); 3641 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(FerrTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS), 0); 3642 3643 3644 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LO_OFFSET, lowerBaseAddress)); 3645 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HI_OFFSET,upperBaseAddress )); 3646 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_LENGTH 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_LENGTH, length)); 3647 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_HANDSHAKE,0 )); 3648 SA_DBG3(("mpiUpdateFatalErrorTable: Offset 0x%08x MPI_FATAL_EDUMP_TABLE_STATUS 0x%x\n",FerrTableOffset + MPI_FATAL_EDUMP_TABLE_STATUS,0 )); 3649 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2U"); 3650} 3651 3652 3653/*******************************************************************************/ 3654/** \fn bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot, pciBar) 3655 * \brief Get PCI BAR Index from PCI BAR 3656 * \param agsaRoot Pointer to a data structure containing both application and LL layer context handles 3657 * \param pciBar - PCI BAR 3658 * 3659 * Return: 3660 * PCI BAR Index 3661 */ 3662/*******************************************************************************/ 3663GLOBAL bit32 mpiGetPCIBarIndex(agsaRoot_t *agRoot, bit32 pciBar) 3664{ 3665 switch(pciBar) 3666 { 3667 case BAR0: 3668 case BAR1: 3669 pciBar = PCIBAR0; 3670 break; 3671 case BAR2: 3672 case BAR3: 3673 pciBar = PCIBAR1; 3674 break; 3675 case BAR4: 3676 pciBar = PCIBAR2; 3677 break; 3678 case BAR5: 3679 pciBar = PCIBAR3; 3680 break; 3681 default: 3682 pciBar = PCIBAR0; 3683 break; 3684 } 3685 3686 return pciBar; 3687} 3688 3689/*******************************************************************************/ 3690/** \fn void mpiReadGSTTable(agsaRoot_t *agRoot, spc_GSTableDescriptor_t *mpiGSTable) 3691 * \brief Reading the General Status Table 3692 * 3693 * \param agsaRoot Handles for this instance of SAS/SATA LLL 3694 * \param mpiGSTable Pointer of General Status Table 3695 * 3696 * Return: 3697 * None 3698 */ 3699/*******************************************************************************/ 3700GLOBAL void mpiReadGSTable(agsaRoot_t *agRoot, 3701 spc_GSTableDescriptor_t *mpiGSTable) 3702{ 3703 bit32 CFGTableOffset, TableOffset; 3704 bit32 GSTableOffset; 3705 bit8 i, pcibar; 3706 3707 smTraceFuncEnter(hpDBG_VERY_LOUD,"m9"); 3708 3709 /* get offset of the configuration table */ 3710 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 3711 3712 if(0xFFFFFFFF == TableOffset) 3713 { 3714 SA_ASSERT(0xFFFFFFFF == TableOffset, "Chip PCI dead"); 3715 3716 SA_DBG1(("mpiReadGSTable: Chip PCI dead TableOffset 0x%x\n", TableOffset)); 3717 return; 3718 } 3719 3720// SA_DBG1(("mpiReadGSTable: TableOffset 0x%x\n", TableOffset)); 3721 CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; 3722 3723 /* get PCI BAR */ 3724 TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 3725 /* convert the PCI BAR to logical bar number */ 3726 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); 3727 3728 /* read GST Table Offset from the configuration table */ 3729 GSTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_GST_OFFSET); 3730// SA_DBG1(("mpiReadGSTable: GSTableOffset 0x%x\n",GSTableOffset )); 3731 3732 GSTableOffset = CFGTableOffset + GSTableOffset; 3733 3734 mpiGSTable->GSTLenMPIS = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_GSTLEN_MPIS_OFFSET)); 3735 mpiGSTable->IQFreezeState0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IQ_FREEZE_STATE0_OFFSET)); 3736 mpiGSTable->IQFreezeState1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IQ_FREEZE_STATE1_OFFSET)); 3737 mpiGSTable->MsguTcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_MSGUTCNT_OFFSET)); 3738 mpiGSTable->IopTcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IOPTCNT_OFFSET)); 3739 mpiGSTable->Iop1Tcnt = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_IOP1TCNT_OFFSET)); 3740 3741 SA_DBG4(("mpiReadGSTable: GSTLenMPIS 0x%x\n", mpiGSTable->GSTLenMPIS)); 3742 SA_DBG4(("mpiReadGSTable: GSTLen 0x%x\n", (mpiGSTable->GSTLenMPIS & 0xfff8) >> SHIFT3)); 3743 SA_DBG4(("mpiReadGSTable: IQFreezeState0 0x%x\n", mpiGSTable->IQFreezeState0)); 3744 SA_DBG4(("mpiReadGSTable: IQFreezeState1 0x%x\n", mpiGSTable->IQFreezeState1)); 3745 SA_DBG4(("mpiReadGSTable: MsguTcnt 0x%x\n", mpiGSTable->MsguTcnt)); 3746 SA_DBG4(("mpiReadGSTable: IopTcnt 0x%x\n", mpiGSTable->IopTcnt)); 3747 SA_DBG4(("mpiReadGSTable: Iop1Tcnt 0x%x\n", mpiGSTable->Iop1Tcnt)); 3748 3749 3750 if(smIS_SPCV(agRoot)) 3751 { 3752 /***** read Phy State from SAS Phy Attribute Table */ 3753 TableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_PHY_ATTRIBUTE_OFFSET); 3754 TableOffset &= 0x00FFFFFF; 3755 TableOffset = TableOffset + CFGTableOffset; 3756 for (i = 0; i < 8; i++) 3757 { 3758 mpiGSTable->PhyState[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(TableOffset + i * sizeof(phyAttrb_t))); 3759 SA_DBG4(("mpiReadGSTable: PhyState[0x%x] 0x%x\n", i, mpiGSTable->PhyState[i])); 3760 } 3761 } 3762 else 3763 { 3764 for (i = 0; i < 8; i++) 3765 { 3766 mpiGSTable->PhyState[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_PHYSTATE_OFFSET + i * 4)); 3767 SA_DBG4(("mpiReadGSTable: PhyState[0x%x] 0x%x\n", i, mpiGSTable->PhyState[i])); 3768 } 3769 } 3770 3771 mpiGSTable->GPIOpins = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_GPIO_PINS_OFFSET)); 3772 SA_DBG4(("mpiReadGSTable: GPIOpins 0x%x\n", mpiGSTable->GPIOpins)); 3773 3774 for (i = 0; i < 8; i++) 3775 { 3776 mpiGSTable->recoverErrInfo[i] = ossaHwRegReadExt(agRoot, pcibar, (bit32)(GSTableOffset + GST_RERRINFO_OFFSET)); 3777 SA_DBG4(("mpiReadGSTable: recoverErrInfo[0x%x] 0x%x\n", i, mpiGSTable->recoverErrInfo[i])); 3778 } 3779 3780 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m9"); 3781 3782} 3783 3784/*******************************************************************************/ 3785/** \fn void siInitResources(agsaRoot_t *agRoot) 3786 * Initialization of LL resources 3787 * 3788 * \param agsaRoot Handles for this instance of SAS/SATA LLL 3789 * \param memoryAllocated Point to the data structure that holds the different 3790 * chunks of memory that are required 3791 * 3792 * Return: 3793 * None 3794 */ 3795/*******************************************************************************/ 3796GLOBAL void siInitResources(agsaRoot_t *agRoot, 3797 agsaMemoryRequirement_t *memoryAllocated, 3798 agsaHwConfig_t *hwConfig, 3799 agsaSwConfig_t *swConfig, 3800 bit32 usecsPerTick) 3801{ 3802 agsaLLRoot_t *saRoot; 3803 agsaDeviceDesc_t *pDeviceDesc; 3804 agsaIORequestDesc_t *pRequestDesc; 3805 agsaTimerDesc_t *pTimerDesc; 3806 agsaPort_t *pPort; 3807 agsaPortMap_t *pPortMap; 3808 agsaDeviceMap_t *pDeviceMap; 3809 agsaIOMap_t *pIOMap; 3810 bit32 maxNumIODevices; 3811 bit32 i, j; 3812 mpiICQueue_t *circularIQ; 3813 mpiOCQueue_t *circularOQ; 3814 3815 if (agNULL == agRoot) 3816 { 3817 return; 3818 } 3819 3820 /* Get the saRoot memory address */ 3821 saRoot = (agsaLLRoot_t *) (memoryAllocated->agMemory[LLROOT_MEM_INDEX].virtPtr); 3822 agRoot->sdkData = (void *) saRoot; 3823 3824 /* Setup Device link */ 3825 /* Save the information of allocated device Link memory */ 3826 saRoot->deviceLinkMem = memoryAllocated->agMemory[DEVICELINK_MEM_INDEX]; 3827 si_memset(saRoot->deviceLinkMem.virtPtr, 0, saRoot->deviceLinkMem.totalLength); 3828 SA_DBG2(("siInitResources: [%d] saRoot->deviceLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n" , 3829 DEVICELINK_MEM_INDEX, 3830 saRoot->deviceLinkMem.virtPtr, 3831 saRoot->deviceLinkMem.phyAddrLower, 3832 saRoot->deviceLinkMem.numElements, 3833 saRoot->deviceLinkMem.totalLength, 3834 saRoot->deviceLinkMem.type)); 3835 3836 maxNumIODevices = swConfig->numDevHandles; 3837 SA_DBG2(("siInitResources: maxNumIODevices=%d, swConfig->numDevHandles=%d \n", 3838 maxNumIODevices, 3839 swConfig->numDevHandles)); 3840 3841 /* Setup free IO Devices link list */ 3842 saLlistInitialize(&(saRoot->freeDevicesList)); 3843 for ( i = 0; i < (bit32) maxNumIODevices; i ++ ) 3844 { 3845 /* get the pointer to the device descriptor */ 3846 pDeviceDesc = (agsaDeviceDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->deviceLinkMem), i); 3847 /* Initialize device descriptor */ 3848 saLlinkInitialize(&(pDeviceDesc->linkNode)); 3849 3850 pDeviceDesc->initiatorDevHandle.osData = agNULL; 3851 pDeviceDesc->initiatorDevHandle.sdkData = agNULL; 3852 pDeviceDesc->targetDevHandle.osData = agNULL; 3853 pDeviceDesc->targetDevHandle.sdkData = agNULL; 3854 pDeviceDesc->deviceType = SAS_SATA_UNKNOWN_DEVICE; 3855 pDeviceDesc->pPort = agNULL; 3856 pDeviceDesc->DeviceMapIndex = 0; 3857 3858 saLlistInitialize(&(pDeviceDesc->pendingIORequests)); 3859 3860 /* Add the device descriptor to the free IO device link list */ 3861 saLlistAdd(&(saRoot->freeDevicesList), &(pDeviceDesc->linkNode)); 3862 } 3863 3864 /* Setup IO Request link */ 3865 /* Save the information of allocated IO Request Link memory */ 3866 saRoot->IORequestMem = memoryAllocated->agMemory[IOREQLINK_MEM_INDEX]; 3867 si_memset(saRoot->IORequestMem.virtPtr, 0, saRoot->IORequestMem.totalLength); 3868 3869 SA_DBG2(("siInitResources: [%d] saRoot->IORequestMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 3870 IOREQLINK_MEM_INDEX, 3871 saRoot->IORequestMem.virtPtr, 3872 saRoot->IORequestMem.phyAddrLower, 3873 saRoot->IORequestMem.numElements, 3874 saRoot->IORequestMem.totalLength, 3875 saRoot->IORequestMem.type)); 3876 3877 /* Setup free IO Request link list */ 3878 saLlistIOInitialize(&(saRoot->freeIORequests)); 3879 saLlistIOInitialize(&(saRoot->freeReservedRequests)); 3880 for ( i = 0; i < swConfig->maxActiveIOs; i ++ ) 3881 { 3882 /* get the pointer to the request descriptor */ 3883 pRequestDesc = (agsaIORequestDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->IORequestMem), i); 3884 /* Initialize request descriptor */ 3885 saLlinkIOInitialize(&(pRequestDesc->linkNode)); 3886 3887 pRequestDesc->valid = agFALSE; 3888 pRequestDesc->requestType = AGSA_REQ_TYPE_UNKNOWN; 3889 pRequestDesc->pIORequestContext = agNULL; 3890 pRequestDesc->HTag = i; 3891 pRequestDesc->pDevice = agNULL; 3892 pRequestDesc->pPort = agNULL; 3893 3894 /* Add the request descriptor to the free IO Request link list */ 3895 /* Add the request descriptor to the free Reserved Request link list */ 3896 /* SMP request must get service so reserve one request when first SMP completes */ 3897 if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 3898 { 3899 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequestDesc->linkNode)); 3900 } 3901 else 3902 { 3903 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequestDesc->linkNode)); 3904 } 3905 } 3906 3907 3908 /* Setup timer link */ 3909 /* Save the information of allocated timer Link memory */ 3910 saRoot->timerLinkMem = memoryAllocated->agMemory[TIMERLINK_MEM_INDEX]; 3911 si_memset(saRoot->timerLinkMem.virtPtr, 0, saRoot->timerLinkMem.totalLength); 3912 SA_DBG2(("siInitResources: [%d] saRoot->timerLinkMem VirtPtr=%p PhysicalLo=%x Count=%x Total=%x type %x\n", 3913 TIMERLINK_MEM_INDEX, 3914 saRoot->timerLinkMem.virtPtr, 3915 saRoot->timerLinkMem.phyAddrLower, 3916 saRoot->timerLinkMem.numElements, 3917 saRoot->timerLinkMem.totalLength, 3918 saRoot->timerLinkMem.type)); 3919 3920 /* Setup free timer link list */ 3921 saLlistInitialize(&(saRoot->freeTimers)); 3922 for ( i = 0; i < NUM_TIMERS; i ++ ) 3923 { 3924 /* get the pointer to the timer descriptor */ 3925 pTimerDesc = (agsaTimerDesc_t *) AGSAMEM_ELEMENT_READ(&(saRoot->timerLinkMem), i); 3926 /* Initialize timer descriptor */ 3927 saLlinkInitialize(&(pTimerDesc->linkNode)); 3928 3929 pTimerDesc->valid = agFALSE; 3930 pTimerDesc->timeoutTick = 0; 3931 pTimerDesc->pfnTimeout = agNULL; 3932 pTimerDesc->Event = 0; 3933 pTimerDesc->pParm = agNULL; 3934 3935 /* Add the timer descriptor to the free timer link list */ 3936 saLlistAdd(&(saRoot->freeTimers), &(pTimerDesc->linkNode)); 3937 } 3938 /* Setup valid timer link list */ 3939 saLlistInitialize(&(saRoot->validTimers)); 3940 3941 /* Setup Phys */ 3942 /* Setup PhyCount */ 3943 saRoot->phyCount = (bit8) hwConfig->phyCount; 3944 /* Init Phy data structure */ 3945 for ( i = 0; i < saRoot->phyCount; i ++ ) 3946 { 3947 saRoot->phys[i].pPort = agNULL; 3948 saRoot->phys[i].phyId = (bit8) i; 3949 3950 /* setup phy status is PHY_STOPPED */ 3951 PHY_STATUS_SET(&(saRoot->phys[i]), PHY_STOPPED); 3952 } 3953 3954 /* Setup Ports */ 3955 /* Setup PortCount */ 3956 saRoot->portCount = saRoot->phyCount; 3957 /* Setup free port link list */ 3958 saLlistInitialize(&(saRoot->freePorts)); 3959 for ( i = 0; i < saRoot->portCount; i ++ ) 3960 { 3961 /* get the pointer to the port */ 3962 pPort = &(saRoot->ports[i]); 3963 /* Initialize port */ 3964 saLlinkInitialize(&(pPort->linkNode)); 3965 3966 pPort->portContext.osData = agNULL; 3967 pPort->portContext.sdkData = pPort; 3968 pPort->portId = 0; 3969 pPort->portIdx = (bit8) i; 3970 pPort->status = PORT_NORMAL; 3971 3972 for ( j = 0; j < saRoot->phyCount; j ++ ) 3973 { 3974 pPort->phyMap[j] = agFALSE; 3975 } 3976 3977 saLlistInitialize(&(pPort->listSASATADevices)); 3978 3979 /* Add the port to the free port link list */ 3980 saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode)); 3981 } 3982 /* Setup valid port link list */ 3983 saLlistInitialize(&(saRoot->validPorts)); 3984 3985 /* Init sysIntsActive */ 3986 saRoot->sysIntsActive = agFALSE; 3987 3988 /* setup timer tick granunarity */ 3989 saRoot->usecsPerTick = usecsPerTick; 3990 3991 /* initialize LL timer tick */ 3992 saRoot->timeTick = 0; 3993 3994 /* initialize device (de)registration callback fns */ 3995 saRoot->DeviceRegistrationCB = agNULL; 3996 saRoot->DeviceDeregistrationCB = agNULL; 3997 3998 /* Initialize the PortMap for port context */ 3999 for ( i = 0; i < saRoot->portCount; i ++ ) 4000 { 4001 pPortMap = &(saRoot->PortMap[i]); 4002 4003 pPortMap->PortContext = agNULL; 4004 pPortMap->PortID = PORT_MARK_OFF; 4005 pPortMap->PortStatus = PORT_NORMAL; 4006 saRoot->autoDeregDeviceflag[i] = 0; 4007 } 4008 4009 /* Initialize the DeviceMap for device handle */ 4010 for ( i = 0; i < MAX_IO_DEVICE_ENTRIES; i ++ ) 4011 { 4012 pDeviceMap = &(saRoot->DeviceMap[i]); 4013 4014 pDeviceMap->DeviceHandle = agNULL; 4015 pDeviceMap->DeviceIdFromFW = i; 4016 } 4017 4018 /* Initialize the IOMap for IOrequest */ 4019 for ( i = 0; i < MAX_ACTIVE_IO_REQUESTS; i ++ ) 4020 { 4021 pIOMap = &(saRoot->IOMap[i]); 4022 4023 pIOMap->IORequest = agNULL; 4024 pIOMap->Tag = MARK_OFF; 4025 } 4026 4027 /* clean the inbound queues */ 4028 for (i = 0; i < saRoot->QueueConfig.numInboundQueues; i ++) 4029 { 4030 if(0 != saRoot->inboundQueue[i].numElements) 4031 { 4032 circularIQ = &saRoot->inboundQueue[i]; 4033 si_memset(circularIQ->memoryRegion.virtPtr, 0, circularIQ->memoryRegion.totalLength); 4034 si_memset(saRoot->inboundQueue[i].ciPointer, 0, sizeof(bit32)); 4035 } 4036 } 4037 /* clean the outbound queues */ 4038 for (i = 0; i < saRoot->QueueConfig.numOutboundQueues; i ++) 4039 { 4040 if(0 != saRoot->outboundQueue[i].numElements) 4041 { 4042 circularOQ = &saRoot->outboundQueue[i]; 4043 si_memset(circularOQ->memoryRegion.virtPtr, 0, circularOQ->memoryRegion.totalLength); 4044 si_memset(saRoot->outboundQueue[i].piPointer, 0, sizeof(bit32)); 4045 circularOQ->producerIdx = 0; 4046 circularOQ->consumerIdx = 0; 4047 SA_DBG3(("siInitResource: Q %d Clean PI 0x%03x CI 0x%03x\n", i,circularOQ->producerIdx, circularOQ->consumerIdx)); 4048 } 4049 } 4050 4051 return; 4052} 4053 4054/*******************************************************************************/ 4055/** \fn void mpiReadCALTable(agsaRoot_t *agRoot, 4056 * spc_SPASTable_t *mpiCALTable, bit32 index) 4057 * \brief Reading the Phy Analog Setup Register Table 4058 * \param agsaRoot Handles for this instance of SAS/SATA LLL 4059 * \param mpiCALTable Pointer of Phy Calibration Table 4060 * 4061 * Return: 4062 * None 4063 */ 4064/*******************************************************************************/ 4065GLOBAL void mpiReadCALTable(agsaRoot_t *agRoot, 4066 spc_SPASTable_t *mpiCALTable, 4067 bit32 index) 4068{ 4069 bit32 CFGTableOffset, TableOffset; 4070 bit32 CALTableOffset; 4071 bit8 pcibar; 4072 4073 /* get offset of the configuration table */ 4074 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4075 4076 CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; 4077 4078 /* get PCI BAR */ 4079 TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4080 /* convert the PCI BAR to logical bar number */ 4081 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); 4082 4083 /* read Calibration Table Offset from the configuration table */ 4084 CALTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); 4085 if(smIS_SPCV(agRoot)) 4086 { 4087 CALTableOffset &= 0x00FFFFFF; 4088 } 4089 CALTableOffset = CFGTableOffset + CALTableOffset + (index * ANALOG_SETUP_ENTRY_SIZE * 4); 4090 4091 mpiCALTable->spaReg0 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET)); 4092 mpiCALTable->spaReg1 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG2_OFFSET)); 4093 mpiCALTable->spaReg2 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG3_OFFSET)); 4094 mpiCALTable->spaReg3 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_CFG_OFFSET)); 4095 mpiCALTable->spaReg4 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET)); 4096 mpiCALTable->spaReg5 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG2_OFFSET)); 4097 mpiCALTable->spaReg6 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG1_OFFSET)); 4098 mpiCALTable->spaReg7 = ossaHwRegReadExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG2_OFFSET)); 4099 4100 SA_DBG3(("mpiReadCALTable: spaReg0 0x%x\n", mpiCALTable->spaReg0)); 4101 SA_DBG3(("mpiReadCALTable: spaReg1 0x%x\n", mpiCALTable->spaReg1)); 4102 SA_DBG3(("mpiReadCALTable: spaReg2 0x%x\n", mpiCALTable->spaReg2)); 4103 SA_DBG3(("mpiReadCALTable: spaReg3 0x%x\n", mpiCALTable->spaReg3)); 4104 SA_DBG3(("mpiReadCALTable: spaReg4 0x%x\n", mpiCALTable->spaReg4)); 4105 SA_DBG3(("mpiReadCALTable: spaReg5 0x%x\n", mpiCALTable->spaReg5)); 4106 SA_DBG3(("mpiReadCALTable: spaReg6 0x%x\n", mpiCALTable->spaReg6)); 4107 SA_DBG3(("mpiReadCALTable: spaReg7 0x%x\n", mpiCALTable->spaReg7)); 4108} 4109 4110/*******************************************************************************/ 4111/** \fn void mpiWriteCALTable(agsaRoot_t *agRoot, 4112 * spc_SPASTable_t *mpiCALTable, index) 4113 * \brief Writing the Phy Analog Setup Register Table 4114 * \param agsaRoot Handles for this instance of SAS/SATA LLL 4115 * \param mpiCALTable Pointer of Phy Calibration Table 4116 * 4117 * Return: 4118 * None 4119 */ 4120/*******************************************************************************/ 4121GLOBAL void mpiWriteCALTable(agsaRoot_t *agRoot, 4122 spc_SPASTable_t *mpiCALTable, 4123 bit32 index) 4124{ 4125 bit32 CFGTableOffset, TableOffset; 4126 bit32 CALTableOffset; 4127 bit8 pcibar; 4128 4129 smTraceFuncEnter(hpDBG_VERY_LOUD,"m6"); 4130 4131 /* get offset of the configuration table */ 4132 TableOffset = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4133 4134 CFGTableOffset = TableOffset & SCRATCH_PAD0_OFFSET_MASK; 4135 4136 /* get PCI BAR */ 4137 TableOffset = (TableOffset & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4138 /* convert the PCI BAR to logical bar number */ 4139 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, TableOffset); 4140 4141 /* read Calibration Table Offset from the configuration table */ 4142 CALTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); 4143 if(smIS_SPCV(agRoot)) 4144 { 4145 CALTableOffset &= 0x00FFFFFF; 4146 } 4147 CALTableOffset = CFGTableOffset + CALTableOffset + (index * ANALOG_SETUP_ENTRY_SIZE * 4); 4148 4149 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET), mpiCALTable->spaReg0); 4150 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG2_OFFSET), mpiCALTable->spaReg1); 4151 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_PORT_CFG3_OFFSET), mpiCALTable->spaReg2); 4152 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + TX_CFG_OFFSET), mpiCALTable->spaReg3); 4153 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET), mpiCALTable->spaReg4); 4154 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_PORT_CFG2_OFFSET), mpiCALTable->spaReg5); 4155 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG1_OFFSET), mpiCALTable->spaReg6); 4156 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(CALTableOffset + RV_CFG2_OFFSET), mpiCALTable->spaReg7); 4157 4158 SA_DBG4(("mpiWriteCALTable: Offset 0x%08x spaReg0 0x%x 0x%x 0x%x 0x%x\n",(bit32)(CALTableOffset + TX_PORT_CFG1_OFFSET), mpiCALTable->spaReg0, mpiCALTable->spaReg1, mpiCALTable->spaReg2, mpiCALTable->spaReg3)); 4159 SA_DBG4(("mpiWriteCALTable: Offset 0x%08x spaReg4 0x%x 0x%x 0x%x 0x%x\n",(bit32)(CALTableOffset + RV_PORT_CFG1_OFFSET), mpiCALTable->spaReg4, mpiCALTable->spaReg5, mpiCALTable->spaReg6, mpiCALTable->spaReg7)); 4160 4161 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "m6"); 4162} 4163 4164/*******************************************************************************/ 4165/** \fn void mpiWriteCALAll(agsaRoot_t *agRoot, 4166 * agsaPhyAnalogSetupTable_t *mpiCALTable) 4167 * \brief Writing the Phy Analog Setup Register Table 4168 * \param agsaRoot Handles for this instance of SAS/SATA LLL 4169 * \param mpiCALTable Pointer of Phy Calibration Table 4170 * 4171 * Return: 4172 * None 4173 */ 4174/*******************************************************************************/ 4175GLOBAL void mpiWriteCALAll(agsaRoot_t *agRoot, 4176 agsaPhyAnalogSetupTable_t *mpiCALTable) 4177{ 4178 bit8 i; 4179 smTraceFuncEnter(hpDBG_VERY_LOUD,"mz"); 4180 4181 if(smIS_SPCV(agRoot)) 4182 { 4183 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "mz"); 4184 return; 4185 } 4186 4187 for (i = 0; i < MAX_INDEX; i++) 4188 { 4189 mpiWriteCALTable(agRoot, (spc_SPASTable_t *)&mpiCALTable->phyAnalogSetupRegisters[i], i); 4190 } 4191 smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "mz"); 4192} 4193 4194GLOBAL void mpiWrAnalogSetupTable(agsaRoot_t *agRoot, 4195 mpiConfig_t *config 4196 ) 4197{ 4198 4199 bit32 AnalogTableBase,CFGTableOffset, value,phy; 4200 bit32 AnalogtableSize; 4201 bit8 pcibar; 4202 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4203 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); 4204 4205 CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; 4206 AnalogtableSize = AnalogTableBase = ossaHwRegReadExt(agRoot,pcibar , (bit32)CFGTableOffset + MAIN_ANALOG_SETUP_OFFSET); 4207 AnalogtableSize &= 0xFF000000; 4208 AnalogtableSize >>= SHIFT24; 4209 AnalogTableBase &= 0x00FFFFFF; 4210 4211 AnalogTableBase = CFGTableOffset + AnalogTableBase; 4212 4213// config->phyAnalogConfig.phyAnalogSetupRegisters[0].spaRegister0 = 0; 4214 SA_DBG1(("mpiWrAnalogSetupTable:Analogtable Base Offset %08X pcibar %d\n",AnalogTableBase, pcibar )); 4215 4216 SA_DBG1(("mpiWrAnalogSetupTable:%d %d\n",(int)sizeof(agsaPhyAnalogSetupRegisters_t), AnalogtableSize)); 4217 4218 for(phy = 0; phy < 10; phy++) /* upto 10 phys See PM*/ 4219 { 4220 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 0 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 ); 4221 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 4 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 ); 4222 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 8 ),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 ); 4223 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 12),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 ); 4224 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 16),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 ); 4225 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 20),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 ); 4226 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 24),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 ); 4227 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 28),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 ); 4228 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 32),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 ); 4229 ossaHwRegWriteExt(agRoot, pcibar,(AnalogTableBase + ( AnalogtableSize * phy)+ 36),config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 ); 4230 4231 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister0 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 0,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister0 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 0 ))); 4232 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister1 0x%x 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 4,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister1 ,ossaHwRegReadExt(agRoot, pcibar,AnalogTableBase + ( AnalogtableSize * phy)+ 4 ))); 4233 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister2 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) + 8,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister2 )); 4234 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister3 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +12,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister3 )); 4235 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister4 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +16,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister4 )); 4236 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister5 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +20,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister5 )); 4237 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister6 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +24,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister6 )); 4238 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister7 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +28,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister7 )); 4239 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister8 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +32,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister8 )); 4240 SA_DBG4(("mpiWrAnalogSetupTable:phy %d Offset 0x%08x spaRegister9 0x%x\n",phy, (bit32) AnalogTableBase+ (AnalogtableSize * phy) +36,config->phyAnalogConfig.phyAnalogSetupRegisters[phy].spaRegister9 )); 4241 } 4242 4243} 4244 4245 4246GLOBAL void mpiWrIntVecTable(agsaRoot_t *agRoot, 4247 mpiConfig_t* config 4248 ) 4249{ 4250 bit32 CFGTableOffset, value; 4251 bit32 INTVTableOffset; 4252 bit32 ValuetoWrite; 4253 bit8 pcibar, i,obq; 4254 4255 /* get offset of the configuration table */ 4256 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4257 4258 CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; 4259 4260 /* get PCI BAR */ 4261 value = (value & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4262 /* convert the PCI BAR to logical bar number */ 4263 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); 4264 4265 /* read Interrupt Table Offset from the main configuration table */ 4266 INTVTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_INT_VEC_TABLE_OFFSET); 4267 INTVTableOffset &= 0x00FFFFFF; 4268 INTVTableOffset = CFGTableOffset + INTVTableOffset; 4269 SA_DBG1(("mpiWrIntVecTable: Base Offset %08X\n",(bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO ) )); 4270 4271 for (i = 0; i < MAX_NUM_VECTOR; i ++) 4272 { 4273 bit32 found=0; 4274 for (obq = 0; obq < MAX_NUM_VECTOR; obq++) 4275 { /* find OBQ for vector i */ 4276 if( config->outboundQueues[obq].interruptVector == i ) 4277 { 4278 found=1; 4279 break; 4280 } 4281 } 4282 4283 if(!found ) 4284 { 4285 continue; 4286 } 4287 4288 ValuetoWrite = (( config->outboundQueues[obq].interruptDelay << SHIFT15) | config->outboundQueues[obq].interruptThreshold ); 4289 4290 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), ValuetoWrite ); 4291 4292 SA_DBG3(("mpiWrIntVecTable: Q %d interruptDelay 0x%X interruptThreshold 0x%X \n",i, 4293 config->outboundQueues[i].interruptDelay, config->outboundQueues[i].interruptThreshold )); 4294 4295 SA_DBG3(("mpiWrIntVecTable: %d INT_VT_Coal_CNT_TO Bar %d Offset %3X Writing 0x%08x\n",i, 4296 pcibar, 4297 (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), 4298 ValuetoWrite)); 4299 4300 } 4301 4302 for (i = 0; i < MAX_NUM_VECTOR; i++) 4303 { 4304 /* read interrupt colescing control and timer */ 4305 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t))); 4306 SA_DBG4(("mpiWrIntVecTable: Offset 0x%08x Interrupt Colescing iccict[%02d] 0x%x\n", (bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO + i * sizeof(InterruptVT_t)), i, value)); 4307 } 4308} 4309 4310GLOBAL void mpiWrPhyAttrbTable(agsaRoot_t *agRoot, sasPhyAttribute_t *phyAttrib) 4311{ 4312 bit32 CFGTableOffset, value; 4313 bit32 PHYTableOffset; 4314 bit8 pcibar, i; 4315 4316 /* get offset of the configuration table */ 4317 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 4318 4319 CFGTableOffset = value & SCRATCH_PAD0_OFFSET_MASK; 4320 4321 /* get PCI BAR */ 4322 value = (value & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 4323 /* convert the PCI BAR to logical bar number */ 4324 pcibar = (bit8)mpiGetPCIBarIndex(agRoot, value); 4325 4326 /* read Phy Attribute Table Offset from the configuration table */ 4327 PHYTableOffset = ossaHwRegReadExt(agRoot, pcibar, (bit32)CFGTableOffset + MAIN_PHY_ATTRIBUTE_OFFSET); 4328 4329 PHYTableOffset &=0x00FFFFFF; 4330 4331 PHYTableOffset = CFGTableOffset + PHYTableOffset + PHY_EVENT_OQ; 4332 4333 SA_DBG1(("mpiWrPhyAttrbTable: PHYTableOffset 0x%08x\n", PHYTableOffset)); 4334 4335 /* write OQ event per phy */ 4336 for (i = 0; i < MAX_VALID_PHYS; i ++) 4337 { 4338 ossaHwRegWriteExt(agRoot, pcibar, (bit32)(PHYTableOffset + i * sizeof(phyAttrb_t)), phyAttrib->phyAttribute[i].phyEventOQ); 4339 4340 SA_DBG3(("mpiWrPhyAttrbTable:%d Offset 0x%08x phyAttribute 0x%x\n",i,(bit32)(PHYTableOffset + i * sizeof(phyAttrb_t)), phyAttrib->phyAttribute[i].phyEventOQ )); 4341 4342 4343 } 4344 4345 for (i = 0; i < MAX_VALID_PHYS; i ++) 4346 { 4347 value = ossaHwRegReadExt(agRoot, pcibar, (bit32)(PHYTableOffset + i * sizeof(phyAttrb_t))); 4348 SA_DBG1(("mpiWrPhyAttrbTable: OQ Event per phy[%x] 0x%x\n", i, value)); 4349 } 4350} 4351 4352 4353#ifdef TEST /******************************************************************/ 4354/*******************************************************************************/ 4355/** \fn mpiFreezeInboundQueue(agsaRoot_t *agRoot) 4356 * \brief Freeze the inbound queue 4357 * 4358 * \param agRoot Handles for this instance of SAS/SATA hardware 4359 * \param bitMapQueueNum0 bit map for inbound queue number 0 - 31 to freeze 4360 * \param bitMapQueueNum1 bit map for inbound queue number 32 - 63 to freeze 4361 * 4362 * Return: 4363 * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful 4364 * AGSA_RC_FAILURE if Un-initialize the configuration table failed 4365 */ 4366/*******************************************************************************/ 4367GLOBAL bit32 mpiFreezeInboundQueue(agsaRoot_t *agRoot, bit32 bitMapQueueNum0, bit32 bitMapQueueNum1) 4368{ 4369 bit32 value, togglevalue; 4370 bit32 max_wait_time; 4371 bit32 max_wait_count; 4372 4373 SA_DBG2(("Entering function:mpiFreezeInboundQueue\n")); 4374 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 4375 4376 togglevalue = 0; 4377 4378 if (bitMapQueueNum0) 4379 { 4380 /* update the inbound queue number to HOST_SCRATCH_PAD1 register for queue 0 to 31 */ 4381 SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0))); 4382 SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3))); 4383 4384 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_1); 4385 value |= bitMapQueueNum0; 4386 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_1, MSGU_HOST_SCRATCH_PAD_1, value); 4387 } 4388 4389 if (bitMapQueueNum1) 4390 { 4391 /* update the inbound queue number to HOST_SCRATCH_PAD2 register for queue 32 to 63 */ 4392 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 4393 value |= bitMapQueueNum1; 4394 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_2, MSGU_HOST_SCRATCH_PAD_2, value); 4395 } 4396 4397 /* Write bit 2 to Inbound DoorBell Register */ 4398 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, IBDB_IBQ_FREEZE); 4399 4400 /* wait until Inbound DoorBell Clear Register toggled */ 4401 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 4402 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4403 do 4404 { 4405 ossaStallThread(agRoot, WAIT_INCREMENT); 4406 /* Read Inbound DoorBell Register - for RevB */ 4407// value = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_IBDB_SET); 4408 value = MSGU_READ_IDR; 4409 value &= IBDB_IBQ_FREEZE; 4410 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 4411 4412 if (!max_wait_count) 4413 { 4414 SA_DBG1(("mpiFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 4415 return AGSA_RC_FAILURE; 4416 } 4417 4418 return AGSA_RC_SUCCESS; 4419} 4420 4421/******************************************************************************/ 4422/** \fn mpiUnFreezeInboundQueue(agsaRoot_t *agRoot) 4423 * \brief Freeze the inbound queue 4424 * 4425 * \param agRoot Handles for this instance of SAS/SATA hardware 4426 * \param bitMapQueueNum0 bit map for inbound queue number 0 - 31 to freeze 4427 * \param bitMapQueueNum1 bit map for inbound queue number 32 - 63 to freeze 4428 * 4429 * Return: 4430 * AGSA_RC_SUCCESS if Un-initialize the configuration table sucessful 4431 * AGSA_RC_FAILURE if Un-initialize the configuration table failed 4432 */ 4433/******************************************************************************/ 4434GLOBAL bit32 mpiUnFreezeInboundQueue(agsaRoot_t *agRoot, bit32 bitMapQueueNum0, bit32 bitMapQueueNum1) 4435{ 4436 bit32 value, togglevalue; 4437 bit32 max_wait_time; 4438 bit32 max_wait_count; 4439 4440 SA_DBG2(("Entering function:mpiUnFreezeInboundQueue\n")); 4441 SA_ASSERT(NULL != agRoot, "agRoot argument cannot be null"); 4442 4443 togglevalue = 0; 4444 4445 if (bitMapQueueNum0) 4446 { 4447 /* update the inbound queue number to HOST_SCRATCH_PAD1 register - for queue 0 to 31 */ 4448 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1); 4449 value |= bitMapQueueNum0; 4450 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_1, MSGU_HOST_SCRATCH_PAD_1, value); 4451 } 4452 4453 if (bitMapQueueNum1) 4454 { 4455 /* update the inbound queue number to HOST_SCRATCH_PAD2 register - for queue 32 to 63 */ 4456 value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_2); 4457 value |= bitMapQueueNum1; 4458 siHalRegWriteExt(agRoot, GEN_MSGU_HOST_SCRATCH_PAD_2, MSGU_HOST_SCRATCH_PAD_2, value); 4459 } 4460 4461 /* Write bit 2 to Inbound DoorBell Register */ 4462 siHalRegWriteExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET, IBDB_IBQ_UNFREEZE); 4463 4464 /* wait until Inbound DoorBell Clear Register toggled */ 4465 max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 4466 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4467 do 4468 { 4469 ossaStallThread(agRoot, WAIT_INCREMENT); 4470 /* Read Inbound DoorBell Register - for RevB */ 4471 value = MSGU_READ_IDR; 4472 value &= IBDB_IBQ_UNFREEZE; 4473 } while ((value != togglevalue) && (max_wait_count -= WAIT_INCREMENT)); 4474 4475 if (!max_wait_count) 4476 { 4477 SA_DBG1(("mpiUnFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue)); 4478 return AGSA_RC_FAILURE; 4479 } 4480 4481 return AGSA_RC_SUCCESS; 4482} 4483 4484#endif /* TEST ****************************************************************/ 4485 4486GLOBAL bit32 si_check_V_HDA(agsaRoot_t *agRoot) 4487{ 4488 bit32 ret = AGSA_RC_SUCCESS; 4489 bit32 hda_status = 0; 4490 4491 hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 4492 4493 SA_DBG1(("si_check_V_HDA: hda_status 0x%08X\n",hda_status )); 4494 4495 if((hda_status & SPC_V_HDAR_RSPCODE_MASK) == SPC_V_HDAR_IDLE) 4496 { 4497 /* HDA mode */ 4498 SA_DBG1(("si_check_V_HDA: HDA mode, value = 0x%x\n", hda_status)); 4499 ret = AGSA_RC_HDA_NO_FW_RUNNING; 4500 } 4501 4502 4503 return(ret); 4504} 4505GLOBAL bit32 si_check_V_Ready(agsaRoot_t *agRoot) 4506{ 4507 bit32 ret = AGSA_RC_SUCCESS; 4508 bit32 SCRATCH_PAD1; 4509 bit32 max_wait_time; 4510 bit32 max_wait_count; 4511/* ILA */ 4512 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4513 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4514 do 4515 { 4516 ossaStallThread(agRoot, WAIT_INCREMENT); 4517 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4518 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4519 4520 if (!max_wait_count) 4521 { 4522 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); 4523 return( AGSA_RC_FAILURE); 4524 } 4525 /* RAAE */ 4526 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4527 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4528 do 4529 { 4530 ossaStallThread(agRoot, WAIT_INCREMENT); 4531 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4532 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4533 4534 if (!max_wait_count) 4535 { 4536 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); 4537 return( AGSA_RC_FAILURE); 4538 4539 } 4540 /* IOP0 */ 4541 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4542 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4543 do 4544 { 4545 ossaStallThread(agRoot, WAIT_INCREMENT); 4546 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4547 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4548 4549 if (!max_wait_count) 4550 { 4551 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); 4552 return( AGSA_RC_FAILURE); 4553 4554 } 4555 4556 /* IOP1 */ 4557 max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 4558 max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT); 4559 do 4560 { 4561 ossaStallThread(agRoot, WAIT_INCREMENT); 4562 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4563 } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) != SCRATCH_PAD1_V_IOP1_MASK) && (max_wait_count -= WAIT_INCREMENT)); 4564 4565 if (!max_wait_count) 4566 { 4567 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1)); 4568 // return( AGSA_RC_FAILURE); 4569 } 4570 4571 return(ret); 4572} 4573 4574GLOBAL bit32 siScratchDump(agsaRoot_t *agRoot) 4575{ 4576 bit32 SCRATCH_PAD1; 4577 bit32 ret =0; 4578#ifdef SALLSDK_DEBUG 4579 bit32 SCRATCH_PAD2; 4580 bit32 SCRATCH_PAD3; 4581 bit32 SCRATCH_PAD0; 4582 4583 SCRATCH_PAD0 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0); 4584 SCRATCH_PAD2 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2); 4585 SCRATCH_PAD3 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3); 4586#endif /* SALLSDK_DEBUG */ 4587 SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 4588 SA_DBG1(("siScratchDump: SCRATCH_PAD 0 0x%08x 1 0x%08x 2 0x%08x 3 0x%08x\n",SCRATCH_PAD0,SCRATCH_PAD1,SCRATCH_PAD2,SCRATCH_PAD3 )); 4589 4590 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_RESERVED) == SCRATCH_PAD1_V_RESERVED ) 4591 { 4592 SA_DBG1(("siScratchDump: SCRATCH_PAD1 SCRATCH_PAD1_V_RESERVED 0x%08x\n", SCRATCH_PAD1_V_RESERVED)); 4593 } 4594 else 4595 { 4596 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_MASK ) 4597 { 4598 SA_DBG1(("siScratchDump: SCRATCH_PAD1 valid 0x%08x\n",SCRATCH_PAD0 )); 4599 SA_DBG1(("siScratchDump: RAAE ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK)); 4600 } 4601 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) == SCRATCH_PAD1_V_ILA_MASK) 4602 { 4603 SA_DBG1(("siScratchDump: ILA ready 0x%08x\n", SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK)); 4604 } 4605 4606 if(SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK) 4607 { 4608 SA_DBG1(("siScratchDump: BOOTSTATE not success 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK)); 4609 } 4610 4611 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) == SCRATCH_PAD1_V_IOP0_MASK) 4612 { 4613 SA_DBG1(("siScratchDump: IOP0 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK)); 4614 } 4615 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) == SCRATCH_PAD1_V_IOP1_MASK) 4616 { 4617 SA_DBG1(("siScratchDump: IOP1 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK )); 4618 } 4619 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_READY) == SCRATCH_PAD1_V_READY) 4620 { 4621 SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_READY 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_READY )); 4622 } 4623 if((SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK) == SCRATCH_PAD1_V_BOOTSTATE_MASK) 4624 { 4625 SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_BOOTSTATE_MASK 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK )); 4626 } 4627 } 4628 return(ret); 4629 4630} 4631 4632 4633void si_macro_check(agsaRoot_t *agRoot) 4634{ 4635 4636 SA_DBG1(("si_macro_check:smIS_SPC %d\n",smIS_SPC(agRoot) )); 4637 SA_DBG1(("si_macro_check:smIS_HIL %d\n",smIS_HIL(agRoot) )); 4638 SA_DBG1(("si_macro_check:smIS_SFC %d\n",smIS_SFC(agRoot) )); 4639 4640 SA_DBG1(("si_macro_check:smIS_spc8001 %d\n",smIS_spc8001(agRoot) )); 4641 SA_DBG1(("si_macro_check:smIS_spc8081 %d\n",smIS_spc8081(agRoot) )); 4642 4643 SA_DBG1(("si_macro_check:smIS_SPCV8008 %d\n",smIS_SPCV8008(agRoot) )); 4644 SA_DBG1(("si_macro_check:smIS_SPCV8009 %d\n",smIS_SPCV8009(agRoot) )); 4645 SA_DBG1(("si_macro_check:smIS_SPCV8018 %d\n",smIS_SPCV8018(agRoot) )); 4646 SA_DBG1(("si_macro_check:smIS_SPCV8019 %d\n",smIS_SPCV8019(agRoot) )); 4647 SA_DBG1(("si_macro_check:smIS_ADAP8088 %d\n",smIS_ADAP8088(agRoot) )); 4648 SA_DBG1(("si_macro_check:smIS_ADAP8089 %d\n",smIS_ADAP8089(agRoot) )); 4649 SA_DBG1(("si_macro_check:smIS_SPCV8070 %d\n",smIS_SPCV8070(agRoot) )); 4650 SA_DBG1(("si_macro_check:smIS_SPCV8071 %d\n",smIS_SPCV8071(agRoot) )); 4651 SA_DBG1(("si_macro_check:smIS_SPCV8072 %d\n",smIS_SPCV8072(agRoot) )); 4652 SA_DBG1(("si_macro_check:smIS_SPCV8073 %d\n",smIS_SPCV8073(agRoot) )); 4653 SA_DBG1(("si_macro_check:smIS_SPCV8074 %d\n",smIS_SPCV8074(agRoot) )); 4654 SA_DBG1(("si_macro_check:smIS_SPCV8075 %d\n",smIS_SPCV8075(agRoot) )); 4655 SA_DBG1(("si_macro_check:smIS_SPCV8076 %d\n",smIS_SPCV8076(agRoot) )); 4656 SA_DBG1(("si_macro_check:smIS_SPCV8077 %d\n",smIS_SPCV8077(agRoot) )); 4657 SA_DBG1(("si_macro_check:smIS_SPCV9015 %d\n",smIS_SPCV9015(agRoot) )); 4658 SA_DBG1(("si_macro_check:smIS_SPCV9060 %d\n",smIS_SPCV9060(agRoot) )); 4659 SA_DBG1(("si_macro_check:smIS_SPCV %d\n",smIS_SPCV(agRoot) )); 4660 4661 SA_DBG1(("si_macro_check:smIS64bInt %d\n", smIS64bInt(agRoot) )); 4662 4663} 4664 4665