1331766Sken/*- 2331766Sken * Copyright (c) 2017 Broadcom. All rights reserved. 3331766Sken * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4331766Sken * 5331766Sken * Redistribution and use in source and binary forms, with or without 6331766Sken * modification, are permitted provided that the following conditions are met: 7331766Sken * 8331766Sken * 1. Redistributions of source code must retain the above copyright notice, 9331766Sken * this list of conditions and the following disclaimer. 10331766Sken * 11331766Sken * 2. Redistributions in binary form must reproduce the above copyright notice, 12331766Sken * this list of conditions and the following disclaimer in the documentation 13331766Sken * and/or other materials provided with the distribution. 14331766Sken * 15331766Sken * 3. Neither the name of the copyright holder nor the names of its contributors 16331766Sken * may be used to endorse or promote products derived from this software 17331766Sken * without specific prior written permission. 18331766Sken * 19331766Sken * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20331766Sken * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21331766Sken * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22331766Sken * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23331766Sken * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24331766Sken * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25331766Sken * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26331766Sken * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27331766Sken * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28331766Sken * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29331766Sken * POSSIBILITY OF SUCH DAMAGE. 30331766Sken * 31331766Sken * $FreeBSD: stable/11/sys/dev/ocs_fc/sli4.h 331766 2018-03-30 15:28:25Z ken $ 32331766Sken */ 33331766Sken 34331766Sken/** 35331766Sken * @file 36331766Sken * Define common SLI-4 structures and function prototypes. 37331766Sken */ 38331766Sken 39331766Sken#ifndef _SLI4_H 40331766Sken#define _SLI4_H 41331766Sken 42331766Sken#include "ocs_os.h" 43331766Sken 44331766Sken#define SLI_PAGE_SIZE (4096) 45331766Sken#define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1) 46331766Sken#define SLI_PAGE_SHIFT 12 47331766Sken#define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK) 48331766Sken 49331766Sken#define SLI4_BMBX_TIMEOUT_MSEC 30000 50331766Sken#define SLI4_FW_READY_TIMEOUT_MSEC 30000 51331766Sken 52331766Skenstatic inline uint32_t 53331766Skensli_page_count(size_t bytes, uint32_t page_size) 54331766Sken{ 55331766Sken uint32_t mask = page_size - 1; 56331766Sken uint32_t shift = 0; 57331766Sken 58331766Sken switch (page_size) { 59331766Sken case 4096: 60331766Sken shift = 12; 61331766Sken break; 62331766Sken case 8192: 63331766Sken shift = 13; 64331766Sken break; 65331766Sken case 16384: 66331766Sken shift = 14; 67331766Sken break; 68331766Sken case 32768: 69331766Sken shift = 15; 70331766Sken break; 71331766Sken case 65536: 72331766Sken shift = 16; 73331766Sken break; 74331766Sken default: 75331766Sken return 0; 76331766Sken } 77331766Sken 78331766Sken return (bytes + mask) >> shift; 79331766Sken} 80331766Sken 81331766Sken/************************************************************************* 82331766Sken * Common PCI configuration space register definitions 83331766Sken */ 84331766Sken 85331766Sken#define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */ 86331766Sken#define SLI4_PCI_REV_ID_SHIFT 0 87331766Sken#define SLI4_PCI_REV_ID_MASK 0xff 88331766Sken#define SLI4_PCI_CLASS_SHIFT 8 89331766Sken#define SLI4_PCI_CLASS_MASK 0xfff 90331766Sken 91331766Sken#define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */ 92331766Sken#define SLI4_PCI_SOFT_RESET_MASK 0x0080 93331766Sken 94331766Sken/************************************************************************* 95331766Sken * Common SLI-4 register offsets and field definitions 96331766Sken */ 97331766Sken 98331766Sken/** 99331766Sken * @brief SLI_INTF - SLI Interface Definition Register 100331766Sken */ 101331766Sken#define SLI4_INTF_REG 0x0058 /** register offset */ 102331766Sken#define SLI4_INTF_VALID_SHIFT 29 103331766Sken#define SLI4_INTF_VALID_MASK 0x7 104331766Sken#define SLI4_INTF_VALID 0x6 105331766Sken#define SLI4_INTF_IF_TYPE_SHIFT 12 106331766Sken#define SLI4_INTF_IF_TYPE_MASK 0xf 107331766Sken#define SLI4_INTF_SLI_FAMILY_SHIFT 8 108331766Sken#define SLI4_INTF_SLI_FAMILY_MASK 0xf 109331766Sken#define SLI4_INTF_SLI_REVISION_SHIFT 4 110331766Sken#define SLI4_INTF_SLI_REVISION_MASK 0xf 111331766Sken#define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf 112331766Sken 113331766Sken#define SLI4_IF_TYPE_BE3_SKH_PF 0 114331766Sken#define SLI4_IF_TYPE_BE3_SKH_VF 1 115331766Sken#define SLI4_IF_TYPE_LANCER_FC_ETH 2 116331766Sken#define SLI4_IF_TYPE_LANCER_RDMA 3 117331766Sken#define SLI4_MAX_IF_TYPES 4 118331766Sken 119331766Sken/** 120331766Sken * @brief ASIC_ID - SLI ASIC Type and Revision Register 121331766Sken */ 122331766Sken#define SLI4_ASIC_ID_REG 0x009c /* register offset */ 123331766Sken#define SLI4_ASIC_REV_SHIFT 0 124331766Sken#define SLI4_ASIC_REV_MASK 0xf 125331766Sken#define SLI4_ASIC_VER_SHIFT 4 126331766Sken#define SLI4_ASIC_VER_MASK 0xf 127331766Sken#define SLI4_ASIC_GEN_SHIFT 8 128331766Sken#define SLI4_ASIC_GEN_MASK 0xff 129331766Sken#define SLI4_ASIC_GEN_BE2 0x00 130331766Sken#define SLI4_ASIC_GEN_BE3 0x03 131331766Sken#define SLI4_ASIC_GEN_SKYHAWK 0x04 132331766Sken#define SLI4_ASIC_GEN_CORSAIR 0x05 133331766Sken#define SLI4_ASIC_GEN_LANCER 0x0b 134331766Sken 135331766Sken 136331766Sken/** 137331766Sken * @brief BMBX - Bootstrap Mailbox Register 138331766Sken */ 139331766Sken#define SLI4_BMBX_REG 0x0160 /* register offset */ 140331766Sken#define SLI4_BMBX_MASK_HI 0x3 141331766Sken#define SLI4_BMBX_MASK_LO 0xf 142331766Sken#define SLI4_BMBX_RDY BIT(0) 143331766Sken#define SLI4_BMBX_HI BIT(1) 144331766Sken#define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \ 145331766Sken SLI4_BMBX_HI) 146331766Sken#define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \ 147331766Sken (((r) & ~SLI4_BMBX_MASK_LO) >> 2)) 148331766Sken 149331766Sken#define SLI4_BMBX_SIZE 256 150331766Sken 151331766Sken 152331766Sken/** 153331766Sken * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register 154331766Sken */ 155331766Sken#define SLI4_EQCQ_DOORBELL_REG 0x120 156331766Sken#define SLI4_EQCQ_DOORBELL_CI BIT(9) 157331766Sken#define SLI4_EQCQ_DOORBELL_QT BIT(10) 158331766Sken#define SLI4_EQCQ_DOORBELL_ARM BIT(29) 159331766Sken#define SLI4_EQCQ_DOORBELL_SE BIT(31) 160331766Sken#define SLI4_EQCQ_NUM_SHIFT 16 161331766Sken#define SLI4_EQCQ_NUM_MASK 0x01ff 162331766Sken#define SLI4_EQCQ_EQ_ID_MASK 0x3fff 163331766Sken#define SLI4_EQCQ_CQ_ID_MASK 0x7fff 164331766Sken#define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff 165331766Sken#define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff 166331766Sken#define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800 167331766Sken 168331766Sken/** 169331766Sken * @brief SLIPORT_CONTROL - SLI Port Control Register 170331766Sken */ 171331766Sken#define SLI4_SLIPORT_CONTROL_REG 0x0408 172331766Sken#define SLI4_SLIPORT_CONTROL_END BIT(30) 173331766Sken#define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0) 174331766Sken#define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30) 175331766Sken#define SLI4_SLIPORT_CONTROL_IP BIT(27) 176331766Sken#define SLI4_SLIPORT_CONTROL_IDIS BIT(22) 177331766Sken#define SLI4_SLIPORT_CONTROL_FDD BIT(31) 178331766Sken 179331766Sken/** 180331766Sken * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register 181331766Sken */ 182331766Sken#define SLI4_SLIPORT_ERROR1 0x040c 183331766Sken 184331766Sken/** 185331766Sken * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register 186331766Sken */ 187331766Sken#define SLI4_SLIPORT_ERROR2 0x0410 188331766Sken 189331766Sken/** 190331766Sken * @brief User error registers 191331766Sken */ 192331766Sken#define SLI4_UERR_STATUS_LOW_REG 0xA0 193331766Sken#define SLI4_UERR_STATUS_HIGH_REG 0xA4 194331766Sken#define SLI4_UERR_MASK_LOW_REG 0xA8 195331766Sken#define SLI4_UERR_MASK_HIGH_REG 0xAC 196331766Sken 197331766Sken/** 198331766Sken * @brief Registers for generating software UE (BE3) 199331766Sken */ 200331766Sken#define SLI4_SW_UE_CSR1 0x138 201331766Sken#define SLI4_SW_UE_CSR2 0x1FFFC 202331766Sken 203331766Sken/** 204331766Sken * @brief Registers for generating software UE (Skyhawk) 205331766Sken */ 206331766Sken#define SLI4_SW_UE_REG 0x5C /* register offset */ 207331766Sken 208331766Skenstatic inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 209331766Sken{ 210331766Sken uint32_t reg = 0; 211331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 212331766Sken struct { 213331766Sken uint32_t eq_id_lo:9, 214331766Sken ci:1, /* clear interrupt */ 215331766Sken qt:1, /* queue type */ 216331766Sken eq_id_hi:5, 217331766Sken number_popped:13, 218331766Sken arm:1, 219331766Sken :1, 220331766Sken se:1; 221331766Sken } * eq_doorbell = (void *)® 222331766Sken#else 223331766Sken#error big endian version not defined 224331766Sken#endif 225331766Sken 226331766Sken eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO; 227331766Sken eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */ 228331766Sken eq_doorbell->eq_id_hi = (id >> 9) & 0x1f; 229331766Sken eq_doorbell->number_popped = n_popped; 230331766Sken eq_doorbell->arm = arm; 231331766Sken eq_doorbell->ci = TRUE; 232331766Sken 233331766Sken return reg; 234331766Sken} 235331766Sken 236331766Skenstatic inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 237331766Sken{ 238331766Sken uint32_t reg = 0; 239331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 240331766Sken struct { 241331766Sken uint32_t cq_id_lo:10, 242331766Sken qt:1, /* queue type */ 243331766Sken cq_id_hi:5, 244331766Sken number_popped:13, 245331766Sken arm:1, 246331766Sken :1, 247331766Sken se:1; 248331766Sken } * cq_doorbell = (void *)® 249331766Sken#else 250331766Sken#error big endian version not defined 251331766Sken#endif 252331766Sken 253331766Sken cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO; 254331766Sken cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */ 255331766Sken cq_doorbell->cq_id_hi = (id >> 10) & 0x1f; 256331766Sken cq_doorbell->number_popped = n_popped; 257331766Sken cq_doorbell->arm = arm; 258331766Sken 259331766Sken return reg; 260331766Sken} 261331766Sken 262331766Sken/** 263331766Sken * @brief MQ_DOORBELL - MQ Doorbell Register 264331766Sken */ 265331766Sken#define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */ 266331766Sken#define SLI4_MQ_DOORBELL_NUM_SHIFT 16 267331766Sken#define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff 268331766Sken#define SLI4_MQ_DOORBELL_ID_MASK 0xffff 269331766Sken#define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \ 270331766Sken ((i) & SLI4_MQ_DOORBELL_ID_MASK)) 271331766Sken 272331766Sken/** 273331766Sken * @brief RQ_DOORBELL - RQ Doorbell Register 274331766Sken */ 275331766Sken#define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */ 276331766Sken#define SLI4_RQ_DOORBELL_NUM_SHIFT 16 277331766Sken#define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff 278331766Sken#define SLI4_RQ_DOORBELL_ID_MASK 0xffff 279331766Sken#define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \ 280331766Sken ((i) & SLI4_RQ_DOORBELL_ID_MASK)) 281331766Sken 282331766Sken/** 283331766Sken * @brief WQ_DOORBELL - WQ Doorbell Register 284331766Sken */ 285331766Sken#define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */ 286331766Sken#define SLI4_WQ_DOORBELL_IDX_SHIFT 16 287331766Sken#define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff 288331766Sken#define SLI4_WQ_DOORBELL_NUM_SHIFT 24 289331766Sken#define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff 290331766Sken#define SLI4_WQ_DOORBELL_ID_MASK 0xffff 291331766Sken#define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \ 292331766Sken (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \ 293331766Sken ((i) & SLI4_WQ_DOORBELL_ID_MASK)) 294331766Sken 295331766Sken/** 296331766Sken * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register 297331766Sken */ 298331766Sken#define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */ 299331766Sken#define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */ 300331766Sken#define SLI4_PORT_SEMAPHORE_REG_23 0x0400 /** register offset Interface Type 2 + 3 */ 301331766Sken#define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff 302331766Sken#define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK) 303331766Sken#define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000 304331766Sken#define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16 305331766Sken#define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \ 306331766Sken SLI4_PORT_SEMAPHORE_HOST_SHIFT) 307331766Sken#define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */ 308331766Sken#define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */ 309331766Sken#define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */ 310331766Sken#define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */ 311331766Sken#define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */ 312331766Sken#define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */ 313331766Sken 314331766Sken#define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000 315331766Sken#define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000 316331766Sken#define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000 317331766Sken#define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \ 318331766Sken SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK)) 319331766Sken 320331766Sken/** 321331766Sken * @brief SLIPORT_STATUS - SLI Port Status Register 322331766Sken */ 323331766Sken 324331766Sken#define SLI4_PORT_STATUS_REG_23 0x0404 /** register offset Interface Type 2 + 3 */ 325331766Sken#define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */ 326331766Sken#define SLI4_PORT_STATUS_RDY BIT(23) /** ready */ 327331766Sken#define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */ 328331766Sken#define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */ 329331766Sken#define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */ 330331766Sken#define SLI4_PORT_STATUS_END BIT(30) /** endianness */ 331331766Sken#define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */ 332331766Sken#define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY) 333331766Sken#define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR) 334331766Sken#define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP) 335331766Sken#define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP) 336331766Sken 337331766Sken 338331766Sken#define SLI4_PHSDEV_CONTROL_REG_23 0x0414 /** register offset Interface Type 2 + 3 */ 339331766Sken#define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */ 340331766Sken#define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */ 341331766Sken#define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */ 342331766Sken#define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0 343331766Sken#define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4 344331766Sken#define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \ 345331766Sken SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT) 346331766Sken 347331766Sken/************************************************************************* 348331766Sken * SLI-4 mailbox command formats and definitions 349331766Sken */ 350331766Sken 351331766Skentypedef struct sli4_mbox_command_header_s { 352331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 353331766Sken uint32_t :8, 354331766Sken command:8, 355331766Sken status:16; /** Port writes to indicate success / fail */ 356331766Sken#else 357331766Sken#error big endian version not defined 358331766Sken#endif 359331766Sken} sli4_mbox_command_header_t; 360331766Sken 361331766Sken#define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07 362331766Sken#define SLI4_MBOX_COMMAND_DUMP 0x17 363331766Sken#define SLI4_MBOX_COMMAND_DOWN_LINK 0x06 364331766Sken#define SLI4_MBOX_COMMAND_INIT_LINK 0x05 365331766Sken#define SLI4_MBOX_COMMAND_INIT_VFI 0xa3 366331766Sken#define SLI4_MBOX_COMMAND_INIT_VPI 0xa4 367331766Sken#define SLI4_MBOX_COMMAND_POST_XRI 0xa7 368331766Sken#define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac 369331766Sken#define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b 370331766Sken#define SLI4_MBOX_COMMAND_READ_STATUS 0x0e 371331766Sken#define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02 372331766Sken#define SLI4_MBOX_COMMAND_READ_REV 0x11 373331766Sken#define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12 374331766Sken#define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d 375331766Sken#define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95 376331766Sken#define SLI4_MBOX_COMMAND_REG_FCFI 0xa0 377331766Sken#define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf 378331766Sken#define SLI4_MBOX_COMMAND_REG_RPI 0x93 379331766Sken#define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6 380331766Sken#define SLI4_MBOX_COMMAND_REG_VFI 0x9f 381331766Sken#define SLI4_MBOX_COMMAND_REG_VPI 0x96 382331766Sken#define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d 383331766Sken#define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b 384331766Sken#define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2 385331766Sken#define SLI4_MBOX_COMMAND_UNREG_RPI 0x14 386331766Sken#define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1 387331766Sken#define SLI4_MBOX_COMMAND_UNREG_VPI 0x97 388331766Sken#define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03 389331766Sken#define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD 390331766Sken#define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE 391331766Sken 392331766Sken#define SLI4_MBOX_STATUS_SUCCESS 0x0000 393331766Sken#define SLI4_MBOX_STATUS_FAILURE 0x0001 394331766Sken#define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400 395331766Sken 396331766Sken/** 397331766Sken * @brief Buffer Descriptor Entry (BDE) 398331766Sken */ 399331766Skentypedef struct sli4_bde_s { 400331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 401331766Sken uint32_t buffer_length:24, 402331766Sken bde_type:8; 403331766Sken union { 404331766Sken struct { 405331766Sken uint32_t buffer_address_low; 406331766Sken uint32_t buffer_address_high; 407331766Sken } data; 408331766Sken struct { 409331766Sken uint32_t offset; 410331766Sken uint32_t rsvd2; 411331766Sken } imm; 412331766Sken struct { 413331766Sken uint32_t sgl_segment_address_low; 414331766Sken uint32_t sgl_segment_address_high; 415331766Sken } blp; 416331766Sken } u; 417331766Sken#else 418331766Sken#error big endian version not defined 419331766Sken#endif 420331766Sken} sli4_bde_t; 421331766Sken 422331766Sken#define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */ 423331766Sken#define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */ 424331766Sken#define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */ 425331766Sken 426331766Sken/** 427331766Sken * @brief Scatter-Gather Entry (SGE) 428331766Sken */ 429331766Skentypedef struct sli4_sge_s { 430331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 431331766Sken uint32_t buffer_address_high; 432331766Sken uint32_t buffer_address_low; 433331766Sken uint32_t data_offset:27, 434331766Sken sge_type:4, 435331766Sken last:1; 436331766Sken uint32_t buffer_length; 437331766Sken#else 438331766Sken#error big endian version not defined 439331766Sken#endif 440331766Sken} sli4_sge_t; 441331766Sken 442331766Sken/** 443331766Sken * @brief T10 DIF Scatter-Gather Entry (SGE) 444331766Sken */ 445331766Skentypedef struct sli4_dif_sge_s { 446331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 447331766Sken uint32_t buffer_address_high; 448331766Sken uint32_t buffer_address_low; 449331766Sken uint32_t :27, 450331766Sken sge_type:4, 451331766Sken last:1; 452331766Sken uint32_t :32; 453331766Sken#else 454331766Sken#error big endian version not defined 455331766Sken#endif 456331766Sken} sli4_dif_sge_t; 457331766Sken 458331766Sken/** 459331766Sken * @brief T10 DIF Seed Scatter-Gather Entry (SGE) 460331766Sken */ 461331766Skentypedef struct sli4_diseed_sge_s { 462331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 463331766Sken uint32_t ref_tag_cmp; 464331766Sken uint32_t ref_tag_repl; 465331766Sken uint32_t app_tag_repl:16, 466331766Sken :2, 467331766Sken hs:1, 468331766Sken ws:1, 469331766Sken ic:1, 470331766Sken ics:1, 471331766Sken atrt:1, 472331766Sken at:1, 473331766Sken fwd_app_tag:1, 474331766Sken repl_app_tag:1, 475331766Sken head_insert:1, 476331766Sken sge_type:4, 477331766Sken last:1; 478331766Sken uint32_t app_tag_cmp:16, 479331766Sken dif_blk_size:3, 480331766Sken auto_incr_ref_tag:1, 481331766Sken check_app_tag:1, 482331766Sken check_ref_tag:1, 483331766Sken check_crc:1, 484331766Sken new_ref_tag:1, 485331766Sken dif_op_rx:4, 486331766Sken dif_op_tx:4; 487331766Sken#else 488331766Sken#error big endian version not defined 489331766Sken#endif 490331766Sken} sli4_diseed_sge_t; 491331766Sken 492331766Sken/** 493331766Sken * @brief List Segment Pointer Scatter-Gather Entry (SGE) 494331766Sken */ 495331766Skentypedef struct sli4_lsp_sge_s { 496331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 497331766Sken uint32_t buffer_address_high; 498331766Sken uint32_t buffer_address_low; 499331766Sken uint32_t :27, 500331766Sken sge_type:4, 501331766Sken last:1; 502331766Sken uint32_t segment_length:24, 503331766Sken :8; 504331766Sken#else 505331766Sken#error big endian version not defined 506331766Sken#endif 507331766Sken} sli4_lsp_sge_t; 508331766Sken 509331766Sken#define SLI4_SGE_MAX_RESERVED 3 510331766Sken 511331766Sken#define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00 512331766Sken#define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01 513331766Sken#define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02 514331766Sken#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03 515331766Sken#define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04 516331766Sken#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05 517331766Sken#define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06 518331766Sken#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07 519331766Sken#define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08 520331766Sken 521331766Sken#define SLI4_SGE_TYPE_DATA 0x00 522331766Sken#define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */ 523331766Sken#define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */ 524331766Sken#define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */ 525331766Sken#define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */ 526331766Sken#define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */ 527331766Sken#define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */ 528331766Sken#define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */ 529331766Sken#define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */ 530331766Sken#define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */ 531331766Sken 532331766Sken#define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */ 533331766Sken 534331766Sken/** 535331766Sken * @brief CONFIG_LINK 536331766Sken */ 537331766Skentypedef struct sli4_cmd_config_link_s { 538331766Sken sli4_mbox_command_header_t hdr; 539331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 540331766Sken uint32_t maxbbc:8, /** Max buffer-to-buffer credit */ 541331766Sken :24; 542331766Sken uint32_t alpa:8, 543331766Sken n_port_id:16, 544331766Sken :8; 545331766Sken uint32_t rsvd3; 546331766Sken uint32_t e_d_tov; 547331766Sken uint32_t lp_tov; 548331766Sken uint32_t r_a_tov; 549331766Sken uint32_t r_t_tov; 550331766Sken uint32_t al_tov; 551331766Sken uint32_t rsvd9; 552331766Sken uint32_t :8, 553331766Sken bbscn:4, /** buffer-to-buffer state change number */ 554331766Sken cscn:1, /** configure BBSCN */ 555331766Sken :19; 556331766Sken#else 557331766Sken#error big endian version not defined 558331766Sken#endif 559331766Sken} sli4_cmd_config_link_t; 560331766Sken 561331766Sken/** 562331766Sken * @brief DUMP Type 4 563331766Sken */ 564331766Sken#define SLI4_WKI_TAG_SAT_TEM 0x1040 565331766Skentypedef struct sli4_cmd_dump4_s { 566331766Sken sli4_mbox_command_header_t hdr; 567331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 568331766Sken uint32_t type:4, 569331766Sken :28; 570331766Sken uint32_t wki_selection:16, 571331766Sken :16; 572331766Sken uint32_t resv; 573331766Sken uint32_t returned_byte_cnt; 574331766Sken uint32_t resp_data[59]; 575331766Sken#else 576331766Sken#error big endian version not defined 577331766Sken#endif 578331766Sken} sli4_cmd_dump4_t; 579331766Sken 580331766Sken/** 581331766Sken * @brief FW_INITIALIZE - initialize a SLI port 582331766Sken * 583331766Sken * @note This command uses a different format than all others. 584331766Sken */ 585331766Sken 586331766Skenextern const uint8_t sli4_fw_initialize[8]; 587331766Sken 588331766Sken/** 589331766Sken * @brief FW_DEINITIALIZE - deinitialize a SLI port 590331766Sken * 591331766Sken * @note This command uses a different format than all others. 592331766Sken */ 593331766Sken 594331766Skenextern const uint8_t sli4_fw_deinitialize[8]; 595331766Sken 596331766Sken/** 597331766Sken * @brief INIT_LINK - initialize the link for a FC/FCoE port 598331766Sken */ 599331766Skentypedef struct sli4_cmd_init_link_flags_s { 600331766Sken uint32_t loopback:1, 601331766Sken topology:2, 602331766Sken #define FC_TOPOLOGY_FCAL 0 603331766Sken #define FC_TOPOLOGY_P2P 1 604331766Sken :3, 605331766Sken unfair:1, 606331766Sken skip_lirp_lilp:1, 607331766Sken gen_loop_validity_check:1, 608331766Sken skip_lisa:1, 609331766Sken enable_topology_failover:1, 610331766Sken fixed_speed:1, 611331766Sken :3, 612331766Sken select_hightest_al_pa:1, 613331766Sken :16; /* pad to 32 bits */ 614331766Sken} sli4_cmd_init_link_flags_t; 615331766Sken 616331766Sken#define SLI4_INIT_LINK_F_LOOP_BACK BIT(0) 617331766Sken#define SLI4_INIT_LINK_F_UNFAIR BIT(6) 618331766Sken#define SLI4_INIT_LINK_F_NO_LIRP BIT(7) 619331766Sken#define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8) 620331766Sken#define SLI4_INIT_LINK_F_NO_LISA BIT(9) 621331766Sken#define SLI4_INIT_LINK_F_FAIL_OVER BIT(10) 622331766Sken#define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11) 623331766Sken#define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15) 624331766Sken 625331766Sken#define SLI4_INIT_LINK_F_P2P_ONLY 1 626331766Sken#define SLI4_INIT_LINK_F_FCAL_ONLY 2 627331766Sken 628331766Sken#define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0 629331766Sken#define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1 630331766Sken 631331766Skentypedef struct sli4_cmd_init_link_s { 632331766Sken sli4_mbox_command_header_t hdr; 633331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 634331766Sken uint32_t selective_reset_al_pa:8, 635331766Sken :24; 636331766Sken sli4_cmd_init_link_flags_t link_flags; 637331766Sken uint32_t link_speed_selection_code; 638331766Sken #define FC_LINK_SPEED_1G 1 639331766Sken #define FC_LINK_SPEED_2G 2 640331766Sken #define FC_LINK_SPEED_AUTO_1_2 3 641331766Sken #define FC_LINK_SPEED_4G 4 642331766Sken #define FC_LINK_SPEED_AUTO_4_1 5 643331766Sken #define FC_LINK_SPEED_AUTO_4_2 6 644331766Sken #define FC_LINK_SPEED_AUTO_4_2_1 7 645331766Sken #define FC_LINK_SPEED_8G 8 646331766Sken #define FC_LINK_SPEED_AUTO_8_1 9 647331766Sken #define FC_LINK_SPEED_AUTO_8_2 10 648331766Sken #define FC_LINK_SPEED_AUTO_8_2_1 11 649331766Sken #define FC_LINK_SPEED_AUTO_8_4 12 650331766Sken #define FC_LINK_SPEED_AUTO_8_4_1 13 651331766Sken #define FC_LINK_SPEED_AUTO_8_4_2 14 652331766Sken #define FC_LINK_SPEED_10G 16 653331766Sken #define FC_LINK_SPEED_16G 17 654331766Sken #define FC_LINK_SPEED_AUTO_16_8_4 18 655331766Sken #define FC_LINK_SPEED_AUTO_16_8 19 656331766Sken #define FC_LINK_SPEED_32G 20 657331766Sken #define FC_LINK_SPEED_AUTO_32_16_8 21 658331766Sken #define FC_LINK_SPEED_AUTO_32_16 22 659331766Sken#else 660331766Sken#error big endian version not defined 661331766Sken#endif 662331766Sken} sli4_cmd_init_link_t; 663331766Sken 664331766Sken/** 665331766Sken * @brief INIT_VFI - initialize the VFI resource 666331766Sken */ 667331766Skentypedef struct sli4_cmd_init_vfi_s { 668331766Sken sli4_mbox_command_header_t hdr; 669331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 670331766Sken uint32_t vfi:16, 671331766Sken :12, 672331766Sken vp:1, 673331766Sken vf:1, 674331766Sken vt:1, 675331766Sken vr:1; 676331766Sken uint32_t fcfi:16, 677331766Sken vpi:16; 678331766Sken uint32_t vf_id:13, 679331766Sken pri:3, 680331766Sken :16; 681331766Sken uint32_t :24, 682331766Sken hop_count:8; 683331766Sken#else 684331766Sken#error big endian version not defined 685331766Sken#endif 686331766Sken} sli4_cmd_init_vfi_t; 687331766Sken 688331766Sken/** 689331766Sken * @brief INIT_VPI - initialize the VPI resource 690331766Sken */ 691331766Skentypedef struct sli4_cmd_init_vpi_s { 692331766Sken sli4_mbox_command_header_t hdr; 693331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 694331766Sken uint32_t vpi:16, 695331766Sken vfi:16; 696331766Sken#else 697331766Sken#error big endian version not defined 698331766Sken#endif 699331766Sken} sli4_cmd_init_vpi_t; 700331766Sken 701331766Sken/** 702331766Sken * @brief POST_XRI - post XRI resources to the SLI Port 703331766Sken */ 704331766Skentypedef struct sli4_cmd_post_xri_s { 705331766Sken sli4_mbox_command_header_t hdr; 706331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 707331766Sken uint32_t xri_base:16, 708331766Sken xri_count:12, 709331766Sken enx:1, 710331766Sken dl:1, 711331766Sken di:1, 712331766Sken val:1; 713331766Sken#else 714331766Sken#error big endian version not defined 715331766Sken#endif 716331766Sken} sli4_cmd_post_xri_t; 717331766Sken 718331766Sken/** 719331766Sken * @brief RELEASE_XRI - Release XRI resources from the SLI Port 720331766Sken */ 721331766Skentypedef struct sli4_cmd_release_xri_s { 722331766Sken sli4_mbox_command_header_t hdr; 723331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 724331766Sken uint32_t released_xri_count:5, 725331766Sken :11, 726331766Sken xri_count:5, 727331766Sken :11; 728331766Sken struct { 729331766Sken uint32_t xri_tag0:16, 730331766Sken xri_tag1:16; 731331766Sken } xri_tbl[62]; 732331766Sken#else 733331766Sken#error big endian version not defined 734331766Sken#endif 735331766Sken} sli4_cmd_release_xri_t; 736331766Sken 737331766Sken/** 738331766Sken * @brief READ_CONFIG - read SLI port configuration parameters 739331766Sken */ 740331766Skentypedef struct sli4_cmd_read_config_s { 741331766Sken sli4_mbox_command_header_t hdr; 742331766Sken} sli4_cmd_read_config_t; 743331766Sken 744331766Skentypedef struct sli4_res_read_config_s { 745331766Sken sli4_mbox_command_header_t hdr; 746331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 747331766Sken uint32_t :31, 748331766Sken ext:1; /** Resource Extents */ 749331766Sken uint32_t :24, 750331766Sken topology:8; 751331766Sken uint32_t rsvd3; 752331766Sken uint32_t e_d_tov:16, 753331766Sken :16; 754331766Sken uint32_t rsvd5; 755331766Sken uint32_t r_a_tov:16, 756331766Sken :16; 757331766Sken uint32_t rsvd7; 758331766Sken uint32_t rsvd8; 759331766Sken uint32_t lmt:16, /** Link Module Type */ 760331766Sken :16; 761331766Sken uint32_t rsvd10; 762331766Sken uint32_t rsvd11; 763331766Sken uint32_t xri_base:16, 764331766Sken xri_count:16; 765331766Sken uint32_t rpi_base:16, 766331766Sken rpi_count:16; 767331766Sken uint32_t vpi_base:16, 768331766Sken vpi_count:16; 769331766Sken uint32_t vfi_base:16, 770331766Sken vfi_count:16; 771331766Sken uint32_t :16, 772331766Sken fcfi_count:16; 773331766Sken uint32_t rq_count:16, 774331766Sken eq_count:16; 775331766Sken uint32_t wq_count:16, 776331766Sken cq_count:16; 777331766Sken uint32_t pad[45]; 778331766Sken#else 779331766Sken#error big endian version not defined 780331766Sken#endif 781331766Sken} sli4_res_read_config_t; 782331766Sken 783331766Sken#define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */ 784331766Sken#define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */ 785331766Sken#define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */ 786331766Sken#define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */ 787331766Sken 788331766Sken/** 789331766Sken * @brief READ_NVPARMS - read SLI port configuration parameters 790331766Sken */ 791331766Skentypedef struct sli4_cmd_read_nvparms_s { 792331766Sken sli4_mbox_command_header_t hdr; 793331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 794331766Sken uint32_t rsvd1; 795331766Sken uint32_t rsvd2; 796331766Sken uint32_t rsvd3; 797331766Sken uint32_t rsvd4; 798331766Sken uint8_t wwpn[8]; 799331766Sken uint8_t wwnn[8]; 800331766Sken uint32_t hard_alpa:8, 801331766Sken preferred_d_id:24; 802331766Sken#else 803331766Sken#error big endian version not defined 804331766Sken#endif 805331766Sken} sli4_cmd_read_nvparms_t; 806331766Sken 807331766Sken/** 808331766Sken * @brief WRITE_NVPARMS - write SLI port configuration parameters 809331766Sken */ 810331766Skentypedef struct sli4_cmd_write_nvparms_s { 811331766Sken sli4_mbox_command_header_t hdr; 812331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 813331766Sken uint32_t rsvd1; 814331766Sken uint32_t rsvd2; 815331766Sken uint32_t rsvd3; 816331766Sken uint32_t rsvd4; 817331766Sken uint8_t wwpn[8]; 818331766Sken uint8_t wwnn[8]; 819331766Sken uint32_t hard_alpa:8, 820331766Sken preferred_d_id:24; 821331766Sken#else 822331766Sken#error big endian version not defined 823331766Sken#endif 824331766Sken} sli4_cmd_write_nvparms_t; 825331766Sken 826331766Sken/** 827331766Sken * @brief READ_REV - read the Port revision levels 828331766Sken */ 829331766Skentypedef struct sli4_cmd_read_rev_s { 830331766Sken sli4_mbox_command_header_t hdr; 831331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 832331766Sken uint32_t :16, 833331766Sken sli_level:4, 834331766Sken fcoem:1, 835331766Sken ceev:2, 836331766Sken :6, 837331766Sken vpd:1, 838331766Sken :2; 839331766Sken uint32_t first_hw_revision; 840331766Sken uint32_t second_hw_revision; 841331766Sken uint32_t rsvd4; 842331766Sken uint32_t third_hw_revision; 843331766Sken uint32_t fc_ph_low:8, 844331766Sken fc_ph_high:8, 845331766Sken feature_level_low:8, 846331766Sken feature_level_high:8; 847331766Sken uint32_t rsvd7; 848331766Sken uint32_t first_fw_id; 849331766Sken char first_fw_name[16]; 850331766Sken uint32_t second_fw_id; 851331766Sken char second_fw_name[16]; 852331766Sken uint32_t rsvd18[30]; 853331766Sken uint32_t available_length:24, 854331766Sken :8; 855331766Sken uint32_t physical_address_low; 856331766Sken uint32_t physical_address_high; 857331766Sken uint32_t returned_vpd_length; 858331766Sken uint32_t actual_vpd_length; 859331766Sken#else 860331766Sken#error big endian version not defined 861331766Sken#endif 862331766Sken} sli4_cmd_read_rev_t; 863331766Sken 864331766Sken/** 865331766Sken * @brief READ_SPARM64 - read the Port service parameters 866331766Sken */ 867331766Skentypedef struct sli4_cmd_read_sparm64_s { 868331766Sken sli4_mbox_command_header_t hdr; 869331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 870331766Sken uint32_t rsvd1; 871331766Sken uint32_t rsvd2; 872331766Sken sli4_bde_t bde_64; 873331766Sken uint32_t vpi:16, 874331766Sken :16; 875331766Sken uint32_t port_name_start:16, 876331766Sken port_name_length:16; 877331766Sken uint32_t node_name_start:16, 878331766Sken node_name_length:16; 879331766Sken#else 880331766Sken#error big endian version not defined 881331766Sken#endif 882331766Sken} sli4_cmd_read_sparm64_t; 883331766Sken 884331766Sken#define SLI4_READ_SPARM64_VPI_DEFAULT 0 885331766Sken#define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX 886331766Sken 887331766Sken#define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t)) 888331766Sken#define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t)) 889331766Sken 890331766Skentypedef struct sli4_port_state_s { 891331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 892331766Sken uint32_t nx_port_recv_state:2, 893331766Sken nx_port_trans_state:2, 894331766Sken nx_port_state_machine:4, 895331766Sken link_speed:8, 896331766Sken :14, 897331766Sken tf:1, 898331766Sken lu:1; 899331766Sken#else 900331766Sken#error big endian version not defined 901331766Sken#endif 902331766Sken} sli4_port_state_t; 903331766Sken 904331766Sken/** 905331766Sken * @brief READ_TOPOLOGY - read the link event information 906331766Sken */ 907331766Skentypedef struct sli4_cmd_read_topology_s { 908331766Sken sli4_mbox_command_header_t hdr; 909331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 910331766Sken uint32_t event_tag; 911331766Sken uint32_t attention_type:8, 912331766Sken il:1, 913331766Sken pb_recvd:1, 914331766Sken :22; 915331766Sken uint32_t topology:8, 916331766Sken lip_type:8, 917331766Sken lip_al_ps:8, 918331766Sken al_pa_granted:8; 919331766Sken sli4_bde_t bde_loop_map; 920331766Sken sli4_port_state_t link_down; 921331766Sken sli4_port_state_t link_current; 922331766Sken uint32_t max_bbc:8, 923331766Sken init_bbc:8, 924331766Sken bbscn:4, 925331766Sken cbbscn:4, 926331766Sken :8; 927331766Sken uint32_t r_t_tov:9, 928331766Sken :3, 929331766Sken al_tov:4, 930331766Sken lp_tov:16; 931331766Sken uint32_t acquired_al_pa:8, 932331766Sken :7, 933331766Sken pb:1, 934331766Sken specified_al_pa:16; 935331766Sken uint32_t initial_n_port_id:24, 936331766Sken :8; 937331766Sken#else 938331766Sken#error big endian version not defined 939331766Sken#endif 940331766Sken} sli4_cmd_read_topology_t; 941331766Sken 942331766Sken#define SLI4_MIN_LOOP_MAP_BYTES 128 943331766Sken 944331766Sken#define SLI4_READ_TOPOLOGY_LINK_UP 0x1 945331766Sken#define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2 946331766Sken#define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3 947331766Sken 948331766Sken#define SLI4_READ_TOPOLOGY_UNKNOWN 0x0 949331766Sken#define SLI4_READ_TOPOLOGY_NPORT 0x1 950331766Sken#define SLI4_READ_TOPOLOGY_FC_AL 0x2 951331766Sken 952331766Sken#define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00 953331766Sken#define SLI4_READ_TOPOLOGY_SPEED_1G 0x04 954331766Sken#define SLI4_READ_TOPOLOGY_SPEED_2G 0x08 955331766Sken#define SLI4_READ_TOPOLOGY_SPEED_4G 0x10 956331766Sken#define SLI4_READ_TOPOLOGY_SPEED_8G 0x20 957331766Sken#define SLI4_READ_TOPOLOGY_SPEED_10G 0x40 958331766Sken#define SLI4_READ_TOPOLOGY_SPEED_16G 0x80 959331766Sken#define SLI4_READ_TOPOLOGY_SPEED_32G 0x90 960331766Sken 961331766Sken/** 962331766Sken * @brief REG_FCFI - activate a FC Forwarder 963331766Sken */ 964331766Sken#define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4 965331766Skentypedef struct sli4_cmd_reg_fcfi_s { 966331766Sken sli4_mbox_command_header_t hdr; 967331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 968331766Sken uint32_t fcf_index:16, 969331766Sken fcfi:16; 970331766Sken uint32_t rq_id_1:16, 971331766Sken rq_id_0:16; 972331766Sken uint32_t rq_id_3:16, 973331766Sken rq_id_2:16; 974331766Sken struct { 975331766Sken uint32_t r_ctl_mask:8, 976331766Sken r_ctl_match:8, 977331766Sken type_mask:8, 978331766Sken type_match:8; 979331766Sken } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]; 980331766Sken uint32_t vlan_tag:12, 981331766Sken vv:1, 982331766Sken :19; 983331766Sken#else 984331766Sken#error big endian version not defined 985331766Sken#endif 986331766Sken} sli4_cmd_reg_fcfi_t; 987331766Sken 988331766Sken#define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4 989331766Sken#define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32 990331766Sken#define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0 991331766Sken#define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1 992331766Sken 993331766Skentypedef struct sli4_cmd_reg_fcfi_mrq_s { 994331766Sken sli4_mbox_command_header_t hdr; 995331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 996331766Sken uint32_t fcf_index:16, 997331766Sken fcfi:16; 998331766Sken 999331766Sken uint32_t rq_id_1:16, 1000331766Sken rq_id_0:16; 1001331766Sken 1002331766Sken uint32_t rq_id_3:16, 1003331766Sken rq_id_2:16; 1004331766Sken 1005331766Sken struct { 1006331766Sken uint32_t r_ctl_mask:8, 1007331766Sken r_ctl_match:8, 1008331766Sken type_mask:8, 1009331766Sken type_match:8; 1010331766Sken } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG]; 1011331766Sken 1012331766Sken uint32_t vlan_tag:12, 1013331766Sken vv:1, 1014331766Sken mode:1, 1015331766Sken :18; 1016331766Sken 1017331766Sken uint32_t num_mrq_pairs:8, 1018331766Sken mrq_filter_bitmask:4, 1019331766Sken rq_selection_policy:4, 1020331766Sken :16; 1021331766Sken#endif 1022331766Sken} sli4_cmd_reg_fcfi_mrq_t; 1023331766Sken 1024331766Sken/** 1025331766Sken * @brief REG_RPI - register a Remote Port Indicator 1026331766Sken */ 1027331766Skentypedef struct sli4_cmd_reg_rpi_s { 1028331766Sken sli4_mbox_command_header_t hdr; 1029331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1030331766Sken uint32_t rpi:16, 1031331766Sken :16; 1032331766Sken uint32_t remote_n_port_id:24, 1033331766Sken upd:1, 1034331766Sken :2, 1035331766Sken etow:1, 1036331766Sken :1, 1037331766Sken terp:1, 1038331766Sken :1, 1039331766Sken ci:1; 1040331766Sken sli4_bde_t bde_64; 1041331766Sken uint32_t vpi:16, 1042331766Sken :16; 1043331766Sken#else 1044331766Sken#error big endian version not defined 1045331766Sken#endif 1046331766Sken} sli4_cmd_reg_rpi_t; 1047331766Sken#define SLI4_REG_RPI_BUF_LEN 0x70 1048331766Sken 1049331766Sken 1050331766Sken/** 1051331766Sken * @brief REG_VFI - register a Virtual Fabric Indicator 1052331766Sken */ 1053331766Skentypedef struct sli4_cmd_reg_vfi_s { 1054331766Sken sli4_mbox_command_header_t hdr; 1055331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1056331766Sken uint32_t vfi:16, 1057331766Sken :12, 1058331766Sken vp:1, 1059331766Sken upd:1, 1060331766Sken :2; 1061331766Sken uint32_t fcfi:16, 1062331766Sken vpi:16; /* vp=TRUE */ 1063331766Sken uint8_t wwpn[8]; /* vp=TRUE */ 1064331766Sken sli4_bde_t sparm; /* either FLOGI or PLOGI */ 1065331766Sken uint32_t e_d_tov; 1066331766Sken uint32_t r_a_tov; 1067331766Sken uint32_t local_n_port_id:24, /* vp=TRUE */ 1068331766Sken :8; 1069331766Sken#else 1070331766Sken#error big endian version not defined 1071331766Sken#endif 1072331766Sken} sli4_cmd_reg_vfi_t; 1073331766Sken 1074331766Sken/** 1075331766Sken * @brief REG_VPI - register a Virtual Port Indicator 1076331766Sken */ 1077331766Skentypedef struct sli4_cmd_reg_vpi_s { 1078331766Sken sli4_mbox_command_header_t hdr; 1079331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1080331766Sken uint32_t rsvd1; 1081331766Sken uint32_t local_n_port_id:24, 1082331766Sken upd:1, 1083331766Sken :7; 1084331766Sken uint8_t wwpn[8]; 1085331766Sken uint32_t rsvd5; 1086331766Sken uint32_t vpi:16, 1087331766Sken vfi:16; 1088331766Sken#else 1089331766Sken#error big endian version not defined 1090331766Sken#endif 1091331766Sken} sli4_cmd_reg_vpi_t; 1092331766Sken 1093331766Sken/** 1094331766Sken * @brief REQUEST_FEATURES - request / query SLI features 1095331766Sken */ 1096331766Skentypedef union { 1097331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1098331766Sken struct { 1099331766Sken uint32_t iaab:1, /** inhibit auto-ABTS originator */ 1100331766Sken npiv:1, /** NPIV support */ 1101331766Sken dif:1, /** DIF/DIX support */ 1102331766Sken vf:1, /** virtual fabric support */ 1103331766Sken fcpi:1, /** FCP initiator support */ 1104331766Sken fcpt:1, /** FCP target support */ 1105331766Sken fcpc:1, /** combined FCP initiator/target */ 1106331766Sken :1, 1107331766Sken rqd:1, /** recovery qualified delay */ 1108331766Sken iaar:1, /** inhibit auto-ABTS responder */ 1109331766Sken hlm:1, /** High Login Mode */ 1110331766Sken perfh:1, /** performance hints */ 1111331766Sken rxseq:1, /** RX Sequence Coalescing */ 1112331766Sken rxri:1, /** Release XRI variant of Coalescing */ 1113331766Sken dcl2:1, /** Disable Class 2 */ 1114331766Sken rsco:1, /** Receive Sequence Coalescing Optimizations */ 1115331766Sken mrqp:1, /** Multi RQ Pair Mode Support */ 1116331766Sken :15; 1117331766Sken } flag; 1118331766Sken uint32_t dword; 1119331766Sken#else 1120331766Sken#error big endian version not defined 1121331766Sken#endif 1122331766Sken} sli4_features_t; 1123331766Sken 1124331766Skentypedef struct sli4_cmd_request_features_s { 1125331766Sken sli4_mbox_command_header_t hdr; 1126331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1127331766Sken uint32_t qry:1, 1128331766Sken :31; 1129331766Sken#else 1130331766Sken#error big endian version not defined 1131331766Sken#endif 1132331766Sken sli4_features_t command; 1133331766Sken sli4_features_t response; 1134331766Sken} sli4_cmd_request_features_t; 1135331766Sken 1136331766Sken/** 1137331766Sken * @brief SLI_CONFIG - submit a configuration command to Port 1138331766Sken * 1139331766Sken * Command is either embedded as part of the payload (embed) or located 1140331766Sken * in a separate memory buffer (mem) 1141331766Sken */ 1142331766Sken 1143331766Sken 1144331766Skentypedef struct sli4_sli_config_pmd_s { 1145331766Sken uint32_t address_low; 1146331766Sken uint32_t address_high; 1147331766Sken uint32_t length:24, 1148331766Sken :8; 1149331766Sken} sli4_sli_config_pmd_t; 1150331766Sken 1151331766Skentypedef struct sli4_cmd_sli_config_s { 1152331766Sken sli4_mbox_command_header_t hdr; 1153331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1154331766Sken uint32_t emb:1, 1155331766Sken :2, 1156331766Sken pmd_count:5, 1157331766Sken :24; 1158331766Sken uint32_t payload_length; 1159331766Sken uint32_t rsvd3; 1160331766Sken uint32_t rsvd4; 1161331766Sken uint32_t rsvd5; 1162331766Sken union { 1163331766Sken uint8_t embed[58 * sizeof(uint32_t)]; 1164331766Sken sli4_sli_config_pmd_t mem; 1165331766Sken } payload; 1166331766Sken#else 1167331766Sken#error big endian version not defined 1168331766Sken#endif 1169331766Sken} sli4_cmd_sli_config_t; 1170331766Sken 1171331766Sken/** 1172331766Sken * @brief READ_STATUS - read tx/rx status of a particular port 1173331766Sken * 1174331766Sken */ 1175331766Sken 1176331766Skentypedef struct sli4_cmd_read_status_s { 1177331766Sken sli4_mbox_command_header_t hdr; 1178331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1179331766Sken uint32_t cc:1, 1180331766Sken :31; 1181331766Sken uint32_t rsvd2; 1182331766Sken uint32_t transmit_kbyte_count; 1183331766Sken uint32_t receive_kbyte_count; 1184331766Sken uint32_t transmit_frame_count; 1185331766Sken uint32_t receive_frame_count; 1186331766Sken uint32_t transmit_sequence_count; 1187331766Sken uint32_t receive_sequence_count; 1188331766Sken uint32_t total_exchanges_originator; 1189331766Sken uint32_t total_exchanges_responder; 1190331766Sken uint32_t receive_p_bsy_count; 1191331766Sken uint32_t receive_f_bsy_count; 1192331766Sken uint32_t dropped_frames_due_to_no_rq_buffer_count; 1193331766Sken uint32_t empty_rq_timeout_count; 1194331766Sken uint32_t dropped_frames_due_to_no_xri_count; 1195331766Sken uint32_t empty_xri_pool_count; 1196331766Sken 1197331766Sken#else 1198331766Sken#error big endian version not defined 1199331766Sken#endif 1200331766Sken} sli4_cmd_read_status_t; 1201331766Sken 1202331766Sken/** 1203331766Sken * @brief READ_LNK_STAT - read link status of a particular port 1204331766Sken * 1205331766Sken */ 1206331766Sken 1207331766Skentypedef struct sli4_cmd_read_link_stats_s { 1208331766Sken sli4_mbox_command_header_t hdr; 1209331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1210331766Sken uint32_t rec:1, 1211331766Sken gec:1, 1212331766Sken w02of:1, 1213331766Sken w03of:1, 1214331766Sken w04of:1, 1215331766Sken w05of:1, 1216331766Sken w06of:1, 1217331766Sken w07of:1, 1218331766Sken w08of:1, 1219331766Sken w09of:1, 1220331766Sken w10of:1, 1221331766Sken w11of:1, 1222331766Sken w12of:1, 1223331766Sken w13of:1, 1224331766Sken w14of:1, 1225331766Sken w15of:1, 1226331766Sken w16of:1, 1227331766Sken w17of:1, 1228331766Sken w18of:1, 1229331766Sken w19of:1, 1230331766Sken w20of:1, 1231331766Sken w21of:1, 1232331766Sken resv0:8, 1233331766Sken clrc:1, 1234331766Sken clof:1; 1235331766Sken uint32_t link_failure_error_count; 1236331766Sken uint32_t loss_of_sync_error_count; 1237331766Sken uint32_t loss_of_signal_error_count; 1238331766Sken uint32_t primitive_sequence_error_count; 1239331766Sken uint32_t invalid_transmission_word_error_count; 1240331766Sken uint32_t crc_error_count; 1241331766Sken uint32_t primitive_sequence_event_timeout_count; 1242331766Sken uint32_t elastic_buffer_overrun_error_count; 1243331766Sken uint32_t arbitration_fc_al_timout_count; 1244331766Sken uint32_t advertised_receive_bufftor_to_buffer_credit; 1245331766Sken uint32_t current_receive_buffer_to_buffer_credit; 1246331766Sken uint32_t advertised_transmit_buffer_to_buffer_credit; 1247331766Sken uint32_t current_transmit_buffer_to_buffer_credit; 1248331766Sken uint32_t received_eofa_count; 1249331766Sken uint32_t received_eofdti_count; 1250331766Sken uint32_t received_eofni_count; 1251331766Sken uint32_t received_soff_count; 1252331766Sken uint32_t received_dropped_no_aer_count; 1253331766Sken uint32_t received_dropped_no_available_rpi_resources_count; 1254331766Sken uint32_t received_dropped_no_available_xri_resources_count; 1255331766Sken 1256331766Sken#else 1257331766Sken#error big endian version not defined 1258331766Sken#endif 1259331766Sken} sli4_cmd_read_link_stats_t; 1260331766Sken 1261331766Sken/** 1262331766Sken * @brief Format a WQE with WQ_ID Association performance hint 1263331766Sken * 1264331766Sken * @par Description 1265331766Sken * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID. 1266331766Sken * 1267331766Sken * @param entry Pointer to the WQE. 1268331766Sken * @param q_id Queue ID. 1269331766Sken * 1270331766Sken * @return None. 1271331766Sken */ 1272331766Skenstatic inline void 1273331766Skensli_set_wq_id_association(void *entry, uint16_t q_id) 1274331766Sken{ 1275331766Sken uint32_t *wqe = entry; 1276331766Sken 1277331766Sken /* 1278331766Sken * Set Word 10, bit 0 to zero 1279331766Sken * Set Word 10, bits 15:1 to the WQ ID 1280331766Sken */ 1281331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1282331766Sken wqe[10] &= ~0xffff; 1283331766Sken wqe[10] |= q_id << 1; 1284331766Sken#else 1285331766Sken#error big endian version not defined 1286331766Sken#endif 1287331766Sken} 1288331766Sken 1289331766Sken/** 1290331766Sken * @brief UNREG_FCFI - unregister a FCFI 1291331766Sken */ 1292331766Skentypedef struct sli4_cmd_unreg_fcfi_s { 1293331766Sken sli4_mbox_command_header_t hdr; 1294331766Sken uint32_t rsvd1; 1295331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1296331766Sken uint32_t fcfi:16, 1297331766Sken :16; 1298331766Sken#else 1299331766Sken#error big endian version not defined 1300331766Sken#endif 1301331766Sken} sli4_cmd_unreg_fcfi_t; 1302331766Sken 1303331766Sken/** 1304331766Sken * @brief UNREG_RPI - unregister one or more RPI 1305331766Sken */ 1306331766Skentypedef struct sli4_cmd_unreg_rpi_s { 1307331766Sken sli4_mbox_command_header_t hdr; 1308331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1309331766Sken uint32_t index:16, 1310331766Sken :13, 1311331766Sken dp:1, 1312331766Sken ii:2; 1313331766Sken uint32_t destination_n_port_id:24, 1314331766Sken :8; 1315331766Sken#else 1316331766Sken#error big endian version not defined 1317331766Sken#endif 1318331766Sken} sli4_cmd_unreg_rpi_t; 1319331766Sken 1320331766Sken#define SLI4_UNREG_RPI_II_RPI 0x0 1321331766Sken#define SLI4_UNREG_RPI_II_VPI 0x1 1322331766Sken#define SLI4_UNREG_RPI_II_VFI 0x2 1323331766Sken#define SLI4_UNREG_RPI_II_FCFI 0x3 1324331766Sken 1325331766Sken/** 1326331766Sken * @brief UNREG_VFI - unregister one or more VFI 1327331766Sken */ 1328331766Skentypedef struct sli4_cmd_unreg_vfi_s { 1329331766Sken sli4_mbox_command_header_t hdr; 1330331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1331331766Sken uint32_t rsvd1; 1332331766Sken uint32_t index:16, 1333331766Sken :14, 1334331766Sken ii:2; 1335331766Sken#else 1336331766Sken#error big endian version not defined 1337331766Sken#endif 1338331766Sken} sli4_cmd_unreg_vfi_t; 1339331766Sken 1340331766Sken#define SLI4_UNREG_VFI_II_VFI 0x0 1341331766Sken#define SLI4_UNREG_VFI_II_FCFI 0x3 1342331766Sken 1343331766Skenenum { 1344331766Sken SLI4_UNREG_TYPE_PORT, 1345331766Sken SLI4_UNREG_TYPE_DOMAIN, 1346331766Sken SLI4_UNREG_TYPE_FCF, 1347331766Sken SLI4_UNREG_TYPE_ALL 1348331766Sken}; 1349331766Sken 1350331766Sken/** 1351331766Sken * @brief UNREG_VPI - unregister one or more VPI 1352331766Sken */ 1353331766Skentypedef struct sli4_cmd_unreg_vpi_s { 1354331766Sken sli4_mbox_command_header_t hdr; 1355331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1356331766Sken uint32_t rsvd1; 1357331766Sken uint32_t index:16, 1358331766Sken :14, 1359331766Sken ii:2; 1360331766Sken#else 1361331766Sken#error big endian version not defined 1362331766Sken#endif 1363331766Sken} sli4_cmd_unreg_vpi_t; 1364331766Sken 1365331766Sken#define SLI4_UNREG_VPI_II_VPI 0x0 1366331766Sken#define SLI4_UNREG_VPI_II_VFI 0x2 1367331766Sken#define SLI4_UNREG_VPI_II_FCFI 0x3 1368331766Sken 1369331766Sken 1370331766Sken/** 1371331766Sken * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature. 1372331766Sken */ 1373331766Skentypedef struct sli4_cmd_config_auto_xfer_rdy_s { 1374331766Sken sli4_mbox_command_header_t hdr; 1375331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1376331766Sken uint32_t resv; 1377331766Sken uint32_t max_burst_len; 1378331766Sken#else 1379331766Sken#error big endian version not defined 1380331766Sken#endif 1381331766Sken} sli4_cmd_config_auto_xfer_rdy_t; 1382331766Sken 1383331766Skentypedef struct sli4_cmd_config_auto_xfer_rdy_hp_s { 1384331766Sken sli4_mbox_command_header_t hdr; 1385331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1386331766Sken uint32_t resv; 1387331766Sken uint32_t max_burst_len; 1388331766Sken uint32_t esoc:1, 1389331766Sken :31; 1390331766Sken uint32_t block_size:16, 1391331766Sken :16; 1392331766Sken#else 1393331766Sken#error big endian version not defined 1394331766Sken#endif 1395331766Sken} sli4_cmd_config_auto_xfer_rdy_hp_t; 1396331766Sken 1397331766Sken 1398331766Sken/************************************************************************* 1399331766Sken * SLI-4 common configuration command formats and definitions 1400331766Sken */ 1401331766Sken 1402331766Sken#define SLI4_CFG_STATUS_SUCCESS 0x00 1403331766Sken#define SLI4_CFG_STATUS_FAILED 0x01 1404331766Sken#define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02 1405331766Sken#define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03 1406331766Sken 1407331766Sken#define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb 1408331766Sken 1409331766Sken#define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00 1410331766Sken#define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e 1411331766Sken 1412331766Sken/** 1413331766Sken * Subsystem values. 1414331766Sken */ 1415331766Sken#define SLI4_SUBSYSTEM_COMMON 0x01 1416331766Sken#define SLI4_SUBSYSTEM_LOWLEVEL 0x0B 1417331766Sken#define SLI4_SUBSYSTEM_FCFCOE 0x0c 1418331766Sken#define SLI4_SUBSYSTEM_DMTF 0x11 1419331766Sken 1420331766Sken#define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36 1421331766Sken 1422331766Sken/** 1423331766Sken * Common opcode (OPC) values. 1424331766Sken */ 1425331766Sken#define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d 1426331766Sken#define SLI4_OPC_COMMON_CREATE_CQ 0x0c 1427331766Sken#define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d 1428331766Sken#define SLI4_OPC_COMMON_DESTROY_CQ 0x36 1429331766Sken#define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29 1430331766Sken#define SLI4_OPC_COMMON_CREATE_EQ 0x0d 1431331766Sken#define SLI4_OPC_COMMON_DESTROY_EQ 0x37 1432331766Sken#define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a 1433331766Sken#define SLI4_OPC_COMMON_DESTROY_MQ 0x35 1434331766Sken#define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20 1435331766Sken#define SLI4_OPC_COMMON_NOP 0x21 1436331766Sken#define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a 1437331766Sken#define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5 1438331766Sken#define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a 1439331766Sken#define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d 1440331766Sken 1441331766Sken#define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07 1442331766Sken#define SLI4_OPC_COMMON_MANAGE_FAT 0x44 1443331766Sken#define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49 1444331766Sken#define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79 1445331766Sken#define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d 1446331766Sken#define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e 1447331766Sken#define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f 1448331766Sken#define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80 1449331766Sken#define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82 1450331766Sken#define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0 1451331766Sken#define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4 1452331766Sken#define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5 1453331766Sken#define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6 1454331766Sken#define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7 1455331766Sken#define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8 1456331766Sken#define SLI4_OPC_COMMON_READ_OBJECT 0xab 1457331766Sken#define SLI4_OPC_COMMON_WRITE_OBJECT 0xac 1458331766Sken#define SLI4_OPC_COMMON_DELETE_OBJECT 0xae 1459331766Sken#define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad 1460331766Sken#define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8 1461331766Sken#define SLI4_OPC_COMMON_SET_FEATURES 0xbf 1462331766Sken#define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9 1463331766Sken#define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca 1464331766Sken 1465331766Sken/** 1466331766Sken * DMTF opcode (OPC) values. 1467331766Sken */ 1468331766Sken#define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01 1469331766Sken 1470331766Sken/** 1471331766Sken * @brief Generic Command Request header 1472331766Sken */ 1473331766Skentypedef struct sli4_req_hdr_s { 1474331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1475331766Sken uint32_t opcode:8, 1476331766Sken subsystem:8, 1477331766Sken :16; 1478331766Sken uint32_t timeout; 1479331766Sken uint32_t request_length; 1480331766Sken uint32_t version:8, 1481331766Sken :24; 1482331766Sken#else 1483331766Sken#error big endian version not defined 1484331766Sken#endif 1485331766Sken} sli4_req_hdr_t; 1486331766Sken 1487331766Sken/** 1488331766Sken * @brief Generic Command Response header 1489331766Sken */ 1490331766Skentypedef struct sli4_res_hdr_s { 1491331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1492331766Sken uint32_t opcode:8, 1493331766Sken subsystem:8, 1494331766Sken :16; 1495331766Sken uint32_t status:8, 1496331766Sken additional_status:8, 1497331766Sken :16; 1498331766Sken uint32_t response_length; 1499331766Sken uint32_t actual_response_length; 1500331766Sken#else 1501331766Sken#error big endian version not defined 1502331766Sken#endif 1503331766Sken} sli4_res_hdr_t; 1504331766Sken 1505331766Sken/** 1506331766Sken * @brief COMMON_FUNCTION_RESET 1507331766Sken * 1508331766Sken * Resets the Port, returning it to a power-on state. This configuration 1509331766Sken * command does not have a payload and should set/expect the lengths to 1510331766Sken * be zero. 1511331766Sken */ 1512331766Skentypedef struct sli4_req_common_function_reset_s { 1513331766Sken sli4_req_hdr_t hdr; 1514331766Sken} sli4_req_common_function_reset_t; 1515331766Sken 1516331766Sken 1517331766Skentypedef struct sli4_res_common_function_reset_s { 1518331766Sken sli4_res_hdr_t hdr; 1519331766Sken} sli4_res_common_function_reset_t; 1520331766Sken 1521331766Sken/** 1522331766Sken * @brief COMMON_CREATE_CQ_V0 1523331766Sken * 1524331766Sken * Create a Completion Queue. 1525331766Sken */ 1526331766Skentypedef struct sli4_req_common_create_cq_v0_s { 1527331766Sken sli4_req_hdr_t hdr; 1528331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1529331766Sken uint32_t num_pages:16, 1530331766Sken :16; 1531331766Sken uint32_t :12, 1532331766Sken clswm:2, 1533331766Sken nodelay:1, 1534331766Sken :12, 1535331766Sken cqecnt:2, 1536331766Sken valid:1, 1537331766Sken :1, 1538331766Sken evt:1; 1539331766Sken uint32_t :22, 1540331766Sken eq_id:8, 1541331766Sken :1, 1542331766Sken arm:1; 1543331766Sken uint32_t rsvd[2]; 1544331766Sken struct { 1545331766Sken uint32_t low; 1546331766Sken uint32_t high; 1547331766Sken } page_physical_address[0]; 1548331766Sken#else 1549331766Sken#error big endian version not defined 1550331766Sken#endif 1551331766Sken} sli4_req_common_create_cq_v0_t; 1552331766Sken 1553331766Sken/** 1554331766Sken * @brief COMMON_CREATE_CQ_V2 1555331766Sken * 1556331766Sken * Create a Completion Queue. 1557331766Sken */ 1558331766Skentypedef struct sli4_req_common_create_cq_v2_s { 1559331766Sken sli4_req_hdr_t hdr; 1560331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1561331766Sken uint32_t num_pages:16, 1562331766Sken page_size:8, 1563331766Sken :8, 1564331766Sken uint32_t :12, 1565331766Sken clswm:2, 1566331766Sken nodelay:1, 1567331766Sken autovalid:1, 1568331766Sken :11, 1569331766Sken cqecnt:2, 1570331766Sken valid:1, 1571331766Sken :1, 1572331766Sken evt:1; 1573331766Sken uint32_t eq_id:16, 1574331766Sken :15, 1575331766Sken arm:1; 1576331766Sken uint32_t cqe_count:16, 1577331766Sken :16; 1578331766Sken uint32_t rsvd[1]; 1579331766Sken struct { 1580331766Sken uint32_t low; 1581331766Sken uint32_t high; 1582331766Sken } page_physical_address[0]; 1583331766Sken#else 1584331766Sken#error big endian version not defined 1585331766Sken#endif 1586331766Sken} sli4_req_common_create_cq_v2_t; 1587331766Sken 1588331766Sken 1589331766Sken 1590331766Sken/** 1591331766Sken * @brief COMMON_CREATE_CQ_SET_V0 1592331766Sken * 1593331766Sken * Create a set of Completion Queues. 1594331766Sken */ 1595331766Skentypedef struct sli4_req_common_create_cq_set_v0_s { 1596331766Sken sli4_req_hdr_t hdr; 1597331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1598331766Sken uint32_t num_pages:16, 1599331766Sken page_size:8, 1600331766Sken :8; 1601331766Sken uint32_t :12, 1602331766Sken clswm:2, 1603331766Sken nodelay:1, 1604331766Sken autovalid:1, 1605331766Sken rsvd:11, 1606331766Sken cqecnt:2, 1607331766Sken valid:1, 1608331766Sken :1, 1609331766Sken evt:1; 1610331766Sken uint32_t num_cq_req:16, 1611331766Sken cqe_count:15, 1612331766Sken arm:1; 1613331766Sken uint16_t eq_id[16]; 1614331766Sken struct { 1615331766Sken uint32_t low; 1616331766Sken uint32_t high; 1617331766Sken } page_physical_address[0]; 1618331766Sken#else 1619331766Sken#error big endian version not defined 1620331766Sken#endif 1621331766Sken} sli4_req_common_create_cq_set_v0_t; 1622331766Sken 1623331766Sken/** 1624331766Sken * CQE count. 1625331766Sken */ 1626331766Sken#define SLI4_CQ_CNT_256 0 1627331766Sken#define SLI4_CQ_CNT_512 1 1628331766Sken#define SLI4_CQ_CNT_1024 2 1629331766Sken#define SLI4_CQ_CNT_LARGE 3 1630331766Sken 1631331766Sken#define SLI4_CQE_BYTES (4 * sizeof(uint32_t)) 1632331766Sken 1633331766Sken#define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8 1634331766Sken 1635331766Sken/** 1636331766Sken * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion 1637331766Sken */ 1638331766Skentypedef struct sli4_res_common_create_queue_s { 1639331766Sken sli4_res_hdr_t hdr; 1640331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1641331766Sken uint32_t q_id:16, 1642331766Sken :8, 1643331766Sken ulp:8; 1644331766Sken uint32_t db_offset; 1645331766Sken uint32_t db_rs:16, 1646331766Sken db_fmt:16; 1647331766Sken#else 1648331766Sken#error big endian version not defined 1649331766Sken#endif 1650331766Sken} sli4_res_common_create_queue_t; 1651331766Sken 1652331766Sken 1653331766Skentypedef struct sli4_res_common_create_queue_set_s { 1654331766Sken sli4_res_hdr_t hdr; 1655331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1656331766Sken uint32_t q_id:16, 1657331766Sken num_q_allocated:16; 1658331766Sken#else 1659331766Sken#error big endian version not defined 1660331766Sken#endif 1661331766Sken} sli4_res_common_create_queue_set_t; 1662331766Sken 1663331766Sken 1664331766Sken/** 1665331766Sken * @brief Common Destroy CQ 1666331766Sken */ 1667331766Skentypedef struct sli4_req_common_destroy_cq_s { 1668331766Sken sli4_req_hdr_t hdr; 1669331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1670331766Sken uint32_t cq_id:16, 1671331766Sken :16; 1672331766Sken#else 1673331766Sken#error big endian version not defined 1674331766Sken#endif 1675331766Sken} sli4_req_common_destroy_cq_t; 1676331766Sken 1677331766Sken/** 1678331766Sken * @brief COMMON_MODIFY_EQ_DELAY 1679331766Sken * 1680331766Sken * Modify the delay multiplier for EQs 1681331766Sken */ 1682331766Skentypedef struct sli4_req_common_modify_eq_delay_s { 1683331766Sken sli4_req_hdr_t hdr; 1684331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1685331766Sken uint32_t num_eq; 1686331766Sken struct { 1687331766Sken uint32_t eq_id; 1688331766Sken uint32_t phase; 1689331766Sken uint32_t delay_multiplier; 1690331766Sken } eq_delay_record[8]; 1691331766Sken#else 1692331766Sken#error big endian version not defined 1693331766Sken#endif 1694331766Sken} sli4_req_common_modify_eq_delay_t; 1695331766Sken 1696331766Sken/** 1697331766Sken * @brief COMMON_CREATE_EQ 1698331766Sken * 1699331766Sken * Create an Event Queue. 1700331766Sken */ 1701331766Skentypedef struct sli4_req_common_create_eq_s { 1702331766Sken sli4_req_hdr_t hdr; 1703331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1704331766Sken uint32_t num_pages:16, 1705331766Sken :16; 1706331766Sken uint32_t :29, 1707331766Sken valid:1, 1708331766Sken :1, 1709331766Sken eqesz:1; 1710331766Sken uint32_t :26, 1711331766Sken count:3, 1712331766Sken :2, 1713331766Sken arm:1; 1714331766Sken uint32_t :13, 1715331766Sken delay_multiplier:10, 1716331766Sken :9; 1717331766Sken uint32_t rsvd; 1718331766Sken struct { 1719331766Sken uint32_t low; 1720331766Sken uint32_t high; 1721331766Sken } page_address[8]; 1722331766Sken#else 1723331766Sken#error big endian version not defined 1724331766Sken#endif 1725331766Sken} sli4_req_common_create_eq_t; 1726331766Sken 1727331766Sken#define SLI4_EQ_CNT_256 0 1728331766Sken#define SLI4_EQ_CNT_512 1 1729331766Sken#define SLI4_EQ_CNT_1024 2 1730331766Sken#define SLI4_EQ_CNT_2048 3 1731331766Sken#define SLI4_EQ_CNT_4096 4 1732331766Sken 1733331766Sken#define SLI4_EQE_SIZE_4 0 1734331766Sken#define SLI4_EQE_SIZE_16 1 1735331766Sken 1736331766Sken/** 1737331766Sken * @brief Common Destroy EQ 1738331766Sken */ 1739331766Skentypedef struct sli4_req_common_destroy_eq_s { 1740331766Sken sli4_req_hdr_t hdr; 1741331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1742331766Sken uint32_t eq_id:16, 1743331766Sken :16; 1744331766Sken#else 1745331766Sken#error big endian version not defined 1746331766Sken#endif 1747331766Sken} sli4_req_common_destroy_eq_t; 1748331766Sken 1749331766Sken/** 1750331766Sken * @brief COMMON_CREATE_MQ_EXT 1751331766Sken * 1752331766Sken * Create a Mailbox Queue; accommodate v0 and v1 forms. 1753331766Sken */ 1754331766Skentypedef struct sli4_req_common_create_mq_ext_s { 1755331766Sken sli4_req_hdr_t hdr; 1756331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1757331766Sken uint32_t num_pages:16, 1758331766Sken cq_id_v1:16; 1759331766Sken uint32_t async_event_bitmap; 1760331766Sken uint32_t async_cq_id_v1:16, 1761331766Sken ring_size:4, 1762331766Sken :2, 1763331766Sken cq_id_v0:10; 1764331766Sken uint32_t :31, 1765331766Sken val:1; 1766331766Sken uint32_t acqv:1, 1767331766Sken async_cq_id_v0:10, 1768331766Sken :21; 1769331766Sken uint32_t rsvd9; 1770331766Sken struct { 1771331766Sken uint32_t low; 1772331766Sken uint32_t high; 1773331766Sken } page_physical_address[8]; 1774331766Sken#else 1775331766Sken#error big endian version not defined 1776331766Sken#endif 1777331766Sken} sli4_req_common_create_mq_ext_t; 1778331766Sken 1779331766Sken#define SLI4_MQE_SIZE_16 0x05 1780331766Sken#define SLI4_MQE_SIZE_32 0x06 1781331766Sken#define SLI4_MQE_SIZE_64 0x07 1782331766Sken#define SLI4_MQE_SIZE_128 0x08 1783331766Sken 1784331766Sken#define SLI4_ASYNC_EVT_LINK_STATE BIT(1) 1785331766Sken#define SLI4_ASYNC_EVT_FCOE_FIP BIT(2) 1786331766Sken#define SLI4_ASYNC_EVT_DCBX BIT(3) 1787331766Sken#define SLI4_ASYNC_EVT_ISCSI BIT(4) 1788331766Sken#define SLI4_ASYNC_EVT_GRP5 BIT(5) 1789331766Sken#define SLI4_ASYNC_EVT_FC BIT(16) 1790331766Sken#define SLI4_ASYNC_EVT_SLI_PORT BIT(17) 1791331766Sken#define SLI4_ASYNC_EVT_VF BIT(18) 1792331766Sken#define SLI4_ASYNC_EVT_MR BIT(19) 1793331766Sken 1794331766Sken#define SLI4_ASYNC_EVT_ALL \ 1795331766Sken SLI4_ASYNC_EVT_LINK_STATE | \ 1796331766Sken SLI4_ASYNC_EVT_FCOE_FIP | \ 1797331766Sken SLI4_ASYNC_EVT_DCBX | \ 1798331766Sken SLI4_ASYNC_EVT_ISCSI | \ 1799331766Sken SLI4_ASYNC_EVT_GRP5 | \ 1800331766Sken SLI4_ASYNC_EVT_FC | \ 1801331766Sken SLI4_ASYNC_EVT_SLI_PORT | \ 1802331766Sken SLI4_ASYNC_EVT_VF |\ 1803331766Sken SLI4_ASYNC_EVT_MR 1804331766Sken 1805331766Sken#define SLI4_ASYNC_EVT_FC_FCOE \ 1806331766Sken SLI4_ASYNC_EVT_LINK_STATE | \ 1807331766Sken SLI4_ASYNC_EVT_FCOE_FIP | \ 1808331766Sken SLI4_ASYNC_EVT_GRP5 | \ 1809331766Sken SLI4_ASYNC_EVT_FC | \ 1810331766Sken SLI4_ASYNC_EVT_SLI_PORT 1811331766Sken 1812331766Sken/** 1813331766Sken * @brief Common Destroy MQ 1814331766Sken */ 1815331766Skentypedef struct sli4_req_common_destroy_mq_s { 1816331766Sken sli4_req_hdr_t hdr; 1817331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1818331766Sken uint32_t mq_id:16, 1819331766Sken :16; 1820331766Sken#else 1821331766Sken#error big endian version not defined 1822331766Sken#endif 1823331766Sken} sli4_req_common_destroy_mq_t; 1824331766Sken 1825331766Sken/** 1826331766Sken * @brief COMMON_GET_CNTL_ATTRIBUTES 1827331766Sken * 1828331766Sken * Query for information about the SLI Port 1829331766Sken */ 1830331766Skentypedef struct sli4_res_common_get_cntl_attributes_s { 1831331766Sken sli4_res_hdr_t hdr; 1832331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1833331766Sken uint8_t version_string[32]; 1834331766Sken uint8_t manufacturer_name[32]; 1835331766Sken uint32_t supported_modes; 1836331766Sken uint32_t eprom_version_lo:8, 1837331766Sken eprom_version_hi:8, 1838331766Sken :16; 1839331766Sken uint32_t mbx_data_structure_version; 1840331766Sken uint32_t ep_firmware_data_structure_version; 1841331766Sken uint8_t ncsi_version_string[12]; 1842331766Sken uint32_t default_extended_timeout; 1843331766Sken uint8_t model_number[32]; 1844331766Sken uint8_t description[64]; 1845331766Sken uint8_t serial_number[32]; 1846331766Sken uint8_t ip_version_string[32]; 1847331766Sken uint8_t fw_version_string[32]; 1848331766Sken uint8_t bios_version_string[32]; 1849331766Sken uint8_t redboot_version_string[32]; 1850331766Sken uint8_t driver_version_string[32]; 1851331766Sken uint8_t fw_on_flash_version_string[32]; 1852331766Sken uint32_t functionalities_supported; 1853331766Sken uint32_t max_cdb_length:16, 1854331766Sken asic_revision:8, 1855331766Sken generational_guid0:8; 1856331766Sken uint32_t generational_guid1_12[3]; 1857331766Sken uint32_t generational_guid13:24, 1858331766Sken hba_port_count:8; 1859331766Sken uint32_t default_link_down_timeout:16, 1860331766Sken iscsi_version_min_max:8, 1861331766Sken multifunctional_device:8; 1862331766Sken uint32_t cache_valid:8, 1863331766Sken hba_status:8, 1864331766Sken max_domains_supported:8, 1865331766Sken port_number:6, 1866331766Sken port_type:2; 1867331766Sken uint32_t firmware_post_status; 1868331766Sken uint32_t hba_mtu; 1869331766Sken uint32_t iscsi_features:8, 1870331766Sken rsvd121:24; 1871331766Sken uint32_t pci_vendor_id:16, 1872331766Sken pci_device_id:16; 1873331766Sken uint32_t pci_sub_vendor_id:16, 1874331766Sken pci_sub_system_id:16; 1875331766Sken uint32_t pci_bus_number:8, 1876331766Sken pci_device_number:8, 1877331766Sken pci_function_number:8, 1878331766Sken interface_type:8; 1879331766Sken uint64_t unique_identifier; 1880331766Sken uint32_t number_of_netfilters:8, 1881331766Sken rsvd130:24; 1882331766Sken#else 1883331766Sken#error big endian version not defined 1884331766Sken#endif 1885331766Sken} sli4_res_common_get_cntl_attributes_t; 1886331766Sken 1887331766Sken/** 1888331766Sken * @brief COMMON_GET_CNTL_ATTRIBUTES 1889331766Sken * 1890331766Sken * This command queries the controller information from the Flash ROM. 1891331766Sken */ 1892331766Skentypedef struct sli4_req_common_get_cntl_addl_attributes_s { 1893331766Sken sli4_req_hdr_t hdr; 1894331766Sken} sli4_req_common_get_cntl_addl_attributes_t; 1895331766Sken 1896331766Sken 1897331766Skentypedef struct sli4_res_common_get_cntl_addl_attributes_s { 1898331766Sken sli4_res_hdr_t hdr; 1899331766Sken uint16_t ipl_file_number; 1900331766Sken uint8_t ipl_file_version; 1901331766Sken uint8_t rsvd0; 1902331766Sken uint8_t on_die_temperature; 1903331766Sken uint8_t rsvd1[3]; 1904331766Sken uint32_t driver_advanced_features_supported; 1905331766Sken uint32_t rsvd2[4]; 1906331766Sken char fcoe_universal_bios_version[32]; 1907331766Sken char fcoe_x86_bios_version[32]; 1908331766Sken char fcoe_efi_bios_version[32]; 1909331766Sken char fcoe_fcode_version[32]; 1910331766Sken char uefi_bios_version[32]; 1911331766Sken char uefi_nic_version[32]; 1912331766Sken char uefi_fcode_version[32]; 1913331766Sken char uefi_iscsi_version[32]; 1914331766Sken char iscsi_x86_bios_version[32]; 1915331766Sken char pxe_x86_bios_version[32]; 1916331766Sken uint8_t fcoe_default_wwpn[8]; 1917331766Sken uint8_t ext_phy_version[32]; 1918331766Sken uint8_t fc_universal_bios_version[32]; 1919331766Sken uint8_t fc_x86_bios_version[32]; 1920331766Sken uint8_t fc_efi_bios_version[32]; 1921331766Sken uint8_t fc_fcode_version[32]; 1922331766Sken uint8_t ext_phy_crc_label[8]; 1923331766Sken uint8_t ipl_file_name[16]; 1924331766Sken uint8_t rsvd3[72]; 1925331766Sken} sli4_res_common_get_cntl_addl_attributes_t; 1926331766Sken 1927331766Sken/** 1928331766Sken * @brief COMMON_NOP 1929331766Sken * 1930331766Sken * This command does not do anything; it only returns the payload in the completion. 1931331766Sken */ 1932331766Skentypedef struct sli4_req_common_nop_s { 1933331766Sken sli4_req_hdr_t hdr; 1934331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1935331766Sken uint32_t context[2]; 1936331766Sken#else 1937331766Sken#error big endian version not defined 1938331766Sken#endif 1939331766Sken} sli4_req_common_nop_t; 1940331766Sken 1941331766Skentypedef struct sli4_res_common_nop_s { 1942331766Sken sli4_res_hdr_t hdr; 1943331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1944331766Sken uint32_t context[2]; 1945331766Sken#else 1946331766Sken#error big endian version not defined 1947331766Sken#endif 1948331766Sken} sli4_res_common_nop_t; 1949331766Sken 1950331766Sken/** 1951331766Sken * @brief COMMON_GET_RESOURCE_EXTENT_INFO 1952331766Sken */ 1953331766Skentypedef struct sli4_req_common_get_resource_extent_info_s { 1954331766Sken sli4_req_hdr_t hdr; 1955331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1956331766Sken uint32_t resource_type:16, 1957331766Sken :16; 1958331766Sken#else 1959331766Sken#error big endian version not defined 1960331766Sken#endif 1961331766Sken} sli4_req_common_get_resource_extent_info_t; 1962331766Sken 1963331766Sken#define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c 1964331766Sken#define SLI4_RSC_TYPE_FCOE_VFI 0x20 1965331766Sken#define SLI4_RSC_TYPE_FCOE_VPI 0x21 1966331766Sken#define SLI4_RSC_TYPE_FCOE_RPI 0x22 1967331766Sken#define SLI4_RSC_TYPE_FCOE_XRI 0x23 1968331766Sken 1969331766Skentypedef struct sli4_res_common_get_resource_extent_info_s { 1970331766Sken sli4_res_hdr_t hdr; 1971331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1972331766Sken uint32_t resource_extent_count:16, 1973331766Sken resource_extent_size:16; 1974331766Sken#else 1975331766Sken#error big endian version not defined 1976331766Sken#endif 1977331766Sken} sli4_res_common_get_resource_extent_info_t; 1978331766Sken 1979331766Sken 1980331766Sken#define SLI4_128BYTE_WQE_SUPPORT 0x02 1981331766Sken/** 1982331766Sken * @brief COMMON_GET_SLI4_PARAMETERS 1983331766Sken */ 1984331766Skentypedef struct sli4_res_common_get_sli4_parameters_s { 1985331766Sken sli4_res_hdr_t hdr; 1986331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 1987331766Sken uint32_t protocol_type:8, 1988331766Sken :24; 1989331766Sken uint32_t ft:1, 1990331766Sken :3, 1991331766Sken sli_revision:4, 1992331766Sken sli_family:4, 1993331766Sken if_type:4, 1994331766Sken sli_hint_1:8, 1995331766Sken sli_hint_2:5, 1996331766Sken :3; 1997331766Sken uint32_t eq_page_cnt:4, 1998331766Sken :4, 1999331766Sken eqe_sizes:4, 2000331766Sken :4, 2001331766Sken eq_page_sizes:8, 2002331766Sken eqe_count_method:4, 2003331766Sken :4; 2004331766Sken uint32_t eqe_count_mask:16, 2005331766Sken :16; 2006331766Sken uint32_t cq_page_cnt:4, 2007331766Sken :4, 2008331766Sken cqe_sizes:4, 2009331766Sken :2, 2010331766Sken cqv:2, 2011331766Sken cq_page_sizes:8, 2012331766Sken cqe_count_method:4, 2013331766Sken :4; 2014331766Sken uint32_t cqe_count_mask:16, 2015331766Sken :16; 2016331766Sken uint32_t mq_page_cnt:4, 2017331766Sken :10, 2018331766Sken mqv:2, 2019331766Sken mq_page_sizes:8, 2020331766Sken mqe_count_method:4, 2021331766Sken :4; 2022331766Sken uint32_t mqe_count_mask:16, 2023331766Sken :16; 2024331766Sken uint32_t wq_page_cnt:4, 2025331766Sken :4, 2026331766Sken wqe_sizes:4, 2027331766Sken :2, 2028331766Sken wqv:2, 2029331766Sken wq_page_sizes:8, 2030331766Sken wqe_count_method:4, 2031331766Sken :4; 2032331766Sken uint32_t wqe_count_mask:16, 2033331766Sken :16; 2034331766Sken uint32_t rq_page_cnt:4, 2035331766Sken :4, 2036331766Sken rqe_sizes:4, 2037331766Sken :2, 2038331766Sken rqv:2, 2039331766Sken rq_page_sizes:8, 2040331766Sken rqe_count_method:4, 2041331766Sken :4; 2042331766Sken uint32_t rqe_count_mask:16, 2043331766Sken :12, 2044331766Sken rq_db_window:4; 2045331766Sken uint32_t fcoe:1, 2046331766Sken ext:1, 2047331766Sken hdrr:1, 2048331766Sken sglr:1, 2049331766Sken fbrr:1, 2050331766Sken areg:1, 2051331766Sken tgt:1, 2052331766Sken terp:1, 2053331766Sken assi:1, 2054331766Sken wchn:1, 2055331766Sken tcca:1, 2056331766Sken trty:1, 2057331766Sken trir:1, 2058331766Sken phoff:1, 2059331766Sken phon:1, 2060331766Sken phwq:1, /** Performance Hint WQ_ID Association */ 2061331766Sken boundary_4ga:1, 2062331766Sken rxc:1, 2063331766Sken hlm:1, 2064331766Sken ipr:1, 2065331766Sken rxri:1, 2066331766Sken sglc:1, 2067331766Sken timm:1, 2068331766Sken tsmm:1, 2069331766Sken :1, 2070331766Sken oas:1, 2071331766Sken lc:1, 2072331766Sken agxf:1, 2073331766Sken loopback_scope:4; 2074331766Sken uint32_t sge_supported_length; 2075331766Sken uint32_t sgl_page_cnt:4, 2076331766Sken :4, 2077331766Sken sgl_page_sizes:8, 2078331766Sken sgl_pp_align:8, 2079331766Sken :8; 2080331766Sken uint32_t min_rq_buffer_size:16, 2081331766Sken :16; 2082331766Sken uint32_t max_rq_buffer_size; 2083331766Sken uint32_t physical_xri_max:16, 2084331766Sken physical_rpi_max:16; 2085331766Sken uint32_t physical_vpi_max:16, 2086331766Sken physical_vfi_max:16; 2087331766Sken uint32_t rsvd19; 2088331766Sken uint32_t frag_num_field_offset:16, /* dword 20 */ 2089331766Sken frag_num_field_size:16; 2090331766Sken uint32_t sgl_index_field_offset:16, /* dword 21 */ 2091331766Sken sgl_index_field_size:16; 2092331766Sken uint32_t chain_sge_initial_value_lo; /* dword 22 */ 2093331766Sken uint32_t chain_sge_initial_value_hi; /* dword 23 */ 2094331766Sken#else 2095331766Sken#error big endian version not defined 2096331766Sken#endif 2097331766Sken} sli4_res_common_get_sli4_parameters_t; 2098331766Sken 2099331766Sken 2100331766Sken/** 2101331766Sken * @brief COMMON_QUERY_FW_CONFIG 2102331766Sken * 2103331766Sken * This command retrieves firmware configuration parameters and adapter 2104331766Sken * resources available to the driver. 2105331766Sken */ 2106331766Skentypedef struct sli4_req_common_query_fw_config_s { 2107331766Sken sli4_req_hdr_t hdr; 2108331766Sken} sli4_req_common_query_fw_config_t; 2109331766Sken 2110331766Sken 2111331766Sken#define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40 2112331766Sken#define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80 2113331766Sken#define SLI4_FUNCTION_MODE_DUA_MODE 0x800 2114331766Sken 2115331766Sken#define SLI4_ULP_MODE_FCOE_INI 0x40 2116331766Sken#define SLI4_ULP_MODE_FCOE_TGT 0x80 2117331766Sken 2118331766Skentypedef struct sli4_res_common_query_fw_config_s { 2119331766Sken sli4_res_hdr_t hdr; 2120331766Sken uint32_t config_number; 2121331766Sken uint32_t asic_rev; 2122331766Sken uint32_t physical_port; 2123331766Sken uint32_t function_mode; 2124331766Sken uint32_t ulp0_mode; 2125331766Sken uint32_t ulp0_nic_wqid_base; 2126331766Sken uint32_t ulp0_nic_wq_total; /* Dword 10 */ 2127331766Sken uint32_t ulp0_toe_wqid_base; 2128331766Sken uint32_t ulp0_toe_wq_total; 2129331766Sken uint32_t ulp0_toe_rqid_base; 2130331766Sken uint32_t ulp0_toe_rq_total; 2131331766Sken uint32_t ulp0_toe_defrqid_base; 2132331766Sken uint32_t ulp0_toe_defrq_total; 2133331766Sken uint32_t ulp0_lro_rqid_base; 2134331766Sken uint32_t ulp0_lro_rq_total; 2135331766Sken uint32_t ulp0_iscsi_icd_base; 2136331766Sken uint32_t ulp0_iscsi_icd_total; /* Dword 20 */ 2137331766Sken uint32_t ulp1_mode; 2138331766Sken uint32_t ulp1_nic_wqid_base; 2139331766Sken uint32_t ulp1_nic_wq_total; 2140331766Sken uint32_t ulp1_toe_wqid_base; 2141331766Sken uint32_t ulp1_toe_wq_total; 2142331766Sken uint32_t ulp1_toe_rqid_base; 2143331766Sken uint32_t ulp1_toe_rq_total; 2144331766Sken uint32_t ulp1_toe_defrqid_base; 2145331766Sken uint32_t ulp1_toe_defrq_total; 2146331766Sken uint32_t ulp1_lro_rqid_base; /* Dword 30 */ 2147331766Sken uint32_t ulp1_lro_rq_total; 2148331766Sken uint32_t ulp1_iscsi_icd_base; 2149331766Sken uint32_t ulp1_iscsi_icd_total; 2150331766Sken uint32_t function_capabilities; 2151331766Sken uint32_t ulp0_cq_base; 2152331766Sken uint32_t ulp0_cq_total; 2153331766Sken uint32_t ulp0_eq_base; 2154331766Sken uint32_t ulp0_eq_total; 2155331766Sken uint32_t ulp0_iscsi_chain_icd_base; 2156331766Sken uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */ 2157331766Sken uint32_t ulp1_iscsi_chain_icd_base; 2158331766Sken uint32_t ulp1_iscsi_chain_icd_total; 2159331766Sken} sli4_res_common_query_fw_config_t; 2160331766Sken 2161331766Sken/** 2162331766Sken * @brief COMMON_GET_PORT_NAME 2163331766Sken */ 2164331766Skentypedef struct sli4_req_common_get_port_name_s { 2165331766Sken sli4_req_hdr_t hdr; 2166331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2167331766Sken uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */ 2168331766Sken :30; 2169331766Sken#else 2170331766Sken#error big endian version not defined 2171331766Sken#endif 2172331766Sken} sli4_req_common_get_port_name_t; 2173331766Sken 2174331766Skentypedef struct sli4_res_common_get_port_name_s { 2175331766Sken sli4_res_hdr_t hdr; 2176331766Sken char port_name[4]; 2177331766Sken} sli4_res_common_get_port_name_t; 2178331766Sken 2179331766Sken/** 2180331766Sken * @brief COMMON_WRITE_FLASHROM 2181331766Sken */ 2182331766Skentypedef struct sli4_req_common_write_flashrom_s { 2183331766Sken sli4_req_hdr_t hdr; 2184331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2185331766Sken uint32_t flash_rom_access_opcode; 2186331766Sken uint32_t flash_rom_access_operation_type; 2187331766Sken uint32_t data_buffer_size; 2188331766Sken uint32_t offset; 2189331766Sken uint8_t data_buffer[4]; 2190331766Sken#else 2191331766Sken#error big endian version not defined 2192331766Sken#endif 2193331766Sken} sli4_req_common_write_flashrom_t; 2194331766Sken 2195331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01 2196331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02 2197331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03 2198331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04 2199331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05 2200331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06 2201331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07 2202331766Sken#define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08 2203331766Sken#define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09 2204331766Sken#define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a 2205331766Sken 2206331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00 2207331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01 2208331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02 2209331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03 2210331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04 2211331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05 2212331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06 2213331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07 2214331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08 2215331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09 2216331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a 2217331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b 2218331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c 2219331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d 2220331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e 2221331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f 2222331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10 2223331766Sken#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11 2224331766Sken 2225331766Sken/** 2226331766Sken * @brief COMMON_MANAGE_FAT 2227331766Sken */ 2228331766Skentypedef struct sli4_req_common_manage_fat_s { 2229331766Sken sli4_req_hdr_t hdr; 2230331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2231331766Sken uint32_t fat_operation; 2232331766Sken uint32_t read_log_offset; 2233331766Sken uint32_t read_log_length; 2234331766Sken uint32_t data_buffer_size; 2235331766Sken uint32_t data_buffer; /* response only */ 2236331766Sken#else 2237331766Sken#error big endian version not defined 2238331766Sken#endif 2239331766Sken} sli4_req_common_manage_fat_t; 2240331766Sken 2241331766Sken/** 2242331766Sken * @brief COMMON_GET_EXT_FAT_CAPABILITIES 2243331766Sken */ 2244331766Skentypedef struct sli4_req_common_get_ext_fat_capabilities_s { 2245331766Sken sli4_req_hdr_t hdr; 2246331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2247331766Sken uint32_t parameter_type; 2248331766Sken#else 2249331766Sken#error big endian version not defined 2250331766Sken#endif 2251331766Sken} sli4_req_common_get_ext_fat_capabilities_t; 2252331766Sken 2253331766Sken/** 2254331766Sken * @brief COMMON_SET_EXT_FAT_CAPABILITIES 2255331766Sken */ 2256331766Skentypedef struct sli4_req_common_set_ext_fat_capabilities_s { 2257331766Sken sli4_req_hdr_t hdr; 2258331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2259331766Sken uint32_t maximum_log_entries; 2260331766Sken uint32_t log_entry_size; 2261331766Sken uint32_t logging_type:8, 2262331766Sken maximum_logging_functions:8, 2263331766Sken maximum_logging_ports:8, 2264331766Sken :8; 2265331766Sken uint32_t supported_modes; 2266331766Sken uint32_t number_modules; 2267331766Sken uint32_t debug_module[14]; 2268331766Sken#else 2269331766Sken#error big endian version not defined 2270331766Sken#endif 2271331766Sken} sli4_req_common_set_ext_fat_capabilities_t; 2272331766Sken 2273331766Sken/** 2274331766Sken * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 2275331766Sken */ 2276331766Skentypedef struct sli4_req_common_ext_fat_configure_snapshot_s { 2277331766Sken sli4_req_hdr_t hdr; 2278331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2279331766Sken uint32_t total_log_entries; 2280331766Sken#else 2281331766Sken#error big endian version not defined 2282331766Sken#endif 2283331766Sken} sli4_req_common_ext_fat_configure_snapshot_t; 2284331766Sken 2285331766Sken/** 2286331766Sken * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 2287331766Sken */ 2288331766Skentypedef struct sli4_req_common_ext_fat_retrieve_snapshot_s { 2289331766Sken sli4_req_hdr_t hdr; 2290331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2291331766Sken uint32_t snapshot_mode; 2292331766Sken uint32_t start_index; 2293331766Sken uint32_t number_log_entries; 2294331766Sken#else 2295331766Sken#error big endian version not defined 2296331766Sken#endif 2297331766Sken} sli4_req_common_ext_fat_retrieve_snapshot_t; 2298331766Sken 2299331766Skentypedef struct sli4_res_common_ext_fat_retrieve_snapshot_s { 2300331766Sken sli4_res_hdr_t hdr; 2301331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2302331766Sken uint32_t number_log_entries; 2303331766Sken uint32_t version:8, 2304331766Sken physical_port:8, 2305331766Sken function_id:16; 2306331766Sken uint32_t trace_level; 2307331766Sken uint32_t module_mask[2]; 2308331766Sken uint32_t trace_table_index; 2309331766Sken uint32_t timestamp; 2310331766Sken uint8_t string_data[16]; 2311331766Sken uint32_t data[6]; 2312331766Sken#else 2313331766Sken#error big endian version not defined 2314331766Sken#endif 2315331766Sken} sli4_res_common_ext_fat_retrieve_snapshot_t; 2316331766Sken 2317331766Sken/** 2318331766Sken * @brief COMMON_EXT_FAT_READ_STRING_TABLE 2319331766Sken */ 2320331766Skentypedef struct sli4_req_common_ext_fat_read_string_table_s { 2321331766Sken sli4_req_hdr_t hdr; 2322331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2323331766Sken uint32_t byte_offset; 2324331766Sken uint32_t number_bytes; 2325331766Sken#else 2326331766Sken#error big endian version not defined 2327331766Sken#endif 2328331766Sken} sli4_req_common_ext_fat_read_string_table_t; 2329331766Sken 2330331766Skentypedef struct sli4_res_common_ext_fat_read_string_table_s { 2331331766Sken sli4_res_hdr_t hdr; 2332331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2333331766Sken uint32_t number_returned_bytes; 2334331766Sken uint32_t number_remaining_bytes; 2335331766Sken uint32_t table_data0:8, 2336331766Sken :24; 2337331766Sken uint8_t table_data[0]; 2338331766Sken#else 2339331766Sken#error big endian version not defined 2340331766Sken#endif 2341331766Sken} sli4_res_common_ext_fat_read_string_table_t; 2342331766Sken 2343331766Sken/** 2344331766Sken * @brief COMMON_READ_TRANSCEIVER_DATA 2345331766Sken * 2346331766Sken * This command reads SFF transceiver data(Format is defined 2347331766Sken * by the SFF-8472 specification). 2348331766Sken */ 2349331766Skentypedef struct sli4_req_common_read_transceiver_data_s { 2350331766Sken sli4_req_hdr_t hdr; 2351331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2352331766Sken uint32_t page_number; 2353331766Sken uint32_t port; 2354331766Sken#else 2355331766Sken#error big endian version not defined 2356331766Sken#endif 2357331766Sken} sli4_req_common_read_transceiver_data_t; 2358331766Sken 2359331766Skentypedef struct sli4_res_common_read_transceiver_data_s { 2360331766Sken sli4_res_hdr_t hdr; 2361331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2362331766Sken uint32_t page_number; 2363331766Sken uint32_t port; 2364331766Sken uint32_t page_data[32]; 2365331766Sken uint32_t page_data_2[32]; 2366331766Sken#else 2367331766Sken#error big endian version not defined 2368331766Sken#endif 2369331766Sken} sli4_res_common_read_transceiver_data_t; 2370331766Sken 2371331766Sken/** 2372331766Sken * @brief COMMON_READ_OBJECT 2373331766Sken */ 2374331766Skentypedef struct sli4_req_common_read_object_s { 2375331766Sken sli4_req_hdr_t hdr; 2376331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2377331766Sken uint32_t desired_read_length:24, 2378331766Sken :8; 2379331766Sken uint32_t read_offset; 2380331766Sken uint8_t object_name[104]; 2381331766Sken uint32_t host_buffer_descriptor_count; 2382331766Sken sli4_bde_t host_buffer_descriptor[0]; 2383331766Sken#else 2384331766Sken#error big endian version not defined 2385331766Sken#endif 2386331766Sken} sli4_req_common_read_object_t; 2387331766Sken 2388331766Skentypedef struct sli4_res_common_read_object_s { 2389331766Sken sli4_res_hdr_t hdr; 2390331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2391331766Sken uint32_t actual_read_length; 2392331766Sken uint32_t resv:31, 2393331766Sken eof:1; 2394331766Sken#else 2395331766Sken#error big endian version not defined 2396331766Sken#endif 2397331766Sken} sli4_res_common_read_object_t; 2398331766Sken 2399331766Sken/** 2400331766Sken * @brief COMMON_WRITE_OBJECT 2401331766Sken */ 2402331766Skentypedef struct sli4_req_common_write_object_s { 2403331766Sken sli4_req_hdr_t hdr; 2404331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2405331766Sken uint32_t desired_write_length:24, 2406331766Sken :6, 2407331766Sken noc:1, 2408331766Sken eof:1; 2409331766Sken uint32_t write_offset; 2410331766Sken uint8_t object_name[104]; 2411331766Sken uint32_t host_buffer_descriptor_count; 2412331766Sken sli4_bde_t host_buffer_descriptor[0]; 2413331766Sken#else 2414331766Sken#error big endian version not defined 2415331766Sken#endif 2416331766Sken} sli4_req_common_write_object_t; 2417331766Sken 2418331766Skentypedef struct sli4_res_common_write_object_s { 2419331766Sken sli4_res_hdr_t hdr; 2420331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2421331766Sken uint32_t actual_write_length; 2422331766Sken uint32_t change_status:8, 2423331766Sken :24; 2424331766Sken#else 2425331766Sken#error big endian version not defined 2426331766Sken#endif 2427331766Sken} sli4_res_common_write_object_t; 2428331766Sken 2429331766Sken/** 2430331766Sken * @brief COMMON_DELETE_OBJECT 2431331766Sken */ 2432331766Skentypedef struct sli4_req_common_delete_object_s { 2433331766Sken sli4_req_hdr_t hdr; 2434331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2435331766Sken uint32_t rsvd4; 2436331766Sken uint32_t rsvd5; 2437331766Sken uint8_t object_name[104]; 2438331766Sken#else 2439331766Sken#error big endian version not defined 2440331766Sken#endif 2441331766Sken} sli4_req_common_delete_object_t; 2442331766Sken 2443331766Sken/** 2444331766Sken * @brief COMMON_READ_OBJECT_LIST 2445331766Sken */ 2446331766Skentypedef struct sli4_req_common_read_object_list_s { 2447331766Sken sli4_req_hdr_t hdr; 2448331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2449331766Sken uint32_t desired_read_length:24, 2450331766Sken :8; 2451331766Sken uint32_t read_offset; 2452331766Sken uint8_t object_name[104]; 2453331766Sken uint32_t host_buffer_descriptor_count; 2454331766Sken sli4_bde_t host_buffer_descriptor[0]; 2455331766Sken#else 2456331766Sken#error big endian version not defined 2457331766Sken#endif 2458331766Sken} sli4_req_common_read_object_list_t; 2459331766Sken 2460331766Sken/** 2461331766Sken * @brief COMMON_SET_DUMP_LOCATION 2462331766Sken */ 2463331766Skentypedef struct sli4_req_common_set_dump_location_s { 2464331766Sken sli4_req_hdr_t hdr; 2465331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2466331766Sken uint32_t buffer_length:24, 2467331766Sken :5, 2468331766Sken fdb:1, 2469331766Sken blp:1, 2470331766Sken qry:1; 2471331766Sken uint32_t buf_addr_low; 2472331766Sken uint32_t buf_addr_high; 2473331766Sken#else 2474331766Sken#error big endian version not defined 2475331766Sken#endif 2476331766Sken} sli4_req_common_set_dump_location_t; 2477331766Sken 2478331766Skentypedef struct sli4_res_common_set_dump_location_s { 2479331766Sken sli4_res_hdr_t hdr; 2480331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2481331766Sken uint32_t buffer_length:24, 2482331766Sken :8; 2483331766Sken#else 2484331766Sken#error big endian version not defined 2485331766Sken#endif 2486331766Sken}sli4_res_common_set_dump_location_t; 2487331766Sken 2488331766Sken/** 2489331766Sken * @brief COMMON_SET_SET_FEATURES 2490331766Sken */ 2491331766Sken#define SLI4_SET_FEATURES_DIF_SEED 0x01 2492331766Sken#define SLI4_SET_FEATURES_XRI_TIMER 0x03 2493331766Sken#define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04 2494331766Sken#define SLI4_SET_FEATURES_FCTL_CHECK 0x05 2495331766Sken#define SLI4_SET_FEATURES_FEC 0x06 2496331766Sken#define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07 2497331766Sken#define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08 2498331766Sken#define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09 2499331766Sken#define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A 2500331766Sken#define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C 2501331766Sken#define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D 2502331766Sken#define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F 2503331766Sken#define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11 2504331766Sken 2505331766Skentypedef struct sli4_req_common_set_features_s { 2506331766Sken sli4_req_hdr_t hdr; 2507331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2508331766Sken uint32_t feature; 2509331766Sken uint32_t param_len; 2510331766Sken uint32_t params[8]; 2511331766Sken#else 2512331766Sken#error big endian version not defined 2513331766Sken#endif 2514331766Sken} sli4_req_common_set_features_t; 2515331766Sken 2516331766Skentypedef struct sli4_req_common_set_features_dif_seed_s { 2517331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2518331766Sken uint32_t seed:16, 2519331766Sken :16; 2520331766Sken#else 2521331766Sken#error big endian version not defined 2522331766Sken#endif 2523331766Sken} sli4_req_common_set_features_dif_seed_t; 2524331766Sken 2525331766Skentypedef struct sli4_req_common_set_features_t10_pi_mem_model_s { 2526331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2527331766Sken uint32_t tmm:1, 2528331766Sken :31; 2529331766Sken#else 2530331766Sken#error big endian version not defined 2531331766Sken#endif 2532331766Sken} sli4_req_common_set_features_t10_pi_mem_model_t; 2533331766Sken 2534331766Skentypedef struct sli4_req_common_set_features_multirq_s { 2535331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2536331766Sken uint32_t isr:1, /*<< Include Sequence Reporting */ 2537331766Sken agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */ 2538331766Sken :30; 2539331766Sken uint32_t num_rqs:8, 2540331766Sken rq_select_policy:4, 2541331766Sken :20; 2542331766Sken#else 2543331766Sken#error big endian version not defined 2544331766Sken#endif 2545331766Sken} sli4_req_common_set_features_multirq_t; 2546331766Sken 2547331766Skentypedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s { 2548331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2549331766Sken uint32_t rtc:1, 2550331766Sken atv:1, 2551331766Sken tmm:1, 2552331766Sken :1, 2553331766Sken p_type:3, 2554331766Sken blk_size:3, 2555331766Sken :22; 2556331766Sken uint32_t app_tag:16, 2557331766Sken :16; 2558331766Sken#else 2559331766Sken#error big endian version not defined 2560331766Sken#endif 2561331766Sken} sli4_req_common_set_features_xfer_rdy_t10pi_t; 2562331766Sken 2563331766Skentypedef struct sli4_req_common_set_features_health_check_s { 2564331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2565331766Sken uint32_t hck:1, 2566331766Sken qry:1, 2567331766Sken :30; 2568331766Sken#else 2569331766Sken#error big endian version not defined 2570331766Sken#endif 2571331766Sken} sli4_req_common_set_features_health_check_t; 2572331766Sken 2573331766Skentypedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s { 2574331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2575331766Sken uint32_t fdt_xfer_hint; 2576331766Sken#else 2577331766Sken#error big endian version not defined 2578331766Sken#endif 2579331766Sken} sli4_req_common_set_features_set_fdt_xfer_hint_t; 2580331766Sken 2581331766Sken/** 2582331766Sken * @brief DMTF_EXEC_CLP_CMD 2583331766Sken */ 2584331766Skentypedef struct sli4_req_dmtf_exec_clp_cmd_s { 2585331766Sken sli4_req_hdr_t hdr; 2586331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2587331766Sken uint32_t cmd_buf_length; 2588331766Sken uint32_t resp_buf_length; 2589331766Sken uint32_t cmd_buf_addr_low; 2590331766Sken uint32_t cmd_buf_addr_high; 2591331766Sken uint32_t resp_buf_addr_low; 2592331766Sken uint32_t resp_buf_addr_high; 2593331766Sken#else 2594331766Sken#error big endian version not defined 2595331766Sken#endif 2596331766Sken} sli4_req_dmtf_exec_clp_cmd_t; 2597331766Sken 2598331766Skentypedef struct sli4_res_dmtf_exec_clp_cmd_s { 2599331766Sken sli4_res_hdr_t hdr; 2600331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2601331766Sken uint32_t :32; 2602331766Sken uint32_t resp_length; 2603331766Sken uint32_t :32; 2604331766Sken uint32_t :32; 2605331766Sken uint32_t :32; 2606331766Sken uint32_t :32; 2607331766Sken uint32_t clp_status; 2608331766Sken uint32_t clp_detailed_status; 2609331766Sken#else 2610331766Sken#error big endian version not defined 2611331766Sken#endif 2612331766Sken} sli4_res_dmtf_exec_clp_cmd_t; 2613331766Sken 2614331766Sken/** 2615331766Sken * @brief Resource descriptor 2616331766Sken */ 2617331766Sken 2618331766Sken#define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50 2619331766Sken#define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51 2620331766Sken#define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52 2621331766Sken#define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53 2622331766Sken#define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54 2623331766Sken#define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55 2624331766Sken#define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56 2625331766Sken 2626331766Sken#define SLI4_PROTOCOL_NIC_TOE 0x01 2627331766Sken#define SLI4_PROTOCOL_ISCSI 0x02 2628331766Sken#define SLI4_PROTOCOL_FCOE 0x04 2629331766Sken#define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08 2630331766Sken#define SLI4_PROTOCOL_FC 0x10 2631331766Sken#define SLI4_PROTOCOL_DEFAULT 0xff 2632331766Sken 2633331766Skentypedef struct sli4_resource_descriptor_v1_s { 2634331766Sken uint32_t descriptor_type:8, 2635331766Sken descriptor_length:8, 2636331766Sken :16; 2637331766Sken uint32_t type_specific[0]; 2638331766Sken} sli4_resource_descriptor_v1_t; 2639331766Sken 2640331766Skentypedef struct sli4_pcie_resource_descriptor_v1_s { 2641331766Sken uint32_t descriptor_type:8, 2642331766Sken descriptor_length:8, 2643331766Sken :14, 2644331766Sken imm:1, 2645331766Sken nosv:1; 2646331766Sken uint32_t :16, 2647331766Sken pf_number:10, 2648331766Sken :6; 2649331766Sken uint32_t rsvd1; 2650331766Sken uint32_t sriov_state:8, 2651331766Sken pf_state:8, 2652331766Sken pf_type:8, 2653331766Sken :8; 2654331766Sken uint32_t number_of_vfs:16, 2655331766Sken :16; 2656331766Sken uint32_t mission_roles:8, 2657331766Sken :19, 2658331766Sken pchg:1, 2659331766Sken schg:1, 2660331766Sken xchg:1, 2661331766Sken xrom:2; 2662331766Sken uint32_t rsvd2[16]; 2663331766Sken} sli4_pcie_resource_descriptor_v1_t; 2664331766Sken 2665331766Skentypedef struct sli4_isap_resource_descriptor_v1_s { 2666331766Sken uint32_t descriptor_type:8, 2667331766Sken descriptor_length:8, 2668331766Sken :16; 2669331766Sken uint32_t iscsi_tgt:1, 2670331766Sken iscsi_ini:1, 2671331766Sken iscsi_dif:1, 2672331766Sken :29; 2673331766Sken uint32_t rsvd1[3]; 2674331766Sken uint32_t fcoe_tgt:1, 2675331766Sken fcoe_ini:1, 2676331766Sken fcoe_dif:1, 2677331766Sken :29; 2678331766Sken uint32_t rsvd2[7]; 2679331766Sken uint32_t mc_type0:8, 2680331766Sken mc_type1:8, 2681331766Sken mc_type2:8, 2682331766Sken mc_type3:8; 2683331766Sken uint32_t rsvd3[3]; 2684331766Sken} sli4_isap_resouce_descriptor_v1_t; 2685331766Sken 2686331766Sken/** 2687331766Sken * @brief COMMON_GET_FUNCTION_CONFIG 2688331766Sken */ 2689331766Skentypedef struct sli4_req_common_get_function_config_s { 2690331766Sken sli4_req_hdr_t hdr; 2691331766Sken} sli4_req_common_get_function_config_t; 2692331766Sken 2693331766Skentypedef struct sli4_res_common_get_function_config_s { 2694331766Sken sli4_res_hdr_t hdr; 2695331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2696331766Sken uint32_t desc_count; 2697331766Sken uint32_t desc[54]; 2698331766Sken#else 2699331766Sken#error big endian version not defined 2700331766Sken#endif 2701331766Sken} sli4_res_common_get_function_config_t; 2702331766Sken 2703331766Sken/** 2704331766Sken * @brief COMMON_GET_PROFILE_CONFIG 2705331766Sken */ 2706331766Skentypedef struct sli4_req_common_get_profile_config_s { 2707331766Sken sli4_req_hdr_t hdr; 2708331766Sken uint32_t profile_id:8, 2709331766Sken typ:2, 2710331766Sken :22; 2711331766Sken} sli4_req_common_get_profile_config_t; 2712331766Sken 2713331766Skentypedef struct sli4_res_common_get_profile_config_s { 2714331766Sken sli4_res_hdr_t hdr; 2715331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2716331766Sken uint32_t desc_count; 2717331766Sken uint32_t desc[0]; 2718331766Sken#else 2719331766Sken#error big endian version not defined 2720331766Sken#endif 2721331766Sken} sli4_res_common_get_profile_config_t; 2722331766Sken 2723331766Sken/** 2724331766Sken * @brief COMMON_SET_PROFILE_CONFIG 2725331766Sken */ 2726331766Skentypedef struct sli4_req_common_set_profile_config_s { 2727331766Sken sli4_req_hdr_t hdr; 2728331766Sken uint32_t profile_id:8, 2729331766Sken :23, 2730331766Sken isap:1; 2731331766Sken uint32_t desc_count; 2732331766Sken uint32_t desc[0]; 2733331766Sken} sli4_req_common_set_profile_config_t; 2734331766Sken 2735331766Skentypedef struct sli4_res_common_set_profile_config_s { 2736331766Sken sli4_res_hdr_t hdr; 2737331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2738331766Sken#else 2739331766Sken#error big endian version not defined 2740331766Sken#endif 2741331766Sken} sli4_res_common_set_profile_config_t; 2742331766Sken 2743331766Sken/** 2744331766Sken * @brief Profile Descriptor for profile functions 2745331766Sken */ 2746331766Skentypedef struct sli4_profile_descriptor_s { 2747331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2748331766Sken uint32_t profile_id:8, 2749331766Sken :8, 2750331766Sken profile_index:8, 2751331766Sken :8; 2752331766Sken uint32_t profile_description[128]; 2753331766Sken#else 2754331766Sken#error big endian version not defined 2755331766Sken#endif 2756331766Sken} sli4_profile_descriptor_t; 2757331766Sken 2758331766Sken/* We don't know in advance how many descriptors there are. We have 2759331766Sken to pick a number that we think will be big enough and ask for that 2760331766Sken many. */ 2761331766Sken 2762331766Sken#define MAX_PRODUCT_DESCRIPTORS 40 2763331766Sken 2764331766Sken/** 2765331766Sken * @brief COMMON_GET_PROFILE_LIST 2766331766Sken */ 2767331766Skentypedef struct sli4_req_common_get_profile_list_s { 2768331766Sken sli4_req_hdr_t hdr; 2769331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2770331766Sken uint32_t start_profile_index:8, 2771331766Sken :24; 2772331766Sken#else 2773331766Sken#error big endian version not defined 2774331766Sken#endif 2775331766Sken} sli4_req_common_get_profile_list_t; 2776331766Sken 2777331766Skentypedef struct sli4_res_common_get_profile_list_s { 2778331766Sken sli4_res_hdr_t hdr; 2779331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2780331766Sken uint32_t profile_descriptor_count; 2781331766Sken sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS]; 2782331766Sken#else 2783331766Sken#error big endian version not defined 2784331766Sken#endif 2785331766Sken} sli4_res_common_get_profile_list_t; 2786331766Sken 2787331766Sken/** 2788331766Sken * @brief COMMON_GET_ACTIVE_PROFILE 2789331766Sken */ 2790331766Skentypedef struct sli4_req_common_get_active_profile_s { 2791331766Sken sli4_req_hdr_t hdr; 2792331766Sken} sli4_req_common_get_active_profile_t; 2793331766Sken 2794331766Skentypedef struct sli4_res_common_get_active_profile_s { 2795331766Sken sli4_res_hdr_t hdr; 2796331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2797331766Sken uint32_t active_profile_id:8, 2798331766Sken :8, 2799331766Sken next_profile_id:8, 2800331766Sken :8; 2801331766Sken#else 2802331766Sken#error big endian version not defined 2803331766Sken#endif 2804331766Sken} sli4_res_common_get_active_profile_t; 2805331766Sken 2806331766Sken/** 2807331766Sken * @brief COMMON_SET_ACTIVE_PROFILE 2808331766Sken */ 2809331766Skentypedef struct sli4_req_common_set_active_profile_s { 2810331766Sken sli4_req_hdr_t hdr; 2811331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2812331766Sken uint32_t active_profile_id:8, 2813331766Sken :23, 2814331766Sken fd:1; 2815331766Sken#else 2816331766Sken#error big endian version not defined 2817331766Sken#endif 2818331766Sken} sli4_req_common_set_active_profile_t; 2819331766Sken 2820331766Skentypedef struct sli4_res_common_set_active_profile_s { 2821331766Sken sli4_res_hdr_t hdr; 2822331766Sken} sli4_res_common_set_active_profile_t; 2823331766Sken 2824331766Sken/** 2825331766Sken * @brief Link Config Descriptor for link config functions 2826331766Sken */ 2827331766Skentypedef struct sli4_link_config_descriptor_s { 2828331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2829331766Sken uint32_t link_config_id:8, 2830331766Sken :24; 2831331766Sken uint32_t config_description[8]; 2832331766Sken#else 2833331766Sken#error big endian version not defined 2834331766Sken#endif 2835331766Sken} sli4_link_config_descriptor_t; 2836331766Sken 2837331766Sken#define MAX_LINK_CONFIG_DESCRIPTORS 10 2838331766Sken 2839331766Sken/** 2840331766Sken * @brief COMMON_GET_RECONFIG_LINK_INFO 2841331766Sken */ 2842331766Skentypedef struct sli4_req_common_get_reconfig_link_info_s { 2843331766Sken sli4_req_hdr_t hdr; 2844331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2845331766Sken#else 2846331766Sken#error big endian version not defined 2847331766Sken#endif 2848331766Sken} sli4_req_common_get_reconfig_link_info_t; 2849331766Sken 2850331766Skentypedef struct sli4_res_common_get_reconfig_link_info_s { 2851331766Sken sli4_res_hdr_t hdr; 2852331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2853331766Sken uint32_t active_link_config_id:8, 2854331766Sken :8, 2855331766Sken next_link_config_id:8, 2856331766Sken :8; 2857331766Sken uint32_t link_configuration_descriptor_count; 2858331766Sken sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS]; 2859331766Sken#else 2860331766Sken#error big endian version not defined 2861331766Sken#endif 2862331766Sken} sli4_res_common_get_reconfig_link_info_t; 2863331766Sken 2864331766Sken/** 2865331766Sken * @brief COMMON_SET_RECONFIG_LINK_ID 2866331766Sken */ 2867331766Skentypedef struct sli4_req_common_set_reconfig_link_id_s { 2868331766Sken sli4_req_hdr_t hdr; 2869331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2870331766Sken uint32_t next_link_config_id:8, 2871331766Sken :23, 2872331766Sken fd:1; 2873331766Sken#else 2874331766Sken#error big endian version not defined 2875331766Sken#endif 2876331766Sken} sli4_req_common_set_reconfig_link_id_t; 2877331766Sken 2878331766Skentypedef struct sli4_res_common_set_reconfig_link_id_s { 2879331766Sken sli4_res_hdr_t hdr; 2880331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2881331766Sken#else 2882331766Sken#error big endian version not defined 2883331766Sken#endif 2884331766Sken} sli4_res_common_set_reconfig_link_id_t; 2885331766Sken 2886331766Sken 2887331766Skentypedef struct sli4_req_lowlevel_set_watchdog_s { 2888331766Sken sli4_req_hdr_t hdr; 2889331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2890331766Sken uint32_t watchdog_timeout:16, 2891331766Sken :16; 2892331766Sken#else 2893331766Sken#error big endian version not defined 2894331766Sken#endif 2895331766Sken 2896331766Sken} sli4_req_lowlevel_set_watchdog_t; 2897331766Sken 2898331766Sken 2899331766Skentypedef struct sli4_res_lowlevel_set_watchdog_s { 2900331766Sken sli4_res_hdr_t hdr; 2901331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2902331766Sken uint32_t rsvd; 2903331766Sken#else 2904331766Sken#error big endian version not defined 2905331766Sken#endif 2906331766Sken} sli4_res_lowlevel_set_watchdog_t; 2907331766Sken 2908331766Sken/** 2909331766Sken * @brief Event Queue Entry 2910331766Sken */ 2911331766Skentypedef struct sli4_eqe_s { 2912331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2913331766Sken uint32_t vld:1, /** valid */ 2914331766Sken major_code:3, 2915331766Sken minor_code:12, 2916331766Sken resource_id:16; 2917331766Sken#else 2918331766Sken#error big endian version not defined 2919331766Sken#endif 2920331766Sken} sli4_eqe_t; 2921331766Sken 2922331766Sken#define SLI4_MAJOR_CODE_STANDARD 0 2923331766Sken#define SLI4_MAJOR_CODE_SENTINEL 1 2924331766Sken 2925331766Sken/** 2926331766Sken * @brief Mailbox Completion Queue Entry 2927331766Sken * 2928331766Sken * A CQE generated on the completion of a MQE from a MQ. 2929331766Sken */ 2930331766Skentypedef struct sli4_mcqe_s { 2931331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2932331766Sken uint32_t completion_status:16, /** values are protocol specific */ 2933331766Sken extended_status:16; 2934331766Sken uint32_t mqe_tag_low; 2935331766Sken uint32_t mqe_tag_high; 2936331766Sken uint32_t :27, 2937331766Sken con:1, /** consumed - command now being executed */ 2938331766Sken cmp:1, /** completed - command still executing if clear */ 2939331766Sken :1, 2940331766Sken ae:1, /** async event - this is an ACQE */ 2941331766Sken val:1; /** valid - contents of CQE are valid */ 2942331766Sken#else 2943331766Sken#error big endian version not defined 2944331766Sken#endif 2945331766Sken} sli4_mcqe_t; 2946331766Sken 2947331766Sken 2948331766Sken/** 2949331766Sken * @brief Asynchronous Completion Queue Entry 2950331766Sken * 2951331766Sken * A CQE generated asynchronously in response to the link or other internal events. 2952331766Sken */ 2953331766Skentypedef struct sli4_acqe_s { 2954331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 2955331766Sken uint32_t event_data[3]; 2956331766Sken uint32_t :8, 2957331766Sken event_code:8, 2958331766Sken event_type:8, /** values are protocol specific */ 2959331766Sken :6, 2960331766Sken ae:1, /** async event - this is an ACQE */ 2961331766Sken val:1; /** valid - contents of CQE are valid */ 2962331766Sken#else 2963331766Sken#error big endian version not defined 2964331766Sken#endif 2965331766Sken} sli4_acqe_t; 2966331766Sken 2967331766Sken#define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01 2968331766Sken#define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02 2969331766Sken#define SLI4_ACQE_EVENT_CODE_DCBX 0x03 2970331766Sken#define SLI4_ACQE_EVENT_CODE_ISCSI 0x04 2971331766Sken#define SLI4_ACQE_EVENT_CODE_GRP_5 0x05 2972331766Sken#define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10 2973331766Sken#define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11 2974331766Sken#define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12 2975331766Sken#define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13 2976331766Sken 2977331766Sken/** 2978331766Sken * @brief Register name enums 2979331766Sken */ 2980331766Skentypedef enum { 2981331766Sken SLI4_REG_BMBX, 2982331766Sken SLI4_REG_EQCQ_DOORBELL, 2983331766Sken SLI4_REG_FCOE_RQ_DOORBELL, 2984331766Sken SLI4_REG_IO_WQ_DOORBELL, 2985331766Sken SLI4_REG_MQ_DOORBELL, 2986331766Sken SLI4_REG_PHYSDEV_CONTROL, 2987331766Sken SLI4_REG_SLIPORT_CONTROL, 2988331766Sken SLI4_REG_SLIPORT_ERROR1, 2989331766Sken SLI4_REG_SLIPORT_ERROR2, 2990331766Sken SLI4_REG_SLIPORT_SEMAPHORE, 2991331766Sken SLI4_REG_SLIPORT_STATUS, 2992331766Sken SLI4_REG_UERR_MASK_HI, 2993331766Sken SLI4_REG_UERR_MASK_LO, 2994331766Sken SLI4_REG_UERR_STATUS_HI, 2995331766Sken SLI4_REG_UERR_STATUS_LO, 2996331766Sken SLI4_REG_SW_UE_CSR1, 2997331766Sken SLI4_REG_SW_UE_CSR2, 2998331766Sken SLI4_REG_MAX /* must be last */ 2999331766Sken} sli4_regname_e; 3000331766Sken 3001331766Skentypedef struct sli4_reg_s { 3002331766Sken uint32_t rset; 3003331766Sken uint32_t off; 3004331766Sken} sli4_reg_t; 3005331766Sken 3006331766Skentypedef enum { 3007331766Sken SLI_QTYPE_EQ, 3008331766Sken SLI_QTYPE_CQ, 3009331766Sken SLI_QTYPE_MQ, 3010331766Sken SLI_QTYPE_WQ, 3011331766Sken SLI_QTYPE_RQ, 3012331766Sken SLI_QTYPE_MAX, /* must be last */ 3013331766Sken} sli4_qtype_e; 3014331766Sken 3015331766Sken#define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */ 3016331766Sken#define SLI_MAX_CQ_SET_COUNT 16 3017331766Sken#define SLI_MAX_RQ_SET_COUNT 16 3018331766Sken 3019331766Skentypedef enum { 3020331766Sken SLI_QENTRY_ASYNC, 3021331766Sken SLI_QENTRY_MQ, 3022331766Sken SLI_QENTRY_RQ, 3023331766Sken SLI_QENTRY_WQ, 3024331766Sken SLI_QENTRY_WQ_RELEASE, 3025331766Sken SLI_QENTRY_OPT_WRITE_CMD, 3026331766Sken SLI_QENTRY_OPT_WRITE_DATA, 3027331766Sken SLI_QENTRY_XABT, 3028331766Sken SLI_QENTRY_MAX /* must be last */ 3029331766Sken} sli4_qentry_e; 3030331766Sken 3031331766Skentypedef struct sli4_queue_s { 3032331766Sken /* Common to all queue types */ 3033331766Sken ocs_dma_t dma; 3034331766Sken ocs_lock_t lock; 3035331766Sken uint32_t index; /** current host entry index */ 3036331766Sken uint16_t size; /** entry size */ 3037331766Sken uint16_t length; /** number of entries */ 3038331766Sken uint16_t n_posted; /** number entries posted */ 3039331766Sken uint16_t id; /** Port assigned xQ_ID */ 3040331766Sken uint16_t ulp; /** ULP assigned to this queue */ 3041331766Sken uint32_t doorbell_offset;/** The offset for the doorbell */ 3042331766Sken uint16_t doorbell_rset; /** register set for the doorbell */ 3043331766Sken uint8_t type; /** queue type ie EQ, CQ, ... */ 3044331766Sken uint32_t proc_limit; /** limit number of CQE processed per iteration */ 3045331766Sken uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */ 3046331766Sken uint32_t max_num_processed; 3047331766Sken time_t max_process_time; 3048331766Sken 3049331766Sken /* Type specific gunk */ 3050331766Sken union { 3051331766Sken uint32_t r_idx; /** "read" index (MQ only) */ 3052331766Sken struct { 3053331766Sken uint32_t is_mq:1,/** CQ contains MQ/Async completions */ 3054331766Sken is_hdr:1,/** is a RQ for packet headers */ 3055331766Sken rq_batch:1;/** RQ index incremented by 8 */ 3056331766Sken } flag; 3057331766Sken } u; 3058331766Sken} sli4_queue_t; 3059331766Sken 3060331766Skenstatic inline void 3061331766Skensli_queue_lock(sli4_queue_t *q) 3062331766Sken{ 3063331766Sken ocs_lock(&q->lock); 3064331766Sken} 3065331766Sken 3066331766Skenstatic inline void 3067331766Skensli_queue_unlock(sli4_queue_t *q) 3068331766Sken{ 3069331766Sken ocs_unlock(&q->lock); 3070331766Sken} 3071331766Sken 3072331766Sken 3073331766Sken#define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */ 3074331766Sken 3075331766Sken#define SLI4_QUEUE_RQ_BATCH 8 3076331766Sken 3077331766Skentypedef enum { 3078331766Sken SLI4_CB_LINK, 3079331766Sken SLI4_CB_FIP, 3080331766Sken SLI4_CB_MAX /* must be last */ 3081331766Sken} sli4_callback_e; 3082331766Sken 3083331766Skentypedef enum { 3084331766Sken SLI_LINK_STATUS_UP, 3085331766Sken SLI_LINK_STATUS_DOWN, 3086331766Sken SLI_LINK_STATUS_NO_ALPA, 3087331766Sken SLI_LINK_STATUS_MAX, 3088331766Sken} sli4_link_status_e; 3089331766Sken 3090331766Skentypedef enum { 3091331766Sken SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */ 3092331766Sken SLI_LINK_TOPO_LOOP, 3093331766Sken SLI_LINK_TOPO_LOOPBACK_INTERNAL, 3094331766Sken SLI_LINK_TOPO_LOOPBACK_EXTERNAL, 3095331766Sken SLI_LINK_TOPO_NONE, 3096331766Sken SLI_LINK_TOPO_MAX, 3097331766Sken} sli4_link_topology_e; 3098331766Sken 3099331766Sken/* TODO do we need both sli4_port_type_e & sli4_link_medium_e */ 3100331766Skentypedef enum { 3101331766Sken SLI_LINK_MEDIUM_ETHERNET, 3102331766Sken SLI_LINK_MEDIUM_FC, 3103331766Sken SLI_LINK_MEDIUM_MAX, 3104331766Sken} sli4_link_medium_e; 3105331766Sken 3106331766Skentypedef struct sli4_link_event_s { 3107331766Sken sli4_link_status_e status; /* link up/down */ 3108331766Sken sli4_link_topology_e topology; 3109331766Sken sli4_link_medium_e medium; /* Ethernet / FC */ 3110331766Sken uint32_t speed; /* Mbps */ 3111331766Sken uint8_t *loop_map; 3112331766Sken uint32_t fc_id; 3113331766Sken} sli4_link_event_t; 3114331766Sken 3115331766Sken/** 3116331766Sken * @brief Fields retrieved from skyhawk that used used to build chained SGL 3117331766Sken */ 3118331766Skentypedef struct sli4_sgl_chaining_params_s { 3119331766Sken uint8_t chaining_capable; 3120331766Sken uint16_t frag_num_field_offset; 3121331766Sken uint16_t sgl_index_field_offset; 3122331766Sken uint64_t frag_num_field_mask; 3123331766Sken uint64_t sgl_index_field_mask; 3124331766Sken uint32_t chain_sge_initial_value_lo; 3125331766Sken uint32_t chain_sge_initial_value_hi; 3126331766Sken} sli4_sgl_chaining_params_t; 3127331766Sken 3128331766Skentypedef struct sli4_fip_event_s { 3129331766Sken uint32_t type; 3130331766Sken uint32_t index; /* FCF index or UINT32_MAX if invalid */ 3131331766Sken} sli4_fip_event_t; 3132331766Sken 3133331766Skentypedef enum { 3134331766Sken SLI_RSRC_FCOE_VFI, 3135331766Sken SLI_RSRC_FCOE_VPI, 3136331766Sken SLI_RSRC_FCOE_RPI, 3137331766Sken SLI_RSRC_FCOE_XRI, 3138331766Sken SLI_RSRC_FCOE_FCFI, 3139331766Sken SLI_RSRC_MAX /* must be last */ 3140331766Sken} sli4_resource_e; 3141331766Sken 3142331766Skentypedef enum { 3143331766Sken SLI4_PORT_TYPE_FC, 3144331766Sken SLI4_PORT_TYPE_NIC, 3145331766Sken SLI4_PORT_TYPE_MAX /* must be last */ 3146331766Sken} sli4_port_type_e; 3147331766Sken 3148331766Skentypedef enum { 3149331766Sken SLI4_ASIC_TYPE_BE3 = 1, 3150331766Sken SLI4_ASIC_TYPE_SKYHAWK, 3151331766Sken SLI4_ASIC_TYPE_LANCER, 3152331766Sken SLI4_ASIC_TYPE_CORSAIR, 3153331766Sken SLI4_ASIC_TYPE_LANCERG6, 3154331766Sken} sli4_asic_type_e; 3155331766Sken 3156331766Skentypedef enum { 3157331766Sken SLI4_ASIC_REV_FPGA = 1, 3158331766Sken SLI4_ASIC_REV_A0, 3159331766Sken SLI4_ASIC_REV_A1, 3160331766Sken SLI4_ASIC_REV_A2, 3161331766Sken SLI4_ASIC_REV_A3, 3162331766Sken SLI4_ASIC_REV_B0, 3163331766Sken SLI4_ASIC_REV_B1, 3164331766Sken SLI4_ASIC_REV_C0, 3165331766Sken SLI4_ASIC_REV_D0, 3166331766Sken} sli4_asic_rev_e; 3167331766Sken 3168331766Skentypedef struct sli4_s { 3169331766Sken ocs_os_handle_t os; 3170331766Sken sli4_port_type_e port_type; 3171331766Sken 3172331766Sken uint32_t sli_rev; /* SLI revision number */ 3173331766Sken uint32_t sli_family; 3174331766Sken uint32_t if_type; /* SLI Interface type */ 3175331766Sken 3176331766Sken sli4_asic_type_e asic_type; /*<< ASIC type */ 3177331766Sken sli4_asic_rev_e asic_rev; /*<< ASIC revision */ 3178331766Sken uint32_t physical_port; 3179331766Sken 3180331766Sken struct { 3181331766Sken uint16_t e_d_tov; 3182331766Sken uint16_t r_a_tov; 3183331766Sken uint16_t max_qcount[SLI_QTYPE_MAX]; 3184331766Sken uint32_t max_qentries[SLI_QTYPE_MAX]; 3185331766Sken uint16_t count_mask[SLI_QTYPE_MAX]; 3186331766Sken uint16_t count_method[SLI_QTYPE_MAX]; 3187331766Sken uint32_t qpage_count[SLI_QTYPE_MAX]; 3188331766Sken uint16_t link_module_type; 3189331766Sken uint8_t rq_batch; 3190331766Sken uint16_t rq_min_buf_size; 3191331766Sken uint32_t rq_max_buf_size; 3192331766Sken uint8_t topology; 3193331766Sken uint8_t wwpn[8]; 3194331766Sken uint8_t wwnn[8]; 3195331766Sken uint32_t fw_rev[2]; 3196331766Sken uint8_t fw_name[2][16]; 3197331766Sken char ipl_name[16]; 3198331766Sken uint32_t hw_rev[3]; 3199331766Sken uint8_t port_number; 3200331766Sken char port_name[2]; 3201331766Sken char bios_version_string[32]; 3202331766Sken uint8_t dual_ulp_capable; 3203331766Sken uint8_t is_ulp_fc[2]; 3204331766Sken /* 3205331766Sken * Tracks the port resources using extents metaphor. For 3206331766Sken * devices that don't implement extents (i.e. 3207331766Sken * has_extents == FALSE), the code models each resource as 3208331766Sken * a single large extent. 3209331766Sken */ 3210331766Sken struct { 3211331766Sken uint32_t number; /* number of extents */ 3212331766Sken uint32_t size; /* number of elements in each extent */ 3213331766Sken uint32_t n_alloc;/* number of elements allocated */ 3214331766Sken uint32_t *base; 3215331766Sken ocs_bitmap_t *use_map;/* bitmap showing resources in use */ 3216331766Sken uint32_t map_size;/* number of bits in bitmap */ 3217331766Sken } extent[SLI_RSRC_MAX]; 3218331766Sken sli4_features_t features; 3219331766Sken uint32_t has_extents:1, 3220331766Sken auto_reg:1, 3221331766Sken auto_xfer_rdy:1, 3222331766Sken hdr_template_req:1, 3223331766Sken perf_hint:1, 3224331766Sken perf_wq_id_association:1, 3225331766Sken cq_create_version:2, 3226331766Sken mq_create_version:2, 3227331766Sken high_login_mode:1, 3228331766Sken sgl_pre_registered:1, 3229331766Sken sgl_pre_registration_required:1, 3230331766Sken t10_dif_inline_capable:1, 3231331766Sken t10_dif_separate_capable:1; 3232331766Sken uint32_t sge_supported_length; 3233331766Sken uint32_t sgl_page_sizes; 3234331766Sken uint32_t max_sgl_pages; 3235331766Sken sli4_sgl_chaining_params_t sgl_chaining_params; 3236331766Sken size_t wqe_size; 3237331766Sken } config; 3238331766Sken 3239331766Sken /* 3240331766Sken * Callback functions 3241331766Sken */ 3242331766Sken int32_t (*link)(void *, void *); 3243331766Sken void *link_arg; 3244331766Sken int32_t (*fip)(void *, void *); 3245331766Sken void *fip_arg; 3246331766Sken 3247331766Sken ocs_dma_t bmbx; 3248331766Sken#if defined(OCS_INCLUDE_DEBUG) 3249331766Sken /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG 3250331766Sken * commands for BMBX dumping purposes */ 3251331766Sken ocs_dma_t *bmbx_non_emb_pmd; 3252331766Sken#endif 3253331766Sken 3254331766Sken struct { 3255331766Sken ocs_dma_t data; 3256331766Sken uint32_t length; 3257331766Sken } vpd; 3258331766Sken} sli4_t; 3259331766Sken 3260331766Sken/** 3261331766Sken * Get / set parameter functions 3262331766Sken */ 3263331766Skenstatic inline uint32_t 3264331766Skensli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc) 3265331766Sken{ 3266331766Sken if (rsrc >= SLI_RSRC_MAX) { 3267331766Sken return 0; 3268331766Sken } 3269331766Sken 3270331766Sken return sli4->config.extent[rsrc].size; 3271331766Sken} 3272331766Sken 3273331766Skenstatic inline uint32_t 3274331766Skensli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype) 3275331766Sken{ 3276331766Sken if (qtype >= SLI_QTYPE_MAX) { 3277331766Sken return 0; 3278331766Sken } 3279331766Sken return sli4->config.max_qcount[qtype]; 3280331766Sken} 3281331766Sken 3282331766Skenstatic inline uint32_t 3283331766Skensli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype) 3284331766Sken{ 3285331766Sken 3286331766Sken return sli4->config.max_qentries[qtype]; 3287331766Sken} 3288331766Sken 3289331766Skenstatic inline uint32_t 3290331766Skensli_get_max_sge(sli4_t *sli4) 3291331766Sken{ 3292331766Sken return sli4->config.sge_supported_length; 3293331766Sken} 3294331766Sken 3295331766Skenstatic inline uint32_t 3296331766Skensli_get_max_sgl(sli4_t *sli4) 3297331766Sken{ 3298331766Sken 3299331766Sken if (sli4->config.sgl_page_sizes != 1) { 3300331766Sken ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n", 3301331766Sken sli4->config.sgl_page_sizes); 3302331766Sken return 0; 3303331766Sken } 3304331766Sken 3305331766Sken return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t)); 3306331766Sken} 3307331766Sken 3308331766Skenstatic inline sli4_link_medium_e 3309331766Skensli_get_medium(sli4_t *sli4) 3310331766Sken{ 3311331766Sken switch (sli4->config.topology) { 3312331766Sken case SLI4_READ_CFG_TOPO_FCOE: 3313331766Sken return SLI_LINK_MEDIUM_ETHERNET; 3314331766Sken case SLI4_READ_CFG_TOPO_FC: 3315331766Sken case SLI4_READ_CFG_TOPO_FC_DA: 3316331766Sken case SLI4_READ_CFG_TOPO_FC_AL: 3317331766Sken return SLI_LINK_MEDIUM_FC; 3318331766Sken default: 3319331766Sken return SLI_LINK_MEDIUM_MAX; 3320331766Sken } 3321331766Sken} 3322331766Sken 3323331766Skenstatic inline void 3324331766Skensli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset) 3325331766Sken{ 3326331766Sken sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params; 3327331766Sken 3328331766Sken 3329331766Sken ocs_memset(sge, 0, sizeof(*sge)); 3330331766Sken sge->sge_type = SLI4_SGE_TYPE_CHAIN; 3331331766Sken sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi; 3332331766Sken sge->buffer_address_low = 3333331766Sken (uint32_t)((cparms->chain_sge_initial_value_lo | 3334331766Sken (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) << 3335331766Sken cparms->sgl_index_field_offset) | 3336331766Sken (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) << 3337331766Sken cparms->frag_num_field_offset) | 3338331766Sken offset) >> 3); 3339331766Sken} 3340331766Sken 3341331766Skenstatic inline uint32_t 3342331766Skensli_get_sli_rev(sli4_t *sli4) 3343331766Sken{ 3344331766Sken return sli4->sli_rev; 3345331766Sken} 3346331766Sken 3347331766Skenstatic inline uint32_t 3348331766Skensli_get_sli_family(sli4_t *sli4) 3349331766Sken{ 3350331766Sken return sli4->sli_family; 3351331766Sken} 3352331766Sken 3353331766Skenstatic inline uint32_t 3354331766Skensli_get_if_type(sli4_t *sli4) 3355331766Sken{ 3356331766Sken return sli4->if_type; 3357331766Sken} 3358331766Sken 3359331766Skenstatic inline void * 3360331766Skensli_get_wwn_port(sli4_t *sli4) 3361331766Sken{ 3362331766Sken return sli4->config.wwpn; 3363331766Sken} 3364331766Sken 3365331766Skenstatic inline void * 3366331766Skensli_get_wwn_node(sli4_t *sli4) 3367331766Sken{ 3368331766Sken return sli4->config.wwnn; 3369331766Sken} 3370331766Sken 3371331766Skenstatic inline void * 3372331766Skensli_get_vpd(sli4_t *sli4) 3373331766Sken{ 3374331766Sken return sli4->vpd.data.virt; 3375331766Sken} 3376331766Sken 3377331766Skenstatic inline uint32_t 3378331766Skensli_get_vpd_len(sli4_t *sli4) 3379331766Sken{ 3380331766Sken return sli4->vpd.length; 3381331766Sken} 3382331766Sken 3383331766Skenstatic inline uint32_t 3384331766Skensli_get_fw_revision(sli4_t *sli4, uint32_t which) 3385331766Sken{ 3386331766Sken return sli4->config.fw_rev[which]; 3387331766Sken} 3388331766Sken 3389331766Skenstatic inline void * 3390331766Skensli_get_fw_name(sli4_t *sli4, uint32_t which) 3391331766Sken{ 3392331766Sken return sli4->config.fw_name[which]; 3393331766Sken} 3394331766Sken 3395331766Skenstatic inline char * 3396331766Skensli_get_ipl_name(sli4_t *sli4) 3397331766Sken{ 3398331766Sken return sli4->config.ipl_name; 3399331766Sken} 3400331766Sken 3401331766Skenstatic inline uint32_t 3402331766Skensli_get_hw_revision(sli4_t *sli4, uint32_t which) 3403331766Sken{ 3404331766Sken return sli4->config.hw_rev[which]; 3405331766Sken} 3406331766Sken 3407331766Skenstatic inline uint32_t 3408331766Skensli_get_auto_xfer_rdy_capable(sli4_t *sli4) 3409331766Sken{ 3410331766Sken return sli4->config.auto_xfer_rdy; 3411331766Sken} 3412331766Sken 3413331766Skenstatic inline uint32_t 3414331766Skensli_get_dif_capable(sli4_t *sli4) 3415331766Sken{ 3416331766Sken return sli4->config.features.flag.dif; 3417331766Sken} 3418331766Sken 3419331766Skenstatic inline uint32_t 3420331766Skensli_is_dif_inline_capable(sli4_t *sli4) 3421331766Sken{ 3422331766Sken return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable; 3423331766Sken} 3424331766Sken 3425331766Skenstatic inline uint32_t 3426331766Skensli_is_dif_separate_capable(sli4_t *sli4) 3427331766Sken{ 3428331766Sken return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable; 3429331766Sken} 3430331766Sken 3431331766Skenstatic inline uint32_t 3432331766Skensli_get_is_dual_ulp_capable(sli4_t *sli4) 3433331766Sken{ 3434331766Sken return sli4->config.dual_ulp_capable; 3435331766Sken} 3436331766Sken 3437331766Skenstatic inline uint32_t 3438331766Skensli_get_is_sgl_chaining_capable(sli4_t *sli4) 3439331766Sken{ 3440331766Sken return sli4->config.sgl_chaining_params.chaining_capable; 3441331766Sken} 3442331766Sken 3443331766Skenstatic inline uint32_t 3444331766Skensli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp) 3445331766Sken{ 3446331766Sken return sli4->config.is_ulp_fc[ulp]; 3447331766Sken} 3448331766Sken 3449331766Skenstatic inline uint32_t 3450331766Skensli_get_hlm_capable(sli4_t *sli4) 3451331766Sken{ 3452331766Sken return sli4->config.features.flag.hlm; 3453331766Sken} 3454331766Sken 3455331766Skenstatic inline int32_t 3456331766Skensli_set_hlm(sli4_t *sli4, uint32_t value) 3457331766Sken{ 3458331766Sken if (value && !sli4->config.features.flag.hlm) { 3459331766Sken ocs_log_test(sli4->os, "HLM not supported\n"); 3460331766Sken return -1; 3461331766Sken } 3462331766Sken 3463331766Sken sli4->config.high_login_mode = value != 0 ? TRUE : FALSE; 3464331766Sken 3465331766Sken return 0; 3466331766Sken} 3467331766Sken 3468331766Skenstatic inline uint32_t 3469331766Skensli_get_hlm(sli4_t *sli4) 3470331766Sken{ 3471331766Sken return sli4->config.high_login_mode; 3472331766Sken} 3473331766Sken 3474331766Skenstatic inline uint32_t 3475331766Skensli_get_sgl_preregister_required(sli4_t *sli4) 3476331766Sken{ 3477331766Sken return sli4->config.sgl_pre_registration_required; 3478331766Sken} 3479331766Sken 3480331766Skenstatic inline uint32_t 3481331766Skensli_get_sgl_preregister(sli4_t *sli4) 3482331766Sken{ 3483331766Sken return sli4->config.sgl_pre_registered; 3484331766Sken} 3485331766Sken 3486331766Skenstatic inline int32_t 3487331766Skensli_set_sgl_preregister(sli4_t *sli4, uint32_t value) 3488331766Sken{ 3489331766Sken if ((value == 0) && sli4->config.sgl_pre_registration_required) { 3490331766Sken ocs_log_test(sli4->os, "SGL pre-registration required\n"); 3491331766Sken return -1; 3492331766Sken } 3493331766Sken 3494331766Sken sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE; 3495331766Sken 3496331766Sken return 0; 3497331766Sken} 3498331766Sken 3499331766Skenstatic inline sli4_asic_type_e 3500331766Skensli_get_asic_type(sli4_t *sli4) 3501331766Sken{ 3502331766Sken return sli4->asic_type; 3503331766Sken} 3504331766Sken 3505331766Skenstatic inline sli4_asic_rev_e 3506331766Skensli_get_asic_rev(sli4_t *sli4) 3507331766Sken{ 3508331766Sken return sli4->asic_rev; 3509331766Sken} 3510331766Sken 3511331766Skenstatic inline int32_t 3512331766Skensli_set_topology(sli4_t *sli4, uint32_t value) 3513331766Sken{ 3514331766Sken int32_t rc = 0; 3515331766Sken 3516331766Sken switch (value) { 3517331766Sken case SLI4_READ_CFG_TOPO_FCOE: 3518331766Sken case SLI4_READ_CFG_TOPO_FC: 3519331766Sken case SLI4_READ_CFG_TOPO_FC_DA: 3520331766Sken case SLI4_READ_CFG_TOPO_FC_AL: 3521331766Sken sli4->config.topology = value; 3522331766Sken break; 3523331766Sken default: 3524331766Sken ocs_log_test(sli4->os, "unsupported topology %#x\n", value); 3525331766Sken rc = -1; 3526331766Sken } 3527331766Sken 3528331766Sken return rc; 3529331766Sken} 3530331766Sken 3531331766Skenstatic inline uint16_t 3532331766Skensli_get_link_module_type(sli4_t *sli4) 3533331766Sken{ 3534331766Sken return sli4->config.link_module_type; 3535331766Sken} 3536331766Sken 3537331766Skenstatic inline char * 3538331766Skensli_get_portnum(sli4_t *sli4) 3539331766Sken{ 3540331766Sken return sli4->config.port_name; 3541331766Sken} 3542331766Sken 3543331766Skenstatic inline char * 3544331766Skensli_get_bios_version_string(sli4_t *sli4) 3545331766Sken{ 3546331766Sken return sli4->config.bios_version_string; 3547331766Sken} 3548331766Sken 3549331766Skenstatic inline uint32_t 3550331766Skensli_convert_mask_to_count(uint32_t method, uint32_t mask) 3551331766Sken{ 3552331766Sken uint32_t count = 0; 3553331766Sken 3554331766Sken if (method) { 3555331766Sken count = 1 << ocs_lg2(mask); 3556331766Sken count *= 16; 3557331766Sken } else { 3558331766Sken count = mask; 3559331766Sken } 3560331766Sken 3561331766Sken return count; 3562331766Sken} 3563331766Sken 3564331766Sken/** 3565331766Sken * @brief Common Create Queue function prototype 3566331766Sken */ 3567331766Skentypedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 3568331766Sken 3569331766Sken/** 3570331766Sken * @brief Common Destroy Queue function prototype 3571331766Sken */ 3572331766Skentypedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t); 3573331766Sken 3574331766Sken 3575331766Sken/**************************************************************************** 3576331766Sken * Function prototypes 3577331766Sken */ 3578331766Skenextern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t); 3579331766Skenextern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t); 3580331766Skenextern int32_t sli_cmd_config_link(sli4_t *, void *, size_t); 3581331766Skenextern int32_t sli_cmd_down_link(sli4_t *, void *, size_t); 3582331766Skenextern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t); 3583331766Skenextern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3584331766Skenextern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t); 3585331766Skenextern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters); 3586331766Skenextern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t); 3587331766Skenextern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 3588331766Skenextern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t); 3589331766Skenextern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t); 3590331766Skenextern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t); 3591331766Skenextern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 3592331766Skenextern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *); 3593331766Skenextern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t); 3594331766Skenextern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t); 3595331766Skentypedef struct { 3596331766Sken uint16_t rq_id; 3597331766Sken uint8_t r_ctl_mask; 3598331766Sken uint8_t r_ctl_match; 3599331766Sken uint8_t type_mask; 3600331766Sken uint8_t type_match; 3601331766Sken} sli4_cmd_rq_cfg_t; 3602331766Skenextern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t, 3603331766Sken sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t); 3604331766Skenextern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *); 3605331766Sken 3606331766Skenextern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t); 3607331766Skenextern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *); 3608331766Skenextern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t); 3609331766Skenextern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3610331766Skenextern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t); 3611331766Skenextern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t); 3612331766Skenextern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t); 3613331766Skenextern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t); 3614331766Skenextern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t); 3615331766Skenextern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t); 3616331766Skenextern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t); 3617331766Skenextern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t, 3618331766Sken uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *); 3619331766Skenextern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *); 3620331766Skenextern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t, 3621331766Sken uint32_t, char *, ocs_dma_t *); 3622331766Skenextern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size, 3623331766Sken ocs_dma_t *cmd, 3624331766Sken ocs_dma_t *resp); 3625331766Skenextern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size, 3626331766Sken uint8_t query, uint8_t is_buffer_list, 3627331766Sken ocs_dma_t *buffer, uint8_t fdb); 3628331766Skenextern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*); 3629331766Skenextern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf, 3630331766Sken size_t size, uint32_t start_profile_index, ocs_dma_t *dma); 3631331766Skenextern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf, 3632331766Sken size_t size); 3633331766Skenextern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf, 3634331766Sken size_t size, 3635331766Sken uint32_t fd, 3636331766Sken uint32_t active_profile_id); 3637331766Skenextern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf, 3638331766Sken size_t size, ocs_dma_t *dma); 3639331766Skenextern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf, 3640331766Sken size_t size, ocs_dma_t *dma, 3641331766Sken uint32_t fd, uint32_t active_link_config_id); 3642331766Skenextern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf, 3643331766Sken size_t size); 3644331766Skenextern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf, 3645331766Sken size_t size, ocs_dma_t *dma); 3646331766Skenextern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf, 3647331766Sken size_t size, ocs_dma_t *dma, 3648331766Sken uint8_t profile_id, uint32_t descriptor_count, 3649331766Sken uint8_t isap); 3650331766Sken 3651331766Skenextern int32_t sli_cqe_mq(void *); 3652331766Skenextern int32_t sli_cqe_async(sli4_t *, void *); 3653331766Sken 3654331766Skenextern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e); 3655331766Skenextern void sli_calc_max_qentries(sli4_t *sli4); 3656331766Skenextern int32_t sli_init(sli4_t *); 3657331766Skenextern int32_t sli_reset(sli4_t *); 3658331766Skenextern int32_t sli_fw_reset(sli4_t *); 3659331766Skenextern int32_t sli_teardown(sli4_t *); 3660331766Skenextern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *); 3661331766Skenextern int32_t sli_bmbx_command(sli4_t *); 3662331766Skenextern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t); 3663331766Skenextern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *); 3664331766Skenextern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult); 3665331766Skenextern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t); 3666331766Skenextern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]); 3667331766Skenextern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t); 3668331766Skenextern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t); 3669331766Skenextern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *); 3670331766Skenextern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *); 3671331766Skenextern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t); 3672331766Skenextern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t); 3673331766Skenextern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3674331766Skenextern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3675331766Skenextern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *); 3676331766Skenextern int32_t sli_queue_index(sli4_t *, sli4_queue_t *); 3677331766Skenextern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3678331766Skenextern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3679331766Skenextern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *); 3680331766Skenextern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t); 3681331766Skenextern int32_t sli_resource_reset(sli4_t *, sli4_resource_e); 3682331766Skenextern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *); 3683331766Skenextern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 3684331766Sken 3685331766Skenextern int32_t sli_raise_ue(sli4_t *, uint8_t); 3686331766Skenextern int32_t sli_dump_is_ready(sli4_t *); 3687331766Skenextern int32_t sli_dump_is_present(sli4_t *); 3688331766Skenextern int32_t sli_reset_required(sli4_t *); 3689331766Skenextern int32_t sli_fw_error_status(sli4_t *); 3690331766Skenextern int32_t sli_fw_ready(sli4_t *); 3691331766Skenextern uint32_t sli_reg_read(sli4_t *, sli4_regname_e); 3692331766Skenextern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t); 3693331766Skenextern int32_t sli_link_is_configurable(sli4_t *); 3694331766Sken 3695331766Sken#include "ocs_fcp.h" 3696331766Sken 3697331766Sken/** 3698331766Sken * @brief Maximum value for a FCFI 3699331766Sken * 3700331766Sken * Note that although most commands provide a 16 bit field for the FCFI, 3701331766Sken * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for 3702331766Sken * the returned FCFI. Then effectively, the FCFI cannot be larger than 3703331766Sken * 1 << 6 or 64. 3704331766Sken */ 3705331766Sken#define SLI4_MAX_FCFI 64 3706331766Sken 3707331766Sken/** 3708331766Sken * @brief Maximum value for FCF index 3709331766Sken * 3710331766Sken * The SLI-4 specification uses a 16 bit field in most places for the FCF 3711331766Sken * index, but practically, this value will be much smaller. Arbitrarily 3712331766Sken * limit the max FCF index to match the max FCFI value. 3713331766Sken */ 3714331766Sken#define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI 3715331766Sken 3716331766Sken/************************************************************************* 3717331766Sken * SLI-4 FC/FCoE mailbox command formats and definitions. 3718331766Sken */ 3719331766Sken 3720331766Sken/** 3721331766Sken * FC/FCoE opcode (OPC) values. 3722331766Sken */ 3723331766Sken#define SLI4_OPC_FCOE_WQ_CREATE 0x1 3724331766Sken#define SLI4_OPC_FCOE_WQ_DESTROY 0x2 3725331766Sken#define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3 3726331766Sken#define SLI4_OPC_FCOE_RQ_CREATE 0x5 3727331766Sken#define SLI4_OPC_FCOE_RQ_DESTROY 0x6 3728331766Sken#define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8 3729331766Sken#define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb 3730331766Sken#define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10 3731331766Sken 3732331766Sken/* Use the default CQ associated with the WQ */ 3733331766Sken#define SLI4_CQ_DEFAULT 0xffff 3734331766Sken 3735331766Skentypedef struct sli4_physical_page_descriptor_s { 3736331766Sken uint32_t low; 3737331766Sken uint32_t high; 3738331766Sken} sli4_physical_page_descriptor_t; 3739331766Sken 3740331766Sken/** 3741331766Sken * @brief FCOE_WQ_CREATE 3742331766Sken * 3743331766Sken * Create a Work Queue for FC/FCoE use. 3744331766Sken */ 3745331766Sken#define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4 3746331766Sken 3747331766Skentypedef struct sli4_req_fcoe_wq_create_s { 3748331766Sken sli4_req_hdr_t hdr; 3749331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3750331766Sken uint32_t num_pages:8, 3751331766Sken dua:1, 3752331766Sken :7, 3753331766Sken cq_id:16; 3754331766Sken sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES]; 3755331766Sken uint32_t bqu:1, 3756331766Sken :7, 3757331766Sken ulp:8, 3758331766Sken :16; 3759331766Sken#else 3760331766Sken#error big endian version not defined 3761331766Sken#endif 3762331766Sken} sli4_req_fcoe_wq_create_t; 3763331766Sken 3764331766Sken/** 3765331766Sken * @brief FCOE_WQ_CREATE_V1 3766331766Sken * 3767331766Sken * Create a version 1 Work Queue for FC/FCoE use. 3768331766Sken */ 3769331766Skentypedef struct sli4_req_fcoe_wq_create_v1_s { 3770331766Sken sli4_req_hdr_t hdr; 3771331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3772331766Sken uint32_t num_pages:16, 3773331766Sken cq_id:16; 3774331766Sken uint32_t page_size:8, 3775331766Sken wqe_size:4, 3776331766Sken :4, 3777331766Sken wqe_count:16; 3778331766Sken uint32_t rsvd6; 3779331766Sken sli4_physical_page_descriptor_t page_physical_address[8]; 3780331766Sken#else 3781331766Sken#error big endian version not defined 3782331766Sken#endif 3783331766Sken} sli4_req_fcoe_wq_create_v1_t; 3784331766Sken 3785331766Sken#define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8 3786331766Sken 3787331766Sken/** 3788331766Sken * @brief FCOE_WQ_DESTROY 3789331766Sken * 3790331766Sken * Destroy an FC/FCoE Work Queue. 3791331766Sken */ 3792331766Skentypedef struct sli4_req_fcoe_wq_destroy_s { 3793331766Sken sli4_req_hdr_t hdr; 3794331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3795331766Sken uint32_t wq_id:16, 3796331766Sken :16; 3797331766Sken#else 3798331766Sken#error big endian version not defined 3799331766Sken#endif 3800331766Sken} sli4_req_fcoe_wq_destroy_t; 3801331766Sken 3802331766Sken/** 3803331766Sken * @brief FCOE_POST_SGL_PAGES 3804331766Sken * 3805331766Sken * Register the scatter gather list (SGL) memory and associate it with an XRI. 3806331766Sken */ 3807331766Skentypedef struct sli4_req_fcoe_post_sgl_pages_s { 3808331766Sken sli4_req_hdr_t hdr; 3809331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3810331766Sken uint32_t xri_start:16, 3811331766Sken xri_count:16; 3812331766Sken struct { 3813331766Sken uint32_t page0_low; 3814331766Sken uint32_t page0_high; 3815331766Sken uint32_t page1_low; 3816331766Sken uint32_t page1_high; 3817331766Sken } page_set[10]; 3818331766Sken#else 3819331766Sken#error big endian version not defined 3820331766Sken#endif 3821331766Sken} sli4_req_fcoe_post_sgl_pages_t; 3822331766Sken 3823331766Sken/** 3824331766Sken * @brief FCOE_RQ_CREATE 3825331766Sken * 3826331766Sken * Create a Receive Queue for FC/FCoE use. 3827331766Sken */ 3828331766Skentypedef struct sli4_req_fcoe_rq_create_s { 3829331766Sken sli4_req_hdr_t hdr; 3830331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3831331766Sken uint32_t num_pages:16, 3832331766Sken dua:1, 3833331766Sken bqu:1, 3834331766Sken :6, 3835331766Sken ulp:8; 3836331766Sken uint32_t :16, 3837331766Sken rqe_count:4, 3838331766Sken :12; 3839331766Sken uint32_t rsvd6; 3840331766Sken uint32_t buffer_size:16, 3841331766Sken cq_id:16; 3842331766Sken uint32_t rsvd8; 3843331766Sken sli4_physical_page_descriptor_t page_physical_address[8]; 3844331766Sken#else 3845331766Sken#error big endian version not defined 3846331766Sken#endif 3847331766Sken} sli4_req_fcoe_rq_create_t; 3848331766Sken 3849331766Sken#define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8 3850331766Sken#define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128 3851331766Sken#define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048 3852331766Sken 3853331766Sken/** 3854331766Sken * @brief FCOE_RQ_CREATE_V1 3855331766Sken * 3856331766Sken * Create a version 1 Receive Queue for FC/FCoE use. 3857331766Sken */ 3858331766Skentypedef struct sli4_req_fcoe_rq_create_v1_s { 3859331766Sken sli4_req_hdr_t hdr; 3860331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3861331766Sken uint32_t num_pages:16, 3862331766Sken :13, 3863331766Sken dim:1, 3864331766Sken dfd:1, 3865331766Sken dnb:1; 3866331766Sken uint32_t page_size:8, 3867331766Sken rqe_size:4, 3868331766Sken :4, 3869331766Sken rqe_count:16; 3870331766Sken uint32_t rsvd6; 3871331766Sken uint32_t :16, 3872331766Sken cq_id:16; 3873331766Sken uint32_t buffer_size; 3874331766Sken sli4_physical_page_descriptor_t page_physical_address[8]; 3875331766Sken#else 3876331766Sken#error big endian version not defined 3877331766Sken#endif 3878331766Sken} sli4_req_fcoe_rq_create_v1_t; 3879331766Sken 3880331766Sken 3881331766Sken/** 3882331766Sken * @brief FCOE_RQ_CREATE_V2 3883331766Sken * 3884331766Sken * Create a version 2 Receive Queue for FC/FCoE use. 3885331766Sken */ 3886331766Skentypedef struct sli4_req_fcoe_rq_create_v2_s { 3887331766Sken sli4_req_hdr_t hdr; 3888331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3889331766Sken uint32_t num_pages:16, 3890331766Sken rq_count:8, 3891331766Sken :5, 3892331766Sken dim:1, 3893331766Sken dfd:1, 3894331766Sken dnb:1; 3895331766Sken uint32_t page_size:8, 3896331766Sken rqe_size:4, 3897331766Sken :4, 3898331766Sken rqe_count:16; 3899331766Sken uint32_t hdr_buffer_size:16, 3900331766Sken payload_buffer_size:16; 3901331766Sken uint32_t base_cq_id:16, 3902331766Sken :16; 3903331766Sken uint32_t rsvd; 3904331766Sken sli4_physical_page_descriptor_t page_physical_address[0]; 3905331766Sken#else 3906331766Sken#error big endian version not defined 3907331766Sken#endif 3908331766Sken} sli4_req_fcoe_rq_create_v2_t; 3909331766Sken 3910331766Sken 3911331766Sken#define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8 3912331766Sken#define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64 3913331766Sken#define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048 3914331766Sken 3915331766Sken#define SLI4_FCOE_RQE_SIZE_8 0x2 3916331766Sken#define SLI4_FCOE_RQE_SIZE_16 0x3 3917331766Sken#define SLI4_FCOE_RQE_SIZE_32 0x4 3918331766Sken#define SLI4_FCOE_RQE_SIZE_64 0x5 3919331766Sken#define SLI4_FCOE_RQE_SIZE_128 0x6 3920331766Sken 3921331766Sken#define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1 3922331766Sken#define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2 3923331766Sken#define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4 3924331766Sken#define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8 3925331766Sken#define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10 3926331766Sken 3927331766Sken#define SLI4_FCOE_RQE_SIZE 8 3928331766Sken 3929331766Sken/** 3930331766Sken * @brief FCOE_RQ_DESTROY 3931331766Sken * 3932331766Sken * Destroy an FC/FCoE Receive Queue. 3933331766Sken */ 3934331766Skentypedef struct sli4_req_fcoe_rq_destroy_s { 3935331766Sken sli4_req_hdr_t hdr; 3936331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3937331766Sken uint32_t rq_id:16, 3938331766Sken :16; 3939331766Sken#else 3940331766Sken#error big endian version not defined 3941331766Sken#endif 3942331766Sken} sli4_req_fcoe_rq_destroy_t; 3943331766Sken 3944331766Sken/** 3945331766Sken * @brief FCOE_READ_FCF_TABLE 3946331766Sken * 3947331766Sken * Retrieve a FCF database (also known as a table) entry created by the SLI Port 3948331766Sken * during FIP discovery. 3949331766Sken */ 3950331766Skentypedef struct sli4_req_fcoe_read_fcf_table_s { 3951331766Sken sli4_req_hdr_t hdr; 3952331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3953331766Sken uint32_t fcf_index:16, 3954331766Sken :16; 3955331766Sken#else 3956331766Sken#error big endian version not defined 3957331766Sken#endif 3958331766Sken} sli4_req_fcoe_read_fcf_table_t; 3959331766Sken 3960331766Sken/* A FCF index of -1 on the request means return the first valid entry */ 3961331766Sken#define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX) 3962331766Sken 3963331766Sken/** 3964331766Sken * @brief FCF table entry 3965331766Sken * 3966331766Sken * This is the information returned by the FCOE_READ_FCF_TABLE command. 3967331766Sken */ 3968331766Skentypedef struct sli4_fcf_entry_s { 3969331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3970331766Sken uint32_t max_receive_size; 3971331766Sken uint32_t fip_keep_alive; 3972331766Sken uint32_t fip_priority; 3973331766Sken uint8_t fcf_mac_address[6]; 3974331766Sken uint8_t fcf_available; 3975331766Sken uint8_t mac_address_provider; 3976331766Sken uint8_t fabric_name_id[8]; 3977331766Sken uint8_t fc_map[3]; 3978331766Sken uint8_t val:1, 3979331766Sken fc:1, 3980331766Sken :5, 3981331766Sken sol:1; 3982331766Sken uint32_t fcf_index:16, 3983331766Sken fcf_state:16; 3984331766Sken uint8_t vlan_bitmap[512]; 3985331766Sken uint8_t switch_name[8]; 3986331766Sken#else 3987331766Sken#error big endian version not defined 3988331766Sken#endif 3989331766Sken} sli4_fcf_entry_t; 3990331766Sken 3991331766Sken/** 3992331766Sken * @brief FCOE_READ_FCF_TABLE response. 3993331766Sken */ 3994331766Skentypedef struct sli4_res_fcoe_read_fcf_table_s { 3995331766Sken sli4_res_hdr_t hdr; 3996331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 3997331766Sken uint32_t event_tag; 3998331766Sken uint32_t next_index:16, 3999331766Sken :16; 4000331766Sken sli4_fcf_entry_t fcf_entry; 4001331766Sken#else 4002331766Sken#error big endian version not defined 4003331766Sken#endif 4004331766Sken} sli4_res_fcoe_read_fcf_table_t; 4005331766Sken 4006331766Sken/* A next FCF index of -1 in the response means this is the last valid entry */ 4007331766Sken#define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX) 4008331766Sken 4009331766Sken 4010331766Sken/** 4011331766Sken * @brief FCOE_POST_HDR_TEMPLATES 4012331766Sken */ 4013331766Skentypedef struct sli4_req_fcoe_post_hdr_templates_s { 4014331766Sken sli4_req_hdr_t hdr; 4015331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4016331766Sken uint32_t rpi_offset:16, 4017331766Sken page_count:16; 4018331766Sken sli4_physical_page_descriptor_t page_descriptor[0]; 4019331766Sken#else 4020331766Sken#error big endian version not defined 4021331766Sken#endif 4022331766Sken} sli4_req_fcoe_post_hdr_templates_t; 4023331766Sken 4024331766Sken#define SLI4_FCOE_HDR_TEMPLATE_SIZE 64 4025331766Sken 4026331766Sken/** 4027331766Sken * @brief FCOE_REDISCOVER_FCF 4028331766Sken */ 4029331766Skentypedef struct sli4_req_fcoe_rediscover_fcf_s { 4030331766Sken sli4_req_hdr_t hdr; 4031331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4032331766Sken uint32_t fcf_count:16, 4033331766Sken :16; 4034331766Sken uint32_t rsvd5; 4035331766Sken uint16_t fcf_index[16]; 4036331766Sken#else 4037331766Sken#error big endian version not defined 4038331766Sken#endif 4039331766Sken} sli4_req_fcoe_rediscover_fcf_t; 4040331766Sken 4041331766Sken 4042331766Sken/** 4043331766Sken * Work Queue Entry (WQE) types. 4044331766Sken */ 4045331766Sken#define SLI4_WQE_ABORT 0x0f 4046331766Sken#define SLI4_WQE_ELS_REQUEST64 0x8a 4047331766Sken#define SLI4_WQE_FCP_IBIDIR64 0xac 4048331766Sken#define SLI4_WQE_FCP_IREAD64 0x9a 4049331766Sken#define SLI4_WQE_FCP_IWRITE64 0x98 4050331766Sken#define SLI4_WQE_FCP_ICMND64 0x9c 4051331766Sken#define SLI4_WQE_FCP_TRECEIVE64 0xa1 4052331766Sken#define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5 4053331766Sken#define SLI4_WQE_FCP_TRSP64 0xa3 4054331766Sken#define SLI4_WQE_FCP_TSEND64 0x9f 4055331766Sken#define SLI4_WQE_GEN_REQUEST64 0xc2 4056331766Sken#define SLI4_WQE_SEND_FRAME 0xe1 4057331766Sken#define SLI4_WQE_XMIT_BCAST64 0X84 4058331766Sken#define SLI4_WQE_XMIT_BLS_RSP 0x97 4059331766Sken#define SLI4_WQE_ELS_RSP64 0x95 4060331766Sken#define SLI4_WQE_XMIT_SEQUENCE64 0x82 4061331766Sken#define SLI4_WQE_REQUEUE_XRI 0x93 4062331766Sken 4063331766Sken/** 4064331766Sken * WQE command types. 4065331766Sken */ 4066331766Sken#define SLI4_CMD_FCP_IREAD64_WQE 0x00 4067331766Sken#define SLI4_CMD_FCP_ICMND64_WQE 0x00 4068331766Sken#define SLI4_CMD_FCP_IWRITE64_WQE 0x01 4069331766Sken#define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02 4070331766Sken#define SLI4_CMD_FCP_TRSP64_WQE 0x03 4071331766Sken#define SLI4_CMD_FCP_TSEND64_WQE 0x07 4072331766Sken#define SLI4_CMD_GEN_REQUEST64_WQE 0x08 4073331766Sken#define SLI4_CMD_XMIT_BCAST64_WQE 0x08 4074331766Sken#define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08 4075331766Sken#define SLI4_CMD_ABORT_WQE 0x08 4076331766Sken#define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08 4077331766Sken#define SLI4_CMD_REQUEUE_XRI_WQE 0x0A 4078331766Sken#define SLI4_CMD_SEND_FRAME_WQE 0x0a 4079331766Sken 4080331766Sken#define SLI4_WQE_SIZE 0x05 4081331766Sken#define SLI4_WQE_EXT_SIZE 0x06 4082331766Sken 4083331766Sken#define SLI4_WQE_BYTES (16 * sizeof(uint32_t)) 4084331766Sken#define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t)) 4085331766Sken 4086331766Sken/* Mask for ccp (CS_CTL) */ 4087331766Sken#define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */ 4088331766Sken 4089331766Sken/** 4090331766Sken * @brief Generic WQE 4091331766Sken */ 4092331766Skentypedef struct sli4_generic_wqe_s { 4093331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4094331766Sken uint32_t cmd_spec0_5[6]; 4095331766Sken uint32_t xri_tag:16, 4096331766Sken context_tag:16; 4097331766Sken uint32_t :2, 4098331766Sken ct:2, 4099331766Sken :4, 4100331766Sken command:8, 4101331766Sken class:3, 4102331766Sken :1, 4103331766Sken pu:2, 4104331766Sken :2, 4105331766Sken timer:8; 4106331766Sken uint32_t abort_tag; 4107331766Sken uint32_t request_tag:16, 4108331766Sken :16; 4109331766Sken uint32_t ebde_cnt:4, 4110331766Sken :3, 4111331766Sken len_loc:2, 4112331766Sken qosd:1, 4113331766Sken :1, 4114331766Sken xbl:1, 4115331766Sken hlm:1, 4116331766Sken iod:1, 4117331766Sken dbde:1, 4118331766Sken wqes:1, 4119331766Sken pri:3, 4120331766Sken pv:1, 4121331766Sken eat:1, 4122331766Sken xc:1, 4123331766Sken :1, 4124331766Sken ccpe:1, 4125331766Sken ccp:8; 4126331766Sken uint32_t cmd_type:4, 4127331766Sken :3, 4128331766Sken wqec:1, 4129331766Sken :8, 4130331766Sken cq_id:16; 4131331766Sken#else 4132331766Sken#error big endian version not defined 4133331766Sken#endif 4134331766Sken} sli4_generic_wqe_t; 4135331766Sken 4136331766Sken/** 4137331766Sken * @brief WQE used to abort exchanges. 4138331766Sken */ 4139331766Skentypedef struct sli4_abort_wqe_s { 4140331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4141331766Sken uint32_t rsvd0; 4142331766Sken uint32_t rsvd1; 4143331766Sken uint32_t ext_t_tag; 4144331766Sken uint32_t ia:1, 4145331766Sken ir:1, 4146331766Sken :6, 4147331766Sken criteria:8, 4148331766Sken :16; 4149331766Sken uint32_t ext_t_mask; 4150331766Sken uint32_t t_mask; 4151331766Sken uint32_t xri_tag:16, 4152331766Sken context_tag:16; 4153331766Sken uint32_t :2, 4154331766Sken ct:2, 4155331766Sken :4, 4156331766Sken command:8, 4157331766Sken class:3, 4158331766Sken :1, 4159331766Sken pu:2, 4160331766Sken :2, 4161331766Sken timer:8; 4162331766Sken uint32_t t_tag; 4163331766Sken uint32_t request_tag:16, 4164331766Sken :16; 4165331766Sken uint32_t ebde_cnt:4, 4166331766Sken :3, 4167331766Sken len_loc:2, 4168331766Sken qosd:1, 4169331766Sken :1, 4170331766Sken xbl:1, 4171331766Sken :1, 4172331766Sken iod:1, 4173331766Sken dbde:1, 4174331766Sken wqes:1, 4175331766Sken pri:3, 4176331766Sken pv:1, 4177331766Sken eat:1, 4178331766Sken xc:1, 4179331766Sken :1, 4180331766Sken ccpe:1, 4181331766Sken ccp:8; 4182331766Sken uint32_t cmd_type:4, 4183331766Sken :3, 4184331766Sken wqec:1, 4185331766Sken :8, 4186331766Sken cq_id:16; 4187331766Sken#else 4188331766Sken#error big endian version not defined 4189331766Sken#endif 4190331766Sken} sli4_abort_wqe_t; 4191331766Sken 4192331766Sken#define SLI4_ABORT_CRITERIA_XRI_TAG 0x01 4193331766Sken#define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02 4194331766Sken#define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03 4195331766Sken#define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04 4196331766Sken 4197331766Skentypedef enum { 4198331766Sken SLI_ABORT_XRI, 4199331766Sken SLI_ABORT_ABORT_ID, 4200331766Sken SLI_ABORT_REQUEST_ID, 4201331766Sken SLI_ABORT_MAX, /* must be last */ 4202331766Sken} sli4_abort_type_e; 4203331766Sken 4204331766Sken/** 4205331766Sken * @brief WQE used to create an ELS request. 4206331766Sken */ 4207331766Skentypedef struct sli4_els_request64_wqe_s { 4208331766Sken sli4_bde_t els_request_payload; 4209331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4210331766Sken uint32_t els_request_payload_length; 4211331766Sken uint32_t sid:24, 4212331766Sken sp:1, 4213331766Sken :7; 4214331766Sken uint32_t remote_id:24, 4215331766Sken :8; 4216331766Sken uint32_t xri_tag:16, 4217331766Sken context_tag:16; 4218331766Sken uint32_t :2, 4219331766Sken ct:2, 4220331766Sken :4, 4221331766Sken command:8, 4222331766Sken class:3, 4223331766Sken ar:1, 4224331766Sken pu:2, 4225331766Sken :2, 4226331766Sken timer:8; 4227331766Sken uint32_t abort_tag; 4228331766Sken uint32_t request_tag:16, 4229331766Sken temporary_rpi:16; 4230331766Sken uint32_t ebde_cnt:4, 4231331766Sken :3, 4232331766Sken len_loc:2, 4233331766Sken qosd:1, 4234331766Sken :1, 4235331766Sken xbl:1, 4236331766Sken hlm:1, 4237331766Sken iod:1, 4238331766Sken dbde:1, 4239331766Sken wqes:1, 4240331766Sken pri:3, 4241331766Sken pv:1, 4242331766Sken eat:1, 4243331766Sken xc:1, 4244331766Sken :1, 4245331766Sken ccpe:1, 4246331766Sken ccp:8; 4247331766Sken uint32_t cmd_type:4, 4248331766Sken els_id:3, 4249331766Sken wqec:1, 4250331766Sken :8, 4251331766Sken cq_id:16; 4252331766Sken sli4_bde_t els_response_payload_bde; 4253331766Sken uint32_t max_response_payload_length; 4254331766Sken#else 4255331766Sken#error big endian version not defined 4256331766Sken#endif 4257331766Sken} sli4_els_request64_wqe_t; 4258331766Sken 4259331766Sken#define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0 4260331766Sken#define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1 4261331766Sken#define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2 4262331766Sken#define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3 4263331766Sken 4264331766Sken#define SLI4_ELS_REQUEST64_CLASS_2 0x1 4265331766Sken#define SLI4_ELS_REQUEST64_CLASS_3 0x2 4266331766Sken 4267331766Sken#define SLI4_ELS_REQUEST64_DIR_WRITE 0x0 4268331766Sken#define SLI4_ELS_REQUEST64_DIR_READ 0x1 4269331766Sken 4270331766Sken#define SLI4_ELS_REQUEST64_OTHER 0x0 4271331766Sken#define SLI4_ELS_REQUEST64_LOGO 0x1 4272331766Sken#define SLI4_ELS_REQUEST64_FDISC 0x2 4273331766Sken#define SLI4_ELS_REQUEST64_FLOGIN 0x3 4274331766Sken#define SLI4_ELS_REQUEST64_PLOGI 0x4 4275331766Sken 4276331766Sken#define SLI4_ELS_REQUEST64_CMD_GEN 0x08 4277331766Sken#define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c 4278331766Sken#define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d 4279331766Sken 4280331766Sken/** 4281331766Sken * @brief WQE used to create an FCP initiator no data command. 4282331766Sken */ 4283331766Skentypedef struct sli4_fcp_icmnd64_wqe_s { 4284331766Sken sli4_bde_t bde; 4285331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4286331766Sken uint32_t payload_offset_length:16, 4287331766Sken fcp_cmd_buffer_length:16; 4288331766Sken uint32_t rsvd4; 4289331766Sken uint32_t remote_n_port_id:24, 4290331766Sken :8; 4291331766Sken uint32_t xri_tag:16, 4292331766Sken context_tag:16; 4293331766Sken uint32_t dif:2, 4294331766Sken ct:2, 4295331766Sken bs:3, 4296331766Sken :1, 4297331766Sken command:8, 4298331766Sken class:3, 4299331766Sken :1, 4300331766Sken pu:2, 4301331766Sken erp:1, 4302331766Sken lnk:1, 4303331766Sken timer:8; 4304331766Sken uint32_t abort_tag; 4305331766Sken uint32_t request_tag:16, 4306331766Sken :16; 4307331766Sken uint32_t ebde_cnt:4, 4308331766Sken :3, 4309331766Sken len_loc:2, 4310331766Sken qosd:1, 4311331766Sken :1, 4312331766Sken xbl:1, 4313331766Sken hlm:1, 4314331766Sken iod:1, 4315331766Sken dbde:1, 4316331766Sken wqes:1, 4317331766Sken pri:3, 4318331766Sken pv:1, 4319331766Sken eat:1, 4320331766Sken xc:1, 4321331766Sken :1, 4322331766Sken ccpe:1, 4323331766Sken ccp:8; 4324331766Sken uint32_t cmd_type:4, 4325331766Sken :3, 4326331766Sken wqec:1, 4327331766Sken :8, 4328331766Sken cq_id:16; 4329331766Sken uint32_t rsvd12; 4330331766Sken uint32_t rsvd13; 4331331766Sken uint32_t rsvd14; 4332331766Sken uint32_t rsvd15; 4333331766Sken#else 4334331766Sken#error big endian version not defined 4335331766Sken#endif 4336331766Sken} sli4_fcp_icmnd64_wqe_t; 4337331766Sken 4338331766Sken/** 4339331766Sken * @brief WQE used to create an FCP initiator read. 4340331766Sken */ 4341331766Skentypedef struct sli4_fcp_iread64_wqe_s { 4342331766Sken sli4_bde_t bde; 4343331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4344331766Sken uint32_t payload_offset_length:16, 4345331766Sken fcp_cmd_buffer_length:16; 4346331766Sken uint32_t total_transfer_length; 4347331766Sken uint32_t remote_n_port_id:24, 4348331766Sken :8; 4349331766Sken uint32_t xri_tag:16, 4350331766Sken context_tag:16; 4351331766Sken uint32_t dif:2, 4352331766Sken ct:2, 4353331766Sken bs:3, 4354331766Sken :1, 4355331766Sken command:8, 4356331766Sken class:3, 4357331766Sken :1, 4358331766Sken pu:2, 4359331766Sken erp:1, 4360331766Sken lnk:1, 4361331766Sken timer:8; 4362331766Sken uint32_t abort_tag; 4363331766Sken uint32_t request_tag:16, 4364331766Sken :16; 4365331766Sken uint32_t ebde_cnt:4, 4366331766Sken :3, 4367331766Sken len_loc:2, 4368331766Sken qosd:1, 4369331766Sken :1, 4370331766Sken xbl:1, 4371331766Sken hlm:1, 4372331766Sken iod:1, 4373331766Sken dbde:1, 4374331766Sken wqes:1, 4375331766Sken pri:3, 4376331766Sken pv:1, 4377331766Sken eat:1, 4378331766Sken xc:1, 4379331766Sken :1, 4380331766Sken ccpe:1, 4381331766Sken ccp:8; 4382331766Sken uint32_t cmd_type:4, 4383331766Sken :3, 4384331766Sken wqec:1, 4385331766Sken :8, 4386331766Sken cq_id:16; 4387331766Sken uint32_t rsvd12; 4388331766Sken#else 4389331766Sken#error big endian version not defined 4390331766Sken#endif 4391331766Sken sli4_bde_t first_data_bde; /* reserved if performance hints disabled */ 4392331766Sken} sli4_fcp_iread64_wqe_t; 4393331766Sken 4394331766Sken/** 4395331766Sken * @brief WQE used to create an FCP initiator write. 4396331766Sken */ 4397331766Skentypedef struct sli4_fcp_iwrite64_wqe_s { 4398331766Sken sli4_bde_t bde; 4399331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4400331766Sken uint32_t payload_offset_length:16, 4401331766Sken fcp_cmd_buffer_length:16; 4402331766Sken uint32_t total_transfer_length; 4403331766Sken uint32_t initial_transfer_length; 4404331766Sken uint32_t xri_tag:16, 4405331766Sken context_tag:16; 4406331766Sken uint32_t dif:2, 4407331766Sken ct:2, 4408331766Sken bs:3, 4409331766Sken :1, 4410331766Sken command:8, 4411331766Sken class:3, 4412331766Sken :1, 4413331766Sken pu:2, 4414331766Sken erp:1, 4415331766Sken lnk:1, 4416331766Sken timer:8; 4417331766Sken uint32_t abort_tag; 4418331766Sken uint32_t request_tag:16, 4419331766Sken :16; 4420331766Sken uint32_t ebde_cnt:4, 4421331766Sken :3, 4422331766Sken len_loc:2, 4423331766Sken qosd:1, 4424331766Sken :1, 4425331766Sken xbl:1, 4426331766Sken hlm:1, 4427331766Sken iod:1, 4428331766Sken dbde:1, 4429331766Sken wqes:1, 4430331766Sken pri:3, 4431331766Sken pv:1, 4432331766Sken eat:1, 4433331766Sken xc:1, 4434331766Sken :1, 4435331766Sken ccpe:1, 4436331766Sken ccp:8; 4437331766Sken uint32_t cmd_type:4, 4438331766Sken :3, 4439331766Sken wqec:1, 4440331766Sken :8, 4441331766Sken cq_id:16; 4442331766Sken uint32_t remote_n_port_id:24, 4443331766Sken :8; 4444331766Sken#else 4445331766Sken#error big endian version not defined 4446331766Sken#endif 4447331766Sken sli4_bde_t first_data_bde; 4448331766Sken} sli4_fcp_iwrite64_wqe_t; 4449331766Sken 4450331766Sken 4451331766Skentypedef struct sli4_fcp_128byte_wqe_s { 4452331766Sken uint32_t dw[32]; 4453331766Sken} sli4_fcp_128byte_wqe_t; 4454331766Sken 4455331766Sken/** 4456331766Sken * @brief WQE used to create an FCP target receive, and FCP target 4457331766Sken * receive continue. 4458331766Sken */ 4459331766Skentypedef struct sli4_fcp_treceive64_wqe_s { 4460331766Sken sli4_bde_t bde; 4461331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4462331766Sken uint32_t payload_offset_length; 4463331766Sken uint32_t relative_offset; 4464331766Sken /** 4465331766Sken * DWord 5 can either be the task retry identifier (HLM=0) or 4466331766Sken * the remote N_Port ID (HLM=1), or if implementing the Skyhawk 4467331766Sken * T10-PI workaround, the secondary xri tag 4468331766Sken */ 4469331766Sken union { 4470331766Sken uint32_t sec_xri_tag:16, 4471331766Sken :16; 4472331766Sken uint32_t dword; 4473331766Sken } dword5; 4474331766Sken uint32_t xri_tag:16, 4475331766Sken context_tag:16; 4476331766Sken uint32_t dif:2, 4477331766Sken ct:2, 4478331766Sken bs:3, 4479331766Sken :1, 4480331766Sken command:8, 4481331766Sken class:3, 4482331766Sken ar:1, 4483331766Sken pu:2, 4484331766Sken conf:1, 4485331766Sken lnk:1, 4486331766Sken timer:8; 4487331766Sken uint32_t abort_tag; 4488331766Sken uint32_t request_tag:16, 4489331766Sken remote_xid:16; 4490331766Sken uint32_t ebde_cnt:4, 4491331766Sken :1, 4492331766Sken app_id_valid:1, 4493331766Sken :1, 4494331766Sken len_loc:2, 4495331766Sken qosd:1, 4496331766Sken wchn:1, 4497331766Sken xbl:1, 4498331766Sken hlm:1, 4499331766Sken iod:1, 4500331766Sken dbde:1, 4501331766Sken wqes:1, 4502331766Sken pri:3, 4503331766Sken pv:1, 4504331766Sken eat:1, 4505331766Sken xc:1, 4506331766Sken sr:1, 4507331766Sken ccpe:1, 4508331766Sken ccp:8; 4509331766Sken uint32_t cmd_type:4, 4510331766Sken :3, 4511331766Sken wqec:1, 4512331766Sken :8, 4513331766Sken cq_id:16; 4514331766Sken uint32_t fcp_data_receive_length; 4515331766Sken 4516331766Sken#else 4517331766Sken#error big endian version not defined 4518331766Sken#endif 4519331766Sken sli4_bde_t first_data_bde; /* For performance hints */ 4520331766Sken 4521331766Sken} sli4_fcp_treceive64_wqe_t; 4522331766Sken 4523331766Sken/** 4524331766Sken * @brief WQE used to create an FCP target response. 4525331766Sken */ 4526331766Skentypedef struct sli4_fcp_trsp64_wqe_s { 4527331766Sken sli4_bde_t bde; 4528331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4529331766Sken uint32_t fcp_response_length; 4530331766Sken uint32_t rsvd4; 4531331766Sken /** 4532331766Sken * DWord 5 can either be the task retry identifier (HLM=0) or 4533331766Sken * the remote N_Port ID (HLM=1) 4534331766Sken */ 4535331766Sken uint32_t dword5; 4536331766Sken uint32_t xri_tag:16, 4537331766Sken rpi:16; 4538331766Sken uint32_t :2, 4539331766Sken ct:2, 4540331766Sken dnrx:1, 4541331766Sken :3, 4542331766Sken command:8, 4543331766Sken class:3, 4544331766Sken ag:1, 4545331766Sken pu:2, 4546331766Sken conf:1, 4547331766Sken lnk:1, 4548331766Sken timer:8; 4549331766Sken uint32_t abort_tag; 4550331766Sken uint32_t request_tag:16, 4551331766Sken remote_xid:16; 4552331766Sken uint32_t ebde_cnt:4, 4553331766Sken :1, 4554331766Sken app_id_valid:1, 4555331766Sken :1, 4556331766Sken len_loc:2, 4557331766Sken qosd:1, 4558331766Sken wchn:1, 4559331766Sken xbl:1, 4560331766Sken hlm:1, 4561331766Sken iod:1, 4562331766Sken dbde:1, 4563331766Sken wqes:1, 4564331766Sken pri:3, 4565331766Sken pv:1, 4566331766Sken eat:1, 4567331766Sken xc:1, 4568331766Sken sr:1, 4569331766Sken ccpe:1, 4570331766Sken ccp:8; 4571331766Sken uint32_t cmd_type:4, 4572331766Sken :3, 4573331766Sken wqec:1, 4574331766Sken :8, 4575331766Sken cq_id:16; 4576331766Sken uint32_t rsvd12; 4577331766Sken uint32_t rsvd13; 4578331766Sken uint32_t rsvd14; 4579331766Sken uint32_t rsvd15; 4580331766Sken#else 4581331766Sken#error big endian version not defined 4582331766Sken#endif 4583331766Sken} sli4_fcp_trsp64_wqe_t; 4584331766Sken 4585331766Sken/** 4586331766Sken * @brief WQE used to create an FCP target send (DATA IN). 4587331766Sken */ 4588331766Skentypedef struct sli4_fcp_tsend64_wqe_s { 4589331766Sken sli4_bde_t bde; 4590331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4591331766Sken uint32_t payload_offset_length; 4592331766Sken uint32_t relative_offset; 4593331766Sken /** 4594331766Sken * DWord 5 can either be the task retry identifier (HLM=0) or 4595331766Sken * the remote N_Port ID (HLM=1) 4596331766Sken */ 4597331766Sken uint32_t dword5; 4598331766Sken uint32_t xri_tag:16, 4599331766Sken rpi:16; 4600331766Sken uint32_t dif:2, 4601331766Sken ct:2, 4602331766Sken bs:3, 4603331766Sken :1, 4604331766Sken command:8, 4605331766Sken class:3, 4606331766Sken ar:1, 4607331766Sken pu:2, 4608331766Sken conf:1, 4609331766Sken lnk:1, 4610331766Sken timer:8; 4611331766Sken uint32_t abort_tag; 4612331766Sken uint32_t request_tag:16, 4613331766Sken remote_xid:16; 4614331766Sken uint32_t ebde_cnt:4, 4615331766Sken :1, 4616331766Sken app_id_valid:1, 4617331766Sken :1, 4618331766Sken len_loc:2, 4619331766Sken qosd:1, 4620331766Sken wchn:1, 4621331766Sken xbl:1, 4622331766Sken hlm:1, 4623331766Sken iod:1, 4624331766Sken dbde:1, 4625331766Sken wqes:1, 4626331766Sken pri:3, 4627331766Sken pv:1, 4628331766Sken eat:1, 4629331766Sken xc:1, 4630331766Sken sr:1, 4631331766Sken ccpe:1, 4632331766Sken ccp:8; 4633331766Sken uint32_t cmd_type:4, 4634331766Sken :3, 4635331766Sken wqec:1, 4636331766Sken :8, 4637331766Sken cq_id:16; 4638331766Sken uint32_t fcp_data_transmit_length; 4639331766Sken 4640331766Sken#else 4641331766Sken#error big endian version not defined 4642331766Sken#endif 4643331766Sken sli4_bde_t first_data_bde; /* For performance hints */ 4644331766Sken} sli4_fcp_tsend64_wqe_t; 4645331766Sken 4646331766Sken#define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */ 4647331766Sken#define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */ 4648331766Sken#define SLI4_IO_NO_ABORT BIT(2) 4649331766Sken#define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */ 4650331766Sken 4651331766Sken/* WQE DIF field contents */ 4652331766Sken#define SLI4_DIF_DISABLED 0 4653331766Sken#define SLI4_DIF_PASS_THROUGH 1 4654331766Sken#define SLI4_DIF_STRIP 2 4655331766Sken#define SLI4_DIF_INSERT 3 4656331766Sken 4657331766Sken/** 4658331766Sken * @brief WQE used to create a general request. 4659331766Sken */ 4660331766Skentypedef struct sli4_gen_request64_wqe_s { 4661331766Sken sli4_bde_t bde; 4662331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4663331766Sken uint32_t request_payload_length; 4664331766Sken uint32_t relative_offset; 4665331766Sken uint32_t :8, 4666331766Sken df_ctl:8, 4667331766Sken type:8, 4668331766Sken r_ctl:8; 4669331766Sken uint32_t xri_tag:16, 4670331766Sken context_tag:16; 4671331766Sken uint32_t :2, 4672331766Sken ct:2, 4673331766Sken :4, 4674331766Sken command:8, 4675331766Sken class:3, 4676331766Sken :1, 4677331766Sken pu:2, 4678331766Sken :2, 4679331766Sken timer:8; 4680331766Sken uint32_t abort_tag; 4681331766Sken uint32_t request_tag:16, 4682331766Sken :16; 4683331766Sken uint32_t ebde_cnt:4, 4684331766Sken :3, 4685331766Sken len_loc:2, 4686331766Sken qosd:1, 4687331766Sken :1, 4688331766Sken xbl:1, 4689331766Sken hlm:1, 4690331766Sken iod:1, 4691331766Sken dbde:1, 4692331766Sken wqes:1, 4693331766Sken pri:3, 4694331766Sken pv:1, 4695331766Sken eat:1, 4696331766Sken xc:1, 4697331766Sken :1, 4698331766Sken ccpe:1, 4699331766Sken ccp:8; 4700331766Sken uint32_t cmd_type:4, 4701331766Sken :3, 4702331766Sken wqec:1, 4703331766Sken :8, 4704331766Sken cq_id:16; 4705331766Sken uint32_t remote_n_port_id:24, 4706331766Sken :8; 4707331766Sken uint32_t rsvd13; 4708331766Sken uint32_t rsvd14; 4709331766Sken uint32_t max_response_payload_length; 4710331766Sken#else 4711331766Sken#error big endian version not defined 4712331766Sken#endif 4713331766Sken} sli4_gen_request64_wqe_t; 4714331766Sken 4715331766Sken/** 4716331766Sken * @brief WQE used to create a send frame request. 4717331766Sken */ 4718331766Skentypedef struct sli4_send_frame_wqe_s { 4719331766Sken sli4_bde_t bde; 4720331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4721331766Sken uint32_t frame_length; 4722331766Sken uint32_t fc_header_0_1[2]; 4723331766Sken uint32_t xri_tag:16, 4724331766Sken context_tag:16; 4725331766Sken uint32_t :2, 4726331766Sken ct:2, 4727331766Sken :4, 4728331766Sken command:8, 4729331766Sken class:3, 4730331766Sken :1, 4731331766Sken pu:2, 4732331766Sken :2, 4733331766Sken timer:8; 4734331766Sken uint32_t abort_tag; 4735331766Sken uint32_t request_tag:16, 4736331766Sken eof:8, 4737331766Sken sof:8; 4738331766Sken uint32_t ebde_cnt:4, 4739331766Sken :3, 4740331766Sken lenloc:2, 4741331766Sken qosd:1, 4742331766Sken wchn:1, 4743331766Sken xbl:1, 4744331766Sken hlm:1, 4745331766Sken iod:1, 4746331766Sken dbde:1, 4747331766Sken wqes:1, 4748331766Sken pri:3, 4749331766Sken pv:1, 4750331766Sken eat:1, 4751331766Sken xc:1, 4752331766Sken :1, 4753331766Sken ccpe:1, 4754331766Sken ccp:8; 4755331766Sken uint32_t cmd_type:4, 4756331766Sken :3, 4757331766Sken wqec:1, 4758331766Sken :8, 4759331766Sken cq_id:16; 4760331766Sken uint32_t fc_header_2_5[4]; 4761331766Sken#else 4762331766Sken#error big endian version not defined 4763331766Sken#endif 4764331766Sken} sli4_send_frame_wqe_t; 4765331766Sken 4766331766Sken/** 4767331766Sken * @brief WQE used to create a transmit sequence. 4768331766Sken */ 4769331766Skentypedef struct sli4_xmit_sequence64_wqe_s { 4770331766Sken sli4_bde_t bde; 4771331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4772331766Sken uint32_t remote_n_port_id:24, 4773331766Sken :8; 4774331766Sken uint32_t relative_offset; 4775331766Sken uint32_t :2, 4776331766Sken si:1, 4777331766Sken ft:1, 4778331766Sken :2, 4779331766Sken xo:1, 4780331766Sken ls:1, 4781331766Sken df_ctl:8, 4782331766Sken type:8, 4783331766Sken r_ctl:8; 4784331766Sken uint32_t xri_tag:16, 4785331766Sken context_tag:16; 4786331766Sken uint32_t dif:2, 4787331766Sken ct:2, 4788331766Sken bs:3, 4789331766Sken :1, 4790331766Sken command:8, 4791331766Sken class:3, 4792331766Sken :1, 4793331766Sken pu:2, 4794331766Sken :2, 4795331766Sken timer:8; 4796331766Sken uint32_t abort_tag; 4797331766Sken uint32_t request_tag:16, 4798331766Sken remote_xid:16; 4799331766Sken uint32_t ebde_cnt:4, 4800331766Sken :3, 4801331766Sken len_loc:2, 4802331766Sken qosd:1, 4803331766Sken :1, 4804331766Sken xbl:1, 4805331766Sken hlm:1, 4806331766Sken iod:1, 4807331766Sken dbde:1, 4808331766Sken wqes:1, 4809331766Sken pri:3, 4810331766Sken pv:1, 4811331766Sken eat:1, 4812331766Sken xc:1, 4813331766Sken sr:1, 4814331766Sken ccpe:1, 4815331766Sken ccp:8; 4816331766Sken uint32_t cmd_type:4, 4817331766Sken :3, 4818331766Sken wqec:1, 4819331766Sken :8, 4820331766Sken cq_id:16; 4821331766Sken uint32_t sequence_payload_len; 4822331766Sken uint32_t rsvd13; 4823331766Sken uint32_t rsvd14; 4824331766Sken uint32_t rsvd15; 4825331766Sken#else 4826331766Sken#error big endian version not defined 4827331766Sken#endif 4828331766Sken} sli4_xmit_sequence64_wqe_t; 4829331766Sken 4830331766Sken/** 4831331766Sken * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool. 4832331766Sken */ 4833331766Skentypedef struct sli4_requeue_xri_wqe_s { 4834331766Sken uint32_t rsvd0; 4835331766Sken uint32_t rsvd1; 4836331766Sken uint32_t rsvd2; 4837331766Sken uint32_t rsvd3; 4838331766Sken uint32_t rsvd4; 4839331766Sken uint32_t rsvd5; 4840331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4841331766Sken uint32_t xri_tag:16, 4842331766Sken context_tag:16; 4843331766Sken uint32_t :2, 4844331766Sken ct:2, 4845331766Sken :4, 4846331766Sken command:8, 4847331766Sken class:3, 4848331766Sken :1, 4849331766Sken pu:2, 4850331766Sken :2, 4851331766Sken timer:8; 4852331766Sken uint32_t rsvd8; 4853331766Sken uint32_t request_tag:16, 4854331766Sken :16; 4855331766Sken uint32_t ebde_cnt:4, 4856331766Sken :3, 4857331766Sken len_loc:2, 4858331766Sken qosd:1, 4859331766Sken wchn:1, 4860331766Sken xbl:1, 4861331766Sken hlm:1, 4862331766Sken iod:1, 4863331766Sken dbde:1, 4864331766Sken wqes:1, 4865331766Sken pri:3, 4866331766Sken pv:1, 4867331766Sken eat:1, 4868331766Sken xc:1, 4869331766Sken :1, 4870331766Sken ccpe:1, 4871331766Sken ccp:8; 4872331766Sken uint32_t cmd_type:4, 4873331766Sken :3, 4874331766Sken wqec:1, 4875331766Sken :8, 4876331766Sken cq_id:16; 4877331766Sken uint32_t rsvd12; 4878331766Sken uint32_t rsvd13; 4879331766Sken uint32_t rsvd14; 4880331766Sken uint32_t rsvd15; 4881331766Sken#else 4882331766Sken#error big endian version not defined 4883331766Sken#endif 4884331766Sken} sli4_requeue_xri_wqe_t; 4885331766Sken 4886331766Sken/** 4887331766Sken * @brief WQE used to send a single frame sequence to broadcast address 4888331766Sken */ 4889331766Skentypedef struct sli4_xmit_bcast64_wqe_s { 4890331766Sken sli4_bde_t sequence_payload; 4891331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4892331766Sken uint32_t sequence_payload_length; 4893331766Sken uint32_t rsvd4; 4894331766Sken uint32_t :8, 4895331766Sken df_ctl:8, 4896331766Sken type:8, 4897331766Sken r_ctl:8; 4898331766Sken uint32_t xri_tag:16, 4899331766Sken context_tag:16; 4900331766Sken uint32_t :2, 4901331766Sken ct:2, 4902331766Sken :4, 4903331766Sken command:8, 4904331766Sken class:3, 4905331766Sken :1, 4906331766Sken pu:2, 4907331766Sken :2, 4908331766Sken timer:8; 4909331766Sken uint32_t abort_tag; 4910331766Sken uint32_t request_tag:16, 4911331766Sken temporary_rpi:16; 4912331766Sken uint32_t ebde_cnt:4, 4913331766Sken :3, 4914331766Sken len_loc:2, 4915331766Sken qosd:1, 4916331766Sken :1, 4917331766Sken xbl:1, 4918331766Sken hlm:1, 4919331766Sken iod:1, 4920331766Sken dbde:1, 4921331766Sken wqes:1, 4922331766Sken pri:3, 4923331766Sken pv:1, 4924331766Sken eat:1, 4925331766Sken xc:1, 4926331766Sken :1, 4927331766Sken ccpe:1, 4928331766Sken ccp:8; 4929331766Sken uint32_t cmd_type:4, 4930331766Sken :3, 4931331766Sken wqec:1, 4932331766Sken :8, 4933331766Sken cq_id:16; 4934331766Sken uint32_t rsvd12; 4935331766Sken uint32_t rsvd13; 4936331766Sken uint32_t rsvd14; 4937331766Sken uint32_t rsvd15; 4938331766Sken#else 4939331766Sken#error big endian version not defined 4940331766Sken#endif 4941331766Sken} sli4_xmit_bcast64_wqe_t; 4942331766Sken 4943331766Sken/** 4944331766Sken * @brief WQE used to create a BLS response. 4945331766Sken */ 4946331766Skentypedef struct sli4_xmit_bls_rsp_wqe_s { 4947331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 4948331766Sken uint32_t payload_word0; 4949331766Sken uint32_t rx_id:16, 4950331766Sken ox_id:16; 4951331766Sken uint32_t high_seq_cnt:16, 4952331766Sken low_seq_cnt:16; 4953331766Sken uint32_t rsvd3; 4954331766Sken uint32_t local_n_port_id:24, 4955331766Sken :8; 4956331766Sken uint32_t remote_id:24, 4957331766Sken :6, 4958331766Sken ar:1, 4959331766Sken xo:1; 4960331766Sken uint32_t xri_tag:16, 4961331766Sken context_tag:16; 4962331766Sken uint32_t :2, 4963331766Sken ct:2, 4964331766Sken :4, 4965331766Sken command:8, 4966331766Sken class:3, 4967331766Sken :1, 4968331766Sken pu:2, 4969331766Sken :2, 4970331766Sken timer:8; 4971331766Sken uint32_t abort_tag; 4972331766Sken uint32_t request_tag:16, 4973331766Sken :16; 4974331766Sken uint32_t ebde_cnt:4, 4975331766Sken :3, 4976331766Sken len_loc:2, 4977331766Sken qosd:1, 4978331766Sken :1, 4979331766Sken xbl:1, 4980331766Sken hlm:1, 4981331766Sken iod:1, 4982331766Sken dbde:1, 4983331766Sken wqes:1, 4984331766Sken pri:3, 4985331766Sken pv:1, 4986331766Sken eat:1, 4987331766Sken xc:1, 4988331766Sken :1, 4989331766Sken ccpe:1, 4990331766Sken ccp:8; 4991331766Sken uint32_t cmd_type:4, 4992331766Sken :3, 4993331766Sken wqec:1, 4994331766Sken :8, 4995331766Sken cq_id:16; 4996331766Sken uint32_t temporary_rpi:16, 4997331766Sken :16; 4998331766Sken uint32_t rsvd13; 4999331766Sken uint32_t rsvd14; 5000331766Sken uint32_t rsvd15; 5001331766Sken#else 5002331766Sken#error big endian version not defined 5003331766Sken#endif 5004331766Sken} sli4_xmit_bls_rsp_wqe_t; 5005331766Sken 5006331766Skentypedef enum { 5007331766Sken SLI_BLS_ACC, 5008331766Sken SLI_BLS_RJT, 5009331766Sken SLI_BLS_MAX 5010331766Sken} sli_bls_type_e; 5011331766Sken 5012331766Skentypedef struct sli_bls_payload_s { 5013331766Sken sli_bls_type_e type; 5014331766Sken uint16_t ox_id; 5015331766Sken uint16_t rx_id; 5016331766Sken union { 5017331766Sken struct { 5018331766Sken uint32_t seq_id_validity:8, 5019331766Sken seq_id_last:8, 5020331766Sken :16; 5021331766Sken uint16_t ox_id; 5022331766Sken uint16_t rx_id; 5023331766Sken uint16_t low_seq_cnt; 5024331766Sken uint16_t high_seq_cnt; 5025331766Sken } acc; 5026331766Sken struct { 5027331766Sken uint32_t vendor_unique:8, 5028331766Sken reason_explanation:8, 5029331766Sken reason_code:8, 5030331766Sken :8; 5031331766Sken } rjt; 5032331766Sken } u; 5033331766Sken} sli_bls_payload_t; 5034331766Sken 5035331766Sken/** 5036331766Sken * @brief WQE used to create an ELS response. 5037331766Sken */ 5038331766Skentypedef struct sli4_xmit_els_rsp64_wqe_s { 5039331766Sken sli4_bde_t els_response_payload; 5040331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5041331766Sken uint32_t els_response_payload_length; 5042331766Sken uint32_t s_id:24, 5043331766Sken sp:1, 5044331766Sken :7; 5045331766Sken uint32_t remote_id:24, 5046331766Sken :8; 5047331766Sken uint32_t xri_tag:16, 5048331766Sken context_tag:16; 5049331766Sken uint32_t :2, 5050331766Sken ct:2, 5051331766Sken :4, 5052331766Sken command:8, 5053331766Sken class:3, 5054331766Sken :1, 5055331766Sken pu:2, 5056331766Sken :2, 5057331766Sken timer:8; 5058331766Sken uint32_t abort_tag; 5059331766Sken uint32_t request_tag:16, 5060331766Sken ox_id:16; 5061331766Sken uint32_t ebde_cnt:4, 5062331766Sken :3, 5063331766Sken len_loc:2, 5064331766Sken qosd:1, 5065331766Sken :1, 5066331766Sken xbl:1, 5067331766Sken hlm:1, 5068331766Sken iod:1, 5069331766Sken dbde:1, 5070331766Sken wqes:1, 5071331766Sken pri:3, 5072331766Sken pv:1, 5073331766Sken eat:1, 5074331766Sken xc:1, 5075331766Sken :1, 5076331766Sken ccpe:1, 5077331766Sken ccp:8; 5078331766Sken uint32_t cmd_type:4, 5079331766Sken :3, 5080331766Sken wqec:1, 5081331766Sken :8, 5082331766Sken cq_id:16; 5083331766Sken uint32_t temporary_rpi:16, 5084331766Sken :16; 5085331766Sken uint32_t rsvd13; 5086331766Sken uint32_t rsvd14; 5087331766Sken uint32_t rsvd15; 5088331766Sken#else 5089331766Sken#error big endian version not defined 5090331766Sken#endif 5091331766Sken} sli4_xmit_els_rsp64_wqe_t; 5092331766Sken 5093331766Sken/** 5094331766Sken * @brief Asynchronouse Event: Link State ACQE. 5095331766Sken */ 5096331766Skentypedef struct sli4_link_state_s { 5097331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5098331766Sken uint32_t link_number:6, 5099331766Sken link_type:2, 5100331766Sken port_link_status:8, 5101331766Sken port_duplex:8, 5102331766Sken port_speed:8; 5103331766Sken uint32_t port_fault:8, 5104331766Sken :8, 5105331766Sken logical_link_speed:16; 5106331766Sken uint32_t event_tag; 5107331766Sken uint32_t :8, 5108331766Sken event_code:8, 5109331766Sken event_type:8, /** values are protocol specific */ 5110331766Sken :6, 5111331766Sken ae:1, /** async event - this is an ACQE */ 5112331766Sken val:1; /** valid - contents of CQE are valid */ 5113331766Sken#else 5114331766Sken#error big endian version not defined 5115331766Sken#endif 5116331766Sken} sli4_link_state_t; 5117331766Sken 5118331766Sken 5119331766Sken#define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01 5120331766Sken#define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02 5121331766Sken#define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03 5122331766Sken 5123331766Sken#define SLI4_LINK_ATTN_P2P 0x01 5124331766Sken#define SLI4_LINK_ATTN_FC_AL 0x02 5125331766Sken#define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03 5126331766Sken#define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04 5127331766Sken 5128331766Sken#define SLI4_LINK_ATTN_1G 0x01 5129331766Sken#define SLI4_LINK_ATTN_2G 0x02 5130331766Sken#define SLI4_LINK_ATTN_4G 0x04 5131331766Sken#define SLI4_LINK_ATTN_8G 0x08 5132331766Sken#define SLI4_LINK_ATTN_10G 0x0a 5133331766Sken#define SLI4_LINK_ATTN_16G 0x10 5134331766Sken 5135331766Sken#define SLI4_LINK_TYPE_ETHERNET 0x0 5136331766Sken#define SLI4_LINK_TYPE_FC 0x1 5137331766Sken 5138331766Sken/** 5139331766Sken * @brief Asynchronouse Event: FC Link Attention Event. 5140331766Sken */ 5141331766Skentypedef struct sli4_link_attention_s { 5142331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5143331766Sken uint32_t link_number:8, 5144331766Sken attn_type:8, 5145331766Sken topology:8, 5146331766Sken port_speed:8; 5147331766Sken uint32_t port_fault:8, 5148331766Sken shared_link_status:8, 5149331766Sken logical_link_speed:16; 5150331766Sken uint32_t event_tag; 5151331766Sken uint32_t :8, 5152331766Sken event_code:8, 5153331766Sken event_type:8, /** values are protocol specific */ 5154331766Sken :6, 5155331766Sken ae:1, /** async event - this is an ACQE */ 5156331766Sken val:1; /** valid - contents of CQE are valid */ 5157331766Sken#else 5158331766Sken#error big endian version not defined 5159331766Sken#endif 5160331766Sken} sli4_link_attention_t; 5161331766Sken 5162331766Sken/** 5163331766Sken * @brief FC/FCoE event types. 5164331766Sken */ 5165331766Sken#define SLI4_LINK_STATE_PHYSICAL 0x00 5166331766Sken#define SLI4_LINK_STATE_LOGICAL 0x01 5167331766Sken 5168331766Sken#define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01 5169331766Sken#define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02 5170331766Sken#define SLI4_FCOE_FIP_FCF_DEAD 0x03 5171331766Sken#define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04 5172331766Sken#define SLI4_FCOE_FIP_FCF_MODIFIED 0x05 5173331766Sken 5174331766Sken#define SLI4_GRP5_QOS_SPEED 0x01 5175331766Sken 5176331766Sken#define SLI4_FC_EVENT_LINK_ATTENTION 0x01 5177331766Sken#define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02 5178331766Sken 5179331766Sken#define SLI4_PORT_SPEED_NO_LINK 0x0 5180331766Sken#define SLI4_PORT_SPEED_10_MBPS 0x1 5181331766Sken#define SLI4_PORT_SPEED_100_MBPS 0x2 5182331766Sken#define SLI4_PORT_SPEED_1_GBPS 0x3 5183331766Sken#define SLI4_PORT_SPEED_10_GBPS 0x4 5184331766Sken 5185331766Sken#define SLI4_PORT_DUPLEX_NONE 0x0 5186331766Sken#define SLI4_PORT_DUPLEX_HWF 0x1 5187331766Sken#define SLI4_PORT_DUPLEX_FULL 0x2 5188331766Sken 5189331766Sken#define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0 5190331766Sken#define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1 5191331766Sken#define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2 5192331766Sken#define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3 5193331766Sken 5194331766Sken/** 5195331766Sken * @brief Asynchronouse Event: FCoE/FIP ACQE. 5196331766Sken */ 5197331766Skentypedef struct sli4_fcoe_fip_s { 5198331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5199331766Sken uint32_t event_information; 5200331766Sken uint32_t fcf_count:16, 5201331766Sken fcoe_event_type:16; 5202331766Sken uint32_t event_tag; 5203331766Sken uint32_t :8, 5204331766Sken event_code:8, 5205331766Sken event_type:8, /** values are protocol specific */ 5206331766Sken :6, 5207331766Sken ae:1, /** async event - this is an ACQE */ 5208331766Sken val:1; /** valid - contents of CQE are valid */ 5209331766Sken#else 5210331766Sken#error big endian version not defined 5211331766Sken#endif 5212331766Sken} sli4_fcoe_fip_t; 5213331766Sken 5214331766Sken/** 5215331766Sken * @brief FC/FCoE WQ completion queue entry. 5216331766Sken */ 5217331766Skentypedef struct sli4_fc_wcqe_s { 5218331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5219331766Sken uint32_t hw_status:8, 5220331766Sken status:8, 5221331766Sken request_tag:16; 5222331766Sken uint32_t wqe_specific_1; 5223331766Sken uint32_t wqe_specific_2; 5224331766Sken uint32_t :15, 5225331766Sken qx:1, 5226331766Sken code:8, 5227331766Sken pri:3, 5228331766Sken pv:1, 5229331766Sken xb:1, 5230331766Sken :2, 5231331766Sken vld:1; 5232331766Sken#else 5233331766Sken#error big endian version not defined 5234331766Sken#endif 5235331766Sken} sli4_fc_wcqe_t; 5236331766Sken 5237331766Sken/** 5238331766Sken * @brief FC/FCoE WQ consumed CQ queue entry. 5239331766Sken */ 5240331766Skentypedef struct sli4_fc_wqec_s { 5241331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5242331766Sken uint32_t :32; 5243331766Sken uint32_t :32; 5244331766Sken uint32_t wqe_index:16, 5245331766Sken wq_id:16; 5246331766Sken uint32_t :16, 5247331766Sken code:8, 5248331766Sken :7, 5249331766Sken vld:1; 5250331766Sken#else 5251331766Sken#error big endian version not defined 5252331766Sken#endif 5253331766Sken} sli4_fc_wqec_t; 5254331766Sken 5255331766Sken/** 5256331766Sken * @brief FC/FCoE Completion Status Codes. 5257331766Sken */ 5258331766Sken#define SLI4_FC_WCQE_STATUS_SUCCESS 0x00 5259331766Sken#define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01 5260331766Sken#define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02 5261331766Sken#define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03 5262331766Sken#define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04 5263331766Sken#define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05 5264331766Sken#define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06 5265331766Sken#define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07 5266331766Sken#define SLI4_FC_WCQE_STATUS_LS_RJT 0x09 5267331766Sken#define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b 5268331766Sken#define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c 5269331766Sken#define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 5270331766Sken#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12 5271331766Sken#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13 5272331766Sken#define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14 5273331766Sken#define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15 5274331766Sken#define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16 5275331766Sken#define SLI4_FC_WCQE_STATUS_BA_RJT 0x17 5276331766Sken#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18 5277331766Sken#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19 5278331766Sken#define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a 5279331766Sken#define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b 5280331766Sken 5281331766Sken/* driver generated status codes; better not overlap with chip's status codes! */ 5282331766Sken#define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT 0xff 5283331766Sken#define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe 5284331766Sken#define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd 5285331766Sken 5286331766Sken/** 5287331766Sken * @brief DI_ERROR Extended Status 5288331766Sken */ 5289331766Sken#define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */ 5290331766Sken#define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */ 5291331766Sken#define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */ 5292331766Sken#define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */ 5293331766Sken#define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */ 5294331766Sken#define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */ 5295331766Sken 5296331766Sken/** 5297331766Sken * @brief Local Reject Reason Codes. 5298331766Sken */ 5299331766Sken#define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01 5300331766Sken#define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02 5301331766Sken#define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03 5302331766Sken#define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04 5303331766Sken#define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05 5304331766Sken#define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06 5305331766Sken#define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07 5306331766Sken#define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08 5307331766Sken#define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c 5308331766Sken#define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d 5309331766Sken#define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e 5310331766Sken#define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f 5311331766Sken#define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11 5312331766Sken#define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12 5313331766Sken#define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13 5314331766Sken#define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14 5315331766Sken#define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15 5316331766Sken#define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16 5317331766Sken#define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17 5318331766Sken#define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18 5319331766Sken#define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a 5320331766Sken#define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b 5321331766Sken#define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c 5322331766Sken#define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d 5323331766Sken#define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e 5324331766Sken#define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f 5325331766Sken#define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20 5326331766Sken#define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21 5327331766Sken#define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23 5328331766Sken#define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24 5329331766Sken#define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25 5330331766Sken#define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28 5331331766Sken#define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29 5332331766Sken#define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e 5333331766Sken#define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30 5334331766Sken#define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40 5335331766Sken#define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41 5336331766Sken#define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42 5337331766Sken#define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43 5338331766Sken#define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44 5339331766Sken#define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45 5340331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46 5341331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47 5342331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48 5343331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49 5344331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a 5345331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c 5346331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d 5347331766Sken#define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e 5348331766Sken 5349331766Skentypedef struct sli4_fc_async_rcqe_s { 5350331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5351331766Sken uint32_t :8, 5352331766Sken status:8, 5353331766Sken rq_element_index:12, 5354331766Sken :4; 5355331766Sken uint32_t rsvd1; 5356331766Sken uint32_t fcfi:6, 5357331766Sken rq_id:10, 5358331766Sken payload_data_placement_length:16; 5359331766Sken uint32_t sof_byte:8, 5360331766Sken eof_byte:8, 5361331766Sken code:8, 5362331766Sken header_data_placement_length:6, 5363331766Sken :1, 5364331766Sken vld:1; 5365331766Sken#else 5366331766Sken#error big endian version not defined 5367331766Sken#endif 5368331766Sken} sli4_fc_async_rcqe_t; 5369331766Sken 5370331766Skentypedef struct sli4_fc_async_rcqe_v1_s { 5371331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5372331766Sken uint32_t :8, 5373331766Sken status:8, 5374331766Sken rq_element_index:12, 5375331766Sken :4; 5376331766Sken uint32_t fcfi:6, 5377331766Sken :26; 5378331766Sken uint32_t rq_id:16, 5379331766Sken payload_data_placement_length:16; 5380331766Sken uint32_t sof_byte:8, 5381331766Sken eof_byte:8, 5382331766Sken code:8, 5383331766Sken header_data_placement_length:6, 5384331766Sken :1, 5385331766Sken vld:1; 5386331766Sken#else 5387331766Sken#error big endian version not defined 5388331766Sken#endif 5389331766Sken} sli4_fc_async_rcqe_v1_t; 5390331766Sken 5391331766Sken#define SLI4_FC_ASYNC_RQ_SUCCESS 0x10 5392331766Sken#define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11 5393331766Sken#define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12 5394331766Sken#define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13 5395331766Sken#define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14 5396331766Sken 5397331766Skentypedef struct sli4_fc_coalescing_rcqe_s { 5398331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5399331766Sken uint32_t :8, 5400331766Sken status:8, 5401331766Sken rq_element_index:12, 5402331766Sken :4; 5403331766Sken uint32_t rsvd1; 5404331766Sken uint32_t rq_id:16, 5405331766Sken sequence_reporting_placement_length:16; 5406331766Sken uint32_t :16, 5407331766Sken code:8, 5408331766Sken :7, 5409331766Sken vld:1; 5410331766Sken#else 5411331766Sken#error big endian version not defined 5412331766Sken#endif 5413331766Sken} sli4_fc_coalescing_rcqe_t; 5414331766Sken 5415331766Sken#define SLI4_FC_COALESCE_RQ_SUCCESS 0x10 5416331766Sken#define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18 5417331766Sken 5418331766Skentypedef struct sli4_fc_optimized_write_cmd_cqe_s { 5419331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5420331766Sken uint32_t :8, 5421331766Sken status:8, 5422331766Sken rq_element_index:15, 5423331766Sken iv:1; 5424331766Sken uint32_t fcfi:6, 5425331766Sken :8, 5426331766Sken oox:1, 5427331766Sken agxr:1, 5428331766Sken xri:16; 5429331766Sken uint32_t rq_id:16, 5430331766Sken payload_data_placement_length:16; 5431331766Sken uint32_t rpi:16, 5432331766Sken code:8, 5433331766Sken header_data_placement_length:6, 5434331766Sken :1, 5435331766Sken vld:1; 5436331766Sken#else 5437331766Sken#error big endian version not defined 5438331766Sken#endif 5439331766Sken} sli4_fc_optimized_write_cmd_cqe_t; 5440331766Sken 5441331766Skentypedef struct sli4_fc_optimized_write_data_cqe_s { 5442331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5443331766Sken uint32_t hw_status:8, 5444331766Sken status:8, 5445331766Sken xri:16; 5446331766Sken uint32_t total_data_placed; 5447331766Sken uint32_t extended_status; 5448331766Sken uint32_t :16, 5449331766Sken code:8, 5450331766Sken pri:3, 5451331766Sken pv:1, 5452331766Sken xb:1, 5453331766Sken rha:1, 5454331766Sken :1, 5455331766Sken vld:1; 5456331766Sken#else 5457331766Sken#error big endian version not defined 5458331766Sken#endif 5459331766Sken} sli4_fc_optimized_write_data_cqe_t; 5460331766Sken 5461331766Skentypedef struct sli4_fc_xri_aborted_cqe_s { 5462331766Sken#if BYTE_ORDER == LITTLE_ENDIAN 5463331766Sken uint32_t :8, 5464331766Sken status:8, 5465331766Sken :16; 5466331766Sken uint32_t extended_status; 5467331766Sken uint32_t xri:16, 5468331766Sken remote_xid:16; 5469331766Sken uint32_t :16, 5470331766Sken code:8, 5471331766Sken xr:1, 5472331766Sken :3, 5473331766Sken eo:1, 5474331766Sken br:1, 5475331766Sken ia:1, 5476331766Sken vld:1; 5477331766Sken#else 5478331766Sken#error big endian version not defined 5479331766Sken#endif 5480331766Sken} sli4_fc_xri_aborted_cqe_t; 5481331766Sken 5482331766Sken/** 5483331766Sken * Code definitions applicable to all FC/FCoE CQE types. 5484331766Sken */ 5485331766Sken#define SLI4_CQE_CODE_OFFSET 14 5486331766Sken 5487331766Sken#define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01 5488331766Sken#define SLI4_CQE_CODE_RELEASE_WQE 0x02 5489331766Sken#define SLI4_CQE_CODE_RQ_ASYNC 0x04 5490331766Sken#define SLI4_CQE_CODE_XRI_ABORTED 0x05 5491331766Sken#define SLI4_CQE_CODE_RQ_COALESCING 0x06 5492331766Sken#define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07 5493331766Sken#define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08 5494331766Sken#define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09 5495331766Sken#define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B 5496331766Sken#define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C 5497331766Sken 5498331766Skenextern int32_t sli_fc_process_link_state(sli4_t *, void *); 5499331766Skenextern int32_t sli_fc_process_link_attention(sli4_t *, void *); 5500331766Skenextern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 5501331766Skenextern uint32_t sli_fc_response_length(sli4_t *, uint8_t *); 5502331766Skenextern uint32_t sli_fc_io_length(sli4_t *, uint8_t *); 5503331766Skenextern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *); 5504331766Skenextern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *); 5505331766Skenextern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *); 5506331766Skenextern int32_t sli_fc_process_fcoe(sli4_t *, void *); 5507331766Skenextern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5508331766Skenextern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5509331766Skenextern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t); 5510331766Skenextern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **, 5511331766Skenocs_dma_t *); 5512331766Skenextern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5513331766Skenextern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5514331766Skenextern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t); 5515331766Skenextern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 5516331766Skenextern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *); 5517331766Skenextern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t); 5518331766Skenextern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t); 5519331766Skenextern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t); 5520331766Skenextern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t); 5521331766Skenextern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t); 5522331766Sken 5523331766Skenextern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *); 5524331766Skenextern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5525331766Skenextern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5526331766Skenextern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t); 5527331766Sken 5528331766Skenextern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5529331766Skenextern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t); 5530331766Skenextern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5531331766Skenextern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5532331766Skenextern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5533331766Skenextern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr, 5534331766Sken ocs_dma_t *payload, uint32_t req_len, uint8_t timeout, 5535331766Sken uint16_t xri, uint16_t req_tag); 5536331766Skenextern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5537331766Skenextern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5538331766Skenextern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t); 5539331766Skenextern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t); 5540331766Skenextern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 5541331766Skenextern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout); 5542331766Sken 5543331766Sken/** 5544331766Sken * @ingroup sli_fc 5545331766Sken * @brief Retrieve the received header and payload length. 5546331766Sken * 5547331766Sken * @param sli4 SLI context. 5548331766Sken * @param cqe Pointer to the CQ entry. 5549331766Sken * @param len_hdr Pointer where the header length is written. 5550331766Sken * @param len_data Pointer where the payload length is written. 5551331766Sken * 5552331766Sken * @return Returns 0 on success, or a non-zero value on failure. 5553331766Sken */ 5554331766Skenstatic inline int32_t 5555331766Skensli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data) 5556331766Sken{ 5557331766Sken sli4_fc_async_rcqe_t *rcqe = cqe; 5558331766Sken 5559331766Sken *len_hdr = *len_data = 0; 5560331766Sken 5561331766Sken if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) { 5562331766Sken *len_hdr = rcqe->header_data_placement_length; 5563331766Sken *len_data = rcqe->payload_data_placement_length; 5564331766Sken return 0; 5565331766Sken } else { 5566331766Sken return -1; 5567331766Sken } 5568331766Sken} 5569331766Sken 5570331766Sken/** 5571331766Sken * @ingroup sli_fc 5572331766Sken * @brief Retrieve the received FCFI. 5573331766Sken * 5574331766Sken * @param sli4 SLI context. 5575331766Sken * @param cqe Pointer to the CQ entry. 5576331766Sken * 5577331766Sken * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code. 5578331766Sken */ 5579331766Skenstatic inline uint8_t 5580331766Skensli_fc_rqe_fcfi(sli4_t *sli4, void *cqe) 5581331766Sken{ 5582331766Sken uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET]; 5583331766Sken uint8_t fcfi = UINT8_MAX; 5584331766Sken 5585331766Sken switch(code) { 5586331766Sken case SLI4_CQE_CODE_RQ_ASYNC: { 5587331766Sken sli4_fc_async_rcqe_t *rcqe = cqe; 5588331766Sken fcfi = rcqe->fcfi; 5589331766Sken break; 5590331766Sken } 5591331766Sken case SLI4_CQE_CODE_RQ_ASYNC_V1: { 5592331766Sken sli4_fc_async_rcqe_v1_t *rcqev1 = cqe; 5593331766Sken fcfi = rcqev1->fcfi; 5594331766Sken break; 5595331766Sken } 5596331766Sken case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: { 5597331766Sken sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe; 5598331766Sken fcfi = opt_wr->fcfi; 5599331766Sken break; 5600331766Sken } 5601331766Sken } 5602331766Sken 5603331766Sken return fcfi; 5604331766Sken} 5605331766Sken 5606331766Skenextern const char *sli_fc_get_status_string(uint32_t status); 5607331766Sken 5608331766Sken#endif /* !_SLI4_H */ 5609331766Sken 5610