1/*- 2 * Copyright (c) 2017 Broadcom. All rights reserved. 3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: stable/11/sys/dev/ocs_fc/sli4.h 331766 2018-03-30 15:28:25Z ken $ 32 */ 33 34/** 35 * @file 36 * Define common SLI-4 structures and function prototypes. 37 */ 38 39#ifndef _SLI4_H 40#define _SLI4_H 41 42#include "ocs_os.h" 43 44#define SLI_PAGE_SIZE (4096) 45#define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1) 46#define SLI_PAGE_SHIFT 12 47#define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK) 48 49#define SLI4_BMBX_TIMEOUT_MSEC 30000 50#define SLI4_FW_READY_TIMEOUT_MSEC 30000 51 52static inline uint32_t 53sli_page_count(size_t bytes, uint32_t page_size) 54{ 55 uint32_t mask = page_size - 1; 56 uint32_t shift = 0; 57 58 switch (page_size) { 59 case 4096: 60 shift = 12; 61 break; 62 case 8192: 63 shift = 13; 64 break; 65 case 16384: 66 shift = 14; 67 break; 68 case 32768: 69 shift = 15; 70 break; 71 case 65536: 72 shift = 16; 73 break; 74 default: 75 return 0; 76 } 77 78 return (bytes + mask) >> shift; 79} 80 81/************************************************************************* 82 * Common PCI configuration space register definitions 83 */ 84 85#define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */ 86#define SLI4_PCI_REV_ID_SHIFT 0 87#define SLI4_PCI_REV_ID_MASK 0xff 88#define SLI4_PCI_CLASS_SHIFT 8 89#define SLI4_PCI_CLASS_MASK 0xfff 90 91#define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */ 92#define SLI4_PCI_SOFT_RESET_MASK 0x0080 93 94/************************************************************************* 95 * Common SLI-4 register offsets and field definitions 96 */ 97 98/** 99 * @brief SLI_INTF - SLI Interface Definition Register 100 */ 101#define SLI4_INTF_REG 0x0058 /** register offset */ 102#define SLI4_INTF_VALID_SHIFT 29 103#define SLI4_INTF_VALID_MASK 0x7 104#define SLI4_INTF_VALID 0x6 105#define SLI4_INTF_IF_TYPE_SHIFT 12 106#define SLI4_INTF_IF_TYPE_MASK 0xf 107#define SLI4_INTF_SLI_FAMILY_SHIFT 8 108#define SLI4_INTF_SLI_FAMILY_MASK 0xf 109#define SLI4_INTF_SLI_REVISION_SHIFT 4 110#define SLI4_INTF_SLI_REVISION_MASK 0xf 111#define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf 112 113#define SLI4_IF_TYPE_BE3_SKH_PF 0 114#define SLI4_IF_TYPE_BE3_SKH_VF 1 115#define SLI4_IF_TYPE_LANCER_FC_ETH 2 116#define SLI4_IF_TYPE_LANCER_RDMA 3 117#define SLI4_MAX_IF_TYPES 4 118 119/** 120 * @brief ASIC_ID - SLI ASIC Type and Revision Register 121 */ 122#define SLI4_ASIC_ID_REG 0x009c /* register offset */ 123#define SLI4_ASIC_REV_SHIFT 0 124#define SLI4_ASIC_REV_MASK 0xf 125#define SLI4_ASIC_VER_SHIFT 4 126#define SLI4_ASIC_VER_MASK 0xf 127#define SLI4_ASIC_GEN_SHIFT 8 128#define SLI4_ASIC_GEN_MASK 0xff 129#define SLI4_ASIC_GEN_BE2 0x00 130#define SLI4_ASIC_GEN_BE3 0x03 131#define SLI4_ASIC_GEN_SKYHAWK 0x04 132#define SLI4_ASIC_GEN_CORSAIR 0x05 133#define SLI4_ASIC_GEN_LANCER 0x0b 134 135 136/** 137 * @brief BMBX - Bootstrap Mailbox Register 138 */ 139#define SLI4_BMBX_REG 0x0160 /* register offset */ 140#define SLI4_BMBX_MASK_HI 0x3 141#define SLI4_BMBX_MASK_LO 0xf 142#define SLI4_BMBX_RDY BIT(0) 143#define SLI4_BMBX_HI BIT(1) 144#define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \ 145 SLI4_BMBX_HI) 146#define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \ 147 (((r) & ~SLI4_BMBX_MASK_LO) >> 2)) 148 149#define SLI4_BMBX_SIZE 256 150 151 152/** 153 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register 154 */ 155#define SLI4_EQCQ_DOORBELL_REG 0x120 156#define SLI4_EQCQ_DOORBELL_CI BIT(9) 157#define SLI4_EQCQ_DOORBELL_QT BIT(10) 158#define SLI4_EQCQ_DOORBELL_ARM BIT(29) 159#define SLI4_EQCQ_DOORBELL_SE BIT(31) 160#define SLI4_EQCQ_NUM_SHIFT 16 161#define SLI4_EQCQ_NUM_MASK 0x01ff 162#define SLI4_EQCQ_EQ_ID_MASK 0x3fff 163#define SLI4_EQCQ_CQ_ID_MASK 0x7fff 164#define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff 165#define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff 166#define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800 167 168/** 169 * @brief SLIPORT_CONTROL - SLI Port Control Register 170 */ 171#define SLI4_SLIPORT_CONTROL_REG 0x0408 172#define SLI4_SLIPORT_CONTROL_END BIT(30) 173#define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0) 174#define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30) 175#define SLI4_SLIPORT_CONTROL_IP BIT(27) 176#define SLI4_SLIPORT_CONTROL_IDIS BIT(22) 177#define SLI4_SLIPORT_CONTROL_FDD BIT(31) 178 179/** 180 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register 181 */ 182#define SLI4_SLIPORT_ERROR1 0x040c 183 184/** 185 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register 186 */ 187#define SLI4_SLIPORT_ERROR2 0x0410 188 189/** 190 * @brief User error registers 191 */ 192#define SLI4_UERR_STATUS_LOW_REG 0xA0 193#define SLI4_UERR_STATUS_HIGH_REG 0xA4 194#define SLI4_UERR_MASK_LOW_REG 0xA8 195#define SLI4_UERR_MASK_HIGH_REG 0xAC 196 197/** 198 * @brief Registers for generating software UE (BE3) 199 */ 200#define SLI4_SW_UE_CSR1 0x138 201#define SLI4_SW_UE_CSR2 0x1FFFC 202 203/** 204 * @brief Registers for generating software UE (Skyhawk) 205 */ 206#define SLI4_SW_UE_REG 0x5C /* register offset */ 207 208static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 209{ 210 uint32_t reg = 0; 211#if BYTE_ORDER == LITTLE_ENDIAN 212 struct { 213 uint32_t eq_id_lo:9, 214 ci:1, /* clear interrupt */ 215 qt:1, /* queue type */ 216 eq_id_hi:5, 217 number_popped:13, 218 arm:1, 219 :1, 220 se:1; 221 } * eq_doorbell = (void *)® 222#else 223#error big endian version not defined 224#endif 225 226 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO; 227 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */ 228 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f; 229 eq_doorbell->number_popped = n_popped; 230 eq_doorbell->arm = arm; 231 eq_doorbell->ci = TRUE; 232 233 return reg; 234} 235 236static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 237{ 238 uint32_t reg = 0; 239#if BYTE_ORDER == LITTLE_ENDIAN 240 struct { 241 uint32_t cq_id_lo:10, 242 qt:1, /* queue type */ 243 cq_id_hi:5, 244 number_popped:13, 245 arm:1, 246 :1, 247 se:1; 248 } * cq_doorbell = (void *)® 249#else 250#error big endian version not defined 251#endif 252 253 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO; 254 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */ 255 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f; 256 cq_doorbell->number_popped = n_popped; 257 cq_doorbell->arm = arm; 258 259 return reg; 260} 261 262/** 263 * @brief MQ_DOORBELL - MQ Doorbell Register 264 */ 265#define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */ 266#define SLI4_MQ_DOORBELL_NUM_SHIFT 16 267#define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff 268#define SLI4_MQ_DOORBELL_ID_MASK 0xffff 269#define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \ 270 ((i) & SLI4_MQ_DOORBELL_ID_MASK)) 271 272/** 273 * @brief RQ_DOORBELL - RQ Doorbell Register 274 */ 275#define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */ 276#define SLI4_RQ_DOORBELL_NUM_SHIFT 16 277#define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff 278#define SLI4_RQ_DOORBELL_ID_MASK 0xffff 279#define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \ 280 ((i) & SLI4_RQ_DOORBELL_ID_MASK)) 281 282/** 283 * @brief WQ_DOORBELL - WQ Doorbell Register 284 */ 285#define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */ 286#define SLI4_WQ_DOORBELL_IDX_SHIFT 16 287#define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff 288#define SLI4_WQ_DOORBELL_NUM_SHIFT 24 289#define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff 290#define SLI4_WQ_DOORBELL_ID_MASK 0xffff 291#define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \ 292 (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \ 293 ((i) & SLI4_WQ_DOORBELL_ID_MASK)) 294 295/** 296 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register 297 */ 298#define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */ 299#define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */ 300#define SLI4_PORT_SEMAPHORE_REG_23 0x0400 /** register offset Interface Type 2 + 3 */ 301#define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff 302#define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK) 303#define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000 304#define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16 305#define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \ 306 SLI4_PORT_SEMAPHORE_HOST_SHIFT) 307#define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */ 308#define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */ 309#define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */ 310#define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */ 311#define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */ 312#define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */ 313 314#define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000 315#define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000 316#define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000 317#define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \ 318 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK)) 319 320/** 321 * @brief SLIPORT_STATUS - SLI Port Status Register 322 */ 323 324#define SLI4_PORT_STATUS_REG_23 0x0404 /** register offset Interface Type 2 + 3 */ 325#define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */ 326#define SLI4_PORT_STATUS_RDY BIT(23) /** ready */ 327#define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */ 328#define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */ 329#define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */ 330#define SLI4_PORT_STATUS_END BIT(30) /** endianness */ 331#define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */ 332#define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY) 333#define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR) 334#define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP) 335#define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP) 336 337 338#define SLI4_PHSDEV_CONTROL_REG_23 0x0414 /** register offset Interface Type 2 + 3 */ 339#define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */ 340#define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */ 341#define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */ 342#define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0 343#define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4 344#define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \ 345 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT) 346 347/************************************************************************* 348 * SLI-4 mailbox command formats and definitions 349 */ 350 351typedef struct sli4_mbox_command_header_s { 352#if BYTE_ORDER == LITTLE_ENDIAN 353 uint32_t :8, 354 command:8, 355 status:16; /** Port writes to indicate success / fail */ 356#else 357#error big endian version not defined 358#endif 359} sli4_mbox_command_header_t; 360 361#define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07 362#define SLI4_MBOX_COMMAND_DUMP 0x17 363#define SLI4_MBOX_COMMAND_DOWN_LINK 0x06 364#define SLI4_MBOX_COMMAND_INIT_LINK 0x05 365#define SLI4_MBOX_COMMAND_INIT_VFI 0xa3 366#define SLI4_MBOX_COMMAND_INIT_VPI 0xa4 367#define SLI4_MBOX_COMMAND_POST_XRI 0xa7 368#define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac 369#define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b 370#define SLI4_MBOX_COMMAND_READ_STATUS 0x0e 371#define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02 372#define SLI4_MBOX_COMMAND_READ_REV 0x11 373#define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12 374#define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d 375#define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95 376#define SLI4_MBOX_COMMAND_REG_FCFI 0xa0 377#define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf 378#define SLI4_MBOX_COMMAND_REG_RPI 0x93 379#define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6 380#define SLI4_MBOX_COMMAND_REG_VFI 0x9f 381#define SLI4_MBOX_COMMAND_REG_VPI 0x96 382#define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d 383#define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b 384#define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2 385#define SLI4_MBOX_COMMAND_UNREG_RPI 0x14 386#define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1 387#define SLI4_MBOX_COMMAND_UNREG_VPI 0x97 388#define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03 389#define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD 390#define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE 391 392#define SLI4_MBOX_STATUS_SUCCESS 0x0000 393#define SLI4_MBOX_STATUS_FAILURE 0x0001 394#define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400 395 396/** 397 * @brief Buffer Descriptor Entry (BDE) 398 */ 399typedef struct sli4_bde_s { 400#if BYTE_ORDER == LITTLE_ENDIAN 401 uint32_t buffer_length:24, 402 bde_type:8; 403 union { 404 struct { 405 uint32_t buffer_address_low; 406 uint32_t buffer_address_high; 407 } data; 408 struct { 409 uint32_t offset; 410 uint32_t rsvd2; 411 } imm; 412 struct { 413 uint32_t sgl_segment_address_low; 414 uint32_t sgl_segment_address_high; 415 } blp; 416 } u; 417#else 418#error big endian version not defined 419#endif 420} sli4_bde_t; 421 422#define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */ 423#define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */ 424#define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */ 425 426/** 427 * @brief Scatter-Gather Entry (SGE) 428 */ 429typedef struct sli4_sge_s { 430#if BYTE_ORDER == LITTLE_ENDIAN 431 uint32_t buffer_address_high; 432 uint32_t buffer_address_low; 433 uint32_t data_offset:27, 434 sge_type:4, 435 last:1; 436 uint32_t buffer_length; 437#else 438#error big endian version not defined 439#endif 440} sli4_sge_t; 441 442/** 443 * @brief T10 DIF Scatter-Gather Entry (SGE) 444 */ 445typedef struct sli4_dif_sge_s { 446#if BYTE_ORDER == LITTLE_ENDIAN 447 uint32_t buffer_address_high; 448 uint32_t buffer_address_low; 449 uint32_t :27, 450 sge_type:4, 451 last:1; 452 uint32_t :32; 453#else 454#error big endian version not defined 455#endif 456} sli4_dif_sge_t; 457 458/** 459 * @brief T10 DIF Seed Scatter-Gather Entry (SGE) 460 */ 461typedef struct sli4_diseed_sge_s { 462#if BYTE_ORDER == LITTLE_ENDIAN 463 uint32_t ref_tag_cmp; 464 uint32_t ref_tag_repl; 465 uint32_t app_tag_repl:16, 466 :2, 467 hs:1, 468 ws:1, 469 ic:1, 470 ics:1, 471 atrt:1, 472 at:1, 473 fwd_app_tag:1, 474 repl_app_tag:1, 475 head_insert:1, 476 sge_type:4, 477 last:1; 478 uint32_t app_tag_cmp:16, 479 dif_blk_size:3, 480 auto_incr_ref_tag:1, 481 check_app_tag:1, 482 check_ref_tag:1, 483 check_crc:1, 484 new_ref_tag:1, 485 dif_op_rx:4, 486 dif_op_tx:4; 487#else 488#error big endian version not defined 489#endif 490} sli4_diseed_sge_t; 491 492/** 493 * @brief List Segment Pointer Scatter-Gather Entry (SGE) 494 */ 495typedef struct sli4_lsp_sge_s { 496#if BYTE_ORDER == LITTLE_ENDIAN 497 uint32_t buffer_address_high; 498 uint32_t buffer_address_low; 499 uint32_t :27, 500 sge_type:4, 501 last:1; 502 uint32_t segment_length:24, 503 :8; 504#else 505#error big endian version not defined 506#endif 507} sli4_lsp_sge_t; 508 509#define SLI4_SGE_MAX_RESERVED 3 510 511#define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00 512#define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01 513#define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02 514#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03 515#define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04 516#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05 517#define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06 518#define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07 519#define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08 520 521#define SLI4_SGE_TYPE_DATA 0x00 522#define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */ 523#define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */ 524#define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */ 525#define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */ 526#define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */ 527#define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */ 528#define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */ 529#define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */ 530#define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */ 531 532#define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */ 533 534/** 535 * @brief CONFIG_LINK 536 */ 537typedef struct sli4_cmd_config_link_s { 538 sli4_mbox_command_header_t hdr; 539#if BYTE_ORDER == LITTLE_ENDIAN 540 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */ 541 :24; 542 uint32_t alpa:8, 543 n_port_id:16, 544 :8; 545 uint32_t rsvd3; 546 uint32_t e_d_tov; 547 uint32_t lp_tov; 548 uint32_t r_a_tov; 549 uint32_t r_t_tov; 550 uint32_t al_tov; 551 uint32_t rsvd9; 552 uint32_t :8, 553 bbscn:4, /** buffer-to-buffer state change number */ 554 cscn:1, /** configure BBSCN */ 555 :19; 556#else 557#error big endian version not defined 558#endif 559} sli4_cmd_config_link_t; 560 561/** 562 * @brief DUMP Type 4 563 */ 564#define SLI4_WKI_TAG_SAT_TEM 0x1040 565typedef struct sli4_cmd_dump4_s { 566 sli4_mbox_command_header_t hdr; 567#if BYTE_ORDER == LITTLE_ENDIAN 568 uint32_t type:4, 569 :28; 570 uint32_t wki_selection:16, 571 :16; 572 uint32_t resv; 573 uint32_t returned_byte_cnt; 574 uint32_t resp_data[59]; 575#else 576#error big endian version not defined 577#endif 578} sli4_cmd_dump4_t; 579 580/** 581 * @brief FW_INITIALIZE - initialize a SLI port 582 * 583 * @note This command uses a different format than all others. 584 */ 585 586extern const uint8_t sli4_fw_initialize[8]; 587 588/** 589 * @brief FW_DEINITIALIZE - deinitialize a SLI port 590 * 591 * @note This command uses a different format than all others. 592 */ 593 594extern const uint8_t sli4_fw_deinitialize[8]; 595 596/** 597 * @brief INIT_LINK - initialize the link for a FC/FCoE port 598 */ 599typedef struct sli4_cmd_init_link_flags_s { 600 uint32_t loopback:1, 601 topology:2, 602 #define FC_TOPOLOGY_FCAL 0 603 #define FC_TOPOLOGY_P2P 1 604 :3, 605 unfair:1, 606 skip_lirp_lilp:1, 607 gen_loop_validity_check:1, 608 skip_lisa:1, 609 enable_topology_failover:1, 610 fixed_speed:1, 611 :3, 612 select_hightest_al_pa:1, 613 :16; /* pad to 32 bits */ 614} sli4_cmd_init_link_flags_t; 615 616#define SLI4_INIT_LINK_F_LOOP_BACK BIT(0) 617#define SLI4_INIT_LINK_F_UNFAIR BIT(6) 618#define SLI4_INIT_LINK_F_NO_LIRP BIT(7) 619#define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8) 620#define SLI4_INIT_LINK_F_NO_LISA BIT(9) 621#define SLI4_INIT_LINK_F_FAIL_OVER BIT(10) 622#define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11) 623#define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15) 624 625#define SLI4_INIT_LINK_F_P2P_ONLY 1 626#define SLI4_INIT_LINK_F_FCAL_ONLY 2 627 628#define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0 629#define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1 630 631typedef struct sli4_cmd_init_link_s { 632 sli4_mbox_command_header_t hdr; 633#if BYTE_ORDER == LITTLE_ENDIAN 634 uint32_t selective_reset_al_pa:8, 635 :24; 636 sli4_cmd_init_link_flags_t link_flags; 637 uint32_t link_speed_selection_code; 638 #define FC_LINK_SPEED_1G 1 639 #define FC_LINK_SPEED_2G 2 640 #define FC_LINK_SPEED_AUTO_1_2 3 641 #define FC_LINK_SPEED_4G 4 642 #define FC_LINK_SPEED_AUTO_4_1 5 643 #define FC_LINK_SPEED_AUTO_4_2 6 644 #define FC_LINK_SPEED_AUTO_4_2_1 7 645 #define FC_LINK_SPEED_8G 8 646 #define FC_LINK_SPEED_AUTO_8_1 9 647 #define FC_LINK_SPEED_AUTO_8_2 10 648 #define FC_LINK_SPEED_AUTO_8_2_1 11 649 #define FC_LINK_SPEED_AUTO_8_4 12 650 #define FC_LINK_SPEED_AUTO_8_4_1 13 651 #define FC_LINK_SPEED_AUTO_8_4_2 14 652 #define FC_LINK_SPEED_10G 16 653 #define FC_LINK_SPEED_16G 17 654 #define FC_LINK_SPEED_AUTO_16_8_4 18 655 #define FC_LINK_SPEED_AUTO_16_8 19 656 #define FC_LINK_SPEED_32G 20 657 #define FC_LINK_SPEED_AUTO_32_16_8 21 658 #define FC_LINK_SPEED_AUTO_32_16 22 659#else 660#error big endian version not defined 661#endif 662} sli4_cmd_init_link_t; 663 664/** 665 * @brief INIT_VFI - initialize the VFI resource 666 */ 667typedef struct sli4_cmd_init_vfi_s { 668 sli4_mbox_command_header_t hdr; 669#if BYTE_ORDER == LITTLE_ENDIAN 670 uint32_t vfi:16, 671 :12, 672 vp:1, 673 vf:1, 674 vt:1, 675 vr:1; 676 uint32_t fcfi:16, 677 vpi:16; 678 uint32_t vf_id:13, 679 pri:3, 680 :16; 681 uint32_t :24, 682 hop_count:8; 683#else 684#error big endian version not defined 685#endif 686} sli4_cmd_init_vfi_t; 687 688/** 689 * @brief INIT_VPI - initialize the VPI resource 690 */ 691typedef struct sli4_cmd_init_vpi_s { 692 sli4_mbox_command_header_t hdr; 693#if BYTE_ORDER == LITTLE_ENDIAN 694 uint32_t vpi:16, 695 vfi:16; 696#else 697#error big endian version not defined 698#endif 699} sli4_cmd_init_vpi_t; 700 701/** 702 * @brief POST_XRI - post XRI resources to the SLI Port 703 */ 704typedef struct sli4_cmd_post_xri_s { 705 sli4_mbox_command_header_t hdr; 706#if BYTE_ORDER == LITTLE_ENDIAN 707 uint32_t xri_base:16, 708 xri_count:12, 709 enx:1, 710 dl:1, 711 di:1, 712 val:1; 713#else 714#error big endian version not defined 715#endif 716} sli4_cmd_post_xri_t; 717 718/** 719 * @brief RELEASE_XRI - Release XRI resources from the SLI Port 720 */ 721typedef struct sli4_cmd_release_xri_s { 722 sli4_mbox_command_header_t hdr; 723#if BYTE_ORDER == LITTLE_ENDIAN 724 uint32_t released_xri_count:5, 725 :11, 726 xri_count:5, 727 :11; 728 struct { 729 uint32_t xri_tag0:16, 730 xri_tag1:16; 731 } xri_tbl[62]; 732#else 733#error big endian version not defined 734#endif 735} sli4_cmd_release_xri_t; 736 737/** 738 * @brief READ_CONFIG - read SLI port configuration parameters 739 */ 740typedef struct sli4_cmd_read_config_s { 741 sli4_mbox_command_header_t hdr; 742} sli4_cmd_read_config_t; 743 744typedef struct sli4_res_read_config_s { 745 sli4_mbox_command_header_t hdr; 746#if BYTE_ORDER == LITTLE_ENDIAN 747 uint32_t :31, 748 ext:1; /** Resource Extents */ 749 uint32_t :24, 750 topology:8; 751 uint32_t rsvd3; 752 uint32_t e_d_tov:16, 753 :16; 754 uint32_t rsvd5; 755 uint32_t r_a_tov:16, 756 :16; 757 uint32_t rsvd7; 758 uint32_t rsvd8; 759 uint32_t lmt:16, /** Link Module Type */ 760 :16; 761 uint32_t rsvd10; 762 uint32_t rsvd11; 763 uint32_t xri_base:16, 764 xri_count:16; 765 uint32_t rpi_base:16, 766 rpi_count:16; 767 uint32_t vpi_base:16, 768 vpi_count:16; 769 uint32_t vfi_base:16, 770 vfi_count:16; 771 uint32_t :16, 772 fcfi_count:16; 773 uint32_t rq_count:16, 774 eq_count:16; 775 uint32_t wq_count:16, 776 cq_count:16; 777 uint32_t pad[45]; 778#else 779#error big endian version not defined 780#endif 781} sli4_res_read_config_t; 782 783#define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */ 784#define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */ 785#define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */ 786#define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */ 787 788/** 789 * @brief READ_NVPARMS - read SLI port configuration parameters 790 */ 791typedef struct sli4_cmd_read_nvparms_s { 792 sli4_mbox_command_header_t hdr; 793#if BYTE_ORDER == LITTLE_ENDIAN 794 uint32_t rsvd1; 795 uint32_t rsvd2; 796 uint32_t rsvd3; 797 uint32_t rsvd4; 798 uint8_t wwpn[8]; 799 uint8_t wwnn[8]; 800 uint32_t hard_alpa:8, 801 preferred_d_id:24; 802#else 803#error big endian version not defined 804#endif 805} sli4_cmd_read_nvparms_t; 806 807/** 808 * @brief WRITE_NVPARMS - write SLI port configuration parameters 809 */ 810typedef struct sli4_cmd_write_nvparms_s { 811 sli4_mbox_command_header_t hdr; 812#if BYTE_ORDER == LITTLE_ENDIAN 813 uint32_t rsvd1; 814 uint32_t rsvd2; 815 uint32_t rsvd3; 816 uint32_t rsvd4; 817 uint8_t wwpn[8]; 818 uint8_t wwnn[8]; 819 uint32_t hard_alpa:8, 820 preferred_d_id:24; 821#else 822#error big endian version not defined 823#endif 824} sli4_cmd_write_nvparms_t; 825 826/** 827 * @brief READ_REV - read the Port revision levels 828 */ 829typedef struct sli4_cmd_read_rev_s { 830 sli4_mbox_command_header_t hdr; 831#if BYTE_ORDER == LITTLE_ENDIAN 832 uint32_t :16, 833 sli_level:4, 834 fcoem:1, 835 ceev:2, 836 :6, 837 vpd:1, 838 :2; 839 uint32_t first_hw_revision; 840 uint32_t second_hw_revision; 841 uint32_t rsvd4; 842 uint32_t third_hw_revision; 843 uint32_t fc_ph_low:8, 844 fc_ph_high:8, 845 feature_level_low:8, 846 feature_level_high:8; 847 uint32_t rsvd7; 848 uint32_t first_fw_id; 849 char first_fw_name[16]; 850 uint32_t second_fw_id; 851 char second_fw_name[16]; 852 uint32_t rsvd18[30]; 853 uint32_t available_length:24, 854 :8; 855 uint32_t physical_address_low; 856 uint32_t physical_address_high; 857 uint32_t returned_vpd_length; 858 uint32_t actual_vpd_length; 859#else 860#error big endian version not defined 861#endif 862} sli4_cmd_read_rev_t; 863 864/** 865 * @brief READ_SPARM64 - read the Port service parameters 866 */ 867typedef struct sli4_cmd_read_sparm64_s { 868 sli4_mbox_command_header_t hdr; 869#if BYTE_ORDER == LITTLE_ENDIAN 870 uint32_t rsvd1; 871 uint32_t rsvd2; 872 sli4_bde_t bde_64; 873 uint32_t vpi:16, 874 :16; 875 uint32_t port_name_start:16, 876 port_name_length:16; 877 uint32_t node_name_start:16, 878 node_name_length:16; 879#else 880#error big endian version not defined 881#endif 882} sli4_cmd_read_sparm64_t; 883 884#define SLI4_READ_SPARM64_VPI_DEFAULT 0 885#define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX 886 887#define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t)) 888#define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t)) 889 890typedef struct sli4_port_state_s { 891#if BYTE_ORDER == LITTLE_ENDIAN 892 uint32_t nx_port_recv_state:2, 893 nx_port_trans_state:2, 894 nx_port_state_machine:4, 895 link_speed:8, 896 :14, 897 tf:1, 898 lu:1; 899#else 900#error big endian version not defined 901#endif 902} sli4_port_state_t; 903 904/** 905 * @brief READ_TOPOLOGY - read the link event information 906 */ 907typedef struct sli4_cmd_read_topology_s { 908 sli4_mbox_command_header_t hdr; 909#if BYTE_ORDER == LITTLE_ENDIAN 910 uint32_t event_tag; 911 uint32_t attention_type:8, 912 il:1, 913 pb_recvd:1, 914 :22; 915 uint32_t topology:8, 916 lip_type:8, 917 lip_al_ps:8, 918 al_pa_granted:8; 919 sli4_bde_t bde_loop_map; 920 sli4_port_state_t link_down; 921 sli4_port_state_t link_current; 922 uint32_t max_bbc:8, 923 init_bbc:8, 924 bbscn:4, 925 cbbscn:4, 926 :8; 927 uint32_t r_t_tov:9, 928 :3, 929 al_tov:4, 930 lp_tov:16; 931 uint32_t acquired_al_pa:8, 932 :7, 933 pb:1, 934 specified_al_pa:16; 935 uint32_t initial_n_port_id:24, 936 :8; 937#else 938#error big endian version not defined 939#endif 940} sli4_cmd_read_topology_t; 941 942#define SLI4_MIN_LOOP_MAP_BYTES 128 943 944#define SLI4_READ_TOPOLOGY_LINK_UP 0x1 945#define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2 946#define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3 947 948#define SLI4_READ_TOPOLOGY_UNKNOWN 0x0 949#define SLI4_READ_TOPOLOGY_NPORT 0x1 950#define SLI4_READ_TOPOLOGY_FC_AL 0x2 951 952#define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00 953#define SLI4_READ_TOPOLOGY_SPEED_1G 0x04 954#define SLI4_READ_TOPOLOGY_SPEED_2G 0x08 955#define SLI4_READ_TOPOLOGY_SPEED_4G 0x10 956#define SLI4_READ_TOPOLOGY_SPEED_8G 0x20 957#define SLI4_READ_TOPOLOGY_SPEED_10G 0x40 958#define SLI4_READ_TOPOLOGY_SPEED_16G 0x80 959#define SLI4_READ_TOPOLOGY_SPEED_32G 0x90 960 961/** 962 * @brief REG_FCFI - activate a FC Forwarder 963 */ 964#define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4 965typedef struct sli4_cmd_reg_fcfi_s { 966 sli4_mbox_command_header_t hdr; 967#if BYTE_ORDER == LITTLE_ENDIAN 968 uint32_t fcf_index:16, 969 fcfi:16; 970 uint32_t rq_id_1:16, 971 rq_id_0:16; 972 uint32_t rq_id_3:16, 973 rq_id_2:16; 974 struct { 975 uint32_t r_ctl_mask:8, 976 r_ctl_match:8, 977 type_mask:8, 978 type_match:8; 979 } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]; 980 uint32_t vlan_tag:12, 981 vv:1, 982 :19; 983#else 984#error big endian version not defined 985#endif 986} sli4_cmd_reg_fcfi_t; 987 988#define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4 989#define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32 990#define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0 991#define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1 992 993typedef struct sli4_cmd_reg_fcfi_mrq_s { 994 sli4_mbox_command_header_t hdr; 995#if BYTE_ORDER == LITTLE_ENDIAN 996 uint32_t fcf_index:16, 997 fcfi:16; 998 999 uint32_t rq_id_1:16, 1000 rq_id_0:16; 1001 1002 uint32_t rq_id_3:16, 1003 rq_id_2:16; 1004 1005 struct { 1006 uint32_t r_ctl_mask:8, 1007 r_ctl_match:8, 1008 type_mask:8, 1009 type_match:8; 1010 } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG]; 1011 1012 uint32_t vlan_tag:12, 1013 vv:1, 1014 mode:1, 1015 :18; 1016 1017 uint32_t num_mrq_pairs:8, 1018 mrq_filter_bitmask:4, 1019 rq_selection_policy:4, 1020 :16; 1021#endif 1022} sli4_cmd_reg_fcfi_mrq_t; 1023 1024/** 1025 * @brief REG_RPI - register a Remote Port Indicator 1026 */ 1027typedef struct sli4_cmd_reg_rpi_s { 1028 sli4_mbox_command_header_t hdr; 1029#if BYTE_ORDER == LITTLE_ENDIAN 1030 uint32_t rpi:16, 1031 :16; 1032 uint32_t remote_n_port_id:24, 1033 upd:1, 1034 :2, 1035 etow:1, 1036 :1, 1037 terp:1, 1038 :1, 1039 ci:1; 1040 sli4_bde_t bde_64; 1041 uint32_t vpi:16, 1042 :16; 1043#else 1044#error big endian version not defined 1045#endif 1046} sli4_cmd_reg_rpi_t; 1047#define SLI4_REG_RPI_BUF_LEN 0x70 1048 1049 1050/** 1051 * @brief REG_VFI - register a Virtual Fabric Indicator 1052 */ 1053typedef struct sli4_cmd_reg_vfi_s { 1054 sli4_mbox_command_header_t hdr; 1055#if BYTE_ORDER == LITTLE_ENDIAN 1056 uint32_t vfi:16, 1057 :12, 1058 vp:1, 1059 upd:1, 1060 :2; 1061 uint32_t fcfi:16, 1062 vpi:16; /* vp=TRUE */ 1063 uint8_t wwpn[8]; /* vp=TRUE */ 1064 sli4_bde_t sparm; /* either FLOGI or PLOGI */ 1065 uint32_t e_d_tov; 1066 uint32_t r_a_tov; 1067 uint32_t local_n_port_id:24, /* vp=TRUE */ 1068 :8; 1069#else 1070#error big endian version not defined 1071#endif 1072} sli4_cmd_reg_vfi_t; 1073 1074/** 1075 * @brief REG_VPI - register a Virtual Port Indicator 1076 */ 1077typedef struct sli4_cmd_reg_vpi_s { 1078 sli4_mbox_command_header_t hdr; 1079#if BYTE_ORDER == LITTLE_ENDIAN 1080 uint32_t rsvd1; 1081 uint32_t local_n_port_id:24, 1082 upd:1, 1083 :7; 1084 uint8_t wwpn[8]; 1085 uint32_t rsvd5; 1086 uint32_t vpi:16, 1087 vfi:16; 1088#else 1089#error big endian version not defined 1090#endif 1091} sli4_cmd_reg_vpi_t; 1092 1093/** 1094 * @brief REQUEST_FEATURES - request / query SLI features 1095 */ 1096typedef union { 1097#if BYTE_ORDER == LITTLE_ENDIAN 1098 struct { 1099 uint32_t iaab:1, /** inhibit auto-ABTS originator */ 1100 npiv:1, /** NPIV support */ 1101 dif:1, /** DIF/DIX support */ 1102 vf:1, /** virtual fabric support */ 1103 fcpi:1, /** FCP initiator support */ 1104 fcpt:1, /** FCP target support */ 1105 fcpc:1, /** combined FCP initiator/target */ 1106 :1, 1107 rqd:1, /** recovery qualified delay */ 1108 iaar:1, /** inhibit auto-ABTS responder */ 1109 hlm:1, /** High Login Mode */ 1110 perfh:1, /** performance hints */ 1111 rxseq:1, /** RX Sequence Coalescing */ 1112 rxri:1, /** Release XRI variant of Coalescing */ 1113 dcl2:1, /** Disable Class 2 */ 1114 rsco:1, /** Receive Sequence Coalescing Optimizations */ 1115 mrqp:1, /** Multi RQ Pair Mode Support */ 1116 :15; 1117 } flag; 1118 uint32_t dword; 1119#else 1120#error big endian version not defined 1121#endif 1122} sli4_features_t; 1123 1124typedef struct sli4_cmd_request_features_s { 1125 sli4_mbox_command_header_t hdr; 1126#if BYTE_ORDER == LITTLE_ENDIAN 1127 uint32_t qry:1, 1128 :31; 1129#else 1130#error big endian version not defined 1131#endif 1132 sli4_features_t command; 1133 sli4_features_t response; 1134} sli4_cmd_request_features_t; 1135 1136/** 1137 * @brief SLI_CONFIG - submit a configuration command to Port 1138 * 1139 * Command is either embedded as part of the payload (embed) or located 1140 * in a separate memory buffer (mem) 1141 */ 1142 1143 1144typedef struct sli4_sli_config_pmd_s { 1145 uint32_t address_low; 1146 uint32_t address_high; 1147 uint32_t length:24, 1148 :8; 1149} sli4_sli_config_pmd_t; 1150 1151typedef struct sli4_cmd_sli_config_s { 1152 sli4_mbox_command_header_t hdr; 1153#if BYTE_ORDER == LITTLE_ENDIAN 1154 uint32_t emb:1, 1155 :2, 1156 pmd_count:5, 1157 :24; 1158 uint32_t payload_length; 1159 uint32_t rsvd3; 1160 uint32_t rsvd4; 1161 uint32_t rsvd5; 1162 union { 1163 uint8_t embed[58 * sizeof(uint32_t)]; 1164 sli4_sli_config_pmd_t mem; 1165 } payload; 1166#else 1167#error big endian version not defined 1168#endif 1169} sli4_cmd_sli_config_t; 1170 1171/** 1172 * @brief READ_STATUS - read tx/rx status of a particular port 1173 * 1174 */ 1175 1176typedef struct sli4_cmd_read_status_s { 1177 sli4_mbox_command_header_t hdr; 1178#if BYTE_ORDER == LITTLE_ENDIAN 1179 uint32_t cc:1, 1180 :31; 1181 uint32_t rsvd2; 1182 uint32_t transmit_kbyte_count; 1183 uint32_t receive_kbyte_count; 1184 uint32_t transmit_frame_count; 1185 uint32_t receive_frame_count; 1186 uint32_t transmit_sequence_count; 1187 uint32_t receive_sequence_count; 1188 uint32_t total_exchanges_originator; 1189 uint32_t total_exchanges_responder; 1190 uint32_t receive_p_bsy_count; 1191 uint32_t receive_f_bsy_count; 1192 uint32_t dropped_frames_due_to_no_rq_buffer_count; 1193 uint32_t empty_rq_timeout_count; 1194 uint32_t dropped_frames_due_to_no_xri_count; 1195 uint32_t empty_xri_pool_count; 1196 1197#else 1198#error big endian version not defined 1199#endif 1200} sli4_cmd_read_status_t; 1201 1202/** 1203 * @brief READ_LNK_STAT - read link status of a particular port 1204 * 1205 */ 1206 1207typedef struct sli4_cmd_read_link_stats_s { 1208 sli4_mbox_command_header_t hdr; 1209#if BYTE_ORDER == LITTLE_ENDIAN 1210 uint32_t rec:1, 1211 gec:1, 1212 w02of:1, 1213 w03of:1, 1214 w04of:1, 1215 w05of:1, 1216 w06of:1, 1217 w07of:1, 1218 w08of:1, 1219 w09of:1, 1220 w10of:1, 1221 w11of:1, 1222 w12of:1, 1223 w13of:1, 1224 w14of:1, 1225 w15of:1, 1226 w16of:1, 1227 w17of:1, 1228 w18of:1, 1229 w19of:1, 1230 w20of:1, 1231 w21of:1, 1232 resv0:8, 1233 clrc:1, 1234 clof:1; 1235 uint32_t link_failure_error_count; 1236 uint32_t loss_of_sync_error_count; 1237 uint32_t loss_of_signal_error_count; 1238 uint32_t primitive_sequence_error_count; 1239 uint32_t invalid_transmission_word_error_count; 1240 uint32_t crc_error_count; 1241 uint32_t primitive_sequence_event_timeout_count; 1242 uint32_t elastic_buffer_overrun_error_count; 1243 uint32_t arbitration_fc_al_timout_count; 1244 uint32_t advertised_receive_bufftor_to_buffer_credit; 1245 uint32_t current_receive_buffer_to_buffer_credit; 1246 uint32_t advertised_transmit_buffer_to_buffer_credit; 1247 uint32_t current_transmit_buffer_to_buffer_credit; 1248 uint32_t received_eofa_count; 1249 uint32_t received_eofdti_count; 1250 uint32_t received_eofni_count; 1251 uint32_t received_soff_count; 1252 uint32_t received_dropped_no_aer_count; 1253 uint32_t received_dropped_no_available_rpi_resources_count; 1254 uint32_t received_dropped_no_available_xri_resources_count; 1255 1256#else 1257#error big endian version not defined 1258#endif 1259} sli4_cmd_read_link_stats_t; 1260 1261/** 1262 * @brief Format a WQE with WQ_ID Association performance hint 1263 * 1264 * @par Description 1265 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID. 1266 * 1267 * @param entry Pointer to the WQE. 1268 * @param q_id Queue ID. 1269 * 1270 * @return None. 1271 */ 1272static inline void 1273sli_set_wq_id_association(void *entry, uint16_t q_id) 1274{ 1275 uint32_t *wqe = entry; 1276 1277 /* 1278 * Set Word 10, bit 0 to zero 1279 * Set Word 10, bits 15:1 to the WQ ID 1280 */ 1281#if BYTE_ORDER == LITTLE_ENDIAN 1282 wqe[10] &= ~0xffff; 1283 wqe[10] |= q_id << 1; 1284#else 1285#error big endian version not defined 1286#endif 1287} 1288 1289/** 1290 * @brief UNREG_FCFI - unregister a FCFI 1291 */ 1292typedef struct sli4_cmd_unreg_fcfi_s { 1293 sli4_mbox_command_header_t hdr; 1294 uint32_t rsvd1; 1295#if BYTE_ORDER == LITTLE_ENDIAN 1296 uint32_t fcfi:16, 1297 :16; 1298#else 1299#error big endian version not defined 1300#endif 1301} sli4_cmd_unreg_fcfi_t; 1302 1303/** 1304 * @brief UNREG_RPI - unregister one or more RPI 1305 */ 1306typedef struct sli4_cmd_unreg_rpi_s { 1307 sli4_mbox_command_header_t hdr; 1308#if BYTE_ORDER == LITTLE_ENDIAN 1309 uint32_t index:16, 1310 :13, 1311 dp:1, 1312 ii:2; 1313 uint32_t destination_n_port_id:24, 1314 :8; 1315#else 1316#error big endian version not defined 1317#endif 1318} sli4_cmd_unreg_rpi_t; 1319 1320#define SLI4_UNREG_RPI_II_RPI 0x0 1321#define SLI4_UNREG_RPI_II_VPI 0x1 1322#define SLI4_UNREG_RPI_II_VFI 0x2 1323#define SLI4_UNREG_RPI_II_FCFI 0x3 1324 1325/** 1326 * @brief UNREG_VFI - unregister one or more VFI 1327 */ 1328typedef struct sli4_cmd_unreg_vfi_s { 1329 sli4_mbox_command_header_t hdr; 1330#if BYTE_ORDER == LITTLE_ENDIAN 1331 uint32_t rsvd1; 1332 uint32_t index:16, 1333 :14, 1334 ii:2; 1335#else 1336#error big endian version not defined 1337#endif 1338} sli4_cmd_unreg_vfi_t; 1339 1340#define SLI4_UNREG_VFI_II_VFI 0x0 1341#define SLI4_UNREG_VFI_II_FCFI 0x3 1342 1343enum { 1344 SLI4_UNREG_TYPE_PORT, 1345 SLI4_UNREG_TYPE_DOMAIN, 1346 SLI4_UNREG_TYPE_FCF, 1347 SLI4_UNREG_TYPE_ALL 1348}; 1349 1350/** 1351 * @brief UNREG_VPI - unregister one or more VPI 1352 */ 1353typedef struct sli4_cmd_unreg_vpi_s { 1354 sli4_mbox_command_header_t hdr; 1355#if BYTE_ORDER == LITTLE_ENDIAN 1356 uint32_t rsvd1; 1357 uint32_t index:16, 1358 :14, 1359 ii:2; 1360#else 1361#error big endian version not defined 1362#endif 1363} sli4_cmd_unreg_vpi_t; 1364 1365#define SLI4_UNREG_VPI_II_VPI 0x0 1366#define SLI4_UNREG_VPI_II_VFI 0x2 1367#define SLI4_UNREG_VPI_II_FCFI 0x3 1368 1369 1370/** 1371 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature. 1372 */ 1373typedef struct sli4_cmd_config_auto_xfer_rdy_s { 1374 sli4_mbox_command_header_t hdr; 1375#if BYTE_ORDER == LITTLE_ENDIAN 1376 uint32_t resv; 1377 uint32_t max_burst_len; 1378#else 1379#error big endian version not defined 1380#endif 1381} sli4_cmd_config_auto_xfer_rdy_t; 1382 1383typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s { 1384 sli4_mbox_command_header_t hdr; 1385#if BYTE_ORDER == LITTLE_ENDIAN 1386 uint32_t resv; 1387 uint32_t max_burst_len; 1388 uint32_t esoc:1, 1389 :31; 1390 uint32_t block_size:16, 1391 :16; 1392#else 1393#error big endian version not defined 1394#endif 1395} sli4_cmd_config_auto_xfer_rdy_hp_t; 1396 1397 1398/************************************************************************* 1399 * SLI-4 common configuration command formats and definitions 1400 */ 1401 1402#define SLI4_CFG_STATUS_SUCCESS 0x00 1403#define SLI4_CFG_STATUS_FAILED 0x01 1404#define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02 1405#define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03 1406 1407#define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb 1408 1409#define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00 1410#define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e 1411 1412/** 1413 * Subsystem values. 1414 */ 1415#define SLI4_SUBSYSTEM_COMMON 0x01 1416#define SLI4_SUBSYSTEM_LOWLEVEL 0x0B 1417#define SLI4_SUBSYSTEM_FCFCOE 0x0c 1418#define SLI4_SUBSYSTEM_DMTF 0x11 1419 1420#define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36 1421 1422/** 1423 * Common opcode (OPC) values. 1424 */ 1425#define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d 1426#define SLI4_OPC_COMMON_CREATE_CQ 0x0c 1427#define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d 1428#define SLI4_OPC_COMMON_DESTROY_CQ 0x36 1429#define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29 1430#define SLI4_OPC_COMMON_CREATE_EQ 0x0d 1431#define SLI4_OPC_COMMON_DESTROY_EQ 0x37 1432#define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a 1433#define SLI4_OPC_COMMON_DESTROY_MQ 0x35 1434#define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20 1435#define SLI4_OPC_COMMON_NOP 0x21 1436#define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a 1437#define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5 1438#define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a 1439#define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d 1440 1441#define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07 1442#define SLI4_OPC_COMMON_MANAGE_FAT 0x44 1443#define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49 1444#define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79 1445#define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d 1446#define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e 1447#define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f 1448#define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80 1449#define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82 1450#define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0 1451#define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4 1452#define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5 1453#define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6 1454#define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7 1455#define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8 1456#define SLI4_OPC_COMMON_READ_OBJECT 0xab 1457#define SLI4_OPC_COMMON_WRITE_OBJECT 0xac 1458#define SLI4_OPC_COMMON_DELETE_OBJECT 0xae 1459#define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad 1460#define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8 1461#define SLI4_OPC_COMMON_SET_FEATURES 0xbf 1462#define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9 1463#define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca 1464 1465/** 1466 * DMTF opcode (OPC) values. 1467 */ 1468#define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01 1469 1470/** 1471 * @brief Generic Command Request header 1472 */ 1473typedef struct sli4_req_hdr_s { 1474#if BYTE_ORDER == LITTLE_ENDIAN 1475 uint32_t opcode:8, 1476 subsystem:8, 1477 :16; 1478 uint32_t timeout; 1479 uint32_t request_length; 1480 uint32_t version:8, 1481 :24; 1482#else 1483#error big endian version not defined 1484#endif 1485} sli4_req_hdr_t; 1486 1487/** 1488 * @brief Generic Command Response header 1489 */ 1490typedef struct sli4_res_hdr_s { 1491#if BYTE_ORDER == LITTLE_ENDIAN 1492 uint32_t opcode:8, 1493 subsystem:8, 1494 :16; 1495 uint32_t status:8, 1496 additional_status:8, 1497 :16; 1498 uint32_t response_length; 1499 uint32_t actual_response_length; 1500#else 1501#error big endian version not defined 1502#endif 1503} sli4_res_hdr_t; 1504 1505/** 1506 * @brief COMMON_FUNCTION_RESET 1507 * 1508 * Resets the Port, returning it to a power-on state. This configuration 1509 * command does not have a payload and should set/expect the lengths to 1510 * be zero. 1511 */ 1512typedef struct sli4_req_common_function_reset_s { 1513 sli4_req_hdr_t hdr; 1514} sli4_req_common_function_reset_t; 1515 1516 1517typedef struct sli4_res_common_function_reset_s { 1518 sli4_res_hdr_t hdr; 1519} sli4_res_common_function_reset_t; 1520 1521/** 1522 * @brief COMMON_CREATE_CQ_V0 1523 * 1524 * Create a Completion Queue. 1525 */ 1526typedef struct sli4_req_common_create_cq_v0_s { 1527 sli4_req_hdr_t hdr; 1528#if BYTE_ORDER == LITTLE_ENDIAN 1529 uint32_t num_pages:16, 1530 :16; 1531 uint32_t :12, 1532 clswm:2, 1533 nodelay:1, 1534 :12, 1535 cqecnt:2, 1536 valid:1, 1537 :1, 1538 evt:1; 1539 uint32_t :22, 1540 eq_id:8, 1541 :1, 1542 arm:1; 1543 uint32_t rsvd[2]; 1544 struct { 1545 uint32_t low; 1546 uint32_t high; 1547 } page_physical_address[0]; 1548#else 1549#error big endian version not defined 1550#endif 1551} sli4_req_common_create_cq_v0_t; 1552 1553/** 1554 * @brief COMMON_CREATE_CQ_V2 1555 * 1556 * Create a Completion Queue. 1557 */ 1558typedef struct sli4_req_common_create_cq_v2_s { 1559 sli4_req_hdr_t hdr; 1560#if BYTE_ORDER == LITTLE_ENDIAN 1561 uint32_t num_pages:16, 1562 page_size:8, 1563 :8, 1564 uint32_t :12, 1565 clswm:2, 1566 nodelay:1, 1567 autovalid:1, 1568 :11, 1569 cqecnt:2, 1570 valid:1, 1571 :1, 1572 evt:1; 1573 uint32_t eq_id:16, 1574 :15, 1575 arm:1; 1576 uint32_t cqe_count:16, 1577 :16; 1578 uint32_t rsvd[1]; 1579 struct { 1580 uint32_t low; 1581 uint32_t high; 1582 } page_physical_address[0]; 1583#else 1584#error big endian version not defined 1585#endif 1586} sli4_req_common_create_cq_v2_t; 1587 1588 1589 1590/** 1591 * @brief COMMON_CREATE_CQ_SET_V0 1592 * 1593 * Create a set of Completion Queues. 1594 */ 1595typedef struct sli4_req_common_create_cq_set_v0_s { 1596 sli4_req_hdr_t hdr; 1597#if BYTE_ORDER == LITTLE_ENDIAN 1598 uint32_t num_pages:16, 1599 page_size:8, 1600 :8; 1601 uint32_t :12, 1602 clswm:2, 1603 nodelay:1, 1604 autovalid:1, 1605 rsvd:11, 1606 cqecnt:2, 1607 valid:1, 1608 :1, 1609 evt:1; 1610 uint32_t num_cq_req:16, 1611 cqe_count:15, 1612 arm:1; 1613 uint16_t eq_id[16]; 1614 struct { 1615 uint32_t low; 1616 uint32_t high; 1617 } page_physical_address[0]; 1618#else 1619#error big endian version not defined 1620#endif 1621} sli4_req_common_create_cq_set_v0_t; 1622 1623/** 1624 * CQE count. 1625 */ 1626#define SLI4_CQ_CNT_256 0 1627#define SLI4_CQ_CNT_512 1 1628#define SLI4_CQ_CNT_1024 2 1629#define SLI4_CQ_CNT_LARGE 3 1630 1631#define SLI4_CQE_BYTES (4 * sizeof(uint32_t)) 1632 1633#define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8 1634 1635/** 1636 * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion 1637 */ 1638typedef struct sli4_res_common_create_queue_s { 1639 sli4_res_hdr_t hdr; 1640#if BYTE_ORDER == LITTLE_ENDIAN 1641 uint32_t q_id:16, 1642 :8, 1643 ulp:8; 1644 uint32_t db_offset; 1645 uint32_t db_rs:16, 1646 db_fmt:16; 1647#else 1648#error big endian version not defined 1649#endif 1650} sli4_res_common_create_queue_t; 1651 1652 1653typedef struct sli4_res_common_create_queue_set_s { 1654 sli4_res_hdr_t hdr; 1655#if BYTE_ORDER == LITTLE_ENDIAN 1656 uint32_t q_id:16, 1657 num_q_allocated:16; 1658#else 1659#error big endian version not defined 1660#endif 1661} sli4_res_common_create_queue_set_t; 1662 1663 1664/** 1665 * @brief Common Destroy CQ 1666 */ 1667typedef struct sli4_req_common_destroy_cq_s { 1668 sli4_req_hdr_t hdr; 1669#if BYTE_ORDER == LITTLE_ENDIAN 1670 uint32_t cq_id:16, 1671 :16; 1672#else 1673#error big endian version not defined 1674#endif 1675} sli4_req_common_destroy_cq_t; 1676 1677/** 1678 * @brief COMMON_MODIFY_EQ_DELAY 1679 * 1680 * Modify the delay multiplier for EQs 1681 */ 1682typedef struct sli4_req_common_modify_eq_delay_s { 1683 sli4_req_hdr_t hdr; 1684#if BYTE_ORDER == LITTLE_ENDIAN 1685 uint32_t num_eq; 1686 struct { 1687 uint32_t eq_id; 1688 uint32_t phase; 1689 uint32_t delay_multiplier; 1690 } eq_delay_record[8]; 1691#else 1692#error big endian version not defined 1693#endif 1694} sli4_req_common_modify_eq_delay_t; 1695 1696/** 1697 * @brief COMMON_CREATE_EQ 1698 * 1699 * Create an Event Queue. 1700 */ 1701typedef struct sli4_req_common_create_eq_s { 1702 sli4_req_hdr_t hdr; 1703#if BYTE_ORDER == LITTLE_ENDIAN 1704 uint32_t num_pages:16, 1705 :16; 1706 uint32_t :29, 1707 valid:1, 1708 :1, 1709 eqesz:1; 1710 uint32_t :26, 1711 count:3, 1712 :2, 1713 arm:1; 1714 uint32_t :13, 1715 delay_multiplier:10, 1716 :9; 1717 uint32_t rsvd; 1718 struct { 1719 uint32_t low; 1720 uint32_t high; 1721 } page_address[8]; 1722#else 1723#error big endian version not defined 1724#endif 1725} sli4_req_common_create_eq_t; 1726 1727#define SLI4_EQ_CNT_256 0 1728#define SLI4_EQ_CNT_512 1 1729#define SLI4_EQ_CNT_1024 2 1730#define SLI4_EQ_CNT_2048 3 1731#define SLI4_EQ_CNT_4096 4 1732 1733#define SLI4_EQE_SIZE_4 0 1734#define SLI4_EQE_SIZE_16 1 1735 1736/** 1737 * @brief Common Destroy EQ 1738 */ 1739typedef struct sli4_req_common_destroy_eq_s { 1740 sli4_req_hdr_t hdr; 1741#if BYTE_ORDER == LITTLE_ENDIAN 1742 uint32_t eq_id:16, 1743 :16; 1744#else 1745#error big endian version not defined 1746#endif 1747} sli4_req_common_destroy_eq_t; 1748 1749/** 1750 * @brief COMMON_CREATE_MQ_EXT 1751 * 1752 * Create a Mailbox Queue; accommodate v0 and v1 forms. 1753 */ 1754typedef struct sli4_req_common_create_mq_ext_s { 1755 sli4_req_hdr_t hdr; 1756#if BYTE_ORDER == LITTLE_ENDIAN 1757 uint32_t num_pages:16, 1758 cq_id_v1:16; 1759 uint32_t async_event_bitmap; 1760 uint32_t async_cq_id_v1:16, 1761 ring_size:4, 1762 :2, 1763 cq_id_v0:10; 1764 uint32_t :31, 1765 val:1; 1766 uint32_t acqv:1, 1767 async_cq_id_v0:10, 1768 :21; 1769 uint32_t rsvd9; 1770 struct { 1771 uint32_t low; 1772 uint32_t high; 1773 } page_physical_address[8]; 1774#else 1775#error big endian version not defined 1776#endif 1777} sli4_req_common_create_mq_ext_t; 1778 1779#define SLI4_MQE_SIZE_16 0x05 1780#define SLI4_MQE_SIZE_32 0x06 1781#define SLI4_MQE_SIZE_64 0x07 1782#define SLI4_MQE_SIZE_128 0x08 1783 1784#define SLI4_ASYNC_EVT_LINK_STATE BIT(1) 1785#define SLI4_ASYNC_EVT_FCOE_FIP BIT(2) 1786#define SLI4_ASYNC_EVT_DCBX BIT(3) 1787#define SLI4_ASYNC_EVT_ISCSI BIT(4) 1788#define SLI4_ASYNC_EVT_GRP5 BIT(5) 1789#define SLI4_ASYNC_EVT_FC BIT(16) 1790#define SLI4_ASYNC_EVT_SLI_PORT BIT(17) 1791#define SLI4_ASYNC_EVT_VF BIT(18) 1792#define SLI4_ASYNC_EVT_MR BIT(19) 1793 1794#define SLI4_ASYNC_EVT_ALL \ 1795 SLI4_ASYNC_EVT_LINK_STATE | \ 1796 SLI4_ASYNC_EVT_FCOE_FIP | \ 1797 SLI4_ASYNC_EVT_DCBX | \ 1798 SLI4_ASYNC_EVT_ISCSI | \ 1799 SLI4_ASYNC_EVT_GRP5 | \ 1800 SLI4_ASYNC_EVT_FC | \ 1801 SLI4_ASYNC_EVT_SLI_PORT | \ 1802 SLI4_ASYNC_EVT_VF |\ 1803 SLI4_ASYNC_EVT_MR 1804 1805#define SLI4_ASYNC_EVT_FC_FCOE \ 1806 SLI4_ASYNC_EVT_LINK_STATE | \ 1807 SLI4_ASYNC_EVT_FCOE_FIP | \ 1808 SLI4_ASYNC_EVT_GRP5 | \ 1809 SLI4_ASYNC_EVT_FC | \ 1810 SLI4_ASYNC_EVT_SLI_PORT 1811 1812/** 1813 * @brief Common Destroy MQ 1814 */ 1815typedef struct sli4_req_common_destroy_mq_s { 1816 sli4_req_hdr_t hdr; 1817#if BYTE_ORDER == LITTLE_ENDIAN 1818 uint32_t mq_id:16, 1819 :16; 1820#else 1821#error big endian version not defined 1822#endif 1823} sli4_req_common_destroy_mq_t; 1824 1825/** 1826 * @brief COMMON_GET_CNTL_ATTRIBUTES 1827 * 1828 * Query for information about the SLI Port 1829 */ 1830typedef struct sli4_res_common_get_cntl_attributes_s { 1831 sli4_res_hdr_t hdr; 1832#if BYTE_ORDER == LITTLE_ENDIAN 1833 uint8_t version_string[32]; 1834 uint8_t manufacturer_name[32]; 1835 uint32_t supported_modes; 1836 uint32_t eprom_version_lo:8, 1837 eprom_version_hi:8, 1838 :16; 1839 uint32_t mbx_data_structure_version; 1840 uint32_t ep_firmware_data_structure_version; 1841 uint8_t ncsi_version_string[12]; 1842 uint32_t default_extended_timeout; 1843 uint8_t model_number[32]; 1844 uint8_t description[64]; 1845 uint8_t serial_number[32]; 1846 uint8_t ip_version_string[32]; 1847 uint8_t fw_version_string[32]; 1848 uint8_t bios_version_string[32]; 1849 uint8_t redboot_version_string[32]; 1850 uint8_t driver_version_string[32]; 1851 uint8_t fw_on_flash_version_string[32]; 1852 uint32_t functionalities_supported; 1853 uint32_t max_cdb_length:16, 1854 asic_revision:8, 1855 generational_guid0:8; 1856 uint32_t generational_guid1_12[3]; 1857 uint32_t generational_guid13:24, 1858 hba_port_count:8; 1859 uint32_t default_link_down_timeout:16, 1860 iscsi_version_min_max:8, 1861 multifunctional_device:8; 1862 uint32_t cache_valid:8, 1863 hba_status:8, 1864 max_domains_supported:8, 1865 port_number:6, 1866 port_type:2; 1867 uint32_t firmware_post_status; 1868 uint32_t hba_mtu; 1869 uint32_t iscsi_features:8, 1870 rsvd121:24; 1871 uint32_t pci_vendor_id:16, 1872 pci_device_id:16; 1873 uint32_t pci_sub_vendor_id:16, 1874 pci_sub_system_id:16; 1875 uint32_t pci_bus_number:8, 1876 pci_device_number:8, 1877 pci_function_number:8, 1878 interface_type:8; 1879 uint64_t unique_identifier; 1880 uint32_t number_of_netfilters:8, 1881 rsvd130:24; 1882#else 1883#error big endian version not defined 1884#endif 1885} sli4_res_common_get_cntl_attributes_t; 1886 1887/** 1888 * @brief COMMON_GET_CNTL_ATTRIBUTES 1889 * 1890 * This command queries the controller information from the Flash ROM. 1891 */ 1892typedef struct sli4_req_common_get_cntl_addl_attributes_s { 1893 sli4_req_hdr_t hdr; 1894} sli4_req_common_get_cntl_addl_attributes_t; 1895 1896 1897typedef struct sli4_res_common_get_cntl_addl_attributes_s { 1898 sli4_res_hdr_t hdr; 1899 uint16_t ipl_file_number; 1900 uint8_t ipl_file_version; 1901 uint8_t rsvd0; 1902 uint8_t on_die_temperature; 1903 uint8_t rsvd1[3]; 1904 uint32_t driver_advanced_features_supported; 1905 uint32_t rsvd2[4]; 1906 char fcoe_universal_bios_version[32]; 1907 char fcoe_x86_bios_version[32]; 1908 char fcoe_efi_bios_version[32]; 1909 char fcoe_fcode_version[32]; 1910 char uefi_bios_version[32]; 1911 char uefi_nic_version[32]; 1912 char uefi_fcode_version[32]; 1913 char uefi_iscsi_version[32]; 1914 char iscsi_x86_bios_version[32]; 1915 char pxe_x86_bios_version[32]; 1916 uint8_t fcoe_default_wwpn[8]; 1917 uint8_t ext_phy_version[32]; 1918 uint8_t fc_universal_bios_version[32]; 1919 uint8_t fc_x86_bios_version[32]; 1920 uint8_t fc_efi_bios_version[32]; 1921 uint8_t fc_fcode_version[32]; 1922 uint8_t ext_phy_crc_label[8]; 1923 uint8_t ipl_file_name[16]; 1924 uint8_t rsvd3[72]; 1925} sli4_res_common_get_cntl_addl_attributes_t; 1926 1927/** 1928 * @brief COMMON_NOP 1929 * 1930 * This command does not do anything; it only returns the payload in the completion. 1931 */ 1932typedef struct sli4_req_common_nop_s { 1933 sli4_req_hdr_t hdr; 1934#if BYTE_ORDER == LITTLE_ENDIAN 1935 uint32_t context[2]; 1936#else 1937#error big endian version not defined 1938#endif 1939} sli4_req_common_nop_t; 1940 1941typedef struct sli4_res_common_nop_s { 1942 sli4_res_hdr_t hdr; 1943#if BYTE_ORDER == LITTLE_ENDIAN 1944 uint32_t context[2]; 1945#else 1946#error big endian version not defined 1947#endif 1948} sli4_res_common_nop_t; 1949 1950/** 1951 * @brief COMMON_GET_RESOURCE_EXTENT_INFO 1952 */ 1953typedef struct sli4_req_common_get_resource_extent_info_s { 1954 sli4_req_hdr_t hdr; 1955#if BYTE_ORDER == LITTLE_ENDIAN 1956 uint32_t resource_type:16, 1957 :16; 1958#else 1959#error big endian version not defined 1960#endif 1961} sli4_req_common_get_resource_extent_info_t; 1962 1963#define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c 1964#define SLI4_RSC_TYPE_FCOE_VFI 0x20 1965#define SLI4_RSC_TYPE_FCOE_VPI 0x21 1966#define SLI4_RSC_TYPE_FCOE_RPI 0x22 1967#define SLI4_RSC_TYPE_FCOE_XRI 0x23 1968 1969typedef struct sli4_res_common_get_resource_extent_info_s { 1970 sli4_res_hdr_t hdr; 1971#if BYTE_ORDER == LITTLE_ENDIAN 1972 uint32_t resource_extent_count:16, 1973 resource_extent_size:16; 1974#else 1975#error big endian version not defined 1976#endif 1977} sli4_res_common_get_resource_extent_info_t; 1978 1979 1980#define SLI4_128BYTE_WQE_SUPPORT 0x02 1981/** 1982 * @brief COMMON_GET_SLI4_PARAMETERS 1983 */ 1984typedef struct sli4_res_common_get_sli4_parameters_s { 1985 sli4_res_hdr_t hdr; 1986#if BYTE_ORDER == LITTLE_ENDIAN 1987 uint32_t protocol_type:8, 1988 :24; 1989 uint32_t ft:1, 1990 :3, 1991 sli_revision:4, 1992 sli_family:4, 1993 if_type:4, 1994 sli_hint_1:8, 1995 sli_hint_2:5, 1996 :3; 1997 uint32_t eq_page_cnt:4, 1998 :4, 1999 eqe_sizes:4, 2000 :4, 2001 eq_page_sizes:8, 2002 eqe_count_method:4, 2003 :4; 2004 uint32_t eqe_count_mask:16, 2005 :16; 2006 uint32_t cq_page_cnt:4, 2007 :4, 2008 cqe_sizes:4, 2009 :2, 2010 cqv:2, 2011 cq_page_sizes:8, 2012 cqe_count_method:4, 2013 :4; 2014 uint32_t cqe_count_mask:16, 2015 :16; 2016 uint32_t mq_page_cnt:4, 2017 :10, 2018 mqv:2, 2019 mq_page_sizes:8, 2020 mqe_count_method:4, 2021 :4; 2022 uint32_t mqe_count_mask:16, 2023 :16; 2024 uint32_t wq_page_cnt:4, 2025 :4, 2026 wqe_sizes:4, 2027 :2, 2028 wqv:2, 2029 wq_page_sizes:8, 2030 wqe_count_method:4, 2031 :4; 2032 uint32_t wqe_count_mask:16, 2033 :16; 2034 uint32_t rq_page_cnt:4, 2035 :4, 2036 rqe_sizes:4, 2037 :2, 2038 rqv:2, 2039 rq_page_sizes:8, 2040 rqe_count_method:4, 2041 :4; 2042 uint32_t rqe_count_mask:16, 2043 :12, 2044 rq_db_window:4; 2045 uint32_t fcoe:1, 2046 ext:1, 2047 hdrr:1, 2048 sglr:1, 2049 fbrr:1, 2050 areg:1, 2051 tgt:1, 2052 terp:1, 2053 assi:1, 2054 wchn:1, 2055 tcca:1, 2056 trty:1, 2057 trir:1, 2058 phoff:1, 2059 phon:1, 2060 phwq:1, /** Performance Hint WQ_ID Association */ 2061 boundary_4ga:1, 2062 rxc:1, 2063 hlm:1, 2064 ipr:1, 2065 rxri:1, 2066 sglc:1, 2067 timm:1, 2068 tsmm:1, 2069 :1, 2070 oas:1, 2071 lc:1, 2072 agxf:1, 2073 loopback_scope:4; 2074 uint32_t sge_supported_length; 2075 uint32_t sgl_page_cnt:4, 2076 :4, 2077 sgl_page_sizes:8, 2078 sgl_pp_align:8, 2079 :8; 2080 uint32_t min_rq_buffer_size:16, 2081 :16; 2082 uint32_t max_rq_buffer_size; 2083 uint32_t physical_xri_max:16, 2084 physical_rpi_max:16; 2085 uint32_t physical_vpi_max:16, 2086 physical_vfi_max:16; 2087 uint32_t rsvd19; 2088 uint32_t frag_num_field_offset:16, /* dword 20 */ 2089 frag_num_field_size:16; 2090 uint32_t sgl_index_field_offset:16, /* dword 21 */ 2091 sgl_index_field_size:16; 2092 uint32_t chain_sge_initial_value_lo; /* dword 22 */ 2093 uint32_t chain_sge_initial_value_hi; /* dword 23 */ 2094#else 2095#error big endian version not defined 2096#endif 2097} sli4_res_common_get_sli4_parameters_t; 2098 2099 2100/** 2101 * @brief COMMON_QUERY_FW_CONFIG 2102 * 2103 * This command retrieves firmware configuration parameters and adapter 2104 * resources available to the driver. 2105 */ 2106typedef struct sli4_req_common_query_fw_config_s { 2107 sli4_req_hdr_t hdr; 2108} sli4_req_common_query_fw_config_t; 2109 2110 2111#define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40 2112#define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80 2113#define SLI4_FUNCTION_MODE_DUA_MODE 0x800 2114 2115#define SLI4_ULP_MODE_FCOE_INI 0x40 2116#define SLI4_ULP_MODE_FCOE_TGT 0x80 2117 2118typedef struct sli4_res_common_query_fw_config_s { 2119 sli4_res_hdr_t hdr; 2120 uint32_t config_number; 2121 uint32_t asic_rev; 2122 uint32_t physical_port; 2123 uint32_t function_mode; 2124 uint32_t ulp0_mode; 2125 uint32_t ulp0_nic_wqid_base; 2126 uint32_t ulp0_nic_wq_total; /* Dword 10 */ 2127 uint32_t ulp0_toe_wqid_base; 2128 uint32_t ulp0_toe_wq_total; 2129 uint32_t ulp0_toe_rqid_base; 2130 uint32_t ulp0_toe_rq_total; 2131 uint32_t ulp0_toe_defrqid_base; 2132 uint32_t ulp0_toe_defrq_total; 2133 uint32_t ulp0_lro_rqid_base; 2134 uint32_t ulp0_lro_rq_total; 2135 uint32_t ulp0_iscsi_icd_base; 2136 uint32_t ulp0_iscsi_icd_total; /* Dword 20 */ 2137 uint32_t ulp1_mode; 2138 uint32_t ulp1_nic_wqid_base; 2139 uint32_t ulp1_nic_wq_total; 2140 uint32_t ulp1_toe_wqid_base; 2141 uint32_t ulp1_toe_wq_total; 2142 uint32_t ulp1_toe_rqid_base; 2143 uint32_t ulp1_toe_rq_total; 2144 uint32_t ulp1_toe_defrqid_base; 2145 uint32_t ulp1_toe_defrq_total; 2146 uint32_t ulp1_lro_rqid_base; /* Dword 30 */ 2147 uint32_t ulp1_lro_rq_total; 2148 uint32_t ulp1_iscsi_icd_base; 2149 uint32_t ulp1_iscsi_icd_total; 2150 uint32_t function_capabilities; 2151 uint32_t ulp0_cq_base; 2152 uint32_t ulp0_cq_total; 2153 uint32_t ulp0_eq_base; 2154 uint32_t ulp0_eq_total; 2155 uint32_t ulp0_iscsi_chain_icd_base; 2156 uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */ 2157 uint32_t ulp1_iscsi_chain_icd_base; 2158 uint32_t ulp1_iscsi_chain_icd_total; 2159} sli4_res_common_query_fw_config_t; 2160 2161/** 2162 * @brief COMMON_GET_PORT_NAME 2163 */ 2164typedef struct sli4_req_common_get_port_name_s { 2165 sli4_req_hdr_t hdr; 2166#if BYTE_ORDER == LITTLE_ENDIAN 2167 uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */ 2168 :30; 2169#else 2170#error big endian version not defined 2171#endif 2172} sli4_req_common_get_port_name_t; 2173 2174typedef struct sli4_res_common_get_port_name_s { 2175 sli4_res_hdr_t hdr; 2176 char port_name[4]; 2177} sli4_res_common_get_port_name_t; 2178 2179/** 2180 * @brief COMMON_WRITE_FLASHROM 2181 */ 2182typedef struct sli4_req_common_write_flashrom_s { 2183 sli4_req_hdr_t hdr; 2184#if BYTE_ORDER == LITTLE_ENDIAN 2185 uint32_t flash_rom_access_opcode; 2186 uint32_t flash_rom_access_operation_type; 2187 uint32_t data_buffer_size; 2188 uint32_t offset; 2189 uint8_t data_buffer[4]; 2190#else 2191#error big endian version not defined 2192#endif 2193} sli4_req_common_write_flashrom_t; 2194 2195#define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01 2196#define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02 2197#define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03 2198#define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04 2199#define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05 2200#define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06 2201#define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07 2202#define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08 2203#define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09 2204#define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a 2205 2206#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00 2207#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01 2208#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02 2209#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03 2210#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04 2211#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05 2212#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06 2213#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07 2214#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08 2215#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09 2216#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a 2217#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b 2218#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c 2219#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d 2220#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e 2221#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f 2222#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10 2223#define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11 2224 2225/** 2226 * @brief COMMON_MANAGE_FAT 2227 */ 2228typedef struct sli4_req_common_manage_fat_s { 2229 sli4_req_hdr_t hdr; 2230#if BYTE_ORDER == LITTLE_ENDIAN 2231 uint32_t fat_operation; 2232 uint32_t read_log_offset; 2233 uint32_t read_log_length; 2234 uint32_t data_buffer_size; 2235 uint32_t data_buffer; /* response only */ 2236#else 2237#error big endian version not defined 2238#endif 2239} sli4_req_common_manage_fat_t; 2240 2241/** 2242 * @brief COMMON_GET_EXT_FAT_CAPABILITIES 2243 */ 2244typedef struct sli4_req_common_get_ext_fat_capabilities_s { 2245 sli4_req_hdr_t hdr; 2246#if BYTE_ORDER == LITTLE_ENDIAN 2247 uint32_t parameter_type; 2248#else 2249#error big endian version not defined 2250#endif 2251} sli4_req_common_get_ext_fat_capabilities_t; 2252 2253/** 2254 * @brief COMMON_SET_EXT_FAT_CAPABILITIES 2255 */ 2256typedef struct sli4_req_common_set_ext_fat_capabilities_s { 2257 sli4_req_hdr_t hdr; 2258#if BYTE_ORDER == LITTLE_ENDIAN 2259 uint32_t maximum_log_entries; 2260 uint32_t log_entry_size; 2261 uint32_t logging_type:8, 2262 maximum_logging_functions:8, 2263 maximum_logging_ports:8, 2264 :8; 2265 uint32_t supported_modes; 2266 uint32_t number_modules; 2267 uint32_t debug_module[14]; 2268#else 2269#error big endian version not defined 2270#endif 2271} sli4_req_common_set_ext_fat_capabilities_t; 2272 2273/** 2274 * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 2275 */ 2276typedef struct sli4_req_common_ext_fat_configure_snapshot_s { 2277 sli4_req_hdr_t hdr; 2278#if BYTE_ORDER == LITTLE_ENDIAN 2279 uint32_t total_log_entries; 2280#else 2281#error big endian version not defined 2282#endif 2283} sli4_req_common_ext_fat_configure_snapshot_t; 2284 2285/** 2286 * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 2287 */ 2288typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s { 2289 sli4_req_hdr_t hdr; 2290#if BYTE_ORDER == LITTLE_ENDIAN 2291 uint32_t snapshot_mode; 2292 uint32_t start_index; 2293 uint32_t number_log_entries; 2294#else 2295#error big endian version not defined 2296#endif 2297} sli4_req_common_ext_fat_retrieve_snapshot_t; 2298 2299typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s { 2300 sli4_res_hdr_t hdr; 2301#if BYTE_ORDER == LITTLE_ENDIAN 2302 uint32_t number_log_entries; 2303 uint32_t version:8, 2304 physical_port:8, 2305 function_id:16; 2306 uint32_t trace_level; 2307 uint32_t module_mask[2]; 2308 uint32_t trace_table_index; 2309 uint32_t timestamp; 2310 uint8_t string_data[16]; 2311 uint32_t data[6]; 2312#else 2313#error big endian version not defined 2314#endif 2315} sli4_res_common_ext_fat_retrieve_snapshot_t; 2316 2317/** 2318 * @brief COMMON_EXT_FAT_READ_STRING_TABLE 2319 */ 2320typedef struct sli4_req_common_ext_fat_read_string_table_s { 2321 sli4_req_hdr_t hdr; 2322#if BYTE_ORDER == LITTLE_ENDIAN 2323 uint32_t byte_offset; 2324 uint32_t number_bytes; 2325#else 2326#error big endian version not defined 2327#endif 2328} sli4_req_common_ext_fat_read_string_table_t; 2329 2330typedef struct sli4_res_common_ext_fat_read_string_table_s { 2331 sli4_res_hdr_t hdr; 2332#if BYTE_ORDER == LITTLE_ENDIAN 2333 uint32_t number_returned_bytes; 2334 uint32_t number_remaining_bytes; 2335 uint32_t table_data0:8, 2336 :24; 2337 uint8_t table_data[0]; 2338#else 2339#error big endian version not defined 2340#endif 2341} sli4_res_common_ext_fat_read_string_table_t; 2342 2343/** 2344 * @brief COMMON_READ_TRANSCEIVER_DATA 2345 * 2346 * This command reads SFF transceiver data(Format is defined 2347 * by the SFF-8472 specification). 2348 */ 2349typedef struct sli4_req_common_read_transceiver_data_s { 2350 sli4_req_hdr_t hdr; 2351#if BYTE_ORDER == LITTLE_ENDIAN 2352 uint32_t page_number; 2353 uint32_t port; 2354#else 2355#error big endian version not defined 2356#endif 2357} sli4_req_common_read_transceiver_data_t; 2358 2359typedef struct sli4_res_common_read_transceiver_data_s { 2360 sli4_res_hdr_t hdr; 2361#if BYTE_ORDER == LITTLE_ENDIAN 2362 uint32_t page_number; 2363 uint32_t port; 2364 uint32_t page_data[32]; 2365 uint32_t page_data_2[32]; 2366#else 2367#error big endian version not defined 2368#endif 2369} sli4_res_common_read_transceiver_data_t; 2370 2371/** 2372 * @brief COMMON_READ_OBJECT 2373 */ 2374typedef struct sli4_req_common_read_object_s { 2375 sli4_req_hdr_t hdr; 2376#if BYTE_ORDER == LITTLE_ENDIAN 2377 uint32_t desired_read_length:24, 2378 :8; 2379 uint32_t read_offset; 2380 uint8_t object_name[104]; 2381 uint32_t host_buffer_descriptor_count; 2382 sli4_bde_t host_buffer_descriptor[0]; 2383#else 2384#error big endian version not defined 2385#endif 2386} sli4_req_common_read_object_t; 2387 2388typedef struct sli4_res_common_read_object_s { 2389 sli4_res_hdr_t hdr; 2390#if BYTE_ORDER == LITTLE_ENDIAN 2391 uint32_t actual_read_length; 2392 uint32_t resv:31, 2393 eof:1; 2394#else 2395#error big endian version not defined 2396#endif 2397} sli4_res_common_read_object_t; 2398 2399/** 2400 * @brief COMMON_WRITE_OBJECT 2401 */ 2402typedef struct sli4_req_common_write_object_s { 2403 sli4_req_hdr_t hdr; 2404#if BYTE_ORDER == LITTLE_ENDIAN 2405 uint32_t desired_write_length:24, 2406 :6, 2407 noc:1, 2408 eof:1; 2409 uint32_t write_offset; 2410 uint8_t object_name[104]; 2411 uint32_t host_buffer_descriptor_count; 2412 sli4_bde_t host_buffer_descriptor[0]; 2413#else 2414#error big endian version not defined 2415#endif 2416} sli4_req_common_write_object_t; 2417 2418typedef struct sli4_res_common_write_object_s { 2419 sli4_res_hdr_t hdr; 2420#if BYTE_ORDER == LITTLE_ENDIAN 2421 uint32_t actual_write_length; 2422 uint32_t change_status:8, 2423 :24; 2424#else 2425#error big endian version not defined 2426#endif 2427} sli4_res_common_write_object_t; 2428 2429/** 2430 * @brief COMMON_DELETE_OBJECT 2431 */ 2432typedef struct sli4_req_common_delete_object_s { 2433 sli4_req_hdr_t hdr; 2434#if BYTE_ORDER == LITTLE_ENDIAN 2435 uint32_t rsvd4; 2436 uint32_t rsvd5; 2437 uint8_t object_name[104]; 2438#else 2439#error big endian version not defined 2440#endif 2441} sli4_req_common_delete_object_t; 2442 2443/** 2444 * @brief COMMON_READ_OBJECT_LIST 2445 */ 2446typedef struct sli4_req_common_read_object_list_s { 2447 sli4_req_hdr_t hdr; 2448#if BYTE_ORDER == LITTLE_ENDIAN 2449 uint32_t desired_read_length:24, 2450 :8; 2451 uint32_t read_offset; 2452 uint8_t object_name[104]; 2453 uint32_t host_buffer_descriptor_count; 2454 sli4_bde_t host_buffer_descriptor[0]; 2455#else 2456#error big endian version not defined 2457#endif 2458} sli4_req_common_read_object_list_t; 2459 2460/** 2461 * @brief COMMON_SET_DUMP_LOCATION 2462 */ 2463typedef struct sli4_req_common_set_dump_location_s { 2464 sli4_req_hdr_t hdr; 2465#if BYTE_ORDER == LITTLE_ENDIAN 2466 uint32_t buffer_length:24, 2467 :5, 2468 fdb:1, 2469 blp:1, 2470 qry:1; 2471 uint32_t buf_addr_low; 2472 uint32_t buf_addr_high; 2473#else 2474#error big endian version not defined 2475#endif 2476} sli4_req_common_set_dump_location_t; 2477 2478typedef struct sli4_res_common_set_dump_location_s { 2479 sli4_res_hdr_t hdr; 2480#if BYTE_ORDER == LITTLE_ENDIAN 2481 uint32_t buffer_length:24, 2482 :8; 2483#else 2484#error big endian version not defined 2485#endif 2486}sli4_res_common_set_dump_location_t; 2487 2488/** 2489 * @brief COMMON_SET_SET_FEATURES 2490 */ 2491#define SLI4_SET_FEATURES_DIF_SEED 0x01 2492#define SLI4_SET_FEATURES_XRI_TIMER 0x03 2493#define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04 2494#define SLI4_SET_FEATURES_FCTL_CHECK 0x05 2495#define SLI4_SET_FEATURES_FEC 0x06 2496#define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07 2497#define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08 2498#define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09 2499#define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A 2500#define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C 2501#define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D 2502#define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F 2503#define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11 2504 2505typedef struct sli4_req_common_set_features_s { 2506 sli4_req_hdr_t hdr; 2507#if BYTE_ORDER == LITTLE_ENDIAN 2508 uint32_t feature; 2509 uint32_t param_len; 2510 uint32_t params[8]; 2511#else 2512#error big endian version not defined 2513#endif 2514} sli4_req_common_set_features_t; 2515 2516typedef struct sli4_req_common_set_features_dif_seed_s { 2517#if BYTE_ORDER == LITTLE_ENDIAN 2518 uint32_t seed:16, 2519 :16; 2520#else 2521#error big endian version not defined 2522#endif 2523} sli4_req_common_set_features_dif_seed_t; 2524 2525typedef struct sli4_req_common_set_features_t10_pi_mem_model_s { 2526#if BYTE_ORDER == LITTLE_ENDIAN 2527 uint32_t tmm:1, 2528 :31; 2529#else 2530#error big endian version not defined 2531#endif 2532} sli4_req_common_set_features_t10_pi_mem_model_t; 2533 2534typedef struct sli4_req_common_set_features_multirq_s { 2535#if BYTE_ORDER == LITTLE_ENDIAN 2536 uint32_t isr:1, /*<< Include Sequence Reporting */ 2537 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */ 2538 :30; 2539 uint32_t num_rqs:8, 2540 rq_select_policy:4, 2541 :20; 2542#else 2543#error big endian version not defined 2544#endif 2545} sli4_req_common_set_features_multirq_t; 2546 2547typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s { 2548#if BYTE_ORDER == LITTLE_ENDIAN 2549 uint32_t rtc:1, 2550 atv:1, 2551 tmm:1, 2552 :1, 2553 p_type:3, 2554 blk_size:3, 2555 :22; 2556 uint32_t app_tag:16, 2557 :16; 2558#else 2559#error big endian version not defined 2560#endif 2561} sli4_req_common_set_features_xfer_rdy_t10pi_t; 2562 2563typedef struct sli4_req_common_set_features_health_check_s { 2564#if BYTE_ORDER == LITTLE_ENDIAN 2565 uint32_t hck:1, 2566 qry:1, 2567 :30; 2568#else 2569#error big endian version not defined 2570#endif 2571} sli4_req_common_set_features_health_check_t; 2572 2573typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s { 2574#if BYTE_ORDER == LITTLE_ENDIAN 2575 uint32_t fdt_xfer_hint; 2576#else 2577#error big endian version not defined 2578#endif 2579} sli4_req_common_set_features_set_fdt_xfer_hint_t; 2580 2581/** 2582 * @brief DMTF_EXEC_CLP_CMD 2583 */ 2584typedef struct sli4_req_dmtf_exec_clp_cmd_s { 2585 sli4_req_hdr_t hdr; 2586#if BYTE_ORDER == LITTLE_ENDIAN 2587 uint32_t cmd_buf_length; 2588 uint32_t resp_buf_length; 2589 uint32_t cmd_buf_addr_low; 2590 uint32_t cmd_buf_addr_high; 2591 uint32_t resp_buf_addr_low; 2592 uint32_t resp_buf_addr_high; 2593#else 2594#error big endian version not defined 2595#endif 2596} sli4_req_dmtf_exec_clp_cmd_t; 2597 2598typedef struct sli4_res_dmtf_exec_clp_cmd_s { 2599 sli4_res_hdr_t hdr; 2600#if BYTE_ORDER == LITTLE_ENDIAN 2601 uint32_t :32; 2602 uint32_t resp_length; 2603 uint32_t :32; 2604 uint32_t :32; 2605 uint32_t :32; 2606 uint32_t :32; 2607 uint32_t clp_status; 2608 uint32_t clp_detailed_status; 2609#else 2610#error big endian version not defined 2611#endif 2612} sli4_res_dmtf_exec_clp_cmd_t; 2613 2614/** 2615 * @brief Resource descriptor 2616 */ 2617 2618#define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50 2619#define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51 2620#define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52 2621#define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53 2622#define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54 2623#define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55 2624#define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56 2625 2626#define SLI4_PROTOCOL_NIC_TOE 0x01 2627#define SLI4_PROTOCOL_ISCSI 0x02 2628#define SLI4_PROTOCOL_FCOE 0x04 2629#define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08 2630#define SLI4_PROTOCOL_FC 0x10 2631#define SLI4_PROTOCOL_DEFAULT 0xff 2632 2633typedef struct sli4_resource_descriptor_v1_s { 2634 uint32_t descriptor_type:8, 2635 descriptor_length:8, 2636 :16; 2637 uint32_t type_specific[0]; 2638} sli4_resource_descriptor_v1_t; 2639 2640typedef struct sli4_pcie_resource_descriptor_v1_s { 2641 uint32_t descriptor_type:8, 2642 descriptor_length:8, 2643 :14, 2644 imm:1, 2645 nosv:1; 2646 uint32_t :16, 2647 pf_number:10, 2648 :6; 2649 uint32_t rsvd1; 2650 uint32_t sriov_state:8, 2651 pf_state:8, 2652 pf_type:8, 2653 :8; 2654 uint32_t number_of_vfs:16, 2655 :16; 2656 uint32_t mission_roles:8, 2657 :19, 2658 pchg:1, 2659 schg:1, 2660 xchg:1, 2661 xrom:2; 2662 uint32_t rsvd2[16]; 2663} sli4_pcie_resource_descriptor_v1_t; 2664 2665typedef struct sli4_isap_resource_descriptor_v1_s { 2666 uint32_t descriptor_type:8, 2667 descriptor_length:8, 2668 :16; 2669 uint32_t iscsi_tgt:1, 2670 iscsi_ini:1, 2671 iscsi_dif:1, 2672 :29; 2673 uint32_t rsvd1[3]; 2674 uint32_t fcoe_tgt:1, 2675 fcoe_ini:1, 2676 fcoe_dif:1, 2677 :29; 2678 uint32_t rsvd2[7]; 2679 uint32_t mc_type0:8, 2680 mc_type1:8, 2681 mc_type2:8, 2682 mc_type3:8; 2683 uint32_t rsvd3[3]; 2684} sli4_isap_resouce_descriptor_v1_t; 2685 2686/** 2687 * @brief COMMON_GET_FUNCTION_CONFIG 2688 */ 2689typedef struct sli4_req_common_get_function_config_s { 2690 sli4_req_hdr_t hdr; 2691} sli4_req_common_get_function_config_t; 2692 2693typedef struct sli4_res_common_get_function_config_s { 2694 sli4_res_hdr_t hdr; 2695#if BYTE_ORDER == LITTLE_ENDIAN 2696 uint32_t desc_count; 2697 uint32_t desc[54]; 2698#else 2699#error big endian version not defined 2700#endif 2701} sli4_res_common_get_function_config_t; 2702 2703/** 2704 * @brief COMMON_GET_PROFILE_CONFIG 2705 */ 2706typedef struct sli4_req_common_get_profile_config_s { 2707 sli4_req_hdr_t hdr; 2708 uint32_t profile_id:8, 2709 typ:2, 2710 :22; 2711} sli4_req_common_get_profile_config_t; 2712 2713typedef struct sli4_res_common_get_profile_config_s { 2714 sli4_res_hdr_t hdr; 2715#if BYTE_ORDER == LITTLE_ENDIAN 2716 uint32_t desc_count; 2717 uint32_t desc[0]; 2718#else 2719#error big endian version not defined 2720#endif 2721} sli4_res_common_get_profile_config_t; 2722 2723/** 2724 * @brief COMMON_SET_PROFILE_CONFIG 2725 */ 2726typedef struct sli4_req_common_set_profile_config_s { 2727 sli4_req_hdr_t hdr; 2728 uint32_t profile_id:8, 2729 :23, 2730 isap:1; 2731 uint32_t desc_count; 2732 uint32_t desc[0]; 2733} sli4_req_common_set_profile_config_t; 2734 2735typedef struct sli4_res_common_set_profile_config_s { 2736 sli4_res_hdr_t hdr; 2737#if BYTE_ORDER == LITTLE_ENDIAN 2738#else 2739#error big endian version not defined 2740#endif 2741} sli4_res_common_set_profile_config_t; 2742 2743/** 2744 * @brief Profile Descriptor for profile functions 2745 */ 2746typedef struct sli4_profile_descriptor_s { 2747#if BYTE_ORDER == LITTLE_ENDIAN 2748 uint32_t profile_id:8, 2749 :8, 2750 profile_index:8, 2751 :8; 2752 uint32_t profile_description[128]; 2753#else 2754#error big endian version not defined 2755#endif 2756} sli4_profile_descriptor_t; 2757 2758/* We don't know in advance how many descriptors there are. We have 2759 to pick a number that we think will be big enough and ask for that 2760 many. */ 2761 2762#define MAX_PRODUCT_DESCRIPTORS 40 2763 2764/** 2765 * @brief COMMON_GET_PROFILE_LIST 2766 */ 2767typedef struct sli4_req_common_get_profile_list_s { 2768 sli4_req_hdr_t hdr; 2769#if BYTE_ORDER == LITTLE_ENDIAN 2770 uint32_t start_profile_index:8, 2771 :24; 2772#else 2773#error big endian version not defined 2774#endif 2775} sli4_req_common_get_profile_list_t; 2776 2777typedef struct sli4_res_common_get_profile_list_s { 2778 sli4_res_hdr_t hdr; 2779#if BYTE_ORDER == LITTLE_ENDIAN 2780 uint32_t profile_descriptor_count; 2781 sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS]; 2782#else 2783#error big endian version not defined 2784#endif 2785} sli4_res_common_get_profile_list_t; 2786 2787/** 2788 * @brief COMMON_GET_ACTIVE_PROFILE 2789 */ 2790typedef struct sli4_req_common_get_active_profile_s { 2791 sli4_req_hdr_t hdr; 2792} sli4_req_common_get_active_profile_t; 2793 2794typedef struct sli4_res_common_get_active_profile_s { 2795 sli4_res_hdr_t hdr; 2796#if BYTE_ORDER == LITTLE_ENDIAN 2797 uint32_t active_profile_id:8, 2798 :8, 2799 next_profile_id:8, 2800 :8; 2801#else 2802#error big endian version not defined 2803#endif 2804} sli4_res_common_get_active_profile_t; 2805 2806/** 2807 * @brief COMMON_SET_ACTIVE_PROFILE 2808 */ 2809typedef struct sli4_req_common_set_active_profile_s { 2810 sli4_req_hdr_t hdr; 2811#if BYTE_ORDER == LITTLE_ENDIAN 2812 uint32_t active_profile_id:8, 2813 :23, 2814 fd:1; 2815#else 2816#error big endian version not defined 2817#endif 2818} sli4_req_common_set_active_profile_t; 2819 2820typedef struct sli4_res_common_set_active_profile_s { 2821 sli4_res_hdr_t hdr; 2822} sli4_res_common_set_active_profile_t; 2823 2824/** 2825 * @brief Link Config Descriptor for link config functions 2826 */ 2827typedef struct sli4_link_config_descriptor_s { 2828#if BYTE_ORDER == LITTLE_ENDIAN 2829 uint32_t link_config_id:8, 2830 :24; 2831 uint32_t config_description[8]; 2832#else 2833#error big endian version not defined 2834#endif 2835} sli4_link_config_descriptor_t; 2836 2837#define MAX_LINK_CONFIG_DESCRIPTORS 10 2838 2839/** 2840 * @brief COMMON_GET_RECONFIG_LINK_INFO 2841 */ 2842typedef struct sli4_req_common_get_reconfig_link_info_s { 2843 sli4_req_hdr_t hdr; 2844#if BYTE_ORDER == LITTLE_ENDIAN 2845#else 2846#error big endian version not defined 2847#endif 2848} sli4_req_common_get_reconfig_link_info_t; 2849 2850typedef struct sli4_res_common_get_reconfig_link_info_s { 2851 sli4_res_hdr_t hdr; 2852#if BYTE_ORDER == LITTLE_ENDIAN 2853 uint32_t active_link_config_id:8, 2854 :8, 2855 next_link_config_id:8, 2856 :8; 2857 uint32_t link_configuration_descriptor_count; 2858 sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS]; 2859#else 2860#error big endian version not defined 2861#endif 2862} sli4_res_common_get_reconfig_link_info_t; 2863 2864/** 2865 * @brief COMMON_SET_RECONFIG_LINK_ID 2866 */ 2867typedef struct sli4_req_common_set_reconfig_link_id_s { 2868 sli4_req_hdr_t hdr; 2869#if BYTE_ORDER == LITTLE_ENDIAN 2870 uint32_t next_link_config_id:8, 2871 :23, 2872 fd:1; 2873#else 2874#error big endian version not defined 2875#endif 2876} sli4_req_common_set_reconfig_link_id_t; 2877 2878typedef struct sli4_res_common_set_reconfig_link_id_s { 2879 sli4_res_hdr_t hdr; 2880#if BYTE_ORDER == LITTLE_ENDIAN 2881#else 2882#error big endian version not defined 2883#endif 2884} sli4_res_common_set_reconfig_link_id_t; 2885 2886 2887typedef struct sli4_req_lowlevel_set_watchdog_s { 2888 sli4_req_hdr_t hdr; 2889#if BYTE_ORDER == LITTLE_ENDIAN 2890 uint32_t watchdog_timeout:16, 2891 :16; 2892#else 2893#error big endian version not defined 2894#endif 2895 2896} sli4_req_lowlevel_set_watchdog_t; 2897 2898 2899typedef struct sli4_res_lowlevel_set_watchdog_s { 2900 sli4_res_hdr_t hdr; 2901#if BYTE_ORDER == LITTLE_ENDIAN 2902 uint32_t rsvd; 2903#else 2904#error big endian version not defined 2905#endif 2906} sli4_res_lowlevel_set_watchdog_t; 2907 2908/** 2909 * @brief Event Queue Entry 2910 */ 2911typedef struct sli4_eqe_s { 2912#if BYTE_ORDER == LITTLE_ENDIAN 2913 uint32_t vld:1, /** valid */ 2914 major_code:3, 2915 minor_code:12, 2916 resource_id:16; 2917#else 2918#error big endian version not defined 2919#endif 2920} sli4_eqe_t; 2921 2922#define SLI4_MAJOR_CODE_STANDARD 0 2923#define SLI4_MAJOR_CODE_SENTINEL 1 2924 2925/** 2926 * @brief Mailbox Completion Queue Entry 2927 * 2928 * A CQE generated on the completion of a MQE from a MQ. 2929 */ 2930typedef struct sli4_mcqe_s { 2931#if BYTE_ORDER == LITTLE_ENDIAN 2932 uint32_t completion_status:16, /** values are protocol specific */ 2933 extended_status:16; 2934 uint32_t mqe_tag_low; 2935 uint32_t mqe_tag_high; 2936 uint32_t :27, 2937 con:1, /** consumed - command now being executed */ 2938 cmp:1, /** completed - command still executing if clear */ 2939 :1, 2940 ae:1, /** async event - this is an ACQE */ 2941 val:1; /** valid - contents of CQE are valid */ 2942#else 2943#error big endian version not defined 2944#endif 2945} sli4_mcqe_t; 2946 2947 2948/** 2949 * @brief Asynchronous Completion Queue Entry 2950 * 2951 * A CQE generated asynchronously in response to the link or other internal events. 2952 */ 2953typedef struct sli4_acqe_s { 2954#if BYTE_ORDER == LITTLE_ENDIAN 2955 uint32_t event_data[3]; 2956 uint32_t :8, 2957 event_code:8, 2958 event_type:8, /** values are protocol specific */ 2959 :6, 2960 ae:1, /** async event - this is an ACQE */ 2961 val:1; /** valid - contents of CQE are valid */ 2962#else 2963#error big endian version not defined 2964#endif 2965} sli4_acqe_t; 2966 2967#define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01 2968#define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02 2969#define SLI4_ACQE_EVENT_CODE_DCBX 0x03 2970#define SLI4_ACQE_EVENT_CODE_ISCSI 0x04 2971#define SLI4_ACQE_EVENT_CODE_GRP_5 0x05 2972#define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10 2973#define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11 2974#define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12 2975#define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13 2976 2977/** 2978 * @brief Register name enums 2979 */ 2980typedef enum { 2981 SLI4_REG_BMBX, 2982 SLI4_REG_EQCQ_DOORBELL, 2983 SLI4_REG_FCOE_RQ_DOORBELL, 2984 SLI4_REG_IO_WQ_DOORBELL, 2985 SLI4_REG_MQ_DOORBELL, 2986 SLI4_REG_PHYSDEV_CONTROL, 2987 SLI4_REG_SLIPORT_CONTROL, 2988 SLI4_REG_SLIPORT_ERROR1, 2989 SLI4_REG_SLIPORT_ERROR2, 2990 SLI4_REG_SLIPORT_SEMAPHORE, 2991 SLI4_REG_SLIPORT_STATUS, 2992 SLI4_REG_UERR_MASK_HI, 2993 SLI4_REG_UERR_MASK_LO, 2994 SLI4_REG_UERR_STATUS_HI, 2995 SLI4_REG_UERR_STATUS_LO, 2996 SLI4_REG_SW_UE_CSR1, 2997 SLI4_REG_SW_UE_CSR2, 2998 SLI4_REG_MAX /* must be last */ 2999} sli4_regname_e; 3000 3001typedef struct sli4_reg_s { 3002 uint32_t rset; 3003 uint32_t off; 3004} sli4_reg_t; 3005 3006typedef enum { 3007 SLI_QTYPE_EQ, 3008 SLI_QTYPE_CQ, 3009 SLI_QTYPE_MQ, 3010 SLI_QTYPE_WQ, 3011 SLI_QTYPE_RQ, 3012 SLI_QTYPE_MAX, /* must be last */ 3013} sli4_qtype_e; 3014 3015#define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */ 3016#define SLI_MAX_CQ_SET_COUNT 16 3017#define SLI_MAX_RQ_SET_COUNT 16 3018 3019typedef enum { 3020 SLI_QENTRY_ASYNC, 3021 SLI_QENTRY_MQ, 3022 SLI_QENTRY_RQ, 3023 SLI_QENTRY_WQ, 3024 SLI_QENTRY_WQ_RELEASE, 3025 SLI_QENTRY_OPT_WRITE_CMD, 3026 SLI_QENTRY_OPT_WRITE_DATA, 3027 SLI_QENTRY_XABT, 3028 SLI_QENTRY_MAX /* must be last */ 3029} sli4_qentry_e; 3030 3031typedef struct sli4_queue_s { 3032 /* Common to all queue types */ 3033 ocs_dma_t dma; 3034 ocs_lock_t lock; 3035 uint32_t index; /** current host entry index */ 3036 uint16_t size; /** entry size */ 3037 uint16_t length; /** number of entries */ 3038 uint16_t n_posted; /** number entries posted */ 3039 uint16_t id; /** Port assigned xQ_ID */ 3040 uint16_t ulp; /** ULP assigned to this queue */ 3041 uint32_t doorbell_offset;/** The offset for the doorbell */ 3042 uint16_t doorbell_rset; /** register set for the doorbell */ 3043 uint8_t type; /** queue type ie EQ, CQ, ... */ 3044 uint32_t proc_limit; /** limit number of CQE processed per iteration */ 3045 uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */ 3046 uint32_t max_num_processed; 3047 time_t max_process_time; 3048 3049 /* Type specific gunk */ 3050 union { 3051 uint32_t r_idx; /** "read" index (MQ only) */ 3052 struct { 3053 uint32_t is_mq:1,/** CQ contains MQ/Async completions */ 3054 is_hdr:1,/** is a RQ for packet headers */ 3055 rq_batch:1;/** RQ index incremented by 8 */ 3056 } flag; 3057 } u; 3058} sli4_queue_t; 3059 3060static inline void 3061sli_queue_lock(sli4_queue_t *q) 3062{ 3063 ocs_lock(&q->lock); 3064} 3065 3066static inline void 3067sli_queue_unlock(sli4_queue_t *q) 3068{ 3069 ocs_unlock(&q->lock); 3070} 3071 3072 3073#define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */ 3074 3075#define SLI4_QUEUE_RQ_BATCH 8 3076 3077typedef enum { 3078 SLI4_CB_LINK, 3079 SLI4_CB_FIP, 3080 SLI4_CB_MAX /* must be last */ 3081} sli4_callback_e; 3082 3083typedef enum { 3084 SLI_LINK_STATUS_UP, 3085 SLI_LINK_STATUS_DOWN, 3086 SLI_LINK_STATUS_NO_ALPA, 3087 SLI_LINK_STATUS_MAX, 3088} sli4_link_status_e; 3089 3090typedef enum { 3091 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */ 3092 SLI_LINK_TOPO_LOOP, 3093 SLI_LINK_TOPO_LOOPBACK_INTERNAL, 3094 SLI_LINK_TOPO_LOOPBACK_EXTERNAL, 3095 SLI_LINK_TOPO_NONE, 3096 SLI_LINK_TOPO_MAX, 3097} sli4_link_topology_e; 3098 3099/* TODO do we need both sli4_port_type_e & sli4_link_medium_e */ 3100typedef enum { 3101 SLI_LINK_MEDIUM_ETHERNET, 3102 SLI_LINK_MEDIUM_FC, 3103 SLI_LINK_MEDIUM_MAX, 3104} sli4_link_medium_e; 3105 3106typedef struct sli4_link_event_s { 3107 sli4_link_status_e status; /* link up/down */ 3108 sli4_link_topology_e topology; 3109 sli4_link_medium_e medium; /* Ethernet / FC */ 3110 uint32_t speed; /* Mbps */ 3111 uint8_t *loop_map; 3112 uint32_t fc_id; 3113} sli4_link_event_t; 3114 3115/** 3116 * @brief Fields retrieved from skyhawk that used used to build chained SGL 3117 */ 3118typedef struct sli4_sgl_chaining_params_s { 3119 uint8_t chaining_capable; 3120 uint16_t frag_num_field_offset; 3121 uint16_t sgl_index_field_offset; 3122 uint64_t frag_num_field_mask; 3123 uint64_t sgl_index_field_mask; 3124 uint32_t chain_sge_initial_value_lo; 3125 uint32_t chain_sge_initial_value_hi; 3126} sli4_sgl_chaining_params_t; 3127 3128typedef struct sli4_fip_event_s { 3129 uint32_t type; 3130 uint32_t index; /* FCF index or UINT32_MAX if invalid */ 3131} sli4_fip_event_t; 3132 3133typedef enum { 3134 SLI_RSRC_FCOE_VFI, 3135 SLI_RSRC_FCOE_VPI, 3136 SLI_RSRC_FCOE_RPI, 3137 SLI_RSRC_FCOE_XRI, 3138 SLI_RSRC_FCOE_FCFI, 3139 SLI_RSRC_MAX /* must be last */ 3140} sli4_resource_e; 3141 3142typedef enum { 3143 SLI4_PORT_TYPE_FC, 3144 SLI4_PORT_TYPE_NIC, 3145 SLI4_PORT_TYPE_MAX /* must be last */ 3146} sli4_port_type_e; 3147 3148typedef enum { 3149 SLI4_ASIC_TYPE_BE3 = 1, 3150 SLI4_ASIC_TYPE_SKYHAWK, 3151 SLI4_ASIC_TYPE_LANCER, 3152 SLI4_ASIC_TYPE_CORSAIR, 3153 SLI4_ASIC_TYPE_LANCERG6, 3154} sli4_asic_type_e; 3155 3156typedef enum { 3157 SLI4_ASIC_REV_FPGA = 1, 3158 SLI4_ASIC_REV_A0, 3159 SLI4_ASIC_REV_A1, 3160 SLI4_ASIC_REV_A2, 3161 SLI4_ASIC_REV_A3, 3162 SLI4_ASIC_REV_B0, 3163 SLI4_ASIC_REV_B1, 3164 SLI4_ASIC_REV_C0, 3165 SLI4_ASIC_REV_D0, 3166} sli4_asic_rev_e; 3167 3168typedef struct sli4_s { 3169 ocs_os_handle_t os; 3170 sli4_port_type_e port_type; 3171 3172 uint32_t sli_rev; /* SLI revision number */ 3173 uint32_t sli_family; 3174 uint32_t if_type; /* SLI Interface type */ 3175 3176 sli4_asic_type_e asic_type; /*<< ASIC type */ 3177 sli4_asic_rev_e asic_rev; /*<< ASIC revision */ 3178 uint32_t physical_port; 3179 3180 struct { 3181 uint16_t e_d_tov; 3182 uint16_t r_a_tov; 3183 uint16_t max_qcount[SLI_QTYPE_MAX]; 3184 uint32_t max_qentries[SLI_QTYPE_MAX]; 3185 uint16_t count_mask[SLI_QTYPE_MAX]; 3186 uint16_t count_method[SLI_QTYPE_MAX]; 3187 uint32_t qpage_count[SLI_QTYPE_MAX]; 3188 uint16_t link_module_type; 3189 uint8_t rq_batch; 3190 uint16_t rq_min_buf_size; 3191 uint32_t rq_max_buf_size; 3192 uint8_t topology; 3193 uint8_t wwpn[8]; 3194 uint8_t wwnn[8]; 3195 uint32_t fw_rev[2]; 3196 uint8_t fw_name[2][16]; 3197 char ipl_name[16]; 3198 uint32_t hw_rev[3]; 3199 uint8_t port_number; 3200 char port_name[2]; 3201 char bios_version_string[32]; 3202 uint8_t dual_ulp_capable; 3203 uint8_t is_ulp_fc[2]; 3204 /* 3205 * Tracks the port resources using extents metaphor. For 3206 * devices that don't implement extents (i.e. 3207 * has_extents == FALSE), the code models each resource as 3208 * a single large extent. 3209 */ 3210 struct { 3211 uint32_t number; /* number of extents */ 3212 uint32_t size; /* number of elements in each extent */ 3213 uint32_t n_alloc;/* number of elements allocated */ 3214 uint32_t *base; 3215 ocs_bitmap_t *use_map;/* bitmap showing resources in use */ 3216 uint32_t map_size;/* number of bits in bitmap */ 3217 } extent[SLI_RSRC_MAX]; 3218 sli4_features_t features; 3219 uint32_t has_extents:1, 3220 auto_reg:1, 3221 auto_xfer_rdy:1, 3222 hdr_template_req:1, 3223 perf_hint:1, 3224 perf_wq_id_association:1, 3225 cq_create_version:2, 3226 mq_create_version:2, 3227 high_login_mode:1, 3228 sgl_pre_registered:1, 3229 sgl_pre_registration_required:1, 3230 t10_dif_inline_capable:1, 3231 t10_dif_separate_capable:1; 3232 uint32_t sge_supported_length; 3233 uint32_t sgl_page_sizes; 3234 uint32_t max_sgl_pages; 3235 sli4_sgl_chaining_params_t sgl_chaining_params; 3236 size_t wqe_size; 3237 } config; 3238 3239 /* 3240 * Callback functions 3241 */ 3242 int32_t (*link)(void *, void *); 3243 void *link_arg; 3244 int32_t (*fip)(void *, void *); 3245 void *fip_arg; 3246 3247 ocs_dma_t bmbx; 3248#if defined(OCS_INCLUDE_DEBUG) 3249 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG 3250 * commands for BMBX dumping purposes */ 3251 ocs_dma_t *bmbx_non_emb_pmd; 3252#endif 3253 3254 struct { 3255 ocs_dma_t data; 3256 uint32_t length; 3257 } vpd; 3258} sli4_t; 3259 3260/** 3261 * Get / set parameter functions 3262 */ 3263static inline uint32_t 3264sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc) 3265{ 3266 if (rsrc >= SLI_RSRC_MAX) { 3267 return 0; 3268 } 3269 3270 return sli4->config.extent[rsrc].size; 3271} 3272 3273static inline uint32_t 3274sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype) 3275{ 3276 if (qtype >= SLI_QTYPE_MAX) { 3277 return 0; 3278 } 3279 return sli4->config.max_qcount[qtype]; 3280} 3281 3282static inline uint32_t 3283sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype) 3284{ 3285 3286 return sli4->config.max_qentries[qtype]; 3287} 3288 3289static inline uint32_t 3290sli_get_max_sge(sli4_t *sli4) 3291{ 3292 return sli4->config.sge_supported_length; 3293} 3294 3295static inline uint32_t 3296sli_get_max_sgl(sli4_t *sli4) 3297{ 3298 3299 if (sli4->config.sgl_page_sizes != 1) { 3300 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n", 3301 sli4->config.sgl_page_sizes); 3302 return 0; 3303 } 3304 3305 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t)); 3306} 3307 3308static inline sli4_link_medium_e 3309sli_get_medium(sli4_t *sli4) 3310{ 3311 switch (sli4->config.topology) { 3312 case SLI4_READ_CFG_TOPO_FCOE: 3313 return SLI_LINK_MEDIUM_ETHERNET; 3314 case SLI4_READ_CFG_TOPO_FC: 3315 case SLI4_READ_CFG_TOPO_FC_DA: 3316 case SLI4_READ_CFG_TOPO_FC_AL: 3317 return SLI_LINK_MEDIUM_FC; 3318 default: 3319 return SLI_LINK_MEDIUM_MAX; 3320 } 3321} 3322 3323static inline void 3324sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset) 3325{ 3326 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params; 3327 3328 3329 ocs_memset(sge, 0, sizeof(*sge)); 3330 sge->sge_type = SLI4_SGE_TYPE_CHAIN; 3331 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi; 3332 sge->buffer_address_low = 3333 (uint32_t)((cparms->chain_sge_initial_value_lo | 3334 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) << 3335 cparms->sgl_index_field_offset) | 3336 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) << 3337 cparms->frag_num_field_offset) | 3338 offset) >> 3); 3339} 3340 3341static inline uint32_t 3342sli_get_sli_rev(sli4_t *sli4) 3343{ 3344 return sli4->sli_rev; 3345} 3346 3347static inline uint32_t 3348sli_get_sli_family(sli4_t *sli4) 3349{ 3350 return sli4->sli_family; 3351} 3352 3353static inline uint32_t 3354sli_get_if_type(sli4_t *sli4) 3355{ 3356 return sli4->if_type; 3357} 3358 3359static inline void * 3360sli_get_wwn_port(sli4_t *sli4) 3361{ 3362 return sli4->config.wwpn; 3363} 3364 3365static inline void * 3366sli_get_wwn_node(sli4_t *sli4) 3367{ 3368 return sli4->config.wwnn; 3369} 3370 3371static inline void * 3372sli_get_vpd(sli4_t *sli4) 3373{ 3374 return sli4->vpd.data.virt; 3375} 3376 3377static inline uint32_t 3378sli_get_vpd_len(sli4_t *sli4) 3379{ 3380 return sli4->vpd.length; 3381} 3382 3383static inline uint32_t 3384sli_get_fw_revision(sli4_t *sli4, uint32_t which) 3385{ 3386 return sli4->config.fw_rev[which]; 3387} 3388 3389static inline void * 3390sli_get_fw_name(sli4_t *sli4, uint32_t which) 3391{ 3392 return sli4->config.fw_name[which]; 3393} 3394 3395static inline char * 3396sli_get_ipl_name(sli4_t *sli4) 3397{ 3398 return sli4->config.ipl_name; 3399} 3400 3401static inline uint32_t 3402sli_get_hw_revision(sli4_t *sli4, uint32_t which) 3403{ 3404 return sli4->config.hw_rev[which]; 3405} 3406 3407static inline uint32_t 3408sli_get_auto_xfer_rdy_capable(sli4_t *sli4) 3409{ 3410 return sli4->config.auto_xfer_rdy; 3411} 3412 3413static inline uint32_t 3414sli_get_dif_capable(sli4_t *sli4) 3415{ 3416 return sli4->config.features.flag.dif; 3417} 3418 3419static inline uint32_t 3420sli_is_dif_inline_capable(sli4_t *sli4) 3421{ 3422 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable; 3423} 3424 3425static inline uint32_t 3426sli_is_dif_separate_capable(sli4_t *sli4) 3427{ 3428 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable; 3429} 3430 3431static inline uint32_t 3432sli_get_is_dual_ulp_capable(sli4_t *sli4) 3433{ 3434 return sli4->config.dual_ulp_capable; 3435} 3436 3437static inline uint32_t 3438sli_get_is_sgl_chaining_capable(sli4_t *sli4) 3439{ 3440 return sli4->config.sgl_chaining_params.chaining_capable; 3441} 3442 3443static inline uint32_t 3444sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp) 3445{ 3446 return sli4->config.is_ulp_fc[ulp]; 3447} 3448 3449static inline uint32_t 3450sli_get_hlm_capable(sli4_t *sli4) 3451{ 3452 return sli4->config.features.flag.hlm; 3453} 3454 3455static inline int32_t 3456sli_set_hlm(sli4_t *sli4, uint32_t value) 3457{ 3458 if (value && !sli4->config.features.flag.hlm) { 3459 ocs_log_test(sli4->os, "HLM not supported\n"); 3460 return -1; 3461 } 3462 3463 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE; 3464 3465 return 0; 3466} 3467 3468static inline uint32_t 3469sli_get_hlm(sli4_t *sli4) 3470{ 3471 return sli4->config.high_login_mode; 3472} 3473 3474static inline uint32_t 3475sli_get_sgl_preregister_required(sli4_t *sli4) 3476{ 3477 return sli4->config.sgl_pre_registration_required; 3478} 3479 3480static inline uint32_t 3481sli_get_sgl_preregister(sli4_t *sli4) 3482{ 3483 return sli4->config.sgl_pre_registered; 3484} 3485 3486static inline int32_t 3487sli_set_sgl_preregister(sli4_t *sli4, uint32_t value) 3488{ 3489 if ((value == 0) && sli4->config.sgl_pre_registration_required) { 3490 ocs_log_test(sli4->os, "SGL pre-registration required\n"); 3491 return -1; 3492 } 3493 3494 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE; 3495 3496 return 0; 3497} 3498 3499static inline sli4_asic_type_e 3500sli_get_asic_type(sli4_t *sli4) 3501{ 3502 return sli4->asic_type; 3503} 3504 3505static inline sli4_asic_rev_e 3506sli_get_asic_rev(sli4_t *sli4) 3507{ 3508 return sli4->asic_rev; 3509} 3510 3511static inline int32_t 3512sli_set_topology(sli4_t *sli4, uint32_t value) 3513{ 3514 int32_t rc = 0; 3515 3516 switch (value) { 3517 case SLI4_READ_CFG_TOPO_FCOE: 3518 case SLI4_READ_CFG_TOPO_FC: 3519 case SLI4_READ_CFG_TOPO_FC_DA: 3520 case SLI4_READ_CFG_TOPO_FC_AL: 3521 sli4->config.topology = value; 3522 break; 3523 default: 3524 ocs_log_test(sli4->os, "unsupported topology %#x\n", value); 3525 rc = -1; 3526 } 3527 3528 return rc; 3529} 3530 3531static inline uint16_t 3532sli_get_link_module_type(sli4_t *sli4) 3533{ 3534 return sli4->config.link_module_type; 3535} 3536 3537static inline char * 3538sli_get_portnum(sli4_t *sli4) 3539{ 3540 return sli4->config.port_name; 3541} 3542 3543static inline char * 3544sli_get_bios_version_string(sli4_t *sli4) 3545{ 3546 return sli4->config.bios_version_string; 3547} 3548 3549static inline uint32_t 3550sli_convert_mask_to_count(uint32_t method, uint32_t mask) 3551{ 3552 uint32_t count = 0; 3553 3554 if (method) { 3555 count = 1 << ocs_lg2(mask); 3556 count *= 16; 3557 } else { 3558 count = mask; 3559 } 3560 3561 return count; 3562} 3563 3564/** 3565 * @brief Common Create Queue function prototype 3566 */ 3567typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 3568 3569/** 3570 * @brief Common Destroy Queue function prototype 3571 */ 3572typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t); 3573 3574 3575/**************************************************************************** 3576 * Function prototypes 3577 */ 3578extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t); 3579extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t); 3580extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t); 3581extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t); 3582extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t); 3583extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3584extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t); 3585extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters); 3586extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t); 3587extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 3588extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t); 3589extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t); 3590extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t); 3591extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 3592extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *); 3593extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t); 3594extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t); 3595typedef struct { 3596 uint16_t rq_id; 3597 uint8_t r_ctl_mask; 3598 uint8_t r_ctl_match; 3599 uint8_t type_mask; 3600 uint8_t type_match; 3601} sli4_cmd_rq_cfg_t; 3602extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t, 3603 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t); 3604extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *); 3605 3606extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t); 3607extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *); 3608extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t); 3609extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3610extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t); 3611extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t); 3612extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t); 3613extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t); 3614extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t); 3615extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t); 3616extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t); 3617extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t, 3618 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *); 3619extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *); 3620extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t, 3621 uint32_t, char *, ocs_dma_t *); 3622extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size, 3623 ocs_dma_t *cmd, 3624 ocs_dma_t *resp); 3625extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size, 3626 uint8_t query, uint8_t is_buffer_list, 3627 ocs_dma_t *buffer, uint8_t fdb); 3628extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*); 3629extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf, 3630 size_t size, uint32_t start_profile_index, ocs_dma_t *dma); 3631extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf, 3632 size_t size); 3633extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf, 3634 size_t size, 3635 uint32_t fd, 3636 uint32_t active_profile_id); 3637extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf, 3638 size_t size, ocs_dma_t *dma); 3639extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf, 3640 size_t size, ocs_dma_t *dma, 3641 uint32_t fd, uint32_t active_link_config_id); 3642extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf, 3643 size_t size); 3644extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf, 3645 size_t size, ocs_dma_t *dma); 3646extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf, 3647 size_t size, ocs_dma_t *dma, 3648 uint8_t profile_id, uint32_t descriptor_count, 3649 uint8_t isap); 3650 3651extern int32_t sli_cqe_mq(void *); 3652extern int32_t sli_cqe_async(sli4_t *, void *); 3653 3654extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e); 3655extern void sli_calc_max_qentries(sli4_t *sli4); 3656extern int32_t sli_init(sli4_t *); 3657extern int32_t sli_reset(sli4_t *); 3658extern int32_t sli_fw_reset(sli4_t *); 3659extern int32_t sli_teardown(sli4_t *); 3660extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *); 3661extern int32_t sli_bmbx_command(sli4_t *); 3662extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t); 3663extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *); 3664extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult); 3665extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t); 3666extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]); 3667extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t); 3668extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t); 3669extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *); 3670extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *); 3671extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t); 3672extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t); 3673extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3674extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3675extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *); 3676extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *); 3677extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3678extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3679extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *); 3680extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t); 3681extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e); 3682extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *); 3683extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 3684 3685extern int32_t sli_raise_ue(sli4_t *, uint8_t); 3686extern int32_t sli_dump_is_ready(sli4_t *); 3687extern int32_t sli_dump_is_present(sli4_t *); 3688extern int32_t sli_reset_required(sli4_t *); 3689extern int32_t sli_fw_error_status(sli4_t *); 3690extern int32_t sli_fw_ready(sli4_t *); 3691extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e); 3692extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t); 3693extern int32_t sli_link_is_configurable(sli4_t *); 3694 3695#include "ocs_fcp.h" 3696 3697/** 3698 * @brief Maximum value for a FCFI 3699 * 3700 * Note that although most commands provide a 16 bit field for the FCFI, 3701 * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for 3702 * the returned FCFI. Then effectively, the FCFI cannot be larger than 3703 * 1 << 6 or 64. 3704 */ 3705#define SLI4_MAX_FCFI 64 3706 3707/** 3708 * @brief Maximum value for FCF index 3709 * 3710 * The SLI-4 specification uses a 16 bit field in most places for the FCF 3711 * index, but practically, this value will be much smaller. Arbitrarily 3712 * limit the max FCF index to match the max FCFI value. 3713 */ 3714#define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI 3715 3716/************************************************************************* 3717 * SLI-4 FC/FCoE mailbox command formats and definitions. 3718 */ 3719 3720/** 3721 * FC/FCoE opcode (OPC) values. 3722 */ 3723#define SLI4_OPC_FCOE_WQ_CREATE 0x1 3724#define SLI4_OPC_FCOE_WQ_DESTROY 0x2 3725#define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3 3726#define SLI4_OPC_FCOE_RQ_CREATE 0x5 3727#define SLI4_OPC_FCOE_RQ_DESTROY 0x6 3728#define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8 3729#define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb 3730#define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10 3731 3732/* Use the default CQ associated with the WQ */ 3733#define SLI4_CQ_DEFAULT 0xffff 3734 3735typedef struct sli4_physical_page_descriptor_s { 3736 uint32_t low; 3737 uint32_t high; 3738} sli4_physical_page_descriptor_t; 3739 3740/** 3741 * @brief FCOE_WQ_CREATE 3742 * 3743 * Create a Work Queue for FC/FCoE use. 3744 */ 3745#define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4 3746 3747typedef struct sli4_req_fcoe_wq_create_s { 3748 sli4_req_hdr_t hdr; 3749#if BYTE_ORDER == LITTLE_ENDIAN 3750 uint32_t num_pages:8, 3751 dua:1, 3752 :7, 3753 cq_id:16; 3754 sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES]; 3755 uint32_t bqu:1, 3756 :7, 3757 ulp:8, 3758 :16; 3759#else 3760#error big endian version not defined 3761#endif 3762} sli4_req_fcoe_wq_create_t; 3763 3764/** 3765 * @brief FCOE_WQ_CREATE_V1 3766 * 3767 * Create a version 1 Work Queue for FC/FCoE use. 3768 */ 3769typedef struct sli4_req_fcoe_wq_create_v1_s { 3770 sli4_req_hdr_t hdr; 3771#if BYTE_ORDER == LITTLE_ENDIAN 3772 uint32_t num_pages:16, 3773 cq_id:16; 3774 uint32_t page_size:8, 3775 wqe_size:4, 3776 :4, 3777 wqe_count:16; 3778 uint32_t rsvd6; 3779 sli4_physical_page_descriptor_t page_physical_address[8]; 3780#else 3781#error big endian version not defined 3782#endif 3783} sli4_req_fcoe_wq_create_v1_t; 3784 3785#define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8 3786 3787/** 3788 * @brief FCOE_WQ_DESTROY 3789 * 3790 * Destroy an FC/FCoE Work Queue. 3791 */ 3792typedef struct sli4_req_fcoe_wq_destroy_s { 3793 sli4_req_hdr_t hdr; 3794#if BYTE_ORDER == LITTLE_ENDIAN 3795 uint32_t wq_id:16, 3796 :16; 3797#else 3798#error big endian version not defined 3799#endif 3800} sli4_req_fcoe_wq_destroy_t; 3801 3802/** 3803 * @brief FCOE_POST_SGL_PAGES 3804 * 3805 * Register the scatter gather list (SGL) memory and associate it with an XRI. 3806 */ 3807typedef struct sli4_req_fcoe_post_sgl_pages_s { 3808 sli4_req_hdr_t hdr; 3809#if BYTE_ORDER == LITTLE_ENDIAN 3810 uint32_t xri_start:16, 3811 xri_count:16; 3812 struct { 3813 uint32_t page0_low; 3814 uint32_t page0_high; 3815 uint32_t page1_low; 3816 uint32_t page1_high; 3817 } page_set[10]; 3818#else 3819#error big endian version not defined 3820#endif 3821} sli4_req_fcoe_post_sgl_pages_t; 3822 3823/** 3824 * @brief FCOE_RQ_CREATE 3825 * 3826 * Create a Receive Queue for FC/FCoE use. 3827 */ 3828typedef struct sli4_req_fcoe_rq_create_s { 3829 sli4_req_hdr_t hdr; 3830#if BYTE_ORDER == LITTLE_ENDIAN 3831 uint32_t num_pages:16, 3832 dua:1, 3833 bqu:1, 3834 :6, 3835 ulp:8; 3836 uint32_t :16, 3837 rqe_count:4, 3838 :12; 3839 uint32_t rsvd6; 3840 uint32_t buffer_size:16, 3841 cq_id:16; 3842 uint32_t rsvd8; 3843 sli4_physical_page_descriptor_t page_physical_address[8]; 3844#else 3845#error big endian version not defined 3846#endif 3847} sli4_req_fcoe_rq_create_t; 3848 3849#define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8 3850#define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128 3851#define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048 3852 3853/** 3854 * @brief FCOE_RQ_CREATE_V1 3855 * 3856 * Create a version 1 Receive Queue for FC/FCoE use. 3857 */ 3858typedef struct sli4_req_fcoe_rq_create_v1_s { 3859 sli4_req_hdr_t hdr; 3860#if BYTE_ORDER == LITTLE_ENDIAN 3861 uint32_t num_pages:16, 3862 :13, 3863 dim:1, 3864 dfd:1, 3865 dnb:1; 3866 uint32_t page_size:8, 3867 rqe_size:4, 3868 :4, 3869 rqe_count:16; 3870 uint32_t rsvd6; 3871 uint32_t :16, 3872 cq_id:16; 3873 uint32_t buffer_size; 3874 sli4_physical_page_descriptor_t page_physical_address[8]; 3875#else 3876#error big endian version not defined 3877#endif 3878} sli4_req_fcoe_rq_create_v1_t; 3879 3880 3881/** 3882 * @brief FCOE_RQ_CREATE_V2 3883 * 3884 * Create a version 2 Receive Queue for FC/FCoE use. 3885 */ 3886typedef struct sli4_req_fcoe_rq_create_v2_s { 3887 sli4_req_hdr_t hdr; 3888#if BYTE_ORDER == LITTLE_ENDIAN 3889 uint32_t num_pages:16, 3890 rq_count:8, 3891 :5, 3892 dim:1, 3893 dfd:1, 3894 dnb:1; 3895 uint32_t page_size:8, 3896 rqe_size:4, 3897 :4, 3898 rqe_count:16; 3899 uint32_t hdr_buffer_size:16, 3900 payload_buffer_size:16; 3901 uint32_t base_cq_id:16, 3902 :16; 3903 uint32_t rsvd; 3904 sli4_physical_page_descriptor_t page_physical_address[0]; 3905#else 3906#error big endian version not defined 3907#endif 3908} sli4_req_fcoe_rq_create_v2_t; 3909 3910 3911#define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8 3912#define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64 3913#define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048 3914 3915#define SLI4_FCOE_RQE_SIZE_8 0x2 3916#define SLI4_FCOE_RQE_SIZE_16 0x3 3917#define SLI4_FCOE_RQE_SIZE_32 0x4 3918#define SLI4_FCOE_RQE_SIZE_64 0x5 3919#define SLI4_FCOE_RQE_SIZE_128 0x6 3920 3921#define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1 3922#define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2 3923#define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4 3924#define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8 3925#define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10 3926 3927#define SLI4_FCOE_RQE_SIZE 8 3928 3929/** 3930 * @brief FCOE_RQ_DESTROY 3931 * 3932 * Destroy an FC/FCoE Receive Queue. 3933 */ 3934typedef struct sli4_req_fcoe_rq_destroy_s { 3935 sli4_req_hdr_t hdr; 3936#if BYTE_ORDER == LITTLE_ENDIAN 3937 uint32_t rq_id:16, 3938 :16; 3939#else 3940#error big endian version not defined 3941#endif 3942} sli4_req_fcoe_rq_destroy_t; 3943 3944/** 3945 * @brief FCOE_READ_FCF_TABLE 3946 * 3947 * Retrieve a FCF database (also known as a table) entry created by the SLI Port 3948 * during FIP discovery. 3949 */ 3950typedef struct sli4_req_fcoe_read_fcf_table_s { 3951 sli4_req_hdr_t hdr; 3952#if BYTE_ORDER == LITTLE_ENDIAN 3953 uint32_t fcf_index:16, 3954 :16; 3955#else 3956#error big endian version not defined 3957#endif 3958} sli4_req_fcoe_read_fcf_table_t; 3959 3960/* A FCF index of -1 on the request means return the first valid entry */ 3961#define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX) 3962 3963/** 3964 * @brief FCF table entry 3965 * 3966 * This is the information returned by the FCOE_READ_FCF_TABLE command. 3967 */ 3968typedef struct sli4_fcf_entry_s { 3969#if BYTE_ORDER == LITTLE_ENDIAN 3970 uint32_t max_receive_size; 3971 uint32_t fip_keep_alive; 3972 uint32_t fip_priority; 3973 uint8_t fcf_mac_address[6]; 3974 uint8_t fcf_available; 3975 uint8_t mac_address_provider; 3976 uint8_t fabric_name_id[8]; 3977 uint8_t fc_map[3]; 3978 uint8_t val:1, 3979 fc:1, 3980 :5, 3981 sol:1; 3982 uint32_t fcf_index:16, 3983 fcf_state:16; 3984 uint8_t vlan_bitmap[512]; 3985 uint8_t switch_name[8]; 3986#else 3987#error big endian version not defined 3988#endif 3989} sli4_fcf_entry_t; 3990 3991/** 3992 * @brief FCOE_READ_FCF_TABLE response. 3993 */ 3994typedef struct sli4_res_fcoe_read_fcf_table_s { 3995 sli4_res_hdr_t hdr; 3996#if BYTE_ORDER == LITTLE_ENDIAN 3997 uint32_t event_tag; 3998 uint32_t next_index:16, 3999 :16; 4000 sli4_fcf_entry_t fcf_entry; 4001#else 4002#error big endian version not defined 4003#endif 4004} sli4_res_fcoe_read_fcf_table_t; 4005 4006/* A next FCF index of -1 in the response means this is the last valid entry */ 4007#define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX) 4008 4009 4010/** 4011 * @brief FCOE_POST_HDR_TEMPLATES 4012 */ 4013typedef struct sli4_req_fcoe_post_hdr_templates_s { 4014 sli4_req_hdr_t hdr; 4015#if BYTE_ORDER == LITTLE_ENDIAN 4016 uint32_t rpi_offset:16, 4017 page_count:16; 4018 sli4_physical_page_descriptor_t page_descriptor[0]; 4019#else 4020#error big endian version not defined 4021#endif 4022} sli4_req_fcoe_post_hdr_templates_t; 4023 4024#define SLI4_FCOE_HDR_TEMPLATE_SIZE 64 4025 4026/** 4027 * @brief FCOE_REDISCOVER_FCF 4028 */ 4029typedef struct sli4_req_fcoe_rediscover_fcf_s { 4030 sli4_req_hdr_t hdr; 4031#if BYTE_ORDER == LITTLE_ENDIAN 4032 uint32_t fcf_count:16, 4033 :16; 4034 uint32_t rsvd5; 4035 uint16_t fcf_index[16]; 4036#else 4037#error big endian version not defined 4038#endif 4039} sli4_req_fcoe_rediscover_fcf_t; 4040 4041 4042/** 4043 * Work Queue Entry (WQE) types. 4044 */ 4045#define SLI4_WQE_ABORT 0x0f 4046#define SLI4_WQE_ELS_REQUEST64 0x8a 4047#define SLI4_WQE_FCP_IBIDIR64 0xac 4048#define SLI4_WQE_FCP_IREAD64 0x9a 4049#define SLI4_WQE_FCP_IWRITE64 0x98 4050#define SLI4_WQE_FCP_ICMND64 0x9c 4051#define SLI4_WQE_FCP_TRECEIVE64 0xa1 4052#define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5 4053#define SLI4_WQE_FCP_TRSP64 0xa3 4054#define SLI4_WQE_FCP_TSEND64 0x9f 4055#define SLI4_WQE_GEN_REQUEST64 0xc2 4056#define SLI4_WQE_SEND_FRAME 0xe1 4057#define SLI4_WQE_XMIT_BCAST64 0X84 4058#define SLI4_WQE_XMIT_BLS_RSP 0x97 4059#define SLI4_WQE_ELS_RSP64 0x95 4060#define SLI4_WQE_XMIT_SEQUENCE64 0x82 4061#define SLI4_WQE_REQUEUE_XRI 0x93 4062 4063/** 4064 * WQE command types. 4065 */ 4066#define SLI4_CMD_FCP_IREAD64_WQE 0x00 4067#define SLI4_CMD_FCP_ICMND64_WQE 0x00 4068#define SLI4_CMD_FCP_IWRITE64_WQE 0x01 4069#define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02 4070#define SLI4_CMD_FCP_TRSP64_WQE 0x03 4071#define SLI4_CMD_FCP_TSEND64_WQE 0x07 4072#define SLI4_CMD_GEN_REQUEST64_WQE 0x08 4073#define SLI4_CMD_XMIT_BCAST64_WQE 0x08 4074#define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08 4075#define SLI4_CMD_ABORT_WQE 0x08 4076#define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08 4077#define SLI4_CMD_REQUEUE_XRI_WQE 0x0A 4078#define SLI4_CMD_SEND_FRAME_WQE 0x0a 4079 4080#define SLI4_WQE_SIZE 0x05 4081#define SLI4_WQE_EXT_SIZE 0x06 4082 4083#define SLI4_WQE_BYTES (16 * sizeof(uint32_t)) 4084#define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t)) 4085 4086/* Mask for ccp (CS_CTL) */ 4087#define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */ 4088 4089/** 4090 * @brief Generic WQE 4091 */ 4092typedef struct sli4_generic_wqe_s { 4093#if BYTE_ORDER == LITTLE_ENDIAN 4094 uint32_t cmd_spec0_5[6]; 4095 uint32_t xri_tag:16, 4096 context_tag:16; 4097 uint32_t :2, 4098 ct:2, 4099 :4, 4100 command:8, 4101 class:3, 4102 :1, 4103 pu:2, 4104 :2, 4105 timer:8; 4106 uint32_t abort_tag; 4107 uint32_t request_tag:16, 4108 :16; 4109 uint32_t ebde_cnt:4, 4110 :3, 4111 len_loc:2, 4112 qosd:1, 4113 :1, 4114 xbl:1, 4115 hlm:1, 4116 iod:1, 4117 dbde:1, 4118 wqes:1, 4119 pri:3, 4120 pv:1, 4121 eat:1, 4122 xc:1, 4123 :1, 4124 ccpe:1, 4125 ccp:8; 4126 uint32_t cmd_type:4, 4127 :3, 4128 wqec:1, 4129 :8, 4130 cq_id:16; 4131#else 4132#error big endian version not defined 4133#endif 4134} sli4_generic_wqe_t; 4135 4136/** 4137 * @brief WQE used to abort exchanges. 4138 */ 4139typedef struct sli4_abort_wqe_s { 4140#if BYTE_ORDER == LITTLE_ENDIAN 4141 uint32_t rsvd0; 4142 uint32_t rsvd1; 4143 uint32_t ext_t_tag; 4144 uint32_t ia:1, 4145 ir:1, 4146 :6, 4147 criteria:8, 4148 :16; 4149 uint32_t ext_t_mask; 4150 uint32_t t_mask; 4151 uint32_t xri_tag:16, 4152 context_tag:16; 4153 uint32_t :2, 4154 ct:2, 4155 :4, 4156 command:8, 4157 class:3, 4158 :1, 4159 pu:2, 4160 :2, 4161 timer:8; 4162 uint32_t t_tag; 4163 uint32_t request_tag:16, 4164 :16; 4165 uint32_t ebde_cnt:4, 4166 :3, 4167 len_loc:2, 4168 qosd:1, 4169 :1, 4170 xbl:1, 4171 :1, 4172 iod:1, 4173 dbde:1, 4174 wqes:1, 4175 pri:3, 4176 pv:1, 4177 eat:1, 4178 xc:1, 4179 :1, 4180 ccpe:1, 4181 ccp:8; 4182 uint32_t cmd_type:4, 4183 :3, 4184 wqec:1, 4185 :8, 4186 cq_id:16; 4187#else 4188#error big endian version not defined 4189#endif 4190} sli4_abort_wqe_t; 4191 4192#define SLI4_ABORT_CRITERIA_XRI_TAG 0x01 4193#define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02 4194#define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03 4195#define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04 4196 4197typedef enum { 4198 SLI_ABORT_XRI, 4199 SLI_ABORT_ABORT_ID, 4200 SLI_ABORT_REQUEST_ID, 4201 SLI_ABORT_MAX, /* must be last */ 4202} sli4_abort_type_e; 4203 4204/** 4205 * @brief WQE used to create an ELS request. 4206 */ 4207typedef struct sli4_els_request64_wqe_s { 4208 sli4_bde_t els_request_payload; 4209#if BYTE_ORDER == LITTLE_ENDIAN 4210 uint32_t els_request_payload_length; 4211 uint32_t sid:24, 4212 sp:1, 4213 :7; 4214 uint32_t remote_id:24, 4215 :8; 4216 uint32_t xri_tag:16, 4217 context_tag:16; 4218 uint32_t :2, 4219 ct:2, 4220 :4, 4221 command:8, 4222 class:3, 4223 ar:1, 4224 pu:2, 4225 :2, 4226 timer:8; 4227 uint32_t abort_tag; 4228 uint32_t request_tag:16, 4229 temporary_rpi:16; 4230 uint32_t ebde_cnt:4, 4231 :3, 4232 len_loc:2, 4233 qosd:1, 4234 :1, 4235 xbl:1, 4236 hlm:1, 4237 iod:1, 4238 dbde:1, 4239 wqes:1, 4240 pri:3, 4241 pv:1, 4242 eat:1, 4243 xc:1, 4244 :1, 4245 ccpe:1, 4246 ccp:8; 4247 uint32_t cmd_type:4, 4248 els_id:3, 4249 wqec:1, 4250 :8, 4251 cq_id:16; 4252 sli4_bde_t els_response_payload_bde; 4253 uint32_t max_response_payload_length; 4254#else 4255#error big endian version not defined 4256#endif 4257} sli4_els_request64_wqe_t; 4258 4259#define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0 4260#define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1 4261#define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2 4262#define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3 4263 4264#define SLI4_ELS_REQUEST64_CLASS_2 0x1 4265#define SLI4_ELS_REQUEST64_CLASS_3 0x2 4266 4267#define SLI4_ELS_REQUEST64_DIR_WRITE 0x0 4268#define SLI4_ELS_REQUEST64_DIR_READ 0x1 4269 4270#define SLI4_ELS_REQUEST64_OTHER 0x0 4271#define SLI4_ELS_REQUEST64_LOGO 0x1 4272#define SLI4_ELS_REQUEST64_FDISC 0x2 4273#define SLI4_ELS_REQUEST64_FLOGIN 0x3 4274#define SLI4_ELS_REQUEST64_PLOGI 0x4 4275 4276#define SLI4_ELS_REQUEST64_CMD_GEN 0x08 4277#define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c 4278#define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d 4279 4280/** 4281 * @brief WQE used to create an FCP initiator no data command. 4282 */ 4283typedef struct sli4_fcp_icmnd64_wqe_s { 4284 sli4_bde_t bde; 4285#if BYTE_ORDER == LITTLE_ENDIAN 4286 uint32_t payload_offset_length:16, 4287 fcp_cmd_buffer_length:16; 4288 uint32_t rsvd4; 4289 uint32_t remote_n_port_id:24, 4290 :8; 4291 uint32_t xri_tag:16, 4292 context_tag:16; 4293 uint32_t dif:2, 4294 ct:2, 4295 bs:3, 4296 :1, 4297 command:8, 4298 class:3, 4299 :1, 4300 pu:2, 4301 erp:1, 4302 lnk:1, 4303 timer:8; 4304 uint32_t abort_tag; 4305 uint32_t request_tag:16, 4306 :16; 4307 uint32_t ebde_cnt:4, 4308 :3, 4309 len_loc:2, 4310 qosd:1, 4311 :1, 4312 xbl:1, 4313 hlm:1, 4314 iod:1, 4315 dbde:1, 4316 wqes:1, 4317 pri:3, 4318 pv:1, 4319 eat:1, 4320 xc:1, 4321 :1, 4322 ccpe:1, 4323 ccp:8; 4324 uint32_t cmd_type:4, 4325 :3, 4326 wqec:1, 4327 :8, 4328 cq_id:16; 4329 uint32_t rsvd12; 4330 uint32_t rsvd13; 4331 uint32_t rsvd14; 4332 uint32_t rsvd15; 4333#else 4334#error big endian version not defined 4335#endif 4336} sli4_fcp_icmnd64_wqe_t; 4337 4338/** 4339 * @brief WQE used to create an FCP initiator read. 4340 */ 4341typedef struct sli4_fcp_iread64_wqe_s { 4342 sli4_bde_t bde; 4343#if BYTE_ORDER == LITTLE_ENDIAN 4344 uint32_t payload_offset_length:16, 4345 fcp_cmd_buffer_length:16; 4346 uint32_t total_transfer_length; 4347 uint32_t remote_n_port_id:24, 4348 :8; 4349 uint32_t xri_tag:16, 4350 context_tag:16; 4351 uint32_t dif:2, 4352 ct:2, 4353 bs:3, 4354 :1, 4355 command:8, 4356 class:3, 4357 :1, 4358 pu:2, 4359 erp:1, 4360 lnk:1, 4361 timer:8; 4362 uint32_t abort_tag; 4363 uint32_t request_tag:16, 4364 :16; 4365 uint32_t ebde_cnt:4, 4366 :3, 4367 len_loc:2, 4368 qosd:1, 4369 :1, 4370 xbl:1, 4371 hlm:1, 4372 iod:1, 4373 dbde:1, 4374 wqes:1, 4375 pri:3, 4376 pv:1, 4377 eat:1, 4378 xc:1, 4379 :1, 4380 ccpe:1, 4381 ccp:8; 4382 uint32_t cmd_type:4, 4383 :3, 4384 wqec:1, 4385 :8, 4386 cq_id:16; 4387 uint32_t rsvd12; 4388#else 4389#error big endian version not defined 4390#endif 4391 sli4_bde_t first_data_bde; /* reserved if performance hints disabled */ 4392} sli4_fcp_iread64_wqe_t; 4393 4394/** 4395 * @brief WQE used to create an FCP initiator write. 4396 */ 4397typedef struct sli4_fcp_iwrite64_wqe_s { 4398 sli4_bde_t bde; 4399#if BYTE_ORDER == LITTLE_ENDIAN 4400 uint32_t payload_offset_length:16, 4401 fcp_cmd_buffer_length:16; 4402 uint32_t total_transfer_length; 4403 uint32_t initial_transfer_length; 4404 uint32_t xri_tag:16, 4405 context_tag:16; 4406 uint32_t dif:2, 4407 ct:2, 4408 bs:3, 4409 :1, 4410 command:8, 4411 class:3, 4412 :1, 4413 pu:2, 4414 erp:1, 4415 lnk:1, 4416 timer:8; 4417 uint32_t abort_tag; 4418 uint32_t request_tag:16, 4419 :16; 4420 uint32_t ebde_cnt:4, 4421 :3, 4422 len_loc:2, 4423 qosd:1, 4424 :1, 4425 xbl:1, 4426 hlm:1, 4427 iod:1, 4428 dbde:1, 4429 wqes:1, 4430 pri:3, 4431 pv:1, 4432 eat:1, 4433 xc:1, 4434 :1, 4435 ccpe:1, 4436 ccp:8; 4437 uint32_t cmd_type:4, 4438 :3, 4439 wqec:1, 4440 :8, 4441 cq_id:16; 4442 uint32_t remote_n_port_id:24, 4443 :8; 4444#else 4445#error big endian version not defined 4446#endif 4447 sli4_bde_t first_data_bde; 4448} sli4_fcp_iwrite64_wqe_t; 4449 4450 4451typedef struct sli4_fcp_128byte_wqe_s { 4452 uint32_t dw[32]; 4453} sli4_fcp_128byte_wqe_t; 4454 4455/** 4456 * @brief WQE used to create an FCP target receive, and FCP target 4457 * receive continue. 4458 */ 4459typedef struct sli4_fcp_treceive64_wqe_s { 4460 sli4_bde_t bde; 4461#if BYTE_ORDER == LITTLE_ENDIAN 4462 uint32_t payload_offset_length; 4463 uint32_t relative_offset; 4464 /** 4465 * DWord 5 can either be the task retry identifier (HLM=0) or 4466 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk 4467 * T10-PI workaround, the secondary xri tag 4468 */ 4469 union { 4470 uint32_t sec_xri_tag:16, 4471 :16; 4472 uint32_t dword; 4473 } dword5; 4474 uint32_t xri_tag:16, 4475 context_tag:16; 4476 uint32_t dif:2, 4477 ct:2, 4478 bs:3, 4479 :1, 4480 command:8, 4481 class:3, 4482 ar:1, 4483 pu:2, 4484 conf:1, 4485 lnk:1, 4486 timer:8; 4487 uint32_t abort_tag; 4488 uint32_t request_tag:16, 4489 remote_xid:16; 4490 uint32_t ebde_cnt:4, 4491 :1, 4492 app_id_valid:1, 4493 :1, 4494 len_loc:2, 4495 qosd:1, 4496 wchn:1, 4497 xbl:1, 4498 hlm:1, 4499 iod:1, 4500 dbde:1, 4501 wqes:1, 4502 pri:3, 4503 pv:1, 4504 eat:1, 4505 xc:1, 4506 sr:1, 4507 ccpe:1, 4508 ccp:8; 4509 uint32_t cmd_type:4, 4510 :3, 4511 wqec:1, 4512 :8, 4513 cq_id:16; 4514 uint32_t fcp_data_receive_length; 4515 4516#else 4517#error big endian version not defined 4518#endif 4519 sli4_bde_t first_data_bde; /* For performance hints */ 4520 4521} sli4_fcp_treceive64_wqe_t; 4522 4523/** 4524 * @brief WQE used to create an FCP target response. 4525 */ 4526typedef struct sli4_fcp_trsp64_wqe_s { 4527 sli4_bde_t bde; 4528#if BYTE_ORDER == LITTLE_ENDIAN 4529 uint32_t fcp_response_length; 4530 uint32_t rsvd4; 4531 /** 4532 * DWord 5 can either be the task retry identifier (HLM=0) or 4533 * the remote N_Port ID (HLM=1) 4534 */ 4535 uint32_t dword5; 4536 uint32_t xri_tag:16, 4537 rpi:16; 4538 uint32_t :2, 4539 ct:2, 4540 dnrx:1, 4541 :3, 4542 command:8, 4543 class:3, 4544 ag:1, 4545 pu:2, 4546 conf:1, 4547 lnk:1, 4548 timer:8; 4549 uint32_t abort_tag; 4550 uint32_t request_tag:16, 4551 remote_xid:16; 4552 uint32_t ebde_cnt:4, 4553 :1, 4554 app_id_valid:1, 4555 :1, 4556 len_loc:2, 4557 qosd:1, 4558 wchn:1, 4559 xbl:1, 4560 hlm:1, 4561 iod:1, 4562 dbde:1, 4563 wqes:1, 4564 pri:3, 4565 pv:1, 4566 eat:1, 4567 xc:1, 4568 sr:1, 4569 ccpe:1, 4570 ccp:8; 4571 uint32_t cmd_type:4, 4572 :3, 4573 wqec:1, 4574 :8, 4575 cq_id:16; 4576 uint32_t rsvd12; 4577 uint32_t rsvd13; 4578 uint32_t rsvd14; 4579 uint32_t rsvd15; 4580#else 4581#error big endian version not defined 4582#endif 4583} sli4_fcp_trsp64_wqe_t; 4584 4585/** 4586 * @brief WQE used to create an FCP target send (DATA IN). 4587 */ 4588typedef struct sli4_fcp_tsend64_wqe_s { 4589 sli4_bde_t bde; 4590#if BYTE_ORDER == LITTLE_ENDIAN 4591 uint32_t payload_offset_length; 4592 uint32_t relative_offset; 4593 /** 4594 * DWord 5 can either be the task retry identifier (HLM=0) or 4595 * the remote N_Port ID (HLM=1) 4596 */ 4597 uint32_t dword5; 4598 uint32_t xri_tag:16, 4599 rpi:16; 4600 uint32_t dif:2, 4601 ct:2, 4602 bs:3, 4603 :1, 4604 command:8, 4605 class:3, 4606 ar:1, 4607 pu:2, 4608 conf:1, 4609 lnk:1, 4610 timer:8; 4611 uint32_t abort_tag; 4612 uint32_t request_tag:16, 4613 remote_xid:16; 4614 uint32_t ebde_cnt:4, 4615 :1, 4616 app_id_valid:1, 4617 :1, 4618 len_loc:2, 4619 qosd:1, 4620 wchn:1, 4621 xbl:1, 4622 hlm:1, 4623 iod:1, 4624 dbde:1, 4625 wqes:1, 4626 pri:3, 4627 pv:1, 4628 eat:1, 4629 xc:1, 4630 sr:1, 4631 ccpe:1, 4632 ccp:8; 4633 uint32_t cmd_type:4, 4634 :3, 4635 wqec:1, 4636 :8, 4637 cq_id:16; 4638 uint32_t fcp_data_transmit_length; 4639 4640#else 4641#error big endian version not defined 4642#endif 4643 sli4_bde_t first_data_bde; /* For performance hints */ 4644} sli4_fcp_tsend64_wqe_t; 4645 4646#define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */ 4647#define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */ 4648#define SLI4_IO_NO_ABORT BIT(2) 4649#define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */ 4650 4651/* WQE DIF field contents */ 4652#define SLI4_DIF_DISABLED 0 4653#define SLI4_DIF_PASS_THROUGH 1 4654#define SLI4_DIF_STRIP 2 4655#define SLI4_DIF_INSERT 3 4656 4657/** 4658 * @brief WQE used to create a general request. 4659 */ 4660typedef struct sli4_gen_request64_wqe_s { 4661 sli4_bde_t bde; 4662#if BYTE_ORDER == LITTLE_ENDIAN 4663 uint32_t request_payload_length; 4664 uint32_t relative_offset; 4665 uint32_t :8, 4666 df_ctl:8, 4667 type:8, 4668 r_ctl:8; 4669 uint32_t xri_tag:16, 4670 context_tag:16; 4671 uint32_t :2, 4672 ct:2, 4673 :4, 4674 command:8, 4675 class:3, 4676 :1, 4677 pu:2, 4678 :2, 4679 timer:8; 4680 uint32_t abort_tag; 4681 uint32_t request_tag:16, 4682 :16; 4683 uint32_t ebde_cnt:4, 4684 :3, 4685 len_loc:2, 4686 qosd:1, 4687 :1, 4688 xbl:1, 4689 hlm:1, 4690 iod:1, 4691 dbde:1, 4692 wqes:1, 4693 pri:3, 4694 pv:1, 4695 eat:1, 4696 xc:1, 4697 :1, 4698 ccpe:1, 4699 ccp:8; 4700 uint32_t cmd_type:4, 4701 :3, 4702 wqec:1, 4703 :8, 4704 cq_id:16; 4705 uint32_t remote_n_port_id:24, 4706 :8; 4707 uint32_t rsvd13; 4708 uint32_t rsvd14; 4709 uint32_t max_response_payload_length; 4710#else 4711#error big endian version not defined 4712#endif 4713} sli4_gen_request64_wqe_t; 4714 4715/** 4716 * @brief WQE used to create a send frame request. 4717 */ 4718typedef struct sli4_send_frame_wqe_s { 4719 sli4_bde_t bde; 4720#if BYTE_ORDER == LITTLE_ENDIAN 4721 uint32_t frame_length; 4722 uint32_t fc_header_0_1[2]; 4723 uint32_t xri_tag:16, 4724 context_tag:16; 4725 uint32_t :2, 4726 ct:2, 4727 :4, 4728 command:8, 4729 class:3, 4730 :1, 4731 pu:2, 4732 :2, 4733 timer:8; 4734 uint32_t abort_tag; 4735 uint32_t request_tag:16, 4736 eof:8, 4737 sof:8; 4738 uint32_t ebde_cnt:4, 4739 :3, 4740 lenloc:2, 4741 qosd:1, 4742 wchn:1, 4743 xbl:1, 4744 hlm:1, 4745 iod:1, 4746 dbde:1, 4747 wqes:1, 4748 pri:3, 4749 pv:1, 4750 eat:1, 4751 xc:1, 4752 :1, 4753 ccpe:1, 4754 ccp:8; 4755 uint32_t cmd_type:4, 4756 :3, 4757 wqec:1, 4758 :8, 4759 cq_id:16; 4760 uint32_t fc_header_2_5[4]; 4761#else 4762#error big endian version not defined 4763#endif 4764} sli4_send_frame_wqe_t; 4765 4766/** 4767 * @brief WQE used to create a transmit sequence. 4768 */ 4769typedef struct sli4_xmit_sequence64_wqe_s { 4770 sli4_bde_t bde; 4771#if BYTE_ORDER == LITTLE_ENDIAN 4772 uint32_t remote_n_port_id:24, 4773 :8; 4774 uint32_t relative_offset; 4775 uint32_t :2, 4776 si:1, 4777 ft:1, 4778 :2, 4779 xo:1, 4780 ls:1, 4781 df_ctl:8, 4782 type:8, 4783 r_ctl:8; 4784 uint32_t xri_tag:16, 4785 context_tag:16; 4786 uint32_t dif:2, 4787 ct:2, 4788 bs:3, 4789 :1, 4790 command:8, 4791 class:3, 4792 :1, 4793 pu:2, 4794 :2, 4795 timer:8; 4796 uint32_t abort_tag; 4797 uint32_t request_tag:16, 4798 remote_xid:16; 4799 uint32_t ebde_cnt:4, 4800 :3, 4801 len_loc:2, 4802 qosd:1, 4803 :1, 4804 xbl:1, 4805 hlm:1, 4806 iod:1, 4807 dbde:1, 4808 wqes:1, 4809 pri:3, 4810 pv:1, 4811 eat:1, 4812 xc:1, 4813 sr:1, 4814 ccpe:1, 4815 ccp:8; 4816 uint32_t cmd_type:4, 4817 :3, 4818 wqec:1, 4819 :8, 4820 cq_id:16; 4821 uint32_t sequence_payload_len; 4822 uint32_t rsvd13; 4823 uint32_t rsvd14; 4824 uint32_t rsvd15; 4825#else 4826#error big endian version not defined 4827#endif 4828} sli4_xmit_sequence64_wqe_t; 4829 4830/** 4831 * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool. 4832 */ 4833typedef struct sli4_requeue_xri_wqe_s { 4834 uint32_t rsvd0; 4835 uint32_t rsvd1; 4836 uint32_t rsvd2; 4837 uint32_t rsvd3; 4838 uint32_t rsvd4; 4839 uint32_t rsvd5; 4840#if BYTE_ORDER == LITTLE_ENDIAN 4841 uint32_t xri_tag:16, 4842 context_tag:16; 4843 uint32_t :2, 4844 ct:2, 4845 :4, 4846 command:8, 4847 class:3, 4848 :1, 4849 pu:2, 4850 :2, 4851 timer:8; 4852 uint32_t rsvd8; 4853 uint32_t request_tag:16, 4854 :16; 4855 uint32_t ebde_cnt:4, 4856 :3, 4857 len_loc:2, 4858 qosd:1, 4859 wchn:1, 4860 xbl:1, 4861 hlm:1, 4862 iod:1, 4863 dbde:1, 4864 wqes:1, 4865 pri:3, 4866 pv:1, 4867 eat:1, 4868 xc:1, 4869 :1, 4870 ccpe:1, 4871 ccp:8; 4872 uint32_t cmd_type:4, 4873 :3, 4874 wqec:1, 4875 :8, 4876 cq_id:16; 4877 uint32_t rsvd12; 4878 uint32_t rsvd13; 4879 uint32_t rsvd14; 4880 uint32_t rsvd15; 4881#else 4882#error big endian version not defined 4883#endif 4884} sli4_requeue_xri_wqe_t; 4885 4886/** 4887 * @brief WQE used to send a single frame sequence to broadcast address 4888 */ 4889typedef struct sli4_xmit_bcast64_wqe_s { 4890 sli4_bde_t sequence_payload; 4891#if BYTE_ORDER == LITTLE_ENDIAN 4892 uint32_t sequence_payload_length; 4893 uint32_t rsvd4; 4894 uint32_t :8, 4895 df_ctl:8, 4896 type:8, 4897 r_ctl:8; 4898 uint32_t xri_tag:16, 4899 context_tag:16; 4900 uint32_t :2, 4901 ct:2, 4902 :4, 4903 command:8, 4904 class:3, 4905 :1, 4906 pu:2, 4907 :2, 4908 timer:8; 4909 uint32_t abort_tag; 4910 uint32_t request_tag:16, 4911 temporary_rpi:16; 4912 uint32_t ebde_cnt:4, 4913 :3, 4914 len_loc:2, 4915 qosd:1, 4916 :1, 4917 xbl:1, 4918 hlm:1, 4919 iod:1, 4920 dbde:1, 4921 wqes:1, 4922 pri:3, 4923 pv:1, 4924 eat:1, 4925 xc:1, 4926 :1, 4927 ccpe:1, 4928 ccp:8; 4929 uint32_t cmd_type:4, 4930 :3, 4931 wqec:1, 4932 :8, 4933 cq_id:16; 4934 uint32_t rsvd12; 4935 uint32_t rsvd13; 4936 uint32_t rsvd14; 4937 uint32_t rsvd15; 4938#else 4939#error big endian version not defined 4940#endif 4941} sli4_xmit_bcast64_wqe_t; 4942 4943/** 4944 * @brief WQE used to create a BLS response. 4945 */ 4946typedef struct sli4_xmit_bls_rsp_wqe_s { 4947#if BYTE_ORDER == LITTLE_ENDIAN 4948 uint32_t payload_word0; 4949 uint32_t rx_id:16, 4950 ox_id:16; 4951 uint32_t high_seq_cnt:16, 4952 low_seq_cnt:16; 4953 uint32_t rsvd3; 4954 uint32_t local_n_port_id:24, 4955 :8; 4956 uint32_t remote_id:24, 4957 :6, 4958 ar:1, 4959 xo:1; 4960 uint32_t xri_tag:16, 4961 context_tag:16; 4962 uint32_t :2, 4963 ct:2, 4964 :4, 4965 command:8, 4966 class:3, 4967 :1, 4968 pu:2, 4969 :2, 4970 timer:8; 4971 uint32_t abort_tag; 4972 uint32_t request_tag:16, 4973 :16; 4974 uint32_t ebde_cnt:4, 4975 :3, 4976 len_loc:2, 4977 qosd:1, 4978 :1, 4979 xbl:1, 4980 hlm:1, 4981 iod:1, 4982 dbde:1, 4983 wqes:1, 4984 pri:3, 4985 pv:1, 4986 eat:1, 4987 xc:1, 4988 :1, 4989 ccpe:1, 4990 ccp:8; 4991 uint32_t cmd_type:4, 4992 :3, 4993 wqec:1, 4994 :8, 4995 cq_id:16; 4996 uint32_t temporary_rpi:16, 4997 :16; 4998 uint32_t rsvd13; 4999 uint32_t rsvd14; 5000 uint32_t rsvd15; 5001#else 5002#error big endian version not defined 5003#endif 5004} sli4_xmit_bls_rsp_wqe_t; 5005 5006typedef enum { 5007 SLI_BLS_ACC, 5008 SLI_BLS_RJT, 5009 SLI_BLS_MAX 5010} sli_bls_type_e; 5011 5012typedef struct sli_bls_payload_s { 5013 sli_bls_type_e type; 5014 uint16_t ox_id; 5015 uint16_t rx_id; 5016 union { 5017 struct { 5018 uint32_t seq_id_validity:8, 5019 seq_id_last:8, 5020 :16; 5021 uint16_t ox_id; 5022 uint16_t rx_id; 5023 uint16_t low_seq_cnt; 5024 uint16_t high_seq_cnt; 5025 } acc; 5026 struct { 5027 uint32_t vendor_unique:8, 5028 reason_explanation:8, 5029 reason_code:8, 5030 :8; 5031 } rjt; 5032 } u; 5033} sli_bls_payload_t; 5034 5035/** 5036 * @brief WQE used to create an ELS response. 5037 */ 5038typedef struct sli4_xmit_els_rsp64_wqe_s { 5039 sli4_bde_t els_response_payload; 5040#if BYTE_ORDER == LITTLE_ENDIAN 5041 uint32_t els_response_payload_length; 5042 uint32_t s_id:24, 5043 sp:1, 5044 :7; 5045 uint32_t remote_id:24, 5046 :8; 5047 uint32_t xri_tag:16, 5048 context_tag:16; 5049 uint32_t :2, 5050 ct:2, 5051 :4, 5052 command:8, 5053 class:3, 5054 :1, 5055 pu:2, 5056 :2, 5057 timer:8; 5058 uint32_t abort_tag; 5059 uint32_t request_tag:16, 5060 ox_id:16; 5061 uint32_t ebde_cnt:4, 5062 :3, 5063 len_loc:2, 5064 qosd:1, 5065 :1, 5066 xbl:1, 5067 hlm:1, 5068 iod:1, 5069 dbde:1, 5070 wqes:1, 5071 pri:3, 5072 pv:1, 5073 eat:1, 5074 xc:1, 5075 :1, 5076 ccpe:1, 5077 ccp:8; 5078 uint32_t cmd_type:4, 5079 :3, 5080 wqec:1, 5081 :8, 5082 cq_id:16; 5083 uint32_t temporary_rpi:16, 5084 :16; 5085 uint32_t rsvd13; 5086 uint32_t rsvd14; 5087 uint32_t rsvd15; 5088#else 5089#error big endian version not defined 5090#endif 5091} sli4_xmit_els_rsp64_wqe_t; 5092 5093/** 5094 * @brief Asynchronouse Event: Link State ACQE. 5095 */ 5096typedef struct sli4_link_state_s { 5097#if BYTE_ORDER == LITTLE_ENDIAN 5098 uint32_t link_number:6, 5099 link_type:2, 5100 port_link_status:8, 5101 port_duplex:8, 5102 port_speed:8; 5103 uint32_t port_fault:8, 5104 :8, 5105 logical_link_speed:16; 5106 uint32_t event_tag; 5107 uint32_t :8, 5108 event_code:8, 5109 event_type:8, /** values are protocol specific */ 5110 :6, 5111 ae:1, /** async event - this is an ACQE */ 5112 val:1; /** valid - contents of CQE are valid */ 5113#else 5114#error big endian version not defined 5115#endif 5116} sli4_link_state_t; 5117 5118 5119#define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01 5120#define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02 5121#define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03 5122 5123#define SLI4_LINK_ATTN_P2P 0x01 5124#define SLI4_LINK_ATTN_FC_AL 0x02 5125#define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03 5126#define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04 5127 5128#define SLI4_LINK_ATTN_1G 0x01 5129#define SLI4_LINK_ATTN_2G 0x02 5130#define SLI4_LINK_ATTN_4G 0x04 5131#define SLI4_LINK_ATTN_8G 0x08 5132#define SLI4_LINK_ATTN_10G 0x0a 5133#define SLI4_LINK_ATTN_16G 0x10 5134 5135#define SLI4_LINK_TYPE_ETHERNET 0x0 5136#define SLI4_LINK_TYPE_FC 0x1 5137 5138/** 5139 * @brief Asynchronouse Event: FC Link Attention Event. 5140 */ 5141typedef struct sli4_link_attention_s { 5142#if BYTE_ORDER == LITTLE_ENDIAN 5143 uint32_t link_number:8, 5144 attn_type:8, 5145 topology:8, 5146 port_speed:8; 5147 uint32_t port_fault:8, 5148 shared_link_status:8, 5149 logical_link_speed:16; 5150 uint32_t event_tag; 5151 uint32_t :8, 5152 event_code:8, 5153 event_type:8, /** values are protocol specific */ 5154 :6, 5155 ae:1, /** async event - this is an ACQE */ 5156 val:1; /** valid - contents of CQE are valid */ 5157#else 5158#error big endian version not defined 5159#endif 5160} sli4_link_attention_t; 5161 5162/** 5163 * @brief FC/FCoE event types. 5164 */ 5165#define SLI4_LINK_STATE_PHYSICAL 0x00 5166#define SLI4_LINK_STATE_LOGICAL 0x01 5167 5168#define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01 5169#define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02 5170#define SLI4_FCOE_FIP_FCF_DEAD 0x03 5171#define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04 5172#define SLI4_FCOE_FIP_FCF_MODIFIED 0x05 5173 5174#define SLI4_GRP5_QOS_SPEED 0x01 5175 5176#define SLI4_FC_EVENT_LINK_ATTENTION 0x01 5177#define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02 5178 5179#define SLI4_PORT_SPEED_NO_LINK 0x0 5180#define SLI4_PORT_SPEED_10_MBPS 0x1 5181#define SLI4_PORT_SPEED_100_MBPS 0x2 5182#define SLI4_PORT_SPEED_1_GBPS 0x3 5183#define SLI4_PORT_SPEED_10_GBPS 0x4 5184 5185#define SLI4_PORT_DUPLEX_NONE 0x0 5186#define SLI4_PORT_DUPLEX_HWF 0x1 5187#define SLI4_PORT_DUPLEX_FULL 0x2 5188 5189#define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0 5190#define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1 5191#define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2 5192#define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3 5193 5194/** 5195 * @brief Asynchronouse Event: FCoE/FIP ACQE. 5196 */ 5197typedef struct sli4_fcoe_fip_s { 5198#if BYTE_ORDER == LITTLE_ENDIAN 5199 uint32_t event_information; 5200 uint32_t fcf_count:16, 5201 fcoe_event_type:16; 5202 uint32_t event_tag; 5203 uint32_t :8, 5204 event_code:8, 5205 event_type:8, /** values are protocol specific */ 5206 :6, 5207 ae:1, /** async event - this is an ACQE */ 5208 val:1; /** valid - contents of CQE are valid */ 5209#else 5210#error big endian version not defined 5211#endif 5212} sli4_fcoe_fip_t; 5213 5214/** 5215 * @brief FC/FCoE WQ completion queue entry. 5216 */ 5217typedef struct sli4_fc_wcqe_s { 5218#if BYTE_ORDER == LITTLE_ENDIAN 5219 uint32_t hw_status:8, 5220 status:8, 5221 request_tag:16; 5222 uint32_t wqe_specific_1; 5223 uint32_t wqe_specific_2; 5224 uint32_t :15, 5225 qx:1, 5226 code:8, 5227 pri:3, 5228 pv:1, 5229 xb:1, 5230 :2, 5231 vld:1; 5232#else 5233#error big endian version not defined 5234#endif 5235} sli4_fc_wcqe_t; 5236 5237/** 5238 * @brief FC/FCoE WQ consumed CQ queue entry. 5239 */ 5240typedef struct sli4_fc_wqec_s { 5241#if BYTE_ORDER == LITTLE_ENDIAN 5242 uint32_t :32; 5243 uint32_t :32; 5244 uint32_t wqe_index:16, 5245 wq_id:16; 5246 uint32_t :16, 5247 code:8, 5248 :7, 5249 vld:1; 5250#else 5251#error big endian version not defined 5252#endif 5253} sli4_fc_wqec_t; 5254 5255/** 5256 * @brief FC/FCoE Completion Status Codes. 5257 */ 5258#define SLI4_FC_WCQE_STATUS_SUCCESS 0x00 5259#define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01 5260#define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02 5261#define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03 5262#define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04 5263#define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05 5264#define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06 5265#define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07 5266#define SLI4_FC_WCQE_STATUS_LS_RJT 0x09 5267#define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b 5268#define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c 5269#define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 5270#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12 5271#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13 5272#define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14 5273#define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15 5274#define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16 5275#define SLI4_FC_WCQE_STATUS_BA_RJT 0x17 5276#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18 5277#define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19 5278#define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a 5279#define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b 5280 5281/* driver generated status codes; better not overlap with chip's status codes! */ 5282#define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT 0xff 5283#define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe 5284#define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd 5285 5286/** 5287 * @brief DI_ERROR Extended Status 5288 */ 5289#define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */ 5290#define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */ 5291#define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */ 5292#define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */ 5293#define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */ 5294#define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */ 5295 5296/** 5297 * @brief Local Reject Reason Codes. 5298 */ 5299#define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01 5300#define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02 5301#define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03 5302#define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04 5303#define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05 5304#define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06 5305#define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07 5306#define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08 5307#define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c 5308#define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d 5309#define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e 5310#define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f 5311#define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11 5312#define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12 5313#define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13 5314#define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14 5315#define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15 5316#define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16 5317#define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17 5318#define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18 5319#define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a 5320#define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b 5321#define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c 5322#define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d 5323#define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e 5324#define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f 5325#define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20 5326#define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21 5327#define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23 5328#define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24 5329#define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25 5330#define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28 5331#define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29 5332#define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e 5333#define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30 5334#define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40 5335#define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41 5336#define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42 5337#define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43 5338#define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44 5339#define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45 5340#define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46 5341#define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47 5342#define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48 5343#define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49 5344#define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a 5345#define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c 5346#define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d 5347#define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e 5348 5349typedef struct sli4_fc_async_rcqe_s { 5350#if BYTE_ORDER == LITTLE_ENDIAN 5351 uint32_t :8, 5352 status:8, 5353 rq_element_index:12, 5354 :4; 5355 uint32_t rsvd1; 5356 uint32_t fcfi:6, 5357 rq_id:10, 5358 payload_data_placement_length:16; 5359 uint32_t sof_byte:8, 5360 eof_byte:8, 5361 code:8, 5362 header_data_placement_length:6, 5363 :1, 5364 vld:1; 5365#else 5366#error big endian version not defined 5367#endif 5368} sli4_fc_async_rcqe_t; 5369 5370typedef struct sli4_fc_async_rcqe_v1_s { 5371#if BYTE_ORDER == LITTLE_ENDIAN 5372 uint32_t :8, 5373 status:8, 5374 rq_element_index:12, 5375 :4; 5376 uint32_t fcfi:6, 5377 :26; 5378 uint32_t rq_id:16, 5379 payload_data_placement_length:16; 5380 uint32_t sof_byte:8, 5381 eof_byte:8, 5382 code:8, 5383 header_data_placement_length:6, 5384 :1, 5385 vld:1; 5386#else 5387#error big endian version not defined 5388#endif 5389} sli4_fc_async_rcqe_v1_t; 5390 5391#define SLI4_FC_ASYNC_RQ_SUCCESS 0x10 5392#define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11 5393#define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12 5394#define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13 5395#define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14 5396 5397typedef struct sli4_fc_coalescing_rcqe_s { 5398#if BYTE_ORDER == LITTLE_ENDIAN 5399 uint32_t :8, 5400 status:8, 5401 rq_element_index:12, 5402 :4; 5403 uint32_t rsvd1; 5404 uint32_t rq_id:16, 5405 sequence_reporting_placement_length:16; 5406 uint32_t :16, 5407 code:8, 5408 :7, 5409 vld:1; 5410#else 5411#error big endian version not defined 5412#endif 5413} sli4_fc_coalescing_rcqe_t; 5414 5415#define SLI4_FC_COALESCE_RQ_SUCCESS 0x10 5416#define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18 5417 5418typedef struct sli4_fc_optimized_write_cmd_cqe_s { 5419#if BYTE_ORDER == LITTLE_ENDIAN 5420 uint32_t :8, 5421 status:8, 5422 rq_element_index:15, 5423 iv:1; 5424 uint32_t fcfi:6, 5425 :8, 5426 oox:1, 5427 agxr:1, 5428 xri:16; 5429 uint32_t rq_id:16, 5430 payload_data_placement_length:16; 5431 uint32_t rpi:16, 5432 code:8, 5433 header_data_placement_length:6, 5434 :1, 5435 vld:1; 5436#else 5437#error big endian version not defined 5438#endif 5439} sli4_fc_optimized_write_cmd_cqe_t; 5440 5441typedef struct sli4_fc_optimized_write_data_cqe_s { 5442#if BYTE_ORDER == LITTLE_ENDIAN 5443 uint32_t hw_status:8, 5444 status:8, 5445 xri:16; 5446 uint32_t total_data_placed; 5447 uint32_t extended_status; 5448 uint32_t :16, 5449 code:8, 5450 pri:3, 5451 pv:1, 5452 xb:1, 5453 rha:1, 5454 :1, 5455 vld:1; 5456#else 5457#error big endian version not defined 5458#endif 5459} sli4_fc_optimized_write_data_cqe_t; 5460 5461typedef struct sli4_fc_xri_aborted_cqe_s { 5462#if BYTE_ORDER == LITTLE_ENDIAN 5463 uint32_t :8, 5464 status:8, 5465 :16; 5466 uint32_t extended_status; 5467 uint32_t xri:16, 5468 remote_xid:16; 5469 uint32_t :16, 5470 code:8, 5471 xr:1, 5472 :3, 5473 eo:1, 5474 br:1, 5475 ia:1, 5476 vld:1; 5477#else 5478#error big endian version not defined 5479#endif 5480} sli4_fc_xri_aborted_cqe_t; 5481 5482/** 5483 * Code definitions applicable to all FC/FCoE CQE types. 5484 */ 5485#define SLI4_CQE_CODE_OFFSET 14 5486 5487#define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01 5488#define SLI4_CQE_CODE_RELEASE_WQE 0x02 5489#define SLI4_CQE_CODE_RQ_ASYNC 0x04 5490#define SLI4_CQE_CODE_XRI_ABORTED 0x05 5491#define SLI4_CQE_CODE_RQ_COALESCING 0x06 5492#define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07 5493#define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08 5494#define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09 5495#define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B 5496#define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C 5497 5498extern int32_t sli_fc_process_link_state(sli4_t *, void *); 5499extern int32_t sli_fc_process_link_attention(sli4_t *, void *); 5500extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 5501extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *); 5502extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *); 5503extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *); 5504extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *); 5505extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *); 5506extern int32_t sli_fc_process_fcoe(sli4_t *, void *); 5507extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5508extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5509extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t); 5510extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **, 5511ocs_dma_t *); 5512extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5513extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5514extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t); 5515extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 5516extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *); 5517extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t); 5518extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t); 5519extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t); 5520extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t); 5521extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t); 5522 5523extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *); 5524extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5525extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5526extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t); 5527 5528extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5529extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t); 5530extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5531extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5532extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5533extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr, 5534 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout, 5535 uint16_t xri, uint16_t req_tag); 5536extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5537extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5538extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t); 5539extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t); 5540extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 5541extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout); 5542 5543/** 5544 * @ingroup sli_fc 5545 * @brief Retrieve the received header and payload length. 5546 * 5547 * @param sli4 SLI context. 5548 * @param cqe Pointer to the CQ entry. 5549 * @param len_hdr Pointer where the header length is written. 5550 * @param len_data Pointer where the payload length is written. 5551 * 5552 * @return Returns 0 on success, or a non-zero value on failure. 5553 */ 5554static inline int32_t 5555sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data) 5556{ 5557 sli4_fc_async_rcqe_t *rcqe = cqe; 5558 5559 *len_hdr = *len_data = 0; 5560 5561 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) { 5562 *len_hdr = rcqe->header_data_placement_length; 5563 *len_data = rcqe->payload_data_placement_length; 5564 return 0; 5565 } else { 5566 return -1; 5567 } 5568} 5569 5570/** 5571 * @ingroup sli_fc 5572 * @brief Retrieve the received FCFI. 5573 * 5574 * @param sli4 SLI context. 5575 * @param cqe Pointer to the CQ entry. 5576 * 5577 * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code. 5578 */ 5579static inline uint8_t 5580sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe) 5581{ 5582 uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET]; 5583 uint8_t fcfi = UINT8_MAX; 5584 5585 switch(code) { 5586 case SLI4_CQE_CODE_RQ_ASYNC: { 5587 sli4_fc_async_rcqe_t *rcqe = cqe; 5588 fcfi = rcqe->fcfi; 5589 break; 5590 } 5591 case SLI4_CQE_CODE_RQ_ASYNC_V1: { 5592 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe; 5593 fcfi = rcqev1->fcfi; 5594 break; 5595 } 5596 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: { 5597 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe; 5598 fcfi = opt_wr->fcfi; 5599 break; 5600 } 5601 } 5602 5603 return fcfi; 5604} 5605 5606extern const char *sli_fc_get_status_string(uint32_t status); 5607 5608#endif /* !_SLI4_H */ 5609 5610