1231437Sluigi/*- 2252869Sdelphij * Copyright (C) 2013 Emulex 3231437Sluigi * All rights reserved. 4231437Sluigi * 5231437Sluigi * Redistribution and use in source and binary forms, with or without 6231437Sluigi * modification, are permitted provided that the following conditions are met: 7231437Sluigi * 8231437Sluigi * 1. Redistributions of source code must retain the above copyright notice, 9231437Sluigi * this list of conditions and the following disclaimer. 10231437Sluigi * 11231437Sluigi * 2. Redistributions in binary form must reproduce the above copyright 12231437Sluigi * notice, this list of conditions and the following disclaimer in the 13231437Sluigi * documentation and/or other materials provided with the distribution. 14231437Sluigi * 15231437Sluigi * 3. Neither the name of the Emulex Corporation nor the names of its 16231437Sluigi * contributors may be used to endorse or promote products derived from 17231437Sluigi * this software without specific prior written permission. 18231437Sluigi * 19231437Sluigi * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20231437Sluigi * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21231437Sluigi * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22231437Sluigi * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23231437Sluigi * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24231437Sluigi * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25231437Sluigi * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26231437Sluigi * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27231437Sluigi * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28231437Sluigi * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29231437Sluigi * POSSIBILITY OF SUCH DAMAGE. 30231437Sluigi * 31231437Sluigi * Contact Information: 32231437Sluigi * freebsd-drivers@emulex.com 33231437Sluigi * 34231437Sluigi * Emulex 35231437Sluigi * 3333 Susan Street 36231437Sluigi * Costa Mesa, CA 92626 37231437Sluigi */ 38231437Sluigi 39231437Sluigi/* $FreeBSD: stable/11/sys/dev/oce/oce_if.h 356090 2019-12-26 16:58:11Z markj $ */ 40231437Sluigi 41231437Sluigi#include <sys/param.h> 42231437Sluigi#include <sys/endian.h> 43257241Sglebius#include <sys/eventhandler.h> 44295126Sglebius#include <sys/malloc.h> 45231437Sluigi#include <sys/module.h> 46231437Sluigi#include <sys/kernel.h> 47231437Sluigi#include <sys/bus.h> 48231437Sluigi#include <sys/mbuf.h> 49356090Smarkj#include <sys/priv.h> 50231437Sluigi#include <sys/rman.h> 51231437Sluigi#include <sys/socket.h> 52231437Sluigi#include <sys/sockio.h> 53231437Sluigi#include <sys/sockopt.h> 54231437Sluigi#include <sys/queue.h> 55231437Sluigi#include <sys/taskqueue.h> 56231437Sluigi#include <sys/lock.h> 57231437Sluigi#include <sys/mutex.h> 58231437Sluigi#include <sys/sysctl.h> 59231437Sluigi#include <sys/random.h> 60231437Sluigi#include <sys/firmware.h> 61231437Sluigi#include <sys/systm.h> 62231437Sluigi#include <sys/proc.h> 63231437Sluigi 64231437Sluigi#include <dev/pci/pcireg.h> 65231437Sluigi#include <dev/pci/pcivar.h> 66231437Sluigi 67231437Sluigi#include <net/bpf.h> 68231437Sluigi#include <net/ethernet.h> 69231437Sluigi#include <net/if.h> 70257176Sglebius#include <net/if_var.h> 71231437Sluigi#include <net/if_types.h> 72231437Sluigi#include <net/if_media.h> 73231437Sluigi#include <net/if_vlan_var.h> 74231437Sluigi#include <net/if_dl.h> 75231437Sluigi 76231437Sluigi#include <netinet/in.h> 77231437Sluigi#include <netinet/in_systm.h> 78231437Sluigi#include <netinet/in_var.h> 79231437Sluigi#include <netinet/if_ether.h> 80231437Sluigi#include <netinet/ip.h> 81231437Sluigi#include <netinet/ip6.h> 82231437Sluigi#include <netinet6/in6_var.h> 83231437Sluigi#include <netinet6/ip6_mroute.h> 84231437Sluigi 85231437Sluigi#include <netinet/udp.h> 86231437Sluigi#include <netinet/tcp.h> 87231437Sluigi#include <netinet/sctp.h> 88231437Sluigi#include <netinet/tcp_lro.h> 89338938Sjpaetzel#include <netinet/icmp6.h> 90231437Sluigi 91231437Sluigi#include <machine/bus.h> 92231437Sluigi 93231437Sluigi#include "oce_hw.h" 94231437Sluigi 95257007Sdelphij/* OCE device driver module component revision informaiton */ 96338938Sjpaetzel#define COMPONENT_REVISION "11.0.50.0" 97231437Sluigi 98231437Sluigi/* OCE devices supported by this driver */ 99231437Sluigi#define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 100231437Sluigi#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 101231437Sluigi#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 102231437Sluigi#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 103231437Sluigi#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 104231437Sluigi#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 105252869Sdelphij#define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */ 106231437Sluigi 107231437Sluigi#define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 108231437Sluigi (sc->flags & OCE_FLAGS_BE2))? 1:0) 109252869Sdelphij#define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3) 110252869Sdelphij#define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2) 111231437Sluigi#define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 112231437Sluigi#define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 113252869Sdelphij#define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0) 114231437Sluigi 115252869Sdelphij#define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \ 116252869Sdelphij (sc->function_mode & FNM_UMC_MODE) || \ 117252869Sdelphij (sc->function_mode & FNM_VNIC_MODE)) 118252869Sdelphij#define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 119252869Sdelphij#define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) 120231437Sluigi 121252869Sdelphij 122231437Sluigi/* proportion Service Level Interface queues */ 123231437Sluigi#define OCE_MAX_UNITS 2 124231437Sluigi#define OCE_MAX_PPORT OCE_MAX_UNITS 125231437Sluigi#define OCE_MAX_VPORT OCE_MAX_UNITS 126231437Sluigi 127231437Sluigiextern int mp_ncpus; /* system's total active cpu cores */ 128231437Sluigi#define OCE_NCPUS mp_ncpus 129231879Sluigi 130231879Sluigi/* This should be powers of 2. Like 2,4,8 & 16 */ 131252869Sdelphij#define OCE_MAX_RSS 8 132231437Sluigi#define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 133252869Sdelphij#define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc)) 134231437Sluigi 135231437Sluigi#define OCE_MIN_RQ 1 136231437Sluigi#define OCE_MIN_WQ 1 137231437Sluigi 138231437Sluigi#define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 139231437Sluigi#define OCE_MAX_WQ 8 140231437Sluigi 141231437Sluigi#define OCE_MAX_EQ 32 142231437Sluigi#define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 143231437Sluigi#define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 144231437Sluigi 145231437Sluigi#define OCE_DEFAULT_WQ_EQD 16 146231437Sluigi#define OCE_MAX_PACKET_Q 16 147231437Sluigi#define OCE_LSO_MAX_SIZE (64 * 1024) 148231437Sluigi#define LONG_TIMEOUT 30 149247880Sdelphij#define OCE_MAX_JUMBO_FRAME_SIZE 9018 150231437Sluigi#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 151231437Sluigi ETHER_VLAN_ENCAP_LEN - \ 152231437Sluigi ETHER_HDR_LEN) 153231437Sluigi 154338938Sjpaetzel#define OCE_RDMA_VECTORS 2 155338938Sjpaetzel 156231437Sluigi#define OCE_MAX_TX_ELEMENTS 29 157231437Sluigi#define OCE_MAX_TX_DESC 1024 158231437Sluigi#define OCE_MAX_TX_SIZE 65535 159338938Sjpaetzel#define OCE_MAX_TSO_SIZE (65535 - ETHER_HDR_LEN) 160231437Sluigi#define OCE_MAX_RX_SIZE 4096 161231437Sluigi#define OCE_MAX_RQ_POSTS 255 162338938Sjpaetzel#define OCE_HWLRO_MAX_RQ_POSTS 64 163231437Sluigi#define OCE_DEFAULT_PROMISCUOUS 0 164231437Sluigi 165231437Sluigi 166231437Sluigi#define RSS_ENABLE_IPV4 0x1 167231437Sluigi#define RSS_ENABLE_TCP_IPV4 0x2 168231437Sluigi#define RSS_ENABLE_IPV6 0x4 169231437Sluigi#define RSS_ENABLE_TCP_IPV6 0x8 170231437Sluigi 171252869Sdelphij#define INDIRECTION_TABLE_ENTRIES 128 172231437Sluigi 173231437Sluigi/* flow control definitions */ 174231437Sluigi#define OCE_FC_NONE 0x00000000 175231437Sluigi#define OCE_FC_TX 0x00000001 176231437Sluigi#define OCE_FC_RX 0x00000002 177231437Sluigi#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 178231437Sluigi 179231437Sluigi 180231437Sluigi/* Interface capabilities to give device when creating interface */ 181231437Sluigi#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 182231437Sluigi MBX_RX_IFACE_FLAGS_UNTAGGED | \ 183231437Sluigi MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 184257007Sdelphij MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \ 185231437Sluigi MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 186231437Sluigi MBX_RX_IFACE_FLAGS_RSS | \ 187231437Sluigi MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 188231437Sluigi 189231437Sluigi/* Interface capabilities to enable by default (others set dynamically) */ 190231437Sluigi#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 191231437Sluigi MBX_RX_IFACE_FLAGS_UNTAGGED | \ 192231437Sluigi MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 193231437Sluigi 194231437Sluigi#define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 195231437Sluigi#define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 196231437Sluigi IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 197231879Sluigi IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 198231437Sluigi#define OCE_IF_HWASSIST_NONE 0 199231437Sluigi#define OCE_IF_CAPABILITIES_NONE 0 200231437Sluigi 201231437Sluigi 202231437Sluigi#define ETH_ADDR_LEN 6 203231437Sluigi#define MAX_VLANFILTER_SIZE 64 204231437Sluigi#define MAX_VLANS 4096 205231437Sluigi 206231437Sluigi#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 207231437Sluigi#define BSWAP_8(x) ((x) & 0xff) 208231437Sluigi#define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 209231437Sluigi#define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 210231437Sluigi BSWAP_16((x) >> 16)) 211231437Sluigi#define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 212231437Sluigi BSWAP_32((x) >> 32)) 213231437Sluigi 214231437Sluigi#define for_all_wq_queues(sc, wq, i) \ 215231437Sluigi for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 216231437Sluigi#define for_all_rq_queues(sc, rq, i) \ 217231437Sluigi for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 218252869Sdelphij#define for_all_rss_queues(sc, rq, i) \ 219252869Sdelphij for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \ 220252869Sdelphij i++, rq = sc->rq[i + 1]) 221231437Sluigi#define for_all_evnt_queues(sc, eq, i) \ 222231437Sluigi for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 223231437Sluigi#define for_all_cq_queues(sc, cq, i) \ 224231437Sluigi for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 225231437Sluigi 226231437Sluigi 227231437Sluigi/* Flash specific */ 228231437Sluigi#define IOCTL_COOKIE "SERVERENGINES CORP" 229231437Sluigi#define MAX_FLASH_COMP 32 230231437Sluigi 231231437Sluigi#define IMG_ISCSI 160 232231437Sluigi#define IMG_REDBOOT 224 233231437Sluigi#define IMG_BIOS 34 234231437Sluigi#define IMG_PXEBIOS 32 235231437Sluigi#define IMG_FCOEBIOS 33 236231437Sluigi#define IMG_ISCSI_BAK 176 237231437Sluigi#define IMG_FCOE 162 238231437Sluigi#define IMG_FCOE_BAK 178 239231437Sluigi#define IMG_NCSI 16 240231437Sluigi#define IMG_PHY 192 241231437Sluigi#define FLASHROM_OPER_FLASH 1 242231437Sluigi#define FLASHROM_OPER_SAVE 2 243231437Sluigi#define FLASHROM_OPER_REPORT 4 244231437Sluigi#define FLASHROM_OPER_FLASH_PHY 9 245231437Sluigi#define FLASHROM_OPER_SAVE_PHY 10 246231437Sluigi#define TN_8022 13 247231437Sluigi 248231437Sluigienum { 249231437Sluigi PHY_TYPE_CX4_10GB = 0, 250231437Sluigi PHY_TYPE_XFP_10GB, 251231437Sluigi PHY_TYPE_SFP_1GB, 252231437Sluigi PHY_TYPE_SFP_PLUS_10GB, 253231437Sluigi PHY_TYPE_KR_10GB, 254231437Sluigi PHY_TYPE_KX4_10GB, 255231437Sluigi PHY_TYPE_BASET_10GB, 256231437Sluigi PHY_TYPE_BASET_1GB, 257231437Sluigi PHY_TYPE_BASEX_1GB, 258231437Sluigi PHY_TYPE_SGMII, 259231437Sluigi PHY_TYPE_DISABLED = 255 260231437Sluigi}; 261231437Sluigi 262231437Sluigi/** 263231437Sluigi * @brief Define and hold all necessary info for a single interrupt 264231437Sluigi */ 265231437Sluigi#define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 266231437Sluigi#define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 267231437Sluigi 268231437Sluigitypedef struct oce_intr_info { 269231437Sluigi void *tag; /* cookie returned by bus_setup_intr */ 270231437Sluigi struct resource *intr_res; /* PCI resource container */ 271231437Sluigi int irq_rr; /* resource id for the interrupt */ 272231437Sluigi struct oce_softc *sc; /* pointer to the parent soft c */ 273231437Sluigi struct oce_eq *eq; /* pointer to the connected EQ */ 274231437Sluigi struct taskqueue *tq; /* Associated task queue */ 275231437Sluigi struct task task; /* task queue task */ 276231437Sluigi char task_name[32]; /* task name */ 277231437Sluigi int vector; /* interrupt vector number */ 278231437Sluigi} OCE_INTR_INFO, *POCE_INTR_INFO; 279231437Sluigi 280231437Sluigi 281231437Sluigi/* Ring related */ 282231437Sluigi#define GET_Q_NEXT(_START, _STEP, _END) \ 283231437Sluigi (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 284231437Sluigi : (((_START) + (_STEP)) - (_END))) 285231437Sluigi 286231437Sluigi#define DBUF_PA(obj) ((obj)->addr) 287231437Sluigi#define DBUF_VA(obj) ((obj)->ptr) 288231437Sluigi#define DBUF_TAG(obj) ((obj)->tag) 289231437Sluigi#define DBUF_MAP(obj) ((obj)->map) 290231437Sluigi#define DBUF_SYNC(obj, flags) \ 291231437Sluigi (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 292231437Sluigi 293231437Sluigi#define RING_NUM_PENDING(ring) ring->num_used 294231437Sluigi#define RING_FULL(ring) (ring->num_used == ring->num_items) 295231437Sluigi#define RING_EMPTY(ring) (ring->num_used == 0) 296231437Sluigi#define RING_NUM_FREE(ring) \ 297231437Sluigi (uint32_t)(ring->num_items - ring->num_used) 298231437Sluigi#define RING_GET(ring, n) \ 299231437Sluigi ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 300231437Sluigi#define RING_PUT(ring, n) \ 301231437Sluigi ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 302231437Sluigi 303231437Sluigi#define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 304231437Sluigi (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 305231437Sluigi#define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 306231437Sluigi (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 307231437Sluigi#define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 308231437Sluigi (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 309231437Sluigi#define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 310231437Sluigi (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 311231437Sluigi 312231437Sluigi#define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 313231437Sluigi 314231437Sluigistruct oce_packet_desc { 315231437Sluigi struct mbuf *mbuf; 316231437Sluigi bus_dmamap_t map; 317231437Sluigi int nsegs; 318231437Sluigi uint32_t wqe_idx; 319231437Sluigi}; 320231437Sluigi 321231437Sluigitypedef struct oce_dma_mem { 322231437Sluigi bus_dma_tag_t tag; 323231437Sluigi bus_dmamap_t map; 324231437Sluigi void *ptr; 325231437Sluigi bus_addr_t paddr; 326231437Sluigi} OCE_DMA_MEM, *POCE_DMA_MEM; 327231437Sluigi 328231437Sluigitypedef struct oce_ring_buffer_s { 329231437Sluigi uint16_t cidx; /* Get ptr */ 330231437Sluigi uint16_t pidx; /* Put Ptr */ 331231437Sluigi size_t item_size; 332231437Sluigi size_t num_items; 333231437Sluigi uint32_t num_used; 334231437Sluigi OCE_DMA_MEM dma; 335231437Sluigi} oce_ring_buffer_t; 336231437Sluigi 337231437Sluigi/* Stats */ 338231437Sluigi#define OCE_UNICAST_PACKET 0 339231437Sluigi#define OCE_MULTICAST_PACKET 1 340231437Sluigi#define OCE_BROADCAST_PACKET 2 341231437Sluigi#define OCE_RSVD_PACKET 3 342231437Sluigi 343231437Sluigistruct oce_rx_stats { 344231437Sluigi /* Total Receive Stats*/ 345231437Sluigi uint64_t t_rx_pkts; 346231437Sluigi uint64_t t_rx_bytes; 347231437Sluigi uint32_t t_rx_frags; 348231437Sluigi uint32_t t_rx_mcast_pkts; 349231437Sluigi uint32_t t_rx_ucast_pkts; 350231437Sluigi uint32_t t_rxcp_errs; 351231437Sluigi}; 352231437Sluigistruct oce_tx_stats { 353231437Sluigi /*Total Transmit Stats */ 354231437Sluigi uint64_t t_tx_pkts; 355231437Sluigi uint64_t t_tx_bytes; 356231437Sluigi uint32_t t_tx_reqs; 357231437Sluigi uint32_t t_tx_stops; 358231437Sluigi uint32_t t_tx_wrbs; 359231437Sluigi uint32_t t_tx_compl; 360231437Sluigi uint32_t t_ipv6_ext_hdr_tx_drop; 361231437Sluigi}; 362231437Sluigi 363231437Sluigistruct oce_be_stats { 364231437Sluigi uint8_t be_on_die_temperature; 365231437Sluigi uint32_t be_tx_events; 366231437Sluigi uint32_t eth_red_drops; 367231437Sluigi uint32_t rx_drops_no_pbuf; 368231437Sluigi uint32_t rx_drops_no_txpb; 369231437Sluigi uint32_t rx_drops_no_erx_descr; 370231437Sluigi uint32_t rx_drops_no_tpre_descr; 371231437Sluigi uint32_t rx_drops_too_many_frags; 372231437Sluigi uint32_t rx_drops_invalid_ring; 373231437Sluigi uint32_t forwarded_packets; 374231437Sluigi uint32_t rx_drops_mtu; 375231437Sluigi uint32_t rx_crc_errors; 376231437Sluigi uint32_t rx_alignment_symbol_errors; 377231437Sluigi uint32_t rx_pause_frames; 378231437Sluigi uint32_t rx_priority_pause_frames; 379231437Sluigi uint32_t rx_control_frames; 380231437Sluigi uint32_t rx_in_range_errors; 381231437Sluigi uint32_t rx_out_range_errors; 382231437Sluigi uint32_t rx_frame_too_long; 383231437Sluigi uint32_t rx_address_match_errors; 384231437Sluigi uint32_t rx_dropped_too_small; 385231437Sluigi uint32_t rx_dropped_too_short; 386231437Sluigi uint32_t rx_dropped_header_too_small; 387231437Sluigi uint32_t rx_dropped_tcp_length; 388231437Sluigi uint32_t rx_dropped_runt; 389231437Sluigi uint32_t rx_ip_checksum_errs; 390231437Sluigi uint32_t rx_tcp_checksum_errs; 391231437Sluigi uint32_t rx_udp_checksum_errs; 392231437Sluigi uint32_t rx_switched_unicast_packets; 393231437Sluigi uint32_t rx_switched_multicast_packets; 394231437Sluigi uint32_t rx_switched_broadcast_packets; 395231437Sluigi uint32_t tx_pauseframes; 396231437Sluigi uint32_t tx_priority_pauseframes; 397231437Sluigi uint32_t tx_controlframes; 398231437Sluigi uint32_t rxpp_fifo_overflow_drop; 399231437Sluigi uint32_t rx_input_fifo_overflow_drop; 400231437Sluigi uint32_t pmem_fifo_overflow_drop; 401231437Sluigi uint32_t jabber_events; 402231437Sluigi}; 403231437Sluigi 404231437Sluigistruct oce_xe201_stats { 405231437Sluigi uint64_t tx_pkts; 406231437Sluigi uint64_t tx_unicast_pkts; 407231437Sluigi uint64_t tx_multicast_pkts; 408231437Sluigi uint64_t tx_broadcast_pkts; 409231437Sluigi uint64_t tx_bytes; 410231437Sluigi uint64_t tx_unicast_bytes; 411231437Sluigi uint64_t tx_multicast_bytes; 412231437Sluigi uint64_t tx_broadcast_bytes; 413231437Sluigi uint64_t tx_discards; 414231437Sluigi uint64_t tx_errors; 415231437Sluigi uint64_t tx_pause_frames; 416231437Sluigi uint64_t tx_pause_on_frames; 417231437Sluigi uint64_t tx_pause_off_frames; 418231437Sluigi uint64_t tx_internal_mac_errors; 419231437Sluigi uint64_t tx_control_frames; 420231437Sluigi uint64_t tx_pkts_64_bytes; 421231437Sluigi uint64_t tx_pkts_65_to_127_bytes; 422231437Sluigi uint64_t tx_pkts_128_to_255_bytes; 423231437Sluigi uint64_t tx_pkts_256_to_511_bytes; 424231437Sluigi uint64_t tx_pkts_512_to_1023_bytes; 425231437Sluigi uint64_t tx_pkts_1024_to_1518_bytes; 426231437Sluigi uint64_t tx_pkts_1519_to_2047_bytes; 427231437Sluigi uint64_t tx_pkts_2048_to_4095_bytes; 428231437Sluigi uint64_t tx_pkts_4096_to_8191_bytes; 429231437Sluigi uint64_t tx_pkts_8192_to_9216_bytes; 430231437Sluigi uint64_t tx_lso_pkts; 431231437Sluigi uint64_t rx_pkts; 432231437Sluigi uint64_t rx_unicast_pkts; 433231437Sluigi uint64_t rx_multicast_pkts; 434231437Sluigi uint64_t rx_broadcast_pkts; 435231437Sluigi uint64_t rx_bytes; 436231437Sluigi uint64_t rx_unicast_bytes; 437231437Sluigi uint64_t rx_multicast_bytes; 438231437Sluigi uint64_t rx_broadcast_bytes; 439231437Sluigi uint32_t rx_unknown_protos; 440231437Sluigi uint64_t rx_discards; 441231437Sluigi uint64_t rx_errors; 442231437Sluigi uint64_t rx_crc_errors; 443231437Sluigi uint64_t rx_alignment_errors; 444231437Sluigi uint64_t rx_symbol_errors; 445231437Sluigi uint64_t rx_pause_frames; 446231437Sluigi uint64_t rx_pause_on_frames; 447231437Sluigi uint64_t rx_pause_off_frames; 448231437Sluigi uint64_t rx_frames_too_long; 449231437Sluigi uint64_t rx_internal_mac_errors; 450231437Sluigi uint32_t rx_undersize_pkts; 451231437Sluigi uint32_t rx_oversize_pkts; 452231437Sluigi uint32_t rx_fragment_pkts; 453231437Sluigi uint32_t rx_jabbers; 454231437Sluigi uint64_t rx_control_frames; 455231437Sluigi uint64_t rx_control_frames_unknown_opcode; 456231437Sluigi uint32_t rx_in_range_errors; 457231437Sluigi uint32_t rx_out_of_range_errors; 458231437Sluigi uint32_t rx_address_match_errors; 459231437Sluigi uint32_t rx_vlan_mismatch_errors; 460231437Sluigi uint32_t rx_dropped_too_small; 461231437Sluigi uint32_t rx_dropped_too_short; 462231437Sluigi uint32_t rx_dropped_header_too_small; 463231437Sluigi uint32_t rx_dropped_invalid_tcp_length; 464231437Sluigi uint32_t rx_dropped_runt; 465231437Sluigi uint32_t rx_ip_checksum_errors; 466231437Sluigi uint32_t rx_tcp_checksum_errors; 467231437Sluigi uint32_t rx_udp_checksum_errors; 468231437Sluigi uint32_t rx_non_rss_pkts; 469231437Sluigi uint64_t rx_ipv4_pkts; 470231437Sluigi uint64_t rx_ipv6_pkts; 471231437Sluigi uint64_t rx_ipv4_bytes; 472231437Sluigi uint64_t rx_ipv6_bytes; 473231437Sluigi uint64_t rx_nic_pkts; 474231437Sluigi uint64_t rx_tcp_pkts; 475231437Sluigi uint64_t rx_iscsi_pkts; 476231437Sluigi uint64_t rx_management_pkts; 477231437Sluigi uint64_t rx_switched_unicast_pkts; 478231437Sluigi uint64_t rx_switched_multicast_pkts; 479231437Sluigi uint64_t rx_switched_broadcast_pkts; 480231437Sluigi uint64_t num_forwards; 481231437Sluigi uint32_t rx_fifo_overflow; 482231437Sluigi uint32_t rx_input_fifo_overflow; 483231437Sluigi uint64_t rx_drops_too_many_frags; 484231437Sluigi uint32_t rx_drops_invalid_queue; 485231437Sluigi uint64_t rx_drops_mtu; 486231437Sluigi uint64_t rx_pkts_64_bytes; 487231437Sluigi uint64_t rx_pkts_65_to_127_bytes; 488231437Sluigi uint64_t rx_pkts_128_to_255_bytes; 489231437Sluigi uint64_t rx_pkts_256_to_511_bytes; 490231437Sluigi uint64_t rx_pkts_512_to_1023_bytes; 491231437Sluigi uint64_t rx_pkts_1024_to_1518_bytes; 492231437Sluigi uint64_t rx_pkts_1519_to_2047_bytes; 493231437Sluigi uint64_t rx_pkts_2048_to_4095_bytes; 494231437Sluigi uint64_t rx_pkts_4096_to_8191_bytes; 495231437Sluigi uint64_t rx_pkts_8192_to_9216_bytes; 496231437Sluigi}; 497231437Sluigi 498231437Sluigistruct oce_drv_stats { 499231437Sluigi struct oce_rx_stats rx; 500231437Sluigi struct oce_tx_stats tx; 501231437Sluigi union { 502231437Sluigi struct oce_be_stats be; 503231437Sluigi struct oce_xe201_stats xe201; 504231437Sluigi } u0; 505231437Sluigi}; 506231437Sluigi 507247880Sdelphij#define INTR_RATE_HWM 15000 508247880Sdelphij#define INTR_RATE_LWM 10000 509231437Sluigi 510247880Sdelphij#define OCE_MAX_EQD 128u 511338938Sjpaetzel#define OCE_MIN_EQD 0u 512231437Sluigi 513247880Sdelphijstruct oce_set_eqd { 514247880Sdelphij uint32_t eq_id; 515247880Sdelphij uint32_t phase; 516247880Sdelphij uint32_t delay_multiplier; 517247880Sdelphij}; 518247880Sdelphij 519247880Sdelphijstruct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 520247880Sdelphij boolean_t enable; 521247880Sdelphij uint32_t min_eqd; /* in usecs */ 522247880Sdelphij uint32_t max_eqd; /* in usecs */ 523247880Sdelphij uint32_t cur_eqd; /* in usecs */ 524247880Sdelphij uint32_t et_eqd; /* configured value when aic is off */ 525247880Sdelphij uint64_t ticks; 526338938Sjpaetzel uint64_t prev_rxpkts; 527338938Sjpaetzel uint64_t prev_txreqs; 528247880Sdelphij}; 529247880Sdelphij 530231437Sluigi#define MAX_LOCK_DESC_LEN 32 531231437Sluigistruct oce_lock { 532231437Sluigi struct mtx mutex; 533231437Sluigi char name[MAX_LOCK_DESC_LEN+1]; 534231437Sluigi}; 535231437Sluigi#define OCE_LOCK struct oce_lock 536231437Sluigi 537231437Sluigi#define LOCK_CREATE(lock, desc) { \ 538231437Sluigi strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \ 539231437Sluigi (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 540246799Sjpaetzel mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \ 541231437Sluigi} 542231437Sluigi#define LOCK_DESTROY(lock) \ 543231437Sluigi if (mtx_initialized(&(lock)->mutex))\ 544231437Sluigi mtx_destroy(&(lock)->mutex) 545231437Sluigi#define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex) 546231437Sluigi#define LOCK(lock) mtx_lock(&(lock)->mutex) 547231437Sluigi#define LOCKED(lock) mtx_owned(&(lock)->mutex) 548231437Sluigi#define UNLOCK(lock) mtx_unlock(&(lock)->mutex) 549231437Sluigi 550231437Sluigi#define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 551231437Sluigi#define MBX_READY_TIMEOUT (1 * 1000 * 1000) 552231437Sluigi#define DEFAULT_DRAIN_TIME 200 553231437Sluigi#define MBX_TIMEOUT_SEC 5 554231437Sluigi#define STAT_TIMEOUT 2000000 555231437Sluigi 556231437Sluigi/* size of the packet descriptor array in a transmit queue */ 557231437Sluigi#define OCE_TX_RING_SIZE 2048 558231437Sluigi#define OCE_RX_RING_SIZE 1024 559231437Sluigi#define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 560231437Sluigi#define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 561231437Sluigi 562231437Sluigistruct oce_dev; 563231437Sluigi 564231437Sluigienum eq_len { 565231437Sluigi EQ_LEN_256 = 256, 566231437Sluigi EQ_LEN_512 = 512, 567231437Sluigi EQ_LEN_1024 = 1024, 568231437Sluigi EQ_LEN_2048 = 2048, 569231437Sluigi EQ_LEN_4096 = 4096 570231437Sluigi}; 571231437Sluigi 572231437Sluigienum eqe_size { 573231437Sluigi EQE_SIZE_4 = 4, 574231437Sluigi EQE_SIZE_16 = 16 575231437Sluigi}; 576231437Sluigi 577231437Sluigienum qtype { 578231437Sluigi QTYPE_EQ, 579231437Sluigi QTYPE_MQ, 580231437Sluigi QTYPE_WQ, 581231437Sluigi QTYPE_RQ, 582231437Sluigi QTYPE_CQ, 583231437Sluigi QTYPE_RSS 584231437Sluigi}; 585231437Sluigi 586231437Sluigitypedef enum qstate_e { 587231437Sluigi QDELETED = 0x0, 588231437Sluigi QCREATED = 0x1 589231437Sluigi} qstate_t; 590231437Sluigi 591231437Sluigistruct eq_config { 592231437Sluigi enum eq_len q_len; 593231437Sluigi enum eqe_size item_size; 594231437Sluigi uint32_t q_vector_num; 595231437Sluigi uint8_t min_eqd; 596231437Sluigi uint8_t max_eqd; 597231437Sluigi uint8_t cur_eqd; 598231437Sluigi uint8_t pad; 599231437Sluigi}; 600231437Sluigi 601231437Sluigistruct oce_eq { 602231437Sluigi uint32_t eq_id; 603231437Sluigi void *parent; 604231437Sluigi void *cb_context; 605231437Sluigi oce_ring_buffer_t *ring; 606231437Sluigi uint32_t ref_count; 607231437Sluigi qstate_t qstate; 608231437Sluigi struct oce_cq *cq[OCE_MAX_CQ_EQ]; 609231437Sluigi int cq_valid; 610231437Sluigi struct eq_config eq_cfg; 611231437Sluigi int vector; 612247880Sdelphij uint64_t intr; 613231437Sluigi}; 614231437Sluigi 615231437Sluigienum cq_len { 616231437Sluigi CQ_LEN_256 = 256, 617231437Sluigi CQ_LEN_512 = 512, 618338938Sjpaetzel CQ_LEN_1024 = 1024, 619338938Sjpaetzel CQ_LEN_2048 = 2048 620231437Sluigi}; 621231437Sluigi 622231437Sluigistruct cq_config { 623231437Sluigi enum cq_len q_len; 624231437Sluigi uint32_t item_size; 625231437Sluigi boolean_t is_eventable; 626231437Sluigi boolean_t sol_eventable; 627231437Sluigi boolean_t nodelay; 628231437Sluigi uint16_t dma_coalescing; 629231437Sluigi}; 630231437Sluigi 631231437Sluigitypedef uint16_t(*cq_handler_t) (void *arg1); 632231437Sluigi 633231437Sluigistruct oce_cq { 634231437Sluigi uint32_t cq_id; 635231437Sluigi void *parent; 636231437Sluigi struct oce_eq *eq; 637231437Sluigi cq_handler_t cq_handler; 638231437Sluigi void *cb_arg; 639231437Sluigi oce_ring_buffer_t *ring; 640231437Sluigi qstate_t qstate; 641231437Sluigi struct cq_config cq_cfg; 642231437Sluigi uint32_t ref_count; 643231437Sluigi}; 644231437Sluigi 645231437Sluigi 646231437Sluigistruct mq_config { 647231437Sluigi uint32_t eqd; 648231437Sluigi uint8_t q_len; 649231437Sluigi uint8_t pad[3]; 650231437Sluigi}; 651231437Sluigi 652231437Sluigi 653231437Sluigistruct oce_mq { 654231437Sluigi void *parent; 655231437Sluigi oce_ring_buffer_t *ring; 656231437Sluigi uint32_t mq_id; 657231437Sluigi struct oce_cq *cq; 658231437Sluigi struct oce_cq *async_cq; 659231437Sluigi uint32_t mq_free; 660231437Sluigi qstate_t qstate; 661231437Sluigi struct mq_config cfg; 662231437Sluigi}; 663231437Sluigi 664231437Sluigistruct oce_mbx_ctx { 665231437Sluigi struct oce_mbx *mbx; 666231437Sluigi void (*cb) (void *ctx); 667231437Sluigi void *cb_ctx; 668231437Sluigi}; 669231437Sluigi 670231437Sluigistruct wq_config { 671231437Sluigi uint8_t wq_type; 672231437Sluigi uint16_t buf_size; 673231437Sluigi uint8_t pad[1]; 674231437Sluigi uint32_t q_len; 675231437Sluigi uint16_t pd_id; 676231437Sluigi uint16_t pci_fn_num; 677231437Sluigi uint32_t eqd; /* interrupt delay */ 678231437Sluigi uint32_t nbufs; 679231437Sluigi uint32_t nhdl; 680231437Sluigi}; 681231437Sluigi 682231437Sluigistruct oce_tx_queue_stats { 683231437Sluigi uint64_t tx_pkts; 684231437Sluigi uint64_t tx_bytes; 685231437Sluigi uint32_t tx_reqs; 686231437Sluigi uint32_t tx_stops; /* number of times TX Q was stopped */ 687231437Sluigi uint32_t tx_wrbs; 688231437Sluigi uint32_t tx_compl; 689231437Sluigi uint32_t tx_rate; 690231437Sluigi uint32_t ipv6_ext_hdr_tx_drop; 691231437Sluigi}; 692231437Sluigi 693231437Sluigistruct oce_wq { 694231437Sluigi OCE_LOCK tx_lock; 695338938Sjpaetzel OCE_LOCK tx_compl_lock; 696231437Sluigi void *parent; 697231437Sluigi oce_ring_buffer_t *ring; 698231437Sluigi struct oce_cq *cq; 699231437Sluigi bus_dma_tag_t tag; 700231437Sluigi struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 701252869Sdelphij uint32_t pkt_desc_tail; 702252869Sdelphij uint32_t pkt_desc_head; 703231437Sluigi uint32_t wqm_used; 704231437Sluigi boolean_t resched; 705231437Sluigi uint32_t wq_free; 706231437Sluigi uint32_t tx_deferd; 707231437Sluigi uint32_t pkt_drops; 708231437Sluigi qstate_t qstate; 709231437Sluigi uint16_t wq_id; 710231437Sluigi struct wq_config cfg; 711231437Sluigi int queue_index; 712231437Sluigi struct oce_tx_queue_stats tx_stats; 713231437Sluigi struct buf_ring *br; 714231437Sluigi struct task txtask; 715252869Sdelphij uint32_t db_offset; 716231437Sluigi}; 717231437Sluigi 718231437Sluigistruct rq_config { 719231437Sluigi uint32_t q_len; 720231437Sluigi uint32_t frag_size; 721231437Sluigi uint32_t mtu; 722231437Sluigi uint32_t if_id; 723231437Sluigi uint32_t is_rss_queue; 724231437Sluigi uint32_t eqd; 725231437Sluigi uint32_t nbufs; 726231437Sluigi}; 727231437Sluigi 728231437Sluigistruct oce_rx_queue_stats { 729231437Sluigi uint32_t rx_post_fail; 730231437Sluigi uint32_t rx_ucast_pkts; 731231437Sluigi uint32_t rx_compl; 732231437Sluigi uint64_t rx_bytes; 733231437Sluigi uint64_t rx_bytes_prev; 734231437Sluigi uint64_t rx_pkts; 735231437Sluigi uint32_t rx_rate; 736231437Sluigi uint32_t rx_mcast_pkts; 737231437Sluigi uint32_t rxcp_err; 738231437Sluigi uint32_t rx_frags; 739231437Sluigi uint32_t prev_rx_frags; 740231437Sluigi uint32_t rx_fps; 741338938Sjpaetzel uint32_t rx_drops_no_frags; /* HW has no fetched frags */ 742231437Sluigi}; 743231437Sluigi 744231437Sluigi 745231437Sluigistruct oce_rq { 746231437Sluigi struct rq_config cfg; 747231437Sluigi uint32_t rq_id; 748231437Sluigi int queue_index; 749231437Sluigi uint32_t rss_cpuid; 750231437Sluigi void *parent; 751231437Sluigi oce_ring_buffer_t *ring; 752231437Sluigi struct oce_cq *cq; 753231437Sluigi void *pad1; 754231437Sluigi bus_dma_tag_t tag; 755231437Sluigi struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 756231437Sluigi uint32_t pending; 757231437Sluigi#ifdef notdef 758231437Sluigi struct mbuf *head; 759231437Sluigi struct mbuf *tail; 760231437Sluigi int fragsleft; 761231437Sluigi#endif 762231437Sluigi qstate_t qstate; 763231437Sluigi OCE_LOCK rx_lock; 764231437Sluigi struct oce_rx_queue_stats rx_stats; 765231437Sluigi struct lro_ctrl lro; 766231437Sluigi int lro_pkts_queued; 767338938Sjpaetzel int islro; 768338938Sjpaetzel struct nic_hwlro_cqe_part1 *cqe_firstpart; 769231437Sluigi 770231437Sluigi}; 771231437Sluigi 772231437Sluigistruct link_status { 773267839Sdelphij uint8_t phys_port_speed; 774267839Sdelphij uint8_t logical_link_status; 775231437Sluigi uint16_t qos_link_speed; 776231437Sluigi}; 777231437Sluigi 778231437Sluigi 779231437Sluigi 780231437Sluigi#define OCE_FLAGS_PCIX 0x00000001 781231437Sluigi#define OCE_FLAGS_PCIE 0x00000002 782231437Sluigi#define OCE_FLAGS_MSI_CAPABLE 0x00000004 783231437Sluigi#define OCE_FLAGS_MSIX_CAPABLE 0x00000008 784231437Sluigi#define OCE_FLAGS_USING_MSI 0x00000010 785231437Sluigi#define OCE_FLAGS_USING_MSIX 0x00000020 786231437Sluigi#define OCE_FLAGS_FUNCRESET_RQD 0x00000040 787231437Sluigi#define OCE_FLAGS_VIRTUAL_PORT 0x00000080 788231437Sluigi#define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 789231437Sluigi#define OCE_FLAGS_BE3 0x00000200 790231437Sluigi#define OCE_FLAGS_XE201 0x00000400 791231437Sluigi#define OCE_FLAGS_BE2 0x00000800 792252869Sdelphij#define OCE_FLAGS_SH 0x00001000 793338938Sjpaetzel#define OCE_FLAGS_OS2BMC 0x00002000 794231437Sluigi 795231437Sluigi#define OCE_DEV_BE2_CFG_BAR 1 796231437Sluigi#define OCE_DEV_CFG_BAR 0 797231437Sluigi#define OCE_PCI_CSR_BAR 2 798231437Sluigi#define OCE_PCI_DB_BAR 4 799231437Sluigi 800231437Sluigitypedef struct oce_softc { 801231437Sluigi device_t dev; 802231437Sluigi OCE_LOCK dev_lock; 803231437Sluigi 804231437Sluigi uint32_t flags; 805231437Sluigi 806231437Sluigi uint32_t pcie_link_speed; 807231437Sluigi uint32_t pcie_link_width; 808231437Sluigi 809231437Sluigi uint8_t fn; /* PCI function number */ 810231437Sluigi 811231437Sluigi struct resource *devcfg_res; 812231437Sluigi bus_space_tag_t devcfg_btag; 813231437Sluigi bus_space_handle_t devcfg_bhandle; 814231437Sluigi void *devcfg_vhandle; 815231437Sluigi 816231437Sluigi struct resource *csr_res; 817231437Sluigi bus_space_tag_t csr_btag; 818231437Sluigi bus_space_handle_t csr_bhandle; 819231437Sluigi void *csr_vhandle; 820231437Sluigi 821231437Sluigi struct resource *db_res; 822231437Sluigi bus_space_tag_t db_btag; 823231437Sluigi bus_space_handle_t db_bhandle; 824231437Sluigi void *db_vhandle; 825231437Sluigi 826231437Sluigi OCE_INTR_INFO intrs[OCE_MAX_EQ]; 827231437Sluigi int intr_count; 828338938Sjpaetzel int roce_intr_count; 829231437Sluigi 830231437Sluigi struct ifnet *ifp; 831231437Sluigi 832231437Sluigi struct ifmedia media; 833231437Sluigi uint8_t link_status; 834231437Sluigi uint8_t link_speed; 835231437Sluigi uint8_t duplex; 836231437Sluigi uint32_t qos_link_speed; 837231437Sluigi uint32_t speed; 838338938Sjpaetzel uint32_t enable_hwlro; 839231437Sluigi 840231437Sluigi char fw_version[32]; 841231437Sluigi struct mac_address_format macaddr; 842231437Sluigi 843231437Sluigi OCE_DMA_MEM bsmbx; 844231437Sluigi OCE_LOCK bmbx_lock; 845231437Sluigi 846231437Sluigi uint32_t config_number; 847231437Sluigi uint32_t asic_revision; 848231437Sluigi uint32_t port_id; 849231437Sluigi uint32_t function_mode; 850231437Sluigi uint32_t function_caps; 851231437Sluigi uint32_t max_tx_rings; 852231437Sluigi uint32_t max_rx_rings; 853231437Sluigi 854231437Sluigi struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 855231437Sluigi struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 856231437Sluigi struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 857231437Sluigi struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 858231437Sluigi struct oce_mq *mq; /* Mailbox queue */ 859231437Sluigi 860231437Sluigi uint32_t neqs; 861231437Sluigi uint32_t ncqs; 862231437Sluigi uint32_t nrqs; 863231437Sluigi uint32_t nwqs; 864252869Sdelphij uint32_t nrssqs; 865231437Sluigi 866231437Sluigi uint32_t tx_ring_size; 867231437Sluigi uint32_t rx_ring_size; 868231437Sluigi uint32_t rq_frag_size; 869231437Sluigi 870231437Sluigi uint32_t if_id; /* interface ID */ 871231437Sluigi uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 872231437Sluigi uint32_t pmac_id; /* PMAC id */ 873231437Sluigi 874231437Sluigi uint32_t if_cap_flags; 875231437Sluigi 876231437Sluigi uint32_t flow_control; 877257007Sdelphij uint8_t promisc; 878247880Sdelphij 879247880Sdelphij struct oce_aic_obj aic_obj[OCE_MAX_EQ]; 880247880Sdelphij 881231437Sluigi /*Vlan Filtering related */ 882231437Sluigi eventhandler_tag vlan_attach; 883231437Sluigi eventhandler_tag vlan_detach; 884231437Sluigi uint16_t vlans_added; 885231437Sluigi uint8_t vlan_tag[MAX_VLANS]; 886231437Sluigi /*stats */ 887231437Sluigi OCE_DMA_MEM stats_mem; 888231437Sluigi struct oce_drv_stats oce_stats_info; 889231437Sluigi struct callout timer; 890231437Sluigi int8_t be3_native; 891257007Sdelphij uint8_t hw_error; 892247880Sdelphij uint16_t qnq_debug_event; 893247880Sdelphij uint16_t qnqid; 894258941Sdelphij uint32_t pvid; 895258941Sdelphij uint32_t max_vlans; 896338938Sjpaetzel uint32_t bmc_filt_mask; 897231437Sluigi 898338938Sjpaetzel void *rdma_context; 899338938Sjpaetzel uint32_t rdma_flags; 900338938Sjpaetzel struct oce_softc *next; 901338938Sjpaetzel 902231437Sluigi} OCE_SOFTC, *POCE_SOFTC; 903231437Sluigi 904338938Sjpaetzel#define OCE_RDMA_FLAG_SUPPORTED 0x00000001 905231437Sluigi 906231437Sluigi 907231437Sluigi/************************************************** 908231437Sluigi * BUS memory read/write macros 909231437Sluigi * BE3: accesses three BAR spaces (CFG, CSR, DB) 910231437Sluigi * Lancer: accesses one BAR space (CFG) 911231437Sluigi **************************************************/ 912252869Sdelphij#define OCE_READ_CSR_MPU(sc, space, o) \ 913252869Sdelphij ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 914252869Sdelphij (sc)->space##_bhandle,o)) \ 915252869Sdelphij : (bus_space_read_4((sc)->devcfg_btag, \ 916252869Sdelphij (sc)->devcfg_bhandle,o))) 917231437Sluigi#define OCE_READ_REG32(sc, space, o) \ 918252869Sdelphij ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 919252869Sdelphij (sc)->space##_bhandle,o)) \ 920252869Sdelphij : (bus_space_read_4((sc)->devcfg_btag, \ 921252869Sdelphij (sc)->devcfg_bhandle,o))) 922231437Sluigi#define OCE_READ_REG16(sc, space, o) \ 923252869Sdelphij ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 924252869Sdelphij (sc)->space##_bhandle,o)) \ 925252869Sdelphij : (bus_space_read_2((sc)->devcfg_btag, \ 926252869Sdelphij (sc)->devcfg_bhandle,o))) 927231437Sluigi#define OCE_READ_REG8(sc, space, o) \ 928252869Sdelphij ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 929252869Sdelphij (sc)->space##_bhandle,o)) \ 930252869Sdelphij : (bus_space_read_1((sc)->devcfg_btag, \ 931252869Sdelphij (sc)->devcfg_bhandle,o))) 932231437Sluigi 933252869Sdelphij#define OCE_WRITE_CSR_MPU(sc, space, o, v) \ 934231437Sluigi ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 935231437Sluigi (sc)->space##_bhandle,o,v)) \ 936252869Sdelphij : (bus_space_write_4((sc)->devcfg_btag, \ 937252869Sdelphij (sc)->devcfg_bhandle,o,v))) 938252869Sdelphij#define OCE_WRITE_REG32(sc, space, o, v) \ 939252869Sdelphij ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 940252869Sdelphij (sc)->space##_bhandle,o,v)) \ 941252869Sdelphij : (bus_space_write_4((sc)->devcfg_btag, \ 942252869Sdelphij (sc)->devcfg_bhandle,o,v))) 943231437Sluigi#define OCE_WRITE_REG16(sc, space, o, v) \ 944252869Sdelphij ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 945231437Sluigi (sc)->space##_bhandle,o,v)) \ 946252869Sdelphij : (bus_space_write_2((sc)->devcfg_btag, \ 947252869Sdelphij (sc)->devcfg_bhandle,o,v))) 948231437Sluigi#define OCE_WRITE_REG8(sc, space, o, v) \ 949252869Sdelphij ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 950231437Sluigi (sc)->space##_bhandle,o,v)) \ 951252869Sdelphij : (bus_space_write_1((sc)->devcfg_btag, \ 952252869Sdelphij (sc)->devcfg_bhandle,o,v))) 953231437Sluigi 954338938Sjpaetzelvoid oce_rx_flush_lro(struct oce_rq *rq); 955231437Sluigi/*********************************************************** 956231437Sluigi * DMA memory functions 957231437Sluigi ***********************************************************/ 958231437Sluigi#define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 959231437Sluigiint oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 960231437Sluigivoid oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 961231437Sluigivoid oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 962231437Sluigivoid oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 963231437Sluigioce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 964231437Sluigi uint32_t q_len, uint32_t num_entries); 965231437Sluigi/************************************************************ 966231437Sluigi * oce_hw_xxx functions 967231437Sluigi ************************************************************/ 968231437Sluigiint oce_clear_rx_buf(struct oce_rq *rq); 969231437Sluigiint oce_hw_pci_alloc(POCE_SOFTC sc); 970231437Sluigiint oce_hw_init(POCE_SOFTC sc); 971231437Sluigiint oce_hw_start(POCE_SOFTC sc); 972231437Sluigiint oce_create_nw_interface(POCE_SOFTC sc); 973231437Sluigiint oce_pci_soft_reset(POCE_SOFTC sc); 974231437Sluigiint oce_hw_update_multicast(POCE_SOFTC sc); 975231437Sluigivoid oce_delete_nw_interface(POCE_SOFTC sc); 976231437Sluigivoid oce_hw_shutdown(POCE_SOFTC sc); 977231437Sluigivoid oce_hw_intr_enable(POCE_SOFTC sc); 978231437Sluigivoid oce_hw_intr_disable(POCE_SOFTC sc); 979231437Sluigivoid oce_hw_pci_free(POCE_SOFTC sc); 980231437Sluigi 981231437Sluigi/*********************************************************** 982231437Sluigi * oce_queue_xxx functions 983231437Sluigi ***********************************************************/ 984231437Sluigiint oce_queue_init_all(POCE_SOFTC sc); 985231437Sluigiint oce_start_rq(struct oce_rq *rq); 986231437Sluigiint oce_start_wq(struct oce_wq *wq); 987231437Sluigiint oce_start_mq(struct oce_mq *mq); 988231437Sluigiint oce_start_rx(POCE_SOFTC sc); 989231437Sluigivoid oce_arm_eq(POCE_SOFTC sc, 990231437Sluigi int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 991231437Sluigivoid oce_queue_release_all(POCE_SOFTC sc); 992231437Sluigivoid oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 993231437Sluigivoid oce_drain_eq(struct oce_eq *eq); 994231437Sluigivoid oce_drain_mq_cq(void *arg); 995231437Sluigivoid oce_drain_rq_cq(struct oce_rq *rq); 996231437Sluigivoid oce_drain_wq_cq(struct oce_wq *wq); 997231437Sluigi 998231437Sluigiuint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 999231437Sluigi 1000231437Sluigi/*********************************************************** 1001231437Sluigi * cleanup functions 1002231437Sluigi ***********************************************************/ 1003231437Sluigivoid oce_stop_rx(POCE_SOFTC sc); 1004338938Sjpaetzelvoid oce_discard_rx_comp(struct oce_rq *rq, int num_frags); 1005338938Sjpaetzelvoid oce_rx_cq_clean(struct oce_rq *rq); 1006338938Sjpaetzelvoid oce_rx_cq_clean_hwlro(struct oce_rq *rq); 1007231437Sluigivoid oce_intr_free(POCE_SOFTC sc); 1008231437Sluigivoid oce_free_posted_rxbuf(struct oce_rq *rq); 1009231879Sluigi#if defined(INET6) || defined(INET) 1010231879Sluigivoid oce_free_lro(POCE_SOFTC sc); 1011231879Sluigi#endif 1012231437Sluigi 1013231437Sluigi 1014231437Sluigi/************************************************************ 1015231437Sluigi * Mailbox functions 1016231437Sluigi ************************************************************/ 1017231437Sluigiint oce_fw_clean(POCE_SOFTC sc); 1018338939Sjpaetzelint oce_wait_ready(POCE_SOFTC sc); 1019231437Sluigiint oce_reset_fun(POCE_SOFTC sc); 1020231437Sluigiint oce_mbox_init(POCE_SOFTC sc); 1021231437Sluigiint oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 1022231437Sluigiint oce_get_fw_version(POCE_SOFTC sc); 1023231879Sluigiint oce_first_mcc_cmd(POCE_SOFTC sc); 1024231879Sluigi 1025231437Sluigiint oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 1026231437Sluigi uint8_t type, struct mac_address_format *mac); 1027231437Sluigiint oce_get_fw_config(POCE_SOFTC sc); 1028231437Sluigiint oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 1029231437Sluigi uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 1030231437Sluigiint oce_if_del(POCE_SOFTC sc, uint32_t if_id); 1031231437Sluigiint oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 1032231437Sluigi struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 1033231437Sluigi uint32_t untagged, uint32_t enable_promisc); 1034231437Sluigiint oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 1035231437Sluigiint oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 1036257007Sdelphijint oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable); 1037231437Sluigiint oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 1038231437Sluigiint oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 1039231437Sluigiint oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1040338938Sjpaetzelint oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1041338938Sjpaetzelint oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1042231437Sluigiint oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1043231437Sluigi uint32_t reset_stats); 1044231437Sluigiint oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1045231437Sluigi uint32_t req_size, uint32_t reset_stats); 1046231437Sluigiint oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 1047231437Sluigiint oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 1048231437Sluigiint oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 1049231437Sluigiint oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1050231437Sluigi uint32_t if_id, uint32_t *pmac_id); 1051231437Sluigiint oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1052231437Sluigi uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1053231437Sluigi uint64_t pattern); 1054231437Sluigi 1055231437Sluigiint oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1056231437Sluigi uint8_t loopback_type, uint8_t enable); 1057231437Sluigi 1058231437Sluigiint oce_mbox_check_native_mode(POCE_SOFTC sc); 1059231437Sluigiint oce_mbox_post(POCE_SOFTC sc, 1060231437Sluigi struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 1061231437Sluigiint oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1062231437Sluigi POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 1063231437Sluigiint oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1064231437Sluigi uint32_t data_offset,POCE_DMA_MEM pdma_mem, 1065231437Sluigi uint32_t *written_data, uint32_t *additional_status); 1066231437Sluigi 1067231437Sluigiint oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1068231437Sluigi uint32_t offset, uint32_t optype); 1069231437Sluigiint oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 1070231437Sluigiint oce_mbox_create_rq(struct oce_rq *rq); 1071231437Sluigiint oce_mbox_create_wq(struct oce_wq *wq); 1072231437Sluigiint oce_mbox_create_eq(struct oce_eq *eq); 1073231437Sluigiint oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 1074231437Sluigi uint32_t is_eventable); 1075247880Sdelphijint oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1076247880Sdelphijvoid oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1077247880Sdelphij int num); 1078258941Sdelphijint oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss); 1079252869Sdelphijint oce_get_func_config(POCE_SOFTC sc); 1080231437Sluigivoid mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1081231437Sluigi uint8_t dom, 1082231437Sluigi uint8_t port, 1083231437Sluigi uint8_t subsys, 1084231437Sluigi uint8_t opcode, 1085231437Sluigi uint32_t timeout, uint32_t pyld_len, 1086231437Sluigi uint8_t version); 1087231437Sluigi 1088231437Sluigi 1089231437Sluigiuint16_t oce_mq_handler(void *arg); 1090231437Sluigi 1091231437Sluigi/************************************************************ 1092231437Sluigi * Transmit functions 1093231437Sluigi ************************************************************/ 1094231437Sluigiuint16_t oce_wq_handler(void *arg); 1095231437Sluigivoid oce_start(struct ifnet *ifp); 1096231437Sluigivoid oce_tx_task(void *arg, int npending); 1097231437Sluigi 1098231437Sluigi/************************************************************ 1099231437Sluigi * Receive functions 1100231437Sluigi ************************************************************/ 1101231437Sluigiint oce_alloc_rx_bufs(struct oce_rq *rq, int count); 1102231437Sluigiuint16_t oce_rq_handler(void *arg); 1103231437Sluigi 1104231437Sluigi 1105231437Sluigi/* Sysctl functions */ 1106231437Sluigivoid oce_add_sysctls(POCE_SOFTC sc); 1107231437Sluigivoid oce_refresh_queue_stats(POCE_SOFTC sc); 1108231437Sluigiint oce_refresh_nic_stats(POCE_SOFTC sc); 1109231437Sluigiint oce_stats_init(POCE_SOFTC sc); 1110231437Sluigivoid oce_stats_free(POCE_SOFTC sc); 1111231437Sluigi 1112338938Sjpaetzel/* hw lro functions */ 1113338938Sjpaetzelint oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags); 1114338938Sjpaetzelint oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable); 1115338938Sjpaetzelint oce_mbox_create_rq_v2(struct oce_rq *rq); 1116338938Sjpaetzel 1117231437Sluigi/* Capabilities */ 1118231437Sluigi#define OCE_MODCAP_RSS 1 1119231437Sluigi#define OCE_MAX_RSP_HANDLED 64 1120231437Sluigiextern uint32_t oce_max_rsp_handled; /* max responses */ 1121338938Sjpaetzelextern uint32_t oce_rq_buf_size; 1122231437Sluigi 1123231437Sluigi#define OCE_MAC_LOOPBACK 0x0 1124231437Sluigi#define OCE_PHY_LOOPBACK 0x1 1125231437Sluigi#define OCE_ONE_PORT_EXT_LOOPBACK 0x2 1126231437Sluigi#define OCE_NO_LOOPBACK 0xff 1127231437Sluigi 1128258941Sdelphij#undef IFM_40G_SR4 1129258941Sdelphij#define IFM_40G_SR4 28 1130258941Sdelphij 1131231437Sluigi#define atomic_inc_32(x) atomic_add_32(x, 1) 1132231437Sluigi#define atomic_dec_32(x) atomic_subtract_32(x, 1) 1133231437Sluigi 1134231437Sluigi#define LE_64(x) htole64(x) 1135231437Sluigi#define LE_32(x) htole32(x) 1136231437Sluigi#define LE_16(x) htole16(x) 1137252869Sdelphij#define HOST_64(x) le64toh(x) 1138252869Sdelphij#define HOST_32(x) le32toh(x) 1139252869Sdelphij#define HOST_16(x) le16toh(x) 1140231437Sluigi#define DW_SWAP(x, l) 1141231437Sluigi#define IS_ALIGNED(x,a) ((x % a) == 0) 1142231437Sluigi#define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1143231437Sluigi#define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1144231437Sluigi 1145231437Sluigi#define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1146231437Sluigi#define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1147231437Sluigi#define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 1148231437Sluigi 1149231437Sluigi#define OCE_LOG2(x) (oce_highbit(x)) 1150231437Sluigistatic inline uint32_t oce_highbit(uint32_t x) 1151231437Sluigi{ 1152231437Sluigi int i; 1153231437Sluigi int c; 1154231437Sluigi int b; 1155231437Sluigi 1156231437Sluigi c = 0; 1157231437Sluigi b = 0; 1158231437Sluigi 1159231437Sluigi for (i = 0; i < 32; i++) { 1160231437Sluigi if ((1 << i) & x) { 1161231437Sluigi c++; 1162231437Sluigi b = i; 1163231437Sluigi } 1164231437Sluigi } 1165231437Sluigi 1166231437Sluigi if (c == 1) 1167231437Sluigi return b; 1168231437Sluigi 1169231437Sluigi return 0; 1170231437Sluigi} 1171231437Sluigi 1172252869Sdelphijstatic inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc) 1173252869Sdelphij{ 1174252869Sdelphij if (IS_BE(sc)) 1175252869Sdelphij return MPU_EP_SEMAPHORE_BE3; 1176252869Sdelphij else if (IS_SH(sc)) 1177252869Sdelphij return MPU_EP_SEMAPHORE_SH; 1178252869Sdelphij else 1179252869Sdelphij return MPU_EP_SEMAPHORE_XE201; 1180252869Sdelphij} 1181252869Sdelphij 1182247880Sdelphij#define TRANSCEIVER_DATA_NUM_ELE 64 1183247880Sdelphij#define TRANSCEIVER_DATA_SIZE 256 1184247880Sdelphij#define TRANSCEIVER_A0_SIZE 128 1185247880Sdelphij#define TRANSCEIVER_A2_SIZE 128 1186247880Sdelphij#define PAGE_NUM_A0 0xa0 1187247880Sdelphij#define PAGE_NUM_A2 0xa2 1188247880Sdelphij#define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1189247880Sdelphij || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE))) 1190343300Sdelphijextern uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE]; 1191247880Sdelphij 1192338938Sjpaetzelstruct oce_rdma_info; 1193338938Sjpaetzelextern struct oce_rdma_if *oce_rdma_if; 1194338938Sjpaetzel 1195338938Sjpaetzel 1196338938Sjpaetzel 1197338938Sjpaetzel/* OS2BMC related */ 1198338938Sjpaetzel 1199338938Sjpaetzel#define DHCP_CLIENT_PORT 68 1200338938Sjpaetzel#define DHCP_SERVER_PORT 67 1201338938Sjpaetzel#define NET_BIOS_PORT1 137 1202338938Sjpaetzel#define NET_BIOS_PORT2 138 1203338938Sjpaetzel#define DHCPV6_RAS_PORT 547 1204338938Sjpaetzel 1205338938Sjpaetzel#define BMC_FILT_BROADCAST_ARP ((uint32_t)(1)) 1206338938Sjpaetzel#define BMC_FILT_BROADCAST_DHCP_CLIENT ((uint32_t)(1 << 1)) 1207338938Sjpaetzel#define BMC_FILT_BROADCAST_DHCP_SERVER ((uint32_t)(1 << 2)) 1208338938Sjpaetzel#define BMC_FILT_BROADCAST_NET_BIOS ((uint32_t)(1 << 3)) 1209338938Sjpaetzel#define BMC_FILT_BROADCAST ((uint32_t)(1 << 4)) 1210338938Sjpaetzel#define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER ((uint32_t)(1 << 5)) 1211338938Sjpaetzel#define BMC_FILT_MULTICAST_IPV6_RA ((uint32_t)(1 << 6)) 1212338938Sjpaetzel#define BMC_FILT_MULTICAST_IPV6_RAS ((uint32_t)(1 << 7)) 1213338938Sjpaetzel#define BMC_FILT_MULTICAST ((uint32_t)(1 << 8)) 1214338938Sjpaetzel 1215338938Sjpaetzel#define ND_ROUTER_ADVERT 134 1216338938Sjpaetzel#define ND_NEIGHBOR_ADVERT 136 1217338938Sjpaetzel 1218338938Sjpaetzel#define is_mc_allowed_on_bmc(sc, eh) \ 1219338938Sjpaetzel (!is_multicast_filt_enabled(sc) && \ 1220338938Sjpaetzel ETHER_IS_MULTICAST(eh->ether_dhost) && \ 1221338938Sjpaetzel !ETHER_IS_BROADCAST(eh->ether_dhost)) 1222338938Sjpaetzel 1223338938Sjpaetzel#define is_bc_allowed_on_bmc(sc, eh) \ 1224338938Sjpaetzel (!is_broadcast_filt_enabled(sc) && \ 1225338938Sjpaetzel ETHER_IS_BROADCAST(eh->ether_dhost)) 1226338938Sjpaetzel 1227338938Sjpaetzel#define is_arp_allowed_on_bmc(sc, et) \ 1228338938Sjpaetzel (is_arp(et) && is_arp_filt_enabled(sc)) 1229338938Sjpaetzel 1230338938Sjpaetzel#define is_arp(et) (et == ETHERTYPE_ARP) 1231338938Sjpaetzel 1232338938Sjpaetzel#define is_arp_filt_enabled(sc) \ 1233338938Sjpaetzel (sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP)) 1234338938Sjpaetzel 1235338938Sjpaetzel#define is_dhcp_client_filt_enabled(sc) \ 1236338938Sjpaetzel (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT) 1237338938Sjpaetzel 1238338938Sjpaetzel#define is_dhcp_srvr_filt_enabled(sc) \ 1239338938Sjpaetzel (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER) 1240338938Sjpaetzel 1241338938Sjpaetzel#define is_nbios_filt_enabled(sc) \ 1242338938Sjpaetzel (sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS) 1243338938Sjpaetzel 1244338938Sjpaetzel#define is_ipv6_na_filt_enabled(sc) \ 1245338938Sjpaetzel (sc->bmc_filt_mask & \ 1246338938Sjpaetzel BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER) 1247338938Sjpaetzel 1248338938Sjpaetzel#define is_ipv6_ra_filt_enabled(sc) \ 1249338938Sjpaetzel (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA) 1250338938Sjpaetzel 1251338938Sjpaetzel#define is_ipv6_ras_filt_enabled(sc) \ 1252338938Sjpaetzel (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS) 1253338938Sjpaetzel 1254338938Sjpaetzel#define is_broadcast_filt_enabled(sc) \ 1255338938Sjpaetzel (sc->bmc_filt_mask & BMC_FILT_BROADCAST) 1256338938Sjpaetzel 1257338938Sjpaetzel#define is_multicast_filt_enabled(sc) \ 1258338938Sjpaetzel (sc->bmc_filt_mask & BMC_FILT_MULTICAST) 1259338938Sjpaetzel 1260338938Sjpaetzel#define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC) 1261338938Sjpaetzel 1262338938Sjpaetzel#define LRO_FLAGS_HASH_MODE 0x00000001 1263338938Sjpaetzel#define LRO_FLAGS_RSS_MODE 0x00000004 1264338938Sjpaetzel#define LRO_FLAGS_CLSC_IPV4 0x00000010 1265338938Sjpaetzel#define LRO_FLAGS_CLSC_IPV6 0x00000020 1266338938Sjpaetzel#define NIC_RQ_FLAGS_RSS 0x0001 1267338938Sjpaetzel#define NIC_RQ_FLAGS_LRO 0x0020 1268338938Sjpaetzel 1269